stm32f1/stm32f101/rtc/divl/
mod.rs

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#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
impl super::DIVL {
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
}
#[doc = r" Value of the field"]
pub struct DIVLR {
    bits: u16,
}
impl DIVLR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u16 {
        self.bits
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 0:15 - RTC prescaler divider register Low"]
    #[inline]
    pub fn divl(&self) -> DIVLR {
        let bits = {
            const MASK: u16 = 65535;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u16
        };
        DIVLR { bits }
    }
}