stm32f1 0.4.0

Device support crates for STM32F1 devices
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#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
impl super::CAN_RDT0R {
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
}
#[doc = r" Value of the field"]
pub struct TIMER {
    bits: u16,
}
impl TIMER {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u16 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct FMIR {
    bits: u8,
}
impl FMIR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct DLCR {
    bits: u8,
}
impl DLCR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 16:31 - TIME"]
    #[inline]
    pub fn time(&self) -> TIMER {
        let bits = {
            const MASK: u16 = 65535;
            const OFFSET: u8 = 16;
            ((self.bits >> OFFSET) & MASK as u32) as u16
        };
        TIMER { bits }
    }
    #[doc = "Bits 8:15 - FMI"]
    #[inline]
    pub fn fmi(&self) -> FMIR {
        let bits = {
            const MASK: u8 = 255;
            const OFFSET: u8 = 8;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        FMIR { bits }
    }
    #[doc = "Bits 0:3 - DLC"]
    #[inline]
    pub fn dlc(&self) -> DLCR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        DLCR { bits }
    }
}