stm32f1-staging 0.20.0

Device support crates for STM32F1 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131

///Register `SR4` reader
pub type R = crate::R<SR4rs>;
///Register `SR4` writer
pub type W = crate::W<SR4rs>;
///Field `IRS` reader - IRS
pub type IRS_R = crate::BitReader;
///Field `IRS` writer - IRS
pub type IRS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ILS` reader - ILS
pub type ILS_R = crate::BitReader;
///Field `ILS` writer - ILS
pub type ILS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IFS` reader - IFS
pub type IFS_R = crate::BitReader;
///Field `IFS` writer - IFS
pub type IFS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IREN` reader - IREN
pub type IREN_R = crate::BitReader;
///Field `IREN` writer - IREN
pub type IREN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ILEN` reader - ILEN
pub type ILEN_R = crate::BitReader;
///Field `ILEN` writer - ILEN
pub type ILEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `IFEN` reader - IFEN
pub type IFEN_R = crate::BitReader;
///Field `IFEN` writer - IFEN
pub type IFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FEMPT` reader - FEMPT
pub type FEMPT_R = crate::BitReader;
impl R {
    ///Bit 0 - IRS
    #[inline(always)]
    pub fn irs(&self) -> IRS_R {
        IRS_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - ILS
    #[inline(always)]
    pub fn ils(&self) -> ILS_R {
        ILS_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - IFS
    #[inline(always)]
    pub fn ifs(&self) -> IFS_R {
        IFS_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - IREN
    #[inline(always)]
    pub fn iren(&self) -> IREN_R {
        IREN_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - ILEN
    #[inline(always)]
    pub fn ilen(&self) -> ILEN_R {
        ILEN_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - IFEN
    #[inline(always)]
    pub fn ifen(&self) -> IFEN_R {
        IFEN_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - FEMPT
    #[inline(always)]
    pub fn fempt(&self) -> FEMPT_R {
        FEMPT_R::new(((self.bits >> 6) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SR4")
            .field("fempt", &self.fempt())
            .field("ifen", &self.ifen())
            .field("ilen", &self.ilen())
            .field("iren", &self.iren())
            .field("ifs", &self.ifs())
            .field("ils", &self.ils())
            .field("irs", &self.irs())
            .finish()
    }
}
impl W {
    ///Bit 0 - IRS
    #[inline(always)]
    pub fn irs(&mut self) -> IRS_W<SR4rs> {
        IRS_W::new(self, 0)
    }
    ///Bit 1 - ILS
    #[inline(always)]
    pub fn ils(&mut self) -> ILS_W<SR4rs> {
        ILS_W::new(self, 1)
    }
    ///Bit 2 - IFS
    #[inline(always)]
    pub fn ifs(&mut self) -> IFS_W<SR4rs> {
        IFS_W::new(self, 2)
    }
    ///Bit 3 - IREN
    #[inline(always)]
    pub fn iren(&mut self) -> IREN_W<SR4rs> {
        IREN_W::new(self, 3)
    }
    ///Bit 4 - ILEN
    #[inline(always)]
    pub fn ilen(&mut self) -> ILEN_W<SR4rs> {
        ILEN_W::new(self, 4)
    }
    ///Bit 5 - IFEN
    #[inline(always)]
    pub fn ifen(&mut self) -> IFEN_W<SR4rs> {
        IFEN_W::new(self, 5)
    }
}
/**FIFO status and interrupt register 4

You can [`read`](crate::Reg::read) this register and get [`sr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC:SR4)*/
pub struct SR4rs;
impl crate::RegisterSpec for SR4rs {
    type Ux = u32;
}
///`read()` method returns [`sr4::R`](R) reader structure
impl crate::Readable for SR4rs {}
///`write(|w| ..)` method takes [`sr4::W`](W) writer structure
impl crate::Writable for SR4rs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets SR4 to value 0x40
impl crate::Resettable for SR4rs {
    const RESET_VALUE: u32 = 0x40;
}