stm32f1_staging/stm32f103/adc1/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5///Field `AWDCH` reader - Analog watchdog channel select bits
6pub type AWDCH_R = crate::FieldReader;
7///Field `AWDCH` writer - Analog watchdog channel select bits
8pub type AWDCH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9/**Interrupt enable for EOC
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum EOCIE {
15    ///0: EOC interrupt disabled
16    Disabled = 0,
17    ///1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set
18    Enabled = 1,
19}
20impl From<EOCIE> for bool {
21    #[inline(always)]
22    fn from(variant: EOCIE) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `EOCIE` reader - Interrupt enable for EOC
27pub type EOCIE_R = crate::BitReader<EOCIE>;
28impl EOCIE_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> EOCIE {
32        match self.bits {
33            false => EOCIE::Disabled,
34            true => EOCIE::Enabled,
35        }
36    }
37    ///EOC interrupt disabled
38    #[inline(always)]
39    pub fn is_disabled(&self) -> bool {
40        *self == EOCIE::Disabled
41    }
42    ///EOC interrupt enabled. An interrupt is generated when the EOC bit is set
43    #[inline(always)]
44    pub fn is_enabled(&self) -> bool {
45        *self == EOCIE::Enabled
46    }
47}
48///Field `EOCIE` writer - Interrupt enable for EOC
49pub type EOCIE_W<'a, REG> = crate::BitWriter<'a, REG, EOCIE>;
50impl<'a, REG> EOCIE_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///EOC interrupt disabled
55    #[inline(always)]
56    pub fn disabled(self) -> &'a mut crate::W<REG> {
57        self.variant(EOCIE::Disabled)
58    }
59    ///EOC interrupt enabled. An interrupt is generated when the EOC bit is set
60    #[inline(always)]
61    pub fn enabled(self) -> &'a mut crate::W<REG> {
62        self.variant(EOCIE::Enabled)
63    }
64}
65/**Analog watchdog interrupt enable
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum AWDIE {
71    ///0: Analog watchdog interrupt disabled
72    Disabled = 0,
73    ///1: Analog watchdog interrupt enabled
74    Enabled = 1,
75}
76impl From<AWDIE> for bool {
77    #[inline(always)]
78    fn from(variant: AWDIE) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `AWDIE` reader - Analog watchdog interrupt enable
83pub type AWDIE_R = crate::BitReader<AWDIE>;
84impl AWDIE_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> AWDIE {
88        match self.bits {
89            false => AWDIE::Disabled,
90            true => AWDIE::Enabled,
91        }
92    }
93    ///Analog watchdog interrupt disabled
94    #[inline(always)]
95    pub fn is_disabled(&self) -> bool {
96        *self == AWDIE::Disabled
97    }
98    ///Analog watchdog interrupt enabled
99    #[inline(always)]
100    pub fn is_enabled(&self) -> bool {
101        *self == AWDIE::Enabled
102    }
103}
104///Field `AWDIE` writer - Analog watchdog interrupt enable
105pub type AWDIE_W<'a, REG> = crate::BitWriter<'a, REG, AWDIE>;
106impl<'a, REG> AWDIE_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///Analog watchdog interrupt disabled
111    #[inline(always)]
112    pub fn disabled(self) -> &'a mut crate::W<REG> {
113        self.variant(AWDIE::Disabled)
114    }
115    ///Analog watchdog interrupt enabled
116    #[inline(always)]
117    pub fn enabled(self) -> &'a mut crate::W<REG> {
118        self.variant(AWDIE::Enabled)
119    }
120}
121/**Interrupt enable for injected channels
122
123Value on reset: 0*/
124#[cfg_attr(feature = "defmt", derive(defmt::Format))]
125#[derive(Clone, Copy, Debug, PartialEq, Eq)]
126pub enum JEOCIE {
127    ///0: JEOC interrupt disabled
128    Disabled = 0,
129    ///1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set
130    Enabled = 1,
131}
132impl From<JEOCIE> for bool {
133    #[inline(always)]
134    fn from(variant: JEOCIE) -> Self {
135        variant as u8 != 0
136    }
137}
138///Field `JEOCIE` reader - Interrupt enable for injected channels
139pub type JEOCIE_R = crate::BitReader<JEOCIE>;
140impl JEOCIE_R {
141    ///Get enumerated values variant
142    #[inline(always)]
143    pub const fn variant(&self) -> JEOCIE {
144        match self.bits {
145            false => JEOCIE::Disabled,
146            true => JEOCIE::Enabled,
147        }
148    }
149    ///JEOC interrupt disabled
150    #[inline(always)]
151    pub fn is_disabled(&self) -> bool {
152        *self == JEOCIE::Disabled
153    }
154    ///JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set
155    #[inline(always)]
156    pub fn is_enabled(&self) -> bool {
157        *self == JEOCIE::Enabled
158    }
159}
160///Field `JEOCIE` writer - Interrupt enable for injected channels
161pub type JEOCIE_W<'a, REG> = crate::BitWriter<'a, REG, JEOCIE>;
162impl<'a, REG> JEOCIE_W<'a, REG>
163where
164    REG: crate::Writable + crate::RegisterSpec,
165{
166    ///JEOC interrupt disabled
167    #[inline(always)]
168    pub fn disabled(self) -> &'a mut crate::W<REG> {
169        self.variant(JEOCIE::Disabled)
170    }
171    ///JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set
172    #[inline(always)]
173    pub fn enabled(self) -> &'a mut crate::W<REG> {
174        self.variant(JEOCIE::Enabled)
175    }
176}
177/**Scan mode
178
179Value on reset: 0*/
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum SCAN {
183    ///0: Scan mode disabled
184    Disabled = 0,
185    ///1: Scan mode enabled
186    Enabled = 1,
187}
188impl From<SCAN> for bool {
189    #[inline(always)]
190    fn from(variant: SCAN) -> Self {
191        variant as u8 != 0
192    }
193}
194///Field `SCAN` reader - Scan mode
195pub type SCAN_R = crate::BitReader<SCAN>;
196impl SCAN_R {
197    ///Get enumerated values variant
198    #[inline(always)]
199    pub const fn variant(&self) -> SCAN {
200        match self.bits {
201            false => SCAN::Disabled,
202            true => SCAN::Enabled,
203        }
204    }
205    ///Scan mode disabled
206    #[inline(always)]
207    pub fn is_disabled(&self) -> bool {
208        *self == SCAN::Disabled
209    }
210    ///Scan mode enabled
211    #[inline(always)]
212    pub fn is_enabled(&self) -> bool {
213        *self == SCAN::Enabled
214    }
215}
216///Field `SCAN` writer - Scan mode
217pub type SCAN_W<'a, REG> = crate::BitWriter<'a, REG, SCAN>;
218impl<'a, REG> SCAN_W<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    ///Scan mode disabled
223    #[inline(always)]
224    pub fn disabled(self) -> &'a mut crate::W<REG> {
225        self.variant(SCAN::Disabled)
226    }
227    ///Scan mode enabled
228    #[inline(always)]
229    pub fn enabled(self) -> &'a mut crate::W<REG> {
230        self.variant(SCAN::Enabled)
231    }
232}
233/**Enable the watchdog on a single channel in scan mode
234
235Value on reset: 0*/
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237#[derive(Clone, Copy, Debug, PartialEq, Eq)]
238pub enum AWDSGL {
239    ///0: Analog watchdog enabled on all channels
240    All = 0,
241    ///1: Analog watchdog enabled on a single channel
242    Single = 1,
243}
244impl From<AWDSGL> for bool {
245    #[inline(always)]
246    fn from(variant: AWDSGL) -> Self {
247        variant as u8 != 0
248    }
249}
250///Field `AWDSGL` reader - Enable the watchdog on a single channel in scan mode
251pub type AWDSGL_R = crate::BitReader<AWDSGL>;
252impl AWDSGL_R {
253    ///Get enumerated values variant
254    #[inline(always)]
255    pub const fn variant(&self) -> AWDSGL {
256        match self.bits {
257            false => AWDSGL::All,
258            true => AWDSGL::Single,
259        }
260    }
261    ///Analog watchdog enabled on all channels
262    #[inline(always)]
263    pub fn is_all(&self) -> bool {
264        *self == AWDSGL::All
265    }
266    ///Analog watchdog enabled on a single channel
267    #[inline(always)]
268    pub fn is_single(&self) -> bool {
269        *self == AWDSGL::Single
270    }
271}
272///Field `AWDSGL` writer - Enable the watchdog on a single channel in scan mode
273pub type AWDSGL_W<'a, REG> = crate::BitWriter<'a, REG, AWDSGL>;
274impl<'a, REG> AWDSGL_W<'a, REG>
275where
276    REG: crate::Writable + crate::RegisterSpec,
277{
278    ///Analog watchdog enabled on all channels
279    #[inline(always)]
280    pub fn all(self) -> &'a mut crate::W<REG> {
281        self.variant(AWDSGL::All)
282    }
283    ///Analog watchdog enabled on a single channel
284    #[inline(always)]
285    pub fn single(self) -> &'a mut crate::W<REG> {
286        self.variant(AWDSGL::Single)
287    }
288}
289/**Automatic injected group conversion
290
291Value on reset: 0*/
292#[cfg_attr(feature = "defmt", derive(defmt::Format))]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum JAUTO {
295    ///0: Automatic injected group conversion disabled
296    Disabled = 0,
297    ///1: Automatic injected group conversion enabled
298    Enabled = 1,
299}
300impl From<JAUTO> for bool {
301    #[inline(always)]
302    fn from(variant: JAUTO) -> Self {
303        variant as u8 != 0
304    }
305}
306///Field `JAUTO` reader - Automatic injected group conversion
307pub type JAUTO_R = crate::BitReader<JAUTO>;
308impl JAUTO_R {
309    ///Get enumerated values variant
310    #[inline(always)]
311    pub const fn variant(&self) -> JAUTO {
312        match self.bits {
313            false => JAUTO::Disabled,
314            true => JAUTO::Enabled,
315        }
316    }
317    ///Automatic injected group conversion disabled
318    #[inline(always)]
319    pub fn is_disabled(&self) -> bool {
320        *self == JAUTO::Disabled
321    }
322    ///Automatic injected group conversion enabled
323    #[inline(always)]
324    pub fn is_enabled(&self) -> bool {
325        *self == JAUTO::Enabled
326    }
327}
328///Field `JAUTO` writer - Automatic injected group conversion
329pub type JAUTO_W<'a, REG> = crate::BitWriter<'a, REG, JAUTO>;
330impl<'a, REG> JAUTO_W<'a, REG>
331where
332    REG: crate::Writable + crate::RegisterSpec,
333{
334    ///Automatic injected group conversion disabled
335    #[inline(always)]
336    pub fn disabled(self) -> &'a mut crate::W<REG> {
337        self.variant(JAUTO::Disabled)
338    }
339    ///Automatic injected group conversion enabled
340    #[inline(always)]
341    pub fn enabled(self) -> &'a mut crate::W<REG> {
342        self.variant(JAUTO::Enabled)
343    }
344}
345/**Discontinuous mode on regular channels
346
347Value on reset: 0*/
348#[cfg_attr(feature = "defmt", derive(defmt::Format))]
349#[derive(Clone, Copy, Debug, PartialEq, Eq)]
350pub enum DISCEN {
351    ///0: Discontinuous mode on regular channels disabled
352    Disabled = 0,
353    ///1: Discontinuous mode on regular channels enabled
354    Enabled = 1,
355}
356impl From<DISCEN> for bool {
357    #[inline(always)]
358    fn from(variant: DISCEN) -> Self {
359        variant as u8 != 0
360    }
361}
362///Field `DISCEN` reader - Discontinuous mode on regular channels
363pub type DISCEN_R = crate::BitReader<DISCEN>;
364impl DISCEN_R {
365    ///Get enumerated values variant
366    #[inline(always)]
367    pub const fn variant(&self) -> DISCEN {
368        match self.bits {
369            false => DISCEN::Disabled,
370            true => DISCEN::Enabled,
371        }
372    }
373    ///Discontinuous mode on regular channels disabled
374    #[inline(always)]
375    pub fn is_disabled(&self) -> bool {
376        *self == DISCEN::Disabled
377    }
378    ///Discontinuous mode on regular channels enabled
379    #[inline(always)]
380    pub fn is_enabled(&self) -> bool {
381        *self == DISCEN::Enabled
382    }
383}
384///Field `DISCEN` writer - Discontinuous mode on regular channels
385pub type DISCEN_W<'a, REG> = crate::BitWriter<'a, REG, DISCEN>;
386impl<'a, REG> DISCEN_W<'a, REG>
387where
388    REG: crate::Writable + crate::RegisterSpec,
389{
390    ///Discontinuous mode on regular channels disabled
391    #[inline(always)]
392    pub fn disabled(self) -> &'a mut crate::W<REG> {
393        self.variant(DISCEN::Disabled)
394    }
395    ///Discontinuous mode on regular channels enabled
396    #[inline(always)]
397    pub fn enabled(self) -> &'a mut crate::W<REG> {
398        self.variant(DISCEN::Enabled)
399    }
400}
401/**Discontinuous mode on injected channels
402
403Value on reset: 0*/
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406pub enum JDISCEN {
407    ///0: Discontinuous mode on injected channels disabled
408    Disabled = 0,
409    ///1: Discontinuous mode on injected channels enabled
410    Enabled = 1,
411}
412impl From<JDISCEN> for bool {
413    #[inline(always)]
414    fn from(variant: JDISCEN) -> Self {
415        variant as u8 != 0
416    }
417}
418///Field `JDISCEN` reader - Discontinuous mode on injected channels
419pub type JDISCEN_R = crate::BitReader<JDISCEN>;
420impl JDISCEN_R {
421    ///Get enumerated values variant
422    #[inline(always)]
423    pub const fn variant(&self) -> JDISCEN {
424        match self.bits {
425            false => JDISCEN::Disabled,
426            true => JDISCEN::Enabled,
427        }
428    }
429    ///Discontinuous mode on injected channels disabled
430    #[inline(always)]
431    pub fn is_disabled(&self) -> bool {
432        *self == JDISCEN::Disabled
433    }
434    ///Discontinuous mode on injected channels enabled
435    #[inline(always)]
436    pub fn is_enabled(&self) -> bool {
437        *self == JDISCEN::Enabled
438    }
439}
440///Field `JDISCEN` writer - Discontinuous mode on injected channels
441pub type JDISCEN_W<'a, REG> = crate::BitWriter<'a, REG, JDISCEN>;
442impl<'a, REG> JDISCEN_W<'a, REG>
443where
444    REG: crate::Writable + crate::RegisterSpec,
445{
446    ///Discontinuous mode on injected channels disabled
447    #[inline(always)]
448    pub fn disabled(self) -> &'a mut crate::W<REG> {
449        self.variant(JDISCEN::Disabled)
450    }
451    ///Discontinuous mode on injected channels enabled
452    #[inline(always)]
453    pub fn enabled(self) -> &'a mut crate::W<REG> {
454        self.variant(JDISCEN::Enabled)
455    }
456}
457///Field `DISCNUM` reader - Discontinuous mode channel count
458pub type DISCNUM_R = crate::FieldReader;
459///Field `DISCNUM` writer - Discontinuous mode channel count
460pub type DISCNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, u8, crate::Safe>;
461/**Dual mode selection
462
463Value on reset: 0*/
464#[cfg_attr(feature = "defmt", derive(defmt::Format))]
465#[derive(Clone, Copy, Debug, PartialEq, Eq)]
466#[repr(u8)]
467pub enum DUALMOD {
468    ///0: Independent mode
469    Independent = 0,
470    ///1: Combined regular simultaneous + injected simultaneous mode
471    RegularInjected = 1,
472    ///2: Combined regular simultaneous + alternate trigger mode
473    RegularAlternateTrigger = 2,
474    ///3: Combined injected simultaneous + fast interleaved mode
475    InjectedFastInterleaved = 3,
476    ///4: Combined injected simultaneous + slow interleaved mode
477    InjectedSlowInterleaved = 4,
478    ///5: Injected simultaneous mode only
479    Injected = 5,
480    ///6: Regular simultaneous mode only
481    Regular = 6,
482    ///7: Fast interleaved mode only
483    FastInterleaved = 7,
484    ///8: Slow interleaved mode only
485    SlowInterleaved = 8,
486    ///9: Alternate trigger mode only
487    AlternateTrigger = 9,
488}
489impl From<DUALMOD> for u8 {
490    #[inline(always)]
491    fn from(variant: DUALMOD) -> Self {
492        variant as _
493    }
494}
495impl crate::FieldSpec for DUALMOD {
496    type Ux = u8;
497}
498impl crate::IsEnum for DUALMOD {}
499///Field `DUALMOD` reader - Dual mode selection
500pub type DUALMOD_R = crate::FieldReader<DUALMOD>;
501impl DUALMOD_R {
502    ///Get enumerated values variant
503    #[inline(always)]
504    pub const fn variant(&self) -> Option<DUALMOD> {
505        match self.bits {
506            0 => Some(DUALMOD::Independent),
507            1 => Some(DUALMOD::RegularInjected),
508            2 => Some(DUALMOD::RegularAlternateTrigger),
509            3 => Some(DUALMOD::InjectedFastInterleaved),
510            4 => Some(DUALMOD::InjectedSlowInterleaved),
511            5 => Some(DUALMOD::Injected),
512            6 => Some(DUALMOD::Regular),
513            7 => Some(DUALMOD::FastInterleaved),
514            8 => Some(DUALMOD::SlowInterleaved),
515            9 => Some(DUALMOD::AlternateTrigger),
516            _ => None,
517        }
518    }
519    ///Independent mode
520    #[inline(always)]
521    pub fn is_independent(&self) -> bool {
522        *self == DUALMOD::Independent
523    }
524    ///Combined regular simultaneous + injected simultaneous mode
525    #[inline(always)]
526    pub fn is_regular_injected(&self) -> bool {
527        *self == DUALMOD::RegularInjected
528    }
529    ///Combined regular simultaneous + alternate trigger mode
530    #[inline(always)]
531    pub fn is_regular_alternate_trigger(&self) -> bool {
532        *self == DUALMOD::RegularAlternateTrigger
533    }
534    ///Combined injected simultaneous + fast interleaved mode
535    #[inline(always)]
536    pub fn is_injected_fast_interleaved(&self) -> bool {
537        *self == DUALMOD::InjectedFastInterleaved
538    }
539    ///Combined injected simultaneous + slow interleaved mode
540    #[inline(always)]
541    pub fn is_injected_slow_interleaved(&self) -> bool {
542        *self == DUALMOD::InjectedSlowInterleaved
543    }
544    ///Injected simultaneous mode only
545    #[inline(always)]
546    pub fn is_injected(&self) -> bool {
547        *self == DUALMOD::Injected
548    }
549    ///Regular simultaneous mode only
550    #[inline(always)]
551    pub fn is_regular(&self) -> bool {
552        *self == DUALMOD::Regular
553    }
554    ///Fast interleaved mode only
555    #[inline(always)]
556    pub fn is_fast_interleaved(&self) -> bool {
557        *self == DUALMOD::FastInterleaved
558    }
559    ///Slow interleaved mode only
560    #[inline(always)]
561    pub fn is_slow_interleaved(&self) -> bool {
562        *self == DUALMOD::SlowInterleaved
563    }
564    ///Alternate trigger mode only
565    #[inline(always)]
566    pub fn is_alternate_trigger(&self) -> bool {
567        *self == DUALMOD::AlternateTrigger
568    }
569}
570///Field `DUALMOD` writer - Dual mode selection
571pub type DUALMOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4, DUALMOD>;
572impl<'a, REG> DUALMOD_W<'a, REG>
573where
574    REG: crate::Writable + crate::RegisterSpec,
575    REG::Ux: From<u8>,
576{
577    ///Independent mode
578    #[inline(always)]
579    pub fn independent(self) -> &'a mut crate::W<REG> {
580        self.variant(DUALMOD::Independent)
581    }
582    ///Combined regular simultaneous + injected simultaneous mode
583    #[inline(always)]
584    pub fn regular_injected(self) -> &'a mut crate::W<REG> {
585        self.variant(DUALMOD::RegularInjected)
586    }
587    ///Combined regular simultaneous + alternate trigger mode
588    #[inline(always)]
589    pub fn regular_alternate_trigger(self) -> &'a mut crate::W<REG> {
590        self.variant(DUALMOD::RegularAlternateTrigger)
591    }
592    ///Combined injected simultaneous + fast interleaved mode
593    #[inline(always)]
594    pub fn injected_fast_interleaved(self) -> &'a mut crate::W<REG> {
595        self.variant(DUALMOD::InjectedFastInterleaved)
596    }
597    ///Combined injected simultaneous + slow interleaved mode
598    #[inline(always)]
599    pub fn injected_slow_interleaved(self) -> &'a mut crate::W<REG> {
600        self.variant(DUALMOD::InjectedSlowInterleaved)
601    }
602    ///Injected simultaneous mode only
603    #[inline(always)]
604    pub fn injected(self) -> &'a mut crate::W<REG> {
605        self.variant(DUALMOD::Injected)
606    }
607    ///Regular simultaneous mode only
608    #[inline(always)]
609    pub fn regular(self) -> &'a mut crate::W<REG> {
610        self.variant(DUALMOD::Regular)
611    }
612    ///Fast interleaved mode only
613    #[inline(always)]
614    pub fn fast_interleaved(self) -> &'a mut crate::W<REG> {
615        self.variant(DUALMOD::FastInterleaved)
616    }
617    ///Slow interleaved mode only
618    #[inline(always)]
619    pub fn slow_interleaved(self) -> &'a mut crate::W<REG> {
620        self.variant(DUALMOD::SlowInterleaved)
621    }
622    ///Alternate trigger mode only
623    #[inline(always)]
624    pub fn alternate_trigger(self) -> &'a mut crate::W<REG> {
625        self.variant(DUALMOD::AlternateTrigger)
626    }
627}
628/**Analog watchdog enable on injected channels
629
630Value on reset: 0*/
631#[cfg_attr(feature = "defmt", derive(defmt::Format))]
632#[derive(Clone, Copy, Debug, PartialEq, Eq)]
633pub enum JAWDEN {
634    ///0: Analog watchdog disabled on injected channels
635    Disabled = 0,
636    ///1: Analog watchdog enabled on injected channels
637    Enabled = 1,
638}
639impl From<JAWDEN> for bool {
640    #[inline(always)]
641    fn from(variant: JAWDEN) -> Self {
642        variant as u8 != 0
643    }
644}
645///Field `JAWDEN` reader - Analog watchdog enable on injected channels
646pub type JAWDEN_R = crate::BitReader<JAWDEN>;
647impl JAWDEN_R {
648    ///Get enumerated values variant
649    #[inline(always)]
650    pub const fn variant(&self) -> JAWDEN {
651        match self.bits {
652            false => JAWDEN::Disabled,
653            true => JAWDEN::Enabled,
654        }
655    }
656    ///Analog watchdog disabled on injected channels
657    #[inline(always)]
658    pub fn is_disabled(&self) -> bool {
659        *self == JAWDEN::Disabled
660    }
661    ///Analog watchdog enabled on injected channels
662    #[inline(always)]
663    pub fn is_enabled(&self) -> bool {
664        *self == JAWDEN::Enabled
665    }
666}
667///Field `JAWDEN` writer - Analog watchdog enable on injected channels
668pub type JAWDEN_W<'a, REG> = crate::BitWriter<'a, REG, JAWDEN>;
669impl<'a, REG> JAWDEN_W<'a, REG>
670where
671    REG: crate::Writable + crate::RegisterSpec,
672{
673    ///Analog watchdog disabled on injected channels
674    #[inline(always)]
675    pub fn disabled(self) -> &'a mut crate::W<REG> {
676        self.variant(JAWDEN::Disabled)
677    }
678    ///Analog watchdog enabled on injected channels
679    #[inline(always)]
680    pub fn enabled(self) -> &'a mut crate::W<REG> {
681        self.variant(JAWDEN::Enabled)
682    }
683}
684/**Analog watchdog enable on regular channels
685
686Value on reset: 0*/
687#[cfg_attr(feature = "defmt", derive(defmt::Format))]
688#[derive(Clone, Copy, Debug, PartialEq, Eq)]
689pub enum AWDEN {
690    ///0: Analog watchdog disabled on regular channels
691    Disabled = 0,
692    ///1: Analog watchdog enabled on regular channels
693    Enabled = 1,
694}
695impl From<AWDEN> for bool {
696    #[inline(always)]
697    fn from(variant: AWDEN) -> Self {
698        variant as u8 != 0
699    }
700}
701///Field `AWDEN` reader - Analog watchdog enable on regular channels
702pub type AWDEN_R = crate::BitReader<AWDEN>;
703impl AWDEN_R {
704    ///Get enumerated values variant
705    #[inline(always)]
706    pub const fn variant(&self) -> AWDEN {
707        match self.bits {
708            false => AWDEN::Disabled,
709            true => AWDEN::Enabled,
710        }
711    }
712    ///Analog watchdog disabled on regular channels
713    #[inline(always)]
714    pub fn is_disabled(&self) -> bool {
715        *self == AWDEN::Disabled
716    }
717    ///Analog watchdog enabled on regular channels
718    #[inline(always)]
719    pub fn is_enabled(&self) -> bool {
720        *self == AWDEN::Enabled
721    }
722}
723///Field `AWDEN` writer - Analog watchdog enable on regular channels
724pub type AWDEN_W<'a, REG> = crate::BitWriter<'a, REG, AWDEN>;
725impl<'a, REG> AWDEN_W<'a, REG>
726where
727    REG: crate::Writable + crate::RegisterSpec,
728{
729    ///Analog watchdog disabled on regular channels
730    #[inline(always)]
731    pub fn disabled(self) -> &'a mut crate::W<REG> {
732        self.variant(AWDEN::Disabled)
733    }
734    ///Analog watchdog enabled on regular channels
735    #[inline(always)]
736    pub fn enabled(self) -> &'a mut crate::W<REG> {
737        self.variant(AWDEN::Enabled)
738    }
739}
740impl R {
741    ///Bits 0:4 - Analog watchdog channel select bits
742    #[inline(always)]
743    pub fn awdch(&self) -> AWDCH_R {
744        AWDCH_R::new((self.bits & 0x1f) as u8)
745    }
746    ///Bit 5 - Interrupt enable for EOC
747    #[inline(always)]
748    pub fn eocie(&self) -> EOCIE_R {
749        EOCIE_R::new(((self.bits >> 5) & 1) != 0)
750    }
751    ///Bit 6 - Analog watchdog interrupt enable
752    #[inline(always)]
753    pub fn awdie(&self) -> AWDIE_R {
754        AWDIE_R::new(((self.bits >> 6) & 1) != 0)
755    }
756    ///Bit 7 - Interrupt enable for injected channels
757    #[inline(always)]
758    pub fn jeocie(&self) -> JEOCIE_R {
759        JEOCIE_R::new(((self.bits >> 7) & 1) != 0)
760    }
761    ///Bit 8 - Scan mode
762    #[inline(always)]
763    pub fn scan(&self) -> SCAN_R {
764        SCAN_R::new(((self.bits >> 8) & 1) != 0)
765    }
766    ///Bit 9 - Enable the watchdog on a single channel in scan mode
767    #[inline(always)]
768    pub fn awdsgl(&self) -> AWDSGL_R {
769        AWDSGL_R::new(((self.bits >> 9) & 1) != 0)
770    }
771    ///Bit 10 - Automatic injected group conversion
772    #[inline(always)]
773    pub fn jauto(&self) -> JAUTO_R {
774        JAUTO_R::new(((self.bits >> 10) & 1) != 0)
775    }
776    ///Bit 11 - Discontinuous mode on regular channels
777    #[inline(always)]
778    pub fn discen(&self) -> DISCEN_R {
779        DISCEN_R::new(((self.bits >> 11) & 1) != 0)
780    }
781    ///Bit 12 - Discontinuous mode on injected channels
782    #[inline(always)]
783    pub fn jdiscen(&self) -> JDISCEN_R {
784        JDISCEN_R::new(((self.bits >> 12) & 1) != 0)
785    }
786    ///Bits 13:15 - Discontinuous mode channel count
787    #[inline(always)]
788    pub fn discnum(&self) -> DISCNUM_R {
789        DISCNUM_R::new(((self.bits >> 13) & 7) as u8)
790    }
791    ///Bits 16:19 - Dual mode selection
792    #[inline(always)]
793    pub fn dualmod(&self) -> DUALMOD_R {
794        DUALMOD_R::new(((self.bits >> 16) & 0x0f) as u8)
795    }
796    ///Bit 22 - Analog watchdog enable on injected channels
797    #[inline(always)]
798    pub fn jawden(&self) -> JAWDEN_R {
799        JAWDEN_R::new(((self.bits >> 22) & 1) != 0)
800    }
801    ///Bit 23 - Analog watchdog enable on regular channels
802    #[inline(always)]
803    pub fn awden(&self) -> AWDEN_R {
804        AWDEN_R::new(((self.bits >> 23) & 1) != 0)
805    }
806}
807impl core::fmt::Debug for R {
808    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
809        f.debug_struct("CR1")
810            .field("awden", &self.awden())
811            .field("jawden", &self.jawden())
812            .field("dualmod", &self.dualmod())
813            .field("discnum", &self.discnum())
814            .field("jdiscen", &self.jdiscen())
815            .field("discen", &self.discen())
816            .field("jauto", &self.jauto())
817            .field("awdsgl", &self.awdsgl())
818            .field("scan", &self.scan())
819            .field("jeocie", &self.jeocie())
820            .field("awdie", &self.awdie())
821            .field("eocie", &self.eocie())
822            .field("awdch", &self.awdch())
823            .finish()
824    }
825}
826impl W {
827    ///Bits 0:4 - Analog watchdog channel select bits
828    #[inline(always)]
829    pub fn awdch(&mut self) -> AWDCH_W<CR1rs> {
830        AWDCH_W::new(self, 0)
831    }
832    ///Bit 5 - Interrupt enable for EOC
833    #[inline(always)]
834    pub fn eocie(&mut self) -> EOCIE_W<CR1rs> {
835        EOCIE_W::new(self, 5)
836    }
837    ///Bit 6 - Analog watchdog interrupt enable
838    #[inline(always)]
839    pub fn awdie(&mut self) -> AWDIE_W<CR1rs> {
840        AWDIE_W::new(self, 6)
841    }
842    ///Bit 7 - Interrupt enable for injected channels
843    #[inline(always)]
844    pub fn jeocie(&mut self) -> JEOCIE_W<CR1rs> {
845        JEOCIE_W::new(self, 7)
846    }
847    ///Bit 8 - Scan mode
848    #[inline(always)]
849    pub fn scan(&mut self) -> SCAN_W<CR1rs> {
850        SCAN_W::new(self, 8)
851    }
852    ///Bit 9 - Enable the watchdog on a single channel in scan mode
853    #[inline(always)]
854    pub fn awdsgl(&mut self) -> AWDSGL_W<CR1rs> {
855        AWDSGL_W::new(self, 9)
856    }
857    ///Bit 10 - Automatic injected group conversion
858    #[inline(always)]
859    pub fn jauto(&mut self) -> JAUTO_W<CR1rs> {
860        JAUTO_W::new(self, 10)
861    }
862    ///Bit 11 - Discontinuous mode on regular channels
863    #[inline(always)]
864    pub fn discen(&mut self) -> DISCEN_W<CR1rs> {
865        DISCEN_W::new(self, 11)
866    }
867    ///Bit 12 - Discontinuous mode on injected channels
868    #[inline(always)]
869    pub fn jdiscen(&mut self) -> JDISCEN_W<CR1rs> {
870        JDISCEN_W::new(self, 12)
871    }
872    ///Bits 13:15 - Discontinuous mode channel count
873    #[inline(always)]
874    pub fn discnum(&mut self) -> DISCNUM_W<CR1rs> {
875        DISCNUM_W::new(self, 13)
876    }
877    ///Bits 16:19 - Dual mode selection
878    #[inline(always)]
879    pub fn dualmod(&mut self) -> DUALMOD_W<CR1rs> {
880        DUALMOD_W::new(self, 16)
881    }
882    ///Bit 22 - Analog watchdog enable on injected channels
883    #[inline(always)]
884    pub fn jawden(&mut self) -> JAWDEN_W<CR1rs> {
885        JAWDEN_W::new(self, 22)
886    }
887    ///Bit 23 - Analog watchdog enable on regular channels
888    #[inline(always)]
889    pub fn awden(&mut self) -> AWDEN_W<CR1rs> {
890        AWDEN_W::new(self, 23)
891    }
892}
893/**control register 1
894
895You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
896
897See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#ADC1:CR1)*/
898pub struct CR1rs;
899impl crate::RegisterSpec for CR1rs {
900    type Ux = u32;
901}
902///`read()` method returns [`cr1::R`](R) reader structure
903impl crate::Readable for CR1rs {}
904///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
905impl crate::Writable for CR1rs {
906    type Safety = crate::Unsafe;
907}
908///`reset()` method sets CR1 to value 0
909impl crate::Resettable for CR1rs {}
stm32f1_staging/stm32f103/adc1/cr1.rs

stm32f1_staging/stm32f103/adc1/
cr1.rs
