Enum stm32f0xx_hal::stm32::tim1::cr1::URSW

source · 
pub enum URSW {
    ANYEVENT,
    COUNTERONLY,
}
Expand description

Values that can be written to the field URS

Variants§

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ANYEVENT

Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request

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COUNTERONLY

Only counter overflow/underflow generates an update interrupt or DMA request

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