stm32f0/stm32f0x8/tsc/
ier.rs

1///Register `IER` reader
2pub type R = crate::R<IERrs>;
3///Register `IER` writer
4pub type W = crate::W<IERrs>;
5/**End of acquisition interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EOAIE {
11    ///0: End of acquisition interrupt disabled
12    Disabled = 0,
13    ///1: End of acquisition interrupt enabled
14    Enabled = 1,
15}
16impl From<EOAIE> for bool {
17    #[inline(always)]
18    fn from(variant: EOAIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EOAIE` reader - End of acquisition interrupt enable
23pub type EOAIE_R = crate::BitReader<EOAIE>;
24impl EOAIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EOAIE {
28        match self.bits {
29            false => EOAIE::Disabled,
30            true => EOAIE::Enabled,
31        }
32    }
33    ///End of acquisition interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EOAIE::Disabled
37    }
38    ///End of acquisition interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EOAIE::Enabled
42    }
43}
44///Field `EOAIE` writer - End of acquisition interrupt enable
45pub type EOAIE_W<'a, REG> = crate::BitWriter<'a, REG, EOAIE>;
46impl<'a, REG> EOAIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///End of acquisition interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EOAIE::Disabled)
54    }
55    ///End of acquisition interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EOAIE::Enabled)
59    }
60}
61/**Max count error interrupt enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum MCEIE {
67    ///0: Max count error interrupt disabled
68    Disabled = 0,
69    ///1: Max count error interrupt enabled
70    Enabled = 1,
71}
72impl From<MCEIE> for bool {
73    #[inline(always)]
74    fn from(variant: MCEIE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `MCEIE` reader - Max count error interrupt enable
79pub type MCEIE_R = crate::BitReader<MCEIE>;
80impl MCEIE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> MCEIE {
84        match self.bits {
85            false => MCEIE::Disabled,
86            true => MCEIE::Enabled,
87        }
88    }
89    ///Max count error interrupt disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == MCEIE::Disabled
93    }
94    ///Max count error interrupt enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == MCEIE::Enabled
98    }
99}
100///Field `MCEIE` writer - Max count error interrupt enable
101pub type MCEIE_W<'a, REG> = crate::BitWriter<'a, REG, MCEIE>;
102impl<'a, REG> MCEIE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Max count error interrupt disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(MCEIE::Disabled)
110    }
111    ///Max count error interrupt enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(MCEIE::Enabled)
115    }
116}
117impl R {
118    ///Bit 0 - End of acquisition interrupt enable
119    #[inline(always)]
120    pub fn eoaie(&self) -> EOAIE_R {
121        EOAIE_R::new((self.bits & 1) != 0)
122    }
123    ///Bit 1 - Max count error interrupt enable
124    #[inline(always)]
125    pub fn mceie(&self) -> MCEIE_R {
126        MCEIE_R::new(((self.bits >> 1) & 1) != 0)
127    }
128}
129impl core::fmt::Debug for R {
130    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
131        f.debug_struct("IER")
132            .field("mceie", &self.mceie())
133            .field("eoaie", &self.eoaie())
134            .finish()
135    }
136}
137impl W {
138    ///Bit 0 - End of acquisition interrupt enable
139    #[inline(always)]
140    pub fn eoaie(&mut self) -> EOAIE_W<IERrs> {
141        EOAIE_W::new(self, 0)
142    }
143    ///Bit 1 - Max count error interrupt enable
144    #[inline(always)]
145    pub fn mceie(&mut self) -> MCEIE_W<IERrs> {
146        MCEIE_W::new(self, 1)
147    }
148}
149/**interrupt enable register
150
151You can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
152
153See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x8.html#TSC:IER)*/
154pub struct IERrs;
155impl crate::RegisterSpec for IERrs {
156    type Ux = u32;
157}
158///`read()` method returns [`ier::R`](R) reader structure
159impl crate::Readable for IERrs {}
160///`write(|w| ..)` method takes [`ier::W`](W) writer structure
161impl crate::Writable for IERrs {
162    type Safety = crate::Unsafe;
163}
164///`reset()` method sets IER to value 0
165impl crate::Resettable for IERrs {}
stm32f0/stm32f0x8/tsc/ier.rs

stm32f0/stm32f0x8/tsc/
ier.rs
