#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::CFGR3 {
    #[doc = r" Modifies the contents of the register"]
    #[inline]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        let r = R { bits: bits };
        let mut w = W { bits: bits };
        f(&r, &mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r" Writes to the register"]
    #[inline]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        let mut w = W::reset_value();
        f(&mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Writes the reset value to the register"]
    #[inline]
    pub fn reset(&self) {
        self.write(|w| w)
    }
}
#[doc = "Possible values of the field `USART1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART1SWR {
    #[doc = "PCLK selected as USART clock source"]
    PCLK,
    #[doc = "SYSCLK selected as USART clock source"]
    SYSCLK,
    #[doc = "LSE selected as USART clock source"]
    LSE,
    #[doc = "HSI selected as USART clock source"]
    HSI,
}
impl USART1SWR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        match *self {
            USART1SWR::PCLK => 0,
            USART1SWR::SYSCLK => 1,
            USART1SWR::LSE => 2,
            USART1SWR::HSI => 3,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: u8) -> USART1SWR {
        match value {
            0 => USART1SWR::PCLK,
            1 => USART1SWR::SYSCLK,
            2 => USART1SWR::LSE,
            3 => USART1SWR::HSI,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `PCLK`"]
    #[inline]
    pub fn is_pclk(&self) -> bool {
        *self == USART1SWR::PCLK
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline]
    pub fn is_sysclk(&self) -> bool {
        *self == USART1SWR::SYSCLK
    }
    #[doc = "Checks if the value of the field is `LSE`"]
    #[inline]
    pub fn is_lse(&self) -> bool {
        *self == USART1SWR::LSE
    }
    #[doc = "Checks if the value of the field is `HSI`"]
    #[inline]
    pub fn is_hsi(&self) -> bool {
        *self == USART1SWR::HSI
    }
}
#[doc = "Possible values of the field `I2C1SW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C1SWR {
    #[doc = "HSI clock selected as I2C1 clock source"]
    HSI,
    #[doc = "SYSCLK clock selected as I2C1 clock source"]
    SYSCLK,
}
impl I2C1SWR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            I2C1SWR::HSI => false,
            I2C1SWR::SYSCLK => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> I2C1SWR {
        match value {
            false => I2C1SWR::HSI,
            true => I2C1SWR::SYSCLK,
        }
    }
    #[doc = "Checks if the value of the field is `HSI`"]
    #[inline]
    pub fn is_hsi(&self) -> bool {
        *self == I2C1SWR::HSI
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline]
    pub fn is_sysclk(&self) -> bool {
        *self == I2C1SWR::SYSCLK
    }
}
#[doc = "Possible values of the field `CECSW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CECSWR {
    #[doc = "HSI clock divided by 244 selected as CEC clock source"]
    HSI_DIV244,
    #[doc = "LSE clock selected as CEC clock source"]
    LSE,
}
impl CECSWR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            CECSWR::HSI_DIV244 => false,
            CECSWR::LSE => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> CECSWR {
        match value {
            false => CECSWR::HSI_DIV244,
            true => CECSWR::LSE,
        }
    }
    #[doc = "Checks if the value of the field is `HSI_DIV244`"]
    #[inline]
    pub fn is_hsi_div244(&self) -> bool {
        *self == CECSWR::HSI_DIV244
    }
    #[doc = "Checks if the value of the field is `LSE`"]
    #[inline]
    pub fn is_lse(&self) -> bool {
        *self == CECSWR::LSE
    }
}
#[doc = "Possible values of the field `USBSW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USBSWR {
    #[doc = "HSI48 selected as USB clock source"]
    HSI48,
    #[doc = "PLL clock selected as USB clock source"]
    PLLCLK,
}
impl USBSWR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            USBSWR::HSI48 => false,
            USBSWR::PLLCLK => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> USBSWR {
        match value {
            false => USBSWR::HSI48,
            true => USBSWR::PLLCLK,
        }
    }
    #[doc = "Checks if the value of the field is `HSI48`"]
    #[inline]
    pub fn is_hsi48(&self) -> bool {
        *self == USBSWR::HSI48
    }
    #[doc = "Checks if the value of the field is `PLLCLK`"]
    #[inline]
    pub fn is_pllclk(&self) -> bool {
        *self == USBSWR::PLLCLK
    }
}
#[doc = r" Value of the field"]
pub struct ADCSWR {
    bits: bool,
}
impl ADCSWR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        self.bits
    }
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
}
#[doc = "Possible values of the field `USART2SW`"]
pub type USART2SWR = USART1SWR;
#[doc = "Possible values of the field `USART3SW`"]
pub type USART3SWR = USART1SWR;
#[doc = "Values that can be written to the field `USART1SW`"]
pub enum USART1SWW {
    #[doc = "PCLK selected as USART clock source"]
    PCLK,
    #[doc = "SYSCLK selected as USART clock source"]
    SYSCLK,
    #[doc = "LSE selected as USART clock source"]
    LSE,
    #[doc = "HSI selected as USART clock source"]
    HSI,
}
impl USART1SWW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> u8 {
        match *self {
            USART1SWW::PCLK => 0,
            USART1SWW::SYSCLK => 1,
            USART1SWW::LSE => 2,
            USART1SWW::HSI => 3,
        }
    }
}
#[doc = r" Proxy"]
pub struct _USART1SWW<'a> {
    w: &'a mut W,
}
impl<'a> _USART1SWW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USART1SWW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "PCLK selected as USART clock source"]
    #[inline]
    pub fn pclk(self) -> &'a mut W {
        self.variant(USART1SWW::PCLK)
    }
    #[doc = "SYSCLK selected as USART clock source"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART1SWW::SYSCLK)
    }
    #[doc = "LSE selected as USART clock source"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART1SWW::LSE)
    }
    #[doc = "HSI selected as USART clock source"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART1SWW::HSI)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 0;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `I2C1SW`"]
pub enum I2C1SWW {
    #[doc = "HSI clock selected as I2C1 clock source"]
    HSI,
    #[doc = "SYSCLK clock selected as I2C1 clock source"]
    SYSCLK,
}
impl I2C1SWW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            I2C1SWW::HSI => false,
            I2C1SWW::SYSCLK => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _I2C1SWW<'a> {
    w: &'a mut W,
}
impl<'a> _I2C1SWW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: I2C1SWW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "HSI clock selected as I2C1 clock source"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(I2C1SWW::HSI)
    }
    #[doc = "SYSCLK clock selected as I2C1 clock source"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(I2C1SWW::SYSCLK)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 4;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `CECSW`"]
pub enum CECSWW {
    #[doc = "HSI clock divided by 244 selected as CEC clock source"]
    HSI_DIV244,
    #[doc = "LSE clock selected as CEC clock source"]
    LSE,
}
impl CECSWW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            CECSWW::HSI_DIV244 => false,
            CECSWW::LSE => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _CECSWW<'a> {
    w: &'a mut W,
}
impl<'a> _CECSWW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: CECSWW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "HSI clock divided by 244 selected as CEC clock source"]
    #[inline]
    pub fn hsi_div244(self) -> &'a mut W {
        self.variant(CECSWW::HSI_DIV244)
    }
    #[doc = "LSE clock selected as CEC clock source"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(CECSWW::LSE)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 6;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `USBSW`"]
pub enum USBSWW {
    #[doc = "HSI48 selected as USB clock source"]
    HSI48,
    #[doc = "PLL clock selected as USB clock source"]
    PLLCLK,
}
impl USBSWW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            USBSWW::HSI48 => false,
            USBSWW::PLLCLK => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _USBSWW<'a> {
    w: &'a mut W,
}
impl<'a> _USBSWW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USBSWW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "HSI48 selected as USB clock source"]
    #[inline]
    pub fn hsi48(self) -> &'a mut W {
        self.variant(USBSWW::HSI48)
    }
    #[doc = "PLL clock selected as USB clock source"]
    #[inline]
    pub fn pllclk(self) -> &'a mut W {
        self.variant(USBSWW::PLLCLK)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 7;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = r" Proxy"]
pub struct _ADCSWW<'a> {
    w: &'a mut W,
}
impl<'a> _ADCSWW<'a> {
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 8;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `USART2SW`"]
pub type USART2SWW = USART1SWW;
#[doc = r" Proxy"]
pub struct _USART2SWW<'a> {
    w: &'a mut W,
}
impl<'a> _USART2SWW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USART2SWW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "PCLK selected as USART clock source"]
    #[inline]
    pub fn pclk(self) -> &'a mut W {
        self.variant(USART1SWW::PCLK)
    }
    #[doc = "SYSCLK selected as USART clock source"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART1SWW::SYSCLK)
    }
    #[doc = "LSE selected as USART clock source"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART1SWW::LSE)
    }
    #[doc = "HSI selected as USART clock source"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART1SWW::HSI)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 16;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `USART3SW`"]
pub type USART3SWW = USART1SWW;
#[doc = r" Proxy"]
pub struct _USART3SWW<'a> {
    w: &'a mut W,
}
impl<'a> _USART3SWW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USART3SWW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "PCLK selected as USART clock source"]
    #[inline]
    pub fn pclk(self) -> &'a mut W {
        self.variant(USART1SWW::PCLK)
    }
    #[doc = "SYSCLK selected as USART clock source"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART1SWW::SYSCLK)
    }
    #[doc = "LSE selected as USART clock source"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART1SWW::LSE)
    }
    #[doc = "HSI selected as USART clock source"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART1SWW::HSI)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 18;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 0:1 - USART1 clock source selection"]
    #[inline]
    pub fn usart1sw(&self) -> USART1SWR {
        USART1SWR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bit 4 - I2C1 clock source selection"]
    #[inline]
    pub fn i2c1sw(&self) -> I2C1SWR {
        I2C1SWR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 4;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 6 - HDMI CEC clock source selection"]
    #[inline]
    pub fn cecsw(&self) -> CECSWR {
        CECSWR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 6;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 7 - USB clock source selection"]
    #[inline]
    pub fn usbsw(&self) -> USBSWR {
        USBSWR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 7;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 8 - ADCSW is deprecated. See ADC field in CFGR2 register."]
    #[inline]
    pub fn adcsw(&self) -> ADCSWR {
        let bits = {
            const MASK: bool = true;
            const OFFSET: u8 = 8;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        };
        ADCSWR { bits }
    }
    #[doc = "Bits 16:17 - USART2 clock source selection"]
    #[inline]
    pub fn usart2sw(&self) -> USART2SWR {
        USART2SWR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 16;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 18:19 - USART3 clock source"]
    #[inline]
    pub fn usart3sw(&self) -> USART3SWR {
        USART3SWR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 18;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
}
impl W {
    #[doc = r" Reset value of the register"]
    #[inline]
    pub fn reset_value() -> W {
        W { bits: 0 }
    }
    #[doc = r" Writes raw bits to the register"]
    #[inline]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 0:1 - USART1 clock source selection"]
    #[inline]
    pub fn usart1sw(&mut self) -> _USART1SWW {
        _USART1SWW { w: self }
    }
    #[doc = "Bit 4 - I2C1 clock source selection"]
    #[inline]
    pub fn i2c1sw(&mut self) -> _I2C1SWW {
        _I2C1SWW { w: self }
    }
    #[doc = "Bit 6 - HDMI CEC clock source selection"]
    #[inline]
    pub fn cecsw(&mut self) -> _CECSWW {
        _CECSWW { w: self }
    }
    #[doc = "Bit 7 - USB clock source selection"]
    #[inline]
    pub fn usbsw(&mut self) -> _USBSWW {
        _USBSWW { w: self }
    }
    #[doc = "Bit 8 - ADCSW is deprecated. See ADC field in CFGR2 register."]
    #[inline]
    pub fn adcsw(&mut self) -> _ADCSWW {
        _ADCSWW { w: self }
    }
    #[doc = "Bits 16:17 - USART2 clock source selection"]
    #[inline]
    pub fn usart2sw(&mut self) -> _USART2SWW {
        _USART2SWW { w: self }
    }
    #[doc = "Bits 18:19 - USART3 clock source"]
    #[inline]
    pub fn usart3sw(&mut self) -> _USART3SWW {
        _USART3SWW { w: self }
    }
}