[][src]Type Definition stm32f0::stm32f0x0::adc::cfgr1::W

type W = W<u32, CFGR1>;

Writer for register CFGR1

Implementations

impl W[src]

pub fn awdch(&mut self) -> AWDCH_W<'_>[src]

Bits 26:30 - Analog watchdog channel selection

pub fn awden(&mut self) -> AWDEN_W<'_>[src]

Bit 23 - Analog watchdog enable

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>[src]

Bit 22 - Enable the watchdog on a single channel or on all channels

pub fn discen(&mut self) -> DISCEN_W<'_>[src]

Bit 16 - Discontinuous mode

pub fn autoff(&mut self) -> AUTOFF_W<'_>[src]

Bit 15 - Auto-off mode

pub fn autdly(&mut self) -> AUTDLY_W<'_>[src]

Bit 14 - Auto-delayed conversion mode

pub fn cont(&mut self) -> CONT_W<'_>[src]

Bit 13 - Single / continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>[src]

Bit 12 - Overrun management mode

pub fn exten(&mut self) -> EXTEN_W<'_>[src]

Bits 10:11 - External trigger enable and polarity selection

pub fn extsel(&mut self) -> EXTSEL_W<'_>[src]

Bits 6:8 - External trigger selection

pub fn align(&mut self) -> ALIGN_W<'_>[src]

Bit 5 - Data alignment

pub fn res(&mut self) -> RES_W<'_>[src]

Bits 3:4 - Data resolution

pub fn scandir(&mut self) -> SCANDIR_W<'_>[src]

Bit 2 - Scan sequence direction

pub fn dmacfg(&mut self) -> DMACFG_W<'_>[src]

Bit 1 - Direct memery access configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 0 - Direct memory access enable

pub fn wait(&mut self) -> WAIT_W<'_>[src]

Bit 14 - Wait conversion mode