[−][src]Struct stm32f0::W
Implementations
impl<U, REG> W<U, REG>
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impl W<u32, Reg<u32, _DR>>
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impl W<u32, Reg<u32, _IDR>>
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impl W<u32, Reg<u32, _CR>>
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pub fn reset(&mut self) -> RESET_W<'_>
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Bit 0 - reset bit
pub fn polysize(&mut self) -> POLYSIZE_W<'_>
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Bits 3:4 - Polynomial size
pub fn rev_in(&mut self) -> REV_IN_W<'_>
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Bits 5:6 - Reverse input data
pub fn rev_out(&mut self) -> REV_OUT_W<'_>
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Bit 7 - Reverse output data
impl W<u32, Reg<u32, _INIT>>
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impl W<u8, Reg<u8, _DR8>>
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impl W<u16, Reg<u16, _DR16>>
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impl W<u32, Reg<u32, _MODER>>
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pub fn moder15(&mut self) -> MODER15_W<'_>
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Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
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Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
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Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
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Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
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Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
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Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
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Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
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Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
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Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
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Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
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Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
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Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
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Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
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Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
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Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
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Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
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pub fn ot15(&mut self) -> OT15_W<'_>
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Bit 15 - Port x configuration bit 15
pub fn ot14(&mut self) -> OT14_W<'_>
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Bit 14 - Port x configuration bit 14
pub fn ot13(&mut self) -> OT13_W<'_>
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Bit 13 - Port x configuration bit 13
pub fn ot12(&mut self) -> OT12_W<'_>
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Bit 12 - Port x configuration bit 12
pub fn ot11(&mut self) -> OT11_W<'_>
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Bit 11 - Port x configuration bit 11
pub fn ot10(&mut self) -> OT10_W<'_>
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Bit 10 - Port x configuration bit 10
pub fn ot9(&mut self) -> OT9_W<'_>
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Bit 9 - Port x configuration bit 9
pub fn ot8(&mut self) -> OT8_W<'_>
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Bit 8 - Port x configuration bit 8
pub fn ot7(&mut self) -> OT7_W<'_>
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Bit 7 - Port x configuration bit 7
pub fn ot6(&mut self) -> OT6_W<'_>
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Bit 6 - Port x configuration bit 6
pub fn ot5(&mut self) -> OT5_W<'_>
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Bit 5 - Port x configuration bit 5
pub fn ot4(&mut self) -> OT4_W<'_>
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Bit 4 - Port x configuration bit 4
pub fn ot3(&mut self) -> OT3_W<'_>
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Bit 3 - Port x configuration bit 3
pub fn ot2(&mut self) -> OT2_W<'_>
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Bit 2 - Port x configuration bit 2
pub fn ot1(&mut self) -> OT1_W<'_>
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Bit 1 - Port x configuration bit 1
pub fn ot0(&mut self) -> OT0_W<'_>
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Bit 0 - Port x configuration bit 0
impl W<u32, Reg<u32, _OSPEEDR>>
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pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
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Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
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Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
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Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
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Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
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Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
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Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
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Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
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Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
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Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
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Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
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Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
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Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
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Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
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Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
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Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
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Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
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pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
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Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
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Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
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Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
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Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
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Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
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Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
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Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
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Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
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Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
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Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
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Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
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Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
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Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
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Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
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Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
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Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
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pub fn odr15(&mut self) -> ODR15_W<'_>
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Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
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Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
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Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
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Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
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Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
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Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
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Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
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Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
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Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
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Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
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Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
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Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
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Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
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Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
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Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
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Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
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pub fn br15(&mut self) -> BR15_W<'_>
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Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
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Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
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Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
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Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
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Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
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Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
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Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
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Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
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Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
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Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
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Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
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Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
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Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
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Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
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Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
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Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
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Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
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Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
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Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
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Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
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Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
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Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
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Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
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Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
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Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
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Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
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Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
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Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
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Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
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Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
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Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
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Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
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pub fn lckk(&mut self) -> LCKK_W<'_>
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Bit 16 - Port x lock bit y
pub fn lck15(&mut self) -> LCK15_W<'_>
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Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
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Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
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Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
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Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
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Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
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Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
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Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
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Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
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Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
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Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
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Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
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Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
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Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
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Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
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Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
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Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
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pub fn afrl7(&mut self) -> AFRL7_W<'_>
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Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
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Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
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Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
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Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
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Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
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Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
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Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
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Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
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pub fn afrh15(&mut self) -> AFRH15_W<'_>
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Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
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Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
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Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
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Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
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Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
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Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
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Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
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Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
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pub fn br0(&mut self) -> BR0_W<'_>
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Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
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Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
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Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
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Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
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Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
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Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
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Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
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Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
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Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
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Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
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Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
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Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
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Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
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Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
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Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
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Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _MODER>>
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pub fn moder15(&mut self) -> MODER15_W<'_>
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Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
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Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
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Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
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Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
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Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
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Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
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Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
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Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
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Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
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Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
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Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
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Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
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Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
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Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
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Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
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Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
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pub fn ot15(&mut self) -> OT15_W<'_>
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Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&mut self) -> OT14_W<'_>
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Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&mut self) -> OT13_W<'_>
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Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&mut self) -> OT12_W<'_>
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Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&mut self) -> OT11_W<'_>
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Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&mut self) -> OT10_W<'_>
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Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&mut self) -> OT9_W<'_>
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Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&mut self) -> OT8_W<'_>
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Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&mut self) -> OT7_W<'_>
[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&mut self) -> OT6_W<'_>
[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&mut self) -> OT5_W<'_>
[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&mut self) -> OT4_W<'_>
[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&mut self) -> OT3_W<'_>
[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&mut self) -> OT2_W<'_>
[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&mut self) -> OT1_W<'_>
[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&mut self) -> OT0_W<'_>
[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
[src]
pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
[src]
pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
[src]
pub fn odr15(&mut self) -> ODR15_W<'_>
[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
[src]
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
[src]
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
[src]
Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
[src]
Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
[src]
Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
[src]
Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
[src]
Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
[src]
Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
[src]
Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
[src]
Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
[src]
Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
[src]
Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
[src]
Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
[src]
Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
[src]
Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
[src]
Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
[src]
Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
[src]
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
[src]
pub fn lckk(&mut self) -> LCKK_W<'_>
[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&mut self) -> LCK15_W<'_>
[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
[src]
pub fn afrl7(&mut self) -> AFRL7_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
[src]
pub fn afrh15(&mut self) -> AFRH15_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
[src]
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn bidimode(&mut self) -> BIDIMODE_W<'_>
[src]
Bit 15 - Bidirectional data mode enable
pub fn bidioe(&mut self) -> BIDIOE_W<'_>
[src]
Bit 14 - Output enable in bidirectional mode
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 13 - Hardware CRC calculation enable
pub fn crcnext(&mut self) -> CRCNEXT_W<'_>
[src]
Bit 12 - CRC transfer next
pub fn crcl(&mut self) -> CRCL_W<'_>
[src]
Bit 11 - CRC length
pub fn rxonly(&mut self) -> RXONLY_W<'_>
[src]
Bit 10 - Receive only
pub fn ssm(&mut self) -> SSM_W<'_>
[src]
Bit 9 - Software slave management
pub fn ssi(&mut self) -> SSI_W<'_>
[src]
Bit 8 - Internal slave select
pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>
[src]
Bit 7 - Frame format
pub fn spe(&mut self) -> SPE_W<'_>
[src]
Bit 6 - SPI enable
pub fn br(&mut self) -> BR_W<'_>
[src]
Bits 3:5 - Baud rate control
pub fn mstr(&mut self) -> MSTR_W<'_>
[src]
Bit 2 - Master selection
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 1 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 0 - Clock phase
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 0 - Rx buffer DMA enable
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 1 - Tx buffer DMA enable
pub fn ssoe(&mut self) -> SSOE_W<'_>
[src]
Bit 2 - SS output enable
pub fn nssp(&mut self) -> NSSP_W<'_>
[src]
Bit 3 - NSS pulse management
pub fn frf(&mut self) -> FRF_W<'_>
[src]
Bit 4 - Frame format
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 5 - Error interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 6 - RX buffer not empty interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - Tx buffer empty interrupt enable
pub fn ds(&mut self) -> DS_W<'_>
[src]
Bits 8:11 - Data size
pub fn frxth(&mut self) -> FRXTH_W<'_>
[src]
Bit 12 - FIFO reception threshold
pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>
[src]
Bit 13 - Last DMA transfer for reception
pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>
[src]
Bit 14 - Last DMA transfer for transmission
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _DR>>
[src]
impl W<u32, Reg<u32, _CRCPR>>
[src]
impl W<u32, Reg<u32, _I2SCFGR>>
[src]
pub fn i2smod(&mut self) -> I2SMOD_W<'_>
[src]
Bit 11 - I2S mode selection
pub fn i2se(&mut self) -> I2SE_W<'_>
[src]
Bit 10 - I2S Enable
pub fn i2scfg(&mut self) -> I2SCFG_W<'_>
[src]
Bits 8:9 - I2S configuration mode
pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>
[src]
Bit 7 - PCM frame synchronization
pub fn i2sstd(&mut self) -> I2SSTD_W<'_>
[src]
Bits 4:5 - I2S standard selection
pub fn ckpol(&mut self) -> CKPOL_W<'_>
[src]
Bit 3 - Steady state clock polarity
pub fn datlen(&mut self) -> DATLEN_W<'_>
[src]
Bits 1:2 - Data length to be transferred
pub fn chlen(&mut self) -> CHLEN_W<'_>
[src]
Bit 0 - Channel length (number of bits per audio channel)
impl W<u32, Reg<u32, _I2SPR>>
[src]
pub fn mckoe(&mut self) -> MCKOE_W<'_>
[src]
Bit 9 - Master clock output enable
pub fn odd(&mut self) -> ODD_W<'_>
[src]
Bit 8 - Odd factor for the prescaler
pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>
[src]
Bits 0:7 - I2S Linear prescaler
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbp(&mut self) -> DBP_W<'_>
[src]
Bit 8 - Disable backup domain write protection
pub fn csbf(&mut self) -> CSBF_W<'_>
[src]
Bit 3 - Clear standby flag
pub fn cwuf(&mut self) -> CWUF_W<'_>
[src]
Bit 2 - Clear wakeup flag
pub fn pdds(&mut self) -> PDDS_W<'_>
[src]
Bit 1 - Power down deepsleep
pub fn lpds(&mut self) -> LPDS_W<'_>
[src]
Bit 0 - Low-power deep sleep
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn ewup1(&mut self) -> EWUP1_W<'_>
[src]
Bit 8 - Enable WKUP pin 1
pub fn ewup2(&mut self) -> EWUP2_W<'_>
[src]
Bit 9 - Enable WKUP pin 2
pub fn ewup4(&mut self) -> EWUP4_W<'_>
[src]
Bit 11 - Enable WKUP pin 4
pub fn ewup5(&mut self) -> EWUP5_W<'_>
[src]
Bit 12 - Enable WKUP pin 5
pub fn ewup6(&mut self) -> EWUP6_W<'_>
[src]
Bit 13 - Enable WKUP pin 6
pub fn ewup7(&mut self) -> EWUP7_W<'_>
[src]
Bit 14 - Enable WKUP pin 7
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn pe(&mut self) -> PE_W<'_>
[src]
Bit 0 - Peripheral enable
pub fn txie(&mut self) -> TXIE_W<'_>
[src]
Bit 1 - TX Interrupt enable
pub fn rxie(&mut self) -> RXIE_W<'_>
[src]
Bit 2 - RX Interrupt enable
pub fn addrie(&mut self) -> ADDRIE_W<'_>
[src]
Bit 3 - Address match interrupt enable (slave only)
pub fn nackie(&mut self) -> NACKIE_W<'_>
[src]
Bit 4 - Not acknowledge received interrupt enable
pub fn stopie(&mut self) -> STOPIE_W<'_>
[src]
Bit 5 - STOP detection Interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transfer Complete interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 7 - Error interrupts enable
pub fn dnf(&mut self) -> DNF_W<'_>
[src]
Bits 8:11 - Digital noise filter
pub fn anfoff(&mut self) -> ANFOFF_W<'_>
[src]
Bit 12 - Analog noise filter OFF
pub fn swrst(&mut self) -> SWRST_W<'_>
[src]
Bit 13 - Software reset
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 14 - DMA transmission requests enable
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 15 - DMA reception requests enable
pub fn sbc(&mut self) -> SBC_W<'_>
[src]
Bit 16 - Slave byte control
pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>
[src]
Bit 17 - Clock stretching disable
pub fn wupen(&mut self) -> WUPEN_W<'_>
[src]
Bit 18 - Wakeup from STOP enable
pub fn gcen(&mut self) -> GCEN_W<'_>
[src]
Bit 19 - General call enable
pub fn smbhen(&mut self) -> SMBHEN_W<'_>
[src]
Bit 20 - SMBus Host address enable
pub fn smbden(&mut self) -> SMBDEN_W<'_>
[src]
Bit 21 - SMBus Device Default address enable
pub fn alerten(&mut self) -> ALERTEN_W<'_>
[src]
Bit 22 - SMBUS alert enable
pub fn pecen(&mut self) -> PECEN_W<'_>
[src]
Bit 23 - PEC enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn pecbyte(&mut self) -> PECBYTE_W<'_>
[src]
Bit 26 - Packet error checking byte
pub fn autoend(&mut self) -> AUTOEND_W<'_>
[src]
Bit 25 - Automatic end mode (master mode)
pub fn reload(&mut self) -> RELOAD_W<'_>
[src]
Bit 24 - NBYTES reload mode
pub fn nbytes(&mut self) -> NBYTES_W<'_>
[src]
Bits 16:23 - Number of bytes
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 15 - NACK generation (slave mode)
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bit 14 - Stop generation (master mode)
pub fn start(&mut self) -> START_W<'_>
[src]
Bit 13 - Start generation
pub fn head10r(&mut self) -> HEAD10R_W<'_>
[src]
Bit 12 - 10-bit address header only read direction (master receiver mode)
pub fn add10(&mut self) -> ADD10_W<'_>
[src]
Bit 11 - 10-bit addressing mode (master mode)
pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>
[src]
Bit 10 - Transfer direction (master mode)
pub fn sadd(&mut self) -> SADD_W<'_>
[src]
Bits 0:9 - Slave address bit 9:8 (master mode)
impl W<u32, Reg<u32, _OAR1>>
[src]
pub fn oa1mode(&mut self) -> OA1MODE_W<'_>
[src]
Bit 10 - Own Address 1 10-bit mode
pub fn oa1en(&mut self) -> OA1EN_W<'_>
[src]
Bit 15 - Own Address 1 enable
pub fn oa1(&mut self) -> OA1_W<'_>
[src]
Bits 0:9 - Interface address
impl W<u32, Reg<u32, _OAR2>>
[src]
pub fn oa2(&mut self) -> OA2_W<'_>
[src]
Bits 1:7 - Interface address
pub fn oa2msk(&mut self) -> OA2MSK_W<'_>
[src]
Bits 8:10 - Own Address 2 masks
pub fn oa2en(&mut self) -> OA2EN_W<'_>
[src]
Bit 15 - Own Address 2 enable
impl W<u32, Reg<u32, _TIMINGR>>
[src]
pub fn scll(&mut self) -> SCLL_W<'_>
[src]
Bits 0:7 - SCL low period (master mode)
pub fn sclh(&mut self) -> SCLH_W<'_>
[src]
Bits 8:15 - SCL high period (master mode)
pub fn sdadel(&mut self) -> SDADEL_W<'_>
[src]
Bits 16:19 - Data hold time
pub fn scldel(&mut self) -> SCLDEL_W<'_>
[src]
Bits 20:23 - Data setup time
pub fn presc(&mut self) -> PRESC_W<'_>
[src]
Bits 28:31 - Timing prescaler
impl W<u32, Reg<u32, _TIMEOUTR>>
[src]
pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>
[src]
Bits 0:11 - Bus timeout A
pub fn tidle(&mut self) -> TIDLE_W<'_>
[src]
Bit 12 - Idle clock timeout detection
pub fn timouten(&mut self) -> TIMOUTEN_W<'_>
[src]
Bit 15 - Clock timeout enable
pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>
[src]
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
[src]
Bit 31 - Extended clock timeout enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn txis(&mut self) -> TXIS_W<'_>
[src]
Bit 1 - Transmit interrupt status (transmitters)
pub fn txe(&mut self) -> TXE_W<'_>
[src]
Bit 0 - Transmit data register empty (transmitters)
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn alertcf(&mut self) -> ALERTCF_W<'_>
[src]
Bit 13 - Alert flag clear
pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>
[src]
Bit 12 - Timeout detection flag clear
pub fn peccf(&mut self) -> PECCF_W<'_>
[src]
Bit 11 - PEC Error flag clear
pub fn ovrcf(&mut self) -> OVRCF_W<'_>
[src]
Bit 10 - Overrun/Underrun flag clear
pub fn arlocf(&mut self) -> ARLOCF_W<'_>
[src]
Bit 9 - Arbitration lost flag clear
pub fn berrcf(&mut self) -> BERRCF_W<'_>
[src]
Bit 8 - Bus error flag clear
pub fn stopcf(&mut self) -> STOPCF_W<'_>
[src]
Bit 5 - Stop detection flag clear
pub fn nackcf(&mut self) -> NACKCF_W<'_>
[src]
Bit 4 - Not Acknowledge flag clear
pub fn addrcf(&mut self) -> ADDRCF_W<'_>
[src]
Bit 3 - Address Matched flag clear
impl W<u32, Reg<u32, _TXDR>>
[src]
impl W<u32, Reg<u32, _KR>>
[src]
impl W<u32, Reg<u32, _PR>>
[src]
impl W<u32, Reg<u32, _RLR>>
[src]
impl W<u32, Reg<u32, _WINR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn wdga(&mut self) -> WDGA_W<'_>
[src]
Bit 7 - Activation bit
pub fn t(&mut self) -> T_W<'_>
[src]
Bits 0:6 - 7-bit counter
impl W<u32, Reg<u32, _CFR>>
[src]
pub fn ewi(&mut self) -> EWI_W<'_>
[src]
Bit 9 - Early wakeup interrupt
pub fn w(&mut self) -> W_W<'_>
[src]
Bits 0:6 - 7-bit window value
pub fn wdgtb(&mut self) -> WDGTB_W<'_>
[src]
Bits 7:8 - Timer base
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois4(&mut self) -> OIS4_W<'_>
[src]
Bit 14 - Output Idle state 4
pub fn ois3n(&mut self) -> OIS3N_W<'_>
[src]
Bit 13 - Output Idle state 3
pub fn ois3(&mut self) -> OIS3_W<'_>
[src]
Bit 12 - Output Idle state 3
pub fn ois2n(&mut self) -> OIS2N_W<'_>
[src]
Bit 11 - Output Idle state 2
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output Compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output Compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3ne(&mut self) -> CC3NE_W<'_>
[src]
Bit 10 - Capture/Compare 3 complementary output enable
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2ne(&mut self) -> CC2NE_W<'_>
[src]
Bit 6 - Capture/Compare 2 complementary output enable
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4np(&mut self) -> CC4NP_W<'_>
[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
pub fn cnt_h(&mut self) -> CNT_H_W<'_>
[src]
Bits 16:31 - High counter value (TIM2 only)
pub fn cnt(&mut self) -> CNT_W<'_>
[src]
Bits 0:15 - Counter value
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
pub fn arr_h(&mut self) -> ARR_H_W<'_>
[src]
Bits 16:31 - High Auto-reload value (TIM2 only)
pub fn arr(&mut self) -> ARR_W<'_>
[src]
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
[src]
pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>
[src]
Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
pub fn ccr(&mut self) -> CCR_W<'_>
[src]
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _OR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _EGR>>
[src]
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _IMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Interrupt Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Interrupt Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Interrupt Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Interrupt Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Interrupt Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Interrupt Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Interrupt Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Interrupt Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Interrupt Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Interrupt Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Interrupt Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Interrupt Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Interrupt Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Interrupt Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Interrupt Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Interrupt Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Interrupt Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Interrupt Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Interrupt Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Interrupt Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Interrupt Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Interrupt Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Interrupt Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Interrupt Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Interrupt Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Interrupt Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Interrupt Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Interrupt Mask on line 27
impl W<u32, Reg<u32, _EMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Event Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Event Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Event Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Event Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Event Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Event Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Event Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Event Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Event Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Event Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Event Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Event Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Event Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Event Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Event Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Event Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Event Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Event Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Event Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Event Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Event Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Event Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Event Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Event Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Event Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Event Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Event Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Event Mask on line 27
impl W<u32, Reg<u32, _RTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Rising trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Rising trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Rising trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Rising trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Rising trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Rising trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Rising trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Rising trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
[src]
Bit 8 - Rising trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
[src]
Bit 9 - Rising trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Rising trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Rising trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Rising trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Rising trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Rising trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Rising trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Rising trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Rising trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Rising trigger event configuration of line 19
impl W<u32, Reg<u32, _FTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Falling trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Falling trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Falling trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Falling trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Falling trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Falling trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Falling trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Falling trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
[src]
Bit 8 - Falling trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
[src]
Bit 9 - Falling trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Falling trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Falling trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Falling trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Falling trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Falling trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Falling trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Falling trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Falling trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Falling trigger event configuration of line 19
impl W<u32, Reg<u32, _SWIER>>
[src]
pub fn swier0(&mut self) -> SWIER0_W<'_>
[src]
Bit 0 - Software Interrupt on line 0
pub fn swier1(&mut self) -> SWIER1_W<'_>
[src]
Bit 1 - Software Interrupt on line 1
pub fn swier2(&mut self) -> SWIER2_W<'_>
[src]
Bit 2 - Software Interrupt on line 2
pub fn swier3(&mut self) -> SWIER3_W<'_>
[src]
Bit 3 - Software Interrupt on line 3
pub fn swier4(&mut self) -> SWIER4_W<'_>
[src]
Bit 4 - Software Interrupt on line 4
pub fn swier5(&mut self) -> SWIER5_W<'_>
[src]
Bit 5 - Software Interrupt on line 5
pub fn swier6(&mut self) -> SWIER6_W<'_>
[src]
Bit 6 - Software Interrupt on line 6
pub fn swier7(&mut self) -> SWIER7_W<'_>
[src]
Bit 7 - Software Interrupt on line 7
pub fn swier8(&mut self) -> SWIER8_W<'_>
[src]
Bit 8 - Software Interrupt on line 8
pub fn swier9(&mut self) -> SWIER9_W<'_>
[src]
Bit 9 - Software Interrupt on line 9
pub fn swier10(&mut self) -> SWIER10_W<'_>
[src]
Bit 10 - Software Interrupt on line 10
pub fn swier11(&mut self) -> SWIER11_W<'_>
[src]
Bit 11 - Software Interrupt on line 11
pub fn swier12(&mut self) -> SWIER12_W<'_>
[src]
Bit 12 - Software Interrupt on line 12
pub fn swier13(&mut self) -> SWIER13_W<'_>
[src]
Bit 13 - Software Interrupt on line 13
pub fn swier14(&mut self) -> SWIER14_W<'_>
[src]
Bit 14 - Software Interrupt on line 14
pub fn swier15(&mut self) -> SWIER15_W<'_>
[src]
Bit 15 - Software Interrupt on line 15
pub fn swier16(&mut self) -> SWIER16_W<'_>
[src]
Bit 16 - Software Interrupt on line 16
pub fn swier17(&mut self) -> SWIER17_W<'_>
[src]
Bit 17 - Software Interrupt on line 17
pub fn swier19(&mut self) -> SWIER19_W<'_>
[src]
Bit 19 - Software Interrupt on line 19
impl W<u32, Reg<u32, _PR>>
[src]
pub fn pr0(&mut self) -> PR0_W<'_>
[src]
Bit 0 - Pending bit 0
pub fn pr1(&mut self) -> PR1_W<'_>
[src]
Bit 1 - Pending bit 1
pub fn pr2(&mut self) -> PR2_W<'_>
[src]
Bit 2 - Pending bit 2
pub fn pr3(&mut self) -> PR3_W<'_>
[src]
Bit 3 - Pending bit 3
pub fn pr4(&mut self) -> PR4_W<'_>
[src]
Bit 4 - Pending bit 4
pub fn pr5(&mut self) -> PR5_W<'_>
[src]
Bit 5 - Pending bit 5
pub fn pr6(&mut self) -> PR6_W<'_>
[src]
Bit 6 - Pending bit 6
pub fn pr7(&mut self) -> PR7_W<'_>
[src]
Bit 7 - Pending bit 7
pub fn pr8(&mut self) -> PR8_W<'_>
[src]
Bit 8 - Pending bit 8
pub fn pr9(&mut self) -> PR9_W<'_>
[src]
Bit 9 - Pending bit 9
pub fn pr10(&mut self) -> PR10_W<'_>
[src]
Bit 10 - Pending bit 10
pub fn pr11(&mut self) -> PR11_W<'_>
[src]
Bit 11 - Pending bit 11
pub fn pr12(&mut self) -> PR12_W<'_>
[src]
Bit 12 - Pending bit 12
pub fn pr13(&mut self) -> PR13_W<'_>
[src]
Bit 13 - Pending bit 13
pub fn pr14(&mut self) -> PR14_W<'_>
[src]
Bit 14 - Pending bit 14
pub fn pr15(&mut self) -> PR15_W<'_>
[src]
Bit 15 - Pending bit 15
pub fn pr16(&mut self) -> PR16_W<'_>
[src]
Bit 16 - Pending bit 16
pub fn pr17(&mut self) -> PR17_W<'_>
[src]
Bit 17 - Pending bit 17
pub fn pr19(&mut self) -> PR19_W<'_>
[src]
Bit 19 - Pending bit 19
impl W<u32, Reg<u32, _CR>>
[src]
pub fn en(&mut self) -> EN_W<'_>
[src]
Bit 0 - Channel enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 1 - Transfer complete interrupt enable
pub fn htie(&mut self) -> HTIE_W<'_>
[src]
Bit 2 - Half Transfer interrupt enable
pub fn teie(&mut self) -> TEIE_W<'_>
[src]
Bit 3 - Transfer error interrupt enable
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Data transfer direction
pub fn circ(&mut self) -> CIRC_W<'_>
[src]
Bit 5 - Circular mode
pub fn pinc(&mut self) -> PINC_W<'_>
[src]
Bit 6 - Peripheral increment mode
pub fn minc(&mut self) -> MINC_W<'_>
[src]
Bit 7 - Memory increment mode
pub fn psize(&mut self) -> PSIZE_W<'_>
[src]
Bits 8:9 - Peripheral size
pub fn msize(&mut self) -> MSIZE_W<'_>
[src]
Bits 10:11 - Memory size
pub fn pl(&mut self) -> PL_W<'_>
[src]
Bits 12:13 - Channel Priority level
pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>
[src]
Bit 14 - Memory to memory mode
impl W<u32, Reg<u32, _NDTR>>
[src]
impl W<u32, Reg<u32, _PAR>>
[src]
impl W<u32, Reg<u32, _MAR>>
[src]
impl W<u32, Reg<u32, _IFCR>>
[src]
pub fn cgif1(&mut self) -> CGIF1_W<'_>
[src]
Bit 0 - Channel 1 Global interrupt clear
pub fn ctcif1(&mut self) -> CTCIF1_W<'_>
[src]
Bit 1 - Channel 1 Transfer Complete clear
pub fn chtif1(&mut self) -> CHTIF1_W<'_>
[src]
Bit 2 - Channel 1 Half Transfer clear
pub fn cteif1(&mut self) -> CTEIF1_W<'_>
[src]
Bit 3 - Channel 1 Transfer Error clear
pub fn cgif2(&mut self) -> CGIF2_W<'_>
[src]
Bit 4 - Channel 2 Global interrupt clear
pub fn ctcif2(&mut self) -> CTCIF2_W<'_>
[src]
Bit 5 - Channel 2 Transfer Complete clear
pub fn chtif2(&mut self) -> CHTIF2_W<'_>
[src]
Bit 6 - Channel 2 Half Transfer clear
pub fn cteif2(&mut self) -> CTEIF2_W<'_>
[src]
Bit 7 - Channel 2 Transfer Error clear
pub fn cgif3(&mut self) -> CGIF3_W<'_>
[src]
Bit 8 - Channel 3 Global interrupt clear
pub fn ctcif3(&mut self) -> CTCIF3_W<'_>
[src]
Bit 9 - Channel 3 Transfer Complete clear
pub fn chtif3(&mut self) -> CHTIF3_W<'_>
[src]
Bit 10 - Channel 3 Half Transfer clear
pub fn cteif3(&mut self) -> CTEIF3_W<'_>
[src]
Bit 11 - Channel 3 Transfer Error clear
pub fn cgif4(&mut self) -> CGIF4_W<'_>
[src]
Bit 12 - Channel 4 Global interrupt clear
pub fn ctcif4(&mut self) -> CTCIF4_W<'_>
[src]
Bit 13 - Channel 4 Transfer Complete clear
pub fn chtif4(&mut self) -> CHTIF4_W<'_>
[src]
Bit 14 - Channel 4 Half Transfer clear
pub fn cteif4(&mut self) -> CTEIF4_W<'_>
[src]
Bit 15 - Channel 4 Transfer Error clear
pub fn cgif5(&mut self) -> CGIF5_W<'_>
[src]
Bit 16 - Channel 5 Global interrupt clear
pub fn ctcif5(&mut self) -> CTCIF5_W<'_>
[src]
Bit 17 - Channel 5 Transfer Complete clear
pub fn chtif5(&mut self) -> CHTIF5_W<'_>
[src]
Bit 18 - Channel 5 Half Transfer clear
pub fn cteif5(&mut self) -> CTEIF5_W<'_>
[src]
Bit 19 - Channel 5 Transfer Error clear
pub fn cgif6(&mut self) -> CGIF6_W<'_>
[src]
Bit 20 - Channel 6 Global interrupt clear
pub fn ctcif6(&mut self) -> CTCIF6_W<'_>
[src]
Bit 21 - Channel 6 Transfer Complete clear
pub fn chtif6(&mut self) -> CHTIF6_W<'_>
[src]
Bit 22 - Channel 6 Half Transfer clear
pub fn cteif6(&mut self) -> CTEIF6_W<'_>
[src]
Bit 23 - Channel 6 Transfer Error clear
pub fn cgif7(&mut self) -> CGIF7_W<'_>
[src]
Bit 24 - Channel 7 Global interrupt clear
pub fn ctcif7(&mut self) -> CTCIF7_W<'_>
[src]
Bit 25 - Channel 7 Transfer Complete clear
pub fn chtif7(&mut self) -> CHTIF7_W<'_>
[src]
Bit 26 - Channel 7 Half Transfer clear
pub fn cteif7(&mut self) -> CTEIF7_W<'_>
[src]
Bit 27 - Channel 7 Transfer Error clear
impl W<u32, Reg<u32, _CR>>
[src]
pub fn hsion(&mut self) -> HSION_W<'_>
[src]
Bit 0 - Internal High Speed clock enable
pub fn hsitrim(&mut self) -> HSITRIM_W<'_>
[src]
Bits 3:7 - Internal High Speed clock trimming
pub fn hseon(&mut self) -> HSEON_W<'_>
[src]
Bit 16 - External High Speed clock enable
pub fn hsebyp(&mut self) -> HSEBYP_W<'_>
[src]
Bit 18 - External High Speed clock Bypass
pub fn csson(&mut self) -> CSSON_W<'_>
[src]
Bit 19 - Clock Security System enable
pub fn pllon(&mut self) -> PLLON_W<'_>
[src]
Bit 24 - PLL enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn sw(&mut self) -> SW_W<'_>
[src]
Bits 0:1 - System clock Switch
pub fn hpre(&mut self) -> HPRE_W<'_>
[src]
Bits 4:7 - AHB prescaler
pub fn ppre(&mut self) -> PPRE_W<'_>
[src]
Bits 8:10 - APB Low speed prescaler (APB1)
pub fn adcpre(&mut self) -> ADCPRE_W<'_>
[src]
Bit 14 - APCPRE is deprecated. See ADC field in CFGR2 register.
pub fn pllsrc(&mut self) -> PLLSRC_W<'_>
[src]
Bit 16 - PLL input clock source
pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>
[src]
Bit 17 - HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning
pub fn pllmul(&mut self) -> PLLMUL_W<'_>
[src]
Bits 18:21 - PLL Multiplication Factor
pub fn mco(&mut self) -> MCO_W<'_>
[src]
Bits 24:26 - Microcontroller clock output
pub fn mcopre(&mut self) -> MCOPRE_W<'_>
[src]
Bits 28:30 - Microcontroller Clock Output Prescaler
pub fn pllnodiv(&mut self) -> PLLNODIV_W<'_>
[src]
Bit 31 - PLL clock not divided for MCO
impl W<u32, Reg<u32, _CIR>>
[src]
pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>
[src]
Bit 8 - LSI Ready Interrupt Enable
pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>
[src]
Bit 9 - LSE Ready Interrupt Enable
pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>
[src]
Bit 10 - HSI Ready Interrupt Enable
pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>
[src]
Bit 11 - HSE Ready Interrupt Enable
pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>
[src]
Bit 12 - PLL Ready Interrupt Enable
pub fn hsi14rdyie(&mut self) -> HSI14RDYIE_W<'_>
[src]
Bit 13 - HSI14 ready interrupt enable
pub fn hsi48rdyie(&mut self) -> HSI48RDYIE_W<'_>
[src]
Bit 14 - HSI48 ready interrupt enable
pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>
[src]
Bit 16 - LSI Ready Interrupt Clear
pub fn lserdyc(&mut self) -> LSERDYC_W<'_>
[src]
Bit 17 - LSE Ready Interrupt Clear
pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>
[src]
Bit 18 - HSI Ready Interrupt Clear
pub fn hserdyc(&mut self) -> HSERDYC_W<'_>
[src]
Bit 19 - HSE Ready Interrupt Clear
pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>
[src]
Bit 20 - PLL Ready Interrupt Clear
pub fn hsi14rdyc(&mut self) -> HSI14RDYC_W<'_>
[src]
Bit 21 - HSI 14 MHz Ready Interrupt Clear
pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W<'_>
[src]
Bit 22 - HSI48 Ready Interrupt Clear
pub fn cssc(&mut self) -> CSSC_W<'_>
[src]
Bit 23 - Clock security system interrupt clear
impl W<u32, Reg<u32, _APB2RSTR>>
[src]
pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>
[src]
Bit 0 - SYSCFG and COMP reset
pub fn adcrst(&mut self) -> ADCRST_W<'_>
[src]
Bit 9 - ADC interface reset
pub fn tim1rst(&mut self) -> TIM1RST_W<'_>
[src]
Bit 11 - TIM1 timer reset
pub fn spi1rst(&mut self) -> SPI1RST_W<'_>
[src]
Bit 12 - SPI 1 reset
pub fn usart1rst(&mut self) -> USART1RST_W<'_>
[src]
Bit 14 - USART1 reset
pub fn tim15rst(&mut self) -> TIM15RST_W<'_>
[src]
Bit 16 - TIM15 timer reset
pub fn tim16rst(&mut self) -> TIM16RST_W<'_>
[src]
Bit 17 - TIM16 timer reset
pub fn tim17rst(&mut self) -> TIM17RST_W<'_>
[src]
Bit 18 - TIM17 timer reset
pub fn dbgmcurst(&mut self) -> DBGMCURST_W<'_>
[src]
Bit 22 - Debug MCU reset
pub fn usart6rst(&mut self) -> USART6RST_W<'_>
[src]
Bit 5 - USART6 reset
impl W<u32, Reg<u32, _APB1RSTR>>
[src]
pub fn tim3rst(&mut self) -> TIM3RST_W<'_>
[src]
Bit 1 - Timer 3 reset
pub fn tim6rst(&mut self) -> TIM6RST_W<'_>
[src]
Bit 4 - Timer 6 reset
pub fn tim7rst(&mut self) -> TIM7RST_W<'_>
[src]
Bit 5 - TIM7 timer reset
pub fn tim14rst(&mut self) -> TIM14RST_W<'_>
[src]
Bit 8 - Timer 14 reset
pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>
[src]
Bit 11 - Window watchdog reset
pub fn spi2rst(&mut self) -> SPI2RST_W<'_>
[src]
Bit 14 - SPI2 reset
pub fn usart2rst(&mut self) -> USART2RST_W<'_>
[src]
Bit 17 - USART 2 reset
pub fn usart3rst(&mut self) -> USART3RST_W<'_>
[src]
Bit 18 - USART3 reset
pub fn usart4rst(&mut self) -> USART4RST_W<'_>
[src]
Bit 19 - USART4 reset
pub fn usart5rst(&mut self) -> USART5RST_W<'_>
[src]
Bit 20 - USART5 reset
pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>
[src]
Bit 21 - I2C1 reset
pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>
[src]
Bit 22 - I2C2 reset
pub fn usbrst(&mut self) -> USBRST_W<'_>
[src]
Bit 23 - USB interface reset
pub fn pwrrst(&mut self) -> PWRRST_W<'_>
[src]
Bit 28 - Power interface reset
impl W<u32, Reg<u32, _AHBENR>>
[src]
pub fn dma1en(&mut self) -> DMA1EN_W<'_>
[src]
Bit 0 - DMA1 clock enable
pub fn sramen(&mut self) -> SRAMEN_W<'_>
[src]
Bit 2 - SRAM interface clock enable
pub fn flitfen(&mut self) -> FLITFEN_W<'_>
[src]
Bit 4 - FLITF clock enable
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 6 - CRC clock enable
pub fn iopaen(&mut self) -> IOPAEN_W<'_>
[src]
Bit 17 - I/O port A clock enable
pub fn iopben(&mut self) -> IOPBEN_W<'_>
[src]
Bit 18 - I/O port B clock enable
pub fn iopcen(&mut self) -> IOPCEN_W<'_>
[src]
Bit 19 - I/O port C clock enable
pub fn iopfen(&mut self) -> IOPFEN_W<'_>
[src]
Bit 22 - I/O port F clock enable
pub fn iopden(&mut self) -> IOPDEN_W<'_>
[src]
Bit 20 - I/O port D clock enable
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - DMA clock enable
impl W<u32, Reg<u32, _APB2ENR>>
[src]
pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>
[src]
Bit 0 - SYSCFG clock enable
pub fn adcen(&mut self) -> ADCEN_W<'_>
[src]
Bit 9 - ADC 1 interface clock enable
pub fn tim1en(&mut self) -> TIM1EN_W<'_>
[src]
Bit 11 - TIM1 Timer clock enable
pub fn spi1en(&mut self) -> SPI1EN_W<'_>
[src]
Bit 12 - SPI 1 clock enable
pub fn usart1en(&mut self) -> USART1EN_W<'_>
[src]
Bit 14 - USART1 clock enable
pub fn tim15en(&mut self) -> TIM15EN_W<'_>
[src]
Bit 16 - TIM15 timer clock enable
pub fn tim16en(&mut self) -> TIM16EN_W<'_>
[src]
Bit 17 - TIM16 timer clock enable
pub fn tim17en(&mut self) -> TIM17EN_W<'_>
[src]
Bit 18 - TIM17 timer clock enable
pub fn dbgmcuen(&mut self) -> DBGMCUEN_W<'_>
[src]
Bit 22 - MCU debug module clock enable
pub fn usart6en(&mut self) -> USART6EN_W<'_>
[src]
Bit 5 - USART6 clock enable
impl W<u32, Reg<u32, _APB1ENR>>
[src]
pub fn tim3en(&mut self) -> TIM3EN_W<'_>
[src]
Bit 1 - Timer 3 clock enable
pub fn tim6en(&mut self) -> TIM6EN_W<'_>
[src]
Bit 4 - Timer 6 clock enable
pub fn tim7en(&mut self) -> TIM7EN_W<'_>
[src]
Bit 5 - TIM7 timer clock enable
pub fn tim14en(&mut self) -> TIM14EN_W<'_>
[src]
Bit 8 - Timer 14 clock enable
pub fn wwdgen(&mut self) -> WWDGEN_W<'_>
[src]
Bit 11 - Window watchdog clock enable
pub fn spi2en(&mut self) -> SPI2EN_W<'_>
[src]
Bit 14 - SPI 2 clock enable
pub fn usart2en(&mut self) -> USART2EN_W<'_>
[src]
Bit 17 - USART 2 clock enable
pub fn usart3en(&mut self) -> USART3EN_W<'_>
[src]
Bit 18 - USART3 clock enable
pub fn usart4en(&mut self) -> USART4EN_W<'_>
[src]
Bit 19 - USART4 clock enable
pub fn usart5en(&mut self) -> USART5EN_W<'_>
[src]
Bit 20 - USART5 clock enable
pub fn i2c1en(&mut self) -> I2C1EN_W<'_>
[src]
Bit 21 - I2C 1 clock enable
pub fn i2c2en(&mut self) -> I2C2EN_W<'_>
[src]
Bit 22 - I2C 2 clock enable
pub fn usben(&mut self) -> USBEN_W<'_>
[src]
Bit 23 - USB interface clock enable
pub fn pwren(&mut self) -> PWREN_W<'_>
[src]
Bit 28 - Power interface clock enable
impl W<u32, Reg<u32, _BDCR>>
[src]
pub fn lseon(&mut self) -> LSEON_W<'_>
[src]
Bit 0 - External Low Speed oscillator enable
pub fn lsebyp(&mut self) -> LSEBYP_W<'_>
[src]
Bit 2 - External Low Speed oscillator bypass
pub fn lsedrv(&mut self) -> LSEDRV_W<'_>
[src]
Bits 3:4 - LSE oscillator drive capability
pub fn rtcsel(&mut self) -> RTCSEL_W<'_>
[src]
Bits 8:9 - RTC clock source selection
pub fn rtcen(&mut self) -> RTCEN_W<'_>
[src]
Bit 15 - RTC clock enable
pub fn bdrst(&mut self) -> BDRST_W<'_>
[src]
Bit 16 - Backup domain software reset
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn lsion(&mut self) -> LSION_W<'_>
[src]
Bit 0 - Internal low speed oscillator enable
pub fn rmvf(&mut self) -> RMVF_W<'_>
[src]
Bit 24 - Remove reset flag
pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>
[src]
Bit 25 - Option byte loader reset flag
pub fn pinrstf(&mut self) -> PINRSTF_W<'_>
[src]
Bit 26 - PIN reset flag
pub fn porrstf(&mut self) -> PORRSTF_W<'_>
[src]
Bit 27 - POR/PDR reset flag
pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>
[src]
Bit 28 - Software reset flag
pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>
[src]
Bit 29 - Independent watchdog reset flag
pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>
[src]
Bit 30 - Window watchdog reset flag
pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>
[src]
Bit 31 - Low-power reset flag
pub fn v18pwrrstf(&mut self) -> V18PWRRSTF_W<'_>
[src]
Bit 23 - 1.8 V domain reset flag
impl W<u32, Reg<u32, _AHBRSTR>>
[src]
pub fn ioparst(&mut self) -> IOPARST_W<'_>
[src]
Bit 17 - I/O port A reset
pub fn iopbrst(&mut self) -> IOPBRST_W<'_>
[src]
Bit 18 - I/O port B reset
pub fn iopcrst(&mut self) -> IOPCRST_W<'_>
[src]
Bit 19 - I/O port C reset
pub fn iopdrst(&mut self) -> IOPDRST_W<'_>
[src]
Bit 20 - I/O port D reset
pub fn iopfrst(&mut self) -> IOPFRST_W<'_>
[src]
Bit 22 - I/O port F reset
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _CFGR3>>
[src]
pub fn usart1sw(&mut self) -> USART1SW_W<'_>
[src]
Bits 0:1 - USART1 clock source selection
pub fn i2c1sw(&mut self) -> I2C1SW_W<'_>
[src]
Bit 4 - I2C1 clock source selection
pub fn usbsw(&mut self) -> USBSW_W<'_>
[src]
Bit 7 - USB clock source selection
pub fn adcsw(&mut self) -> ADCSW_W<'_>
[src]
Bit 8 - ADCSW is deprecated. See ADC field in CFGR2 register.
pub fn usart2sw(&mut self) -> USART2SW_W<'_>
[src]
Bits 16:17 - USART2 clock source selection
pub fn usart3sw(&mut self) -> USART3SW_W<'_>
[src]
Bits 18:19 - USART3 clock source
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn hsi14on(&mut self) -> HSI14ON_W<'_>
[src]
Bit 0 - HSI14 clock enable
pub fn hsi14dis(&mut self) -> HSI14DIS_W<'_>
[src]
Bit 2 - HSI14 clock request from ADC disable
pub fn hsi14trim(&mut self) -> HSI14TRIM_W<'_>
[src]
Bits 3:7 - HSI14 clock trimming
pub fn hsi48on(&mut self) -> HSI48ON_W<'_>
[src]
Bit 16 - HSI48 clock enable
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>
[src]
Bits 0:1 - Memory mapping selection bits
pub fn adc_dma_rmp(&mut self) -> ADC_DMA_RMP_W<'_>
[src]
Bit 8 - ADC DMA remapping bit
pub fn usart1_tx_dma_rmp(&mut self) -> USART1_TX_DMA_RMP_W<'_>
[src]
Bit 9 - USART1_TX DMA remapping bit
pub fn usart1_rx_dma_rmp(&mut self) -> USART1_RX_DMA_RMP_W<'_>
[src]
Bit 10 - USART1_RX DMA request remapping bit
pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<'_>
[src]
Bit 11 - TIM16 DMA request remapping bit
pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<'_>
[src]
Bit 12 - TIM17 DMA request remapping bit
pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>
[src]
Bit 16 - Fast Mode Plus (FM plus) driving capability activation bits.
pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>
[src]
Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>
[src]
Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>
[src]
Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>
[src]
Bit 20 - FM+ driving capability activation for I2C1
pub fn usart3_dma_rmp(&mut self) -> USART3_DMA_RMP_W<'_>
[src]
Bit 26 - USART3 DMA request remapping bit
pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>
[src]
Bit 4 - PA11 and PA12 remapping bit for small packages (28 and 20 pins)
pub fn i2c_pa9_fmp(&mut self) -> I2C_PA9_FMP_W<'_>
[src]
Bit 22 - Fast Mode Plus (FM+) driving capability activation bits
pub fn i2c_pa10_fmp(&mut self) -> I2C_PA10_FMP_W<'_>
[src]
Bit 23 - Fast Mode Plus (FM+) driving capability activation bits
impl W<u32, Reg<u32, _EXTICR1>>
[src]
pub fn exti3(&mut self) -> EXTI3_W<'_>
[src]
Bits 12:15 - EXTI 3 configuration bits
pub fn exti2(&mut self) -> EXTI2_W<'_>
[src]
Bits 8:11 - EXTI 2 configuration bits
pub fn exti1(&mut self) -> EXTI1_W<'_>
[src]
Bits 4:7 - EXTI 1 configuration bits
pub fn exti0(&mut self) -> EXTI0_W<'_>
[src]
Bits 0:3 - EXTI 0 configuration bits
impl W<u32, Reg<u32, _EXTICR2>>
[src]
pub fn exti7(&mut self) -> EXTI7_W<'_>
[src]
Bits 12:15 - EXTI 7 configuration bits
pub fn exti6(&mut self) -> EXTI6_W<'_>
[src]
Bits 8:11 - EXTI 6 configuration bits
pub fn exti5(&mut self) -> EXTI5_W<'_>
[src]
Bits 4:7 - EXTI 5 configuration bits
pub fn exti4(&mut self) -> EXTI4_W<'_>
[src]
Bits 0:3 - EXTI 4 configuration bits
impl W<u32, Reg<u32, _EXTICR3>>
[src]
pub fn exti11(&mut self) -> EXTI11_W<'_>
[src]
Bits 12:15 - EXTI 11 configuration bits
pub fn exti10(&mut self) -> EXTI10_W<'_>
[src]
Bits 8:11 - EXTI 10 configuration bits
pub fn exti9(&mut self) -> EXTI9_W<'_>
[src]
Bits 4:7 - EXTI 9 configuration bits
pub fn exti8(&mut self) -> EXTI8_W<'_>
[src]
Bits 0:3 - EXTI 8 configuration bits
impl W<u32, Reg<u32, _EXTICR4>>
[src]
pub fn exti15(&mut self) -> EXTI15_W<'_>
[src]
Bits 12:15 - EXTI 15 configuration bits
pub fn exti14(&mut self) -> EXTI14_W<'_>
[src]
Bits 8:11 - EXTI 14 configuration bits
pub fn exti13(&mut self) -> EXTI13_W<'_>
[src]
Bits 4:7 - EXTI 13 configuration bits
pub fn exti12(&mut self) -> EXTI12_W<'_>
[src]
Bits 0:3 - EXTI 12 configuration bits
impl W<u32, Reg<u32, _CFGR2>>
[src]
pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>
[src]
Bit 8 - SRAM parity flag
pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>
[src]
Bit 1 - SRAM parity lock bit
pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>
[src]
Bit 0 - Cortex-M0 LOCKUP bit enable bit
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn awd(&mut self) -> AWD_W<'_>
[src]
Bit 7 - Analog watchdog flag
pub fn ovr(&mut self) -> OVR_W<'_>
[src]
Bit 4 - ADC overrun
pub fn eoseq(&mut self) -> EOSEQ_W<'_>
[src]
Bit 3 - End of sequence flag
pub fn eoc(&mut self) -> EOC_W<'_>
[src]
Bit 2 - End of conversion flag
pub fn eosmp(&mut self) -> EOSMP_W<'_>
[src]
Bit 1 - End of sampling flag
pub fn adrdy(&mut self) -> ADRDY_W<'_>
[src]
Bit 0 - ADC ready
impl W<u32, Reg<u32, _IER>>
[src]
pub fn awdie(&mut self) -> AWDIE_W<'_>
[src]
Bit 7 - Analog watchdog interrupt enable
pub fn ovrie(&mut self) -> OVRIE_W<'_>
[src]
Bit 4 - Overrun interrupt enable
pub fn eoseqie(&mut self) -> EOSEQIE_W<'_>
[src]
Bit 3 - End of conversion sequence interrupt enable
pub fn eocie(&mut self) -> EOCIE_W<'_>
[src]
Bit 2 - End of conversion interrupt enable
pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>
[src]
Bit 1 - End of sampling flag interrupt enable
pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>
[src]
Bit 0 - ADC ready interrupt enable
impl W<u32, Reg<u32, _CR>>
[src]
pub fn adcal(&mut self) -> ADCAL_W<'_>
[src]
Bit 31 - ADC calibration
pub fn adstp(&mut self) -> ADSTP_W<'_>
[src]
Bit 4 - ADC stop conversion command
pub fn adstart(&mut self) -> ADSTART_W<'_>
[src]
Bit 2 - ADC start conversion command
pub fn addis(&mut self) -> ADDIS_W<'_>
[src]
Bit 1 - ADC disable command
pub fn aden(&mut self) -> ADEN_W<'_>
[src]
Bit 0 - ADC enable command
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn awdch(&mut self) -> AWDCH_W<'_>
[src]
Bits 26:30 - Analog watchdog channel selection
pub fn awden(&mut self) -> AWDEN_W<'_>
[src]
Bit 23 - Analog watchdog enable
pub fn awdsgl(&mut self) -> AWDSGL_W<'_>
[src]
Bit 22 - Enable the watchdog on a single channel or on all channels
pub fn discen(&mut self) -> DISCEN_W<'_>
[src]
Bit 16 - Discontinuous mode
pub fn autoff(&mut self) -> AUTOFF_W<'_>
[src]
Bit 15 - Auto-off mode
pub fn autdly(&mut self) -> AUTDLY_W<'_>
[src]
Bit 14 - Auto-delayed conversion mode
pub fn cont(&mut self) -> CONT_W<'_>
[src]
Bit 13 - Single / continuous conversion mode
pub fn ovrmod(&mut self) -> OVRMOD_W<'_>
[src]
Bit 12 - Overrun management mode
pub fn exten(&mut self) -> EXTEN_W<'_>
[src]
Bits 10:11 - External trigger enable and polarity selection
pub fn extsel(&mut self) -> EXTSEL_W<'_>
[src]
Bits 6:8 - External trigger selection
pub fn align(&mut self) -> ALIGN_W<'_>
[src]
Bit 5 - Data alignment
pub fn res(&mut self) -> RES_W<'_>
[src]
Bits 3:4 - Data resolution
pub fn scandir(&mut self) -> SCANDIR_W<'_>
[src]
Bit 2 - Scan sequence direction
pub fn dmacfg(&mut self) -> DMACFG_W<'_>
[src]
Bit 1 - Direct memery access configuration
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - Direct memory access enable
pub fn wait(&mut self) -> WAIT_W<'_>
[src]
Bit 14 - Wait conversion mode
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _SMPR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 16:27 - Analog watchdog higher threshold
pub fn lt(&mut self) -> LT_W<'_>
[src]
Bits 0:11 - Analog watchdog lower threshold
impl W<u32, Reg<u32, _CHSELR>>
[src]
pub fn chsel18(&mut self) -> CHSEL18_W<'_>
[src]
Bit 18 - Channel-x selection
pub fn chsel17(&mut self) -> CHSEL17_W<'_>
[src]
Bit 17 - Channel-x selection
pub fn chsel16(&mut self) -> CHSEL16_W<'_>
[src]
Bit 16 - Channel-x selection
pub fn chsel15(&mut self) -> CHSEL15_W<'_>
[src]
Bit 15 - Channel-x selection
pub fn chsel14(&mut self) -> CHSEL14_W<'_>
[src]
Bit 14 - Channel-x selection
pub fn chsel13(&mut self) -> CHSEL13_W<'_>
[src]
Bit 13 - Channel-x selection
pub fn chsel12(&mut self) -> CHSEL12_W<'_>
[src]
Bit 12 - Channel-x selection
pub fn chsel11(&mut self) -> CHSEL11_W<'_>
[src]
Bit 11 - Channel-x selection
pub fn chsel10(&mut self) -> CHSEL10_W<'_>
[src]
Bit 10 - Channel-x selection
pub fn chsel9(&mut self) -> CHSEL9_W<'_>
[src]
Bit 9 - Channel-x selection
pub fn chsel8(&mut self) -> CHSEL8_W<'_>
[src]
Bit 8 - Channel-x selection
pub fn chsel7(&mut self) -> CHSEL7_W<'_>
[src]
Bit 7 - Channel-x selection
pub fn chsel6(&mut self) -> CHSEL6_W<'_>
[src]
Bit 6 - Channel-x selection
pub fn chsel5(&mut self) -> CHSEL5_W<'_>
[src]
Bit 5 - Channel-x selection
pub fn chsel4(&mut self) -> CHSEL4_W<'_>
[src]
Bit 4 - Channel-x selection
pub fn chsel3(&mut self) -> CHSEL3_W<'_>
[src]
Bit 3 - Channel-x selection
pub fn chsel2(&mut self) -> CHSEL2_W<'_>
[src]
Bit 2 - Channel-x selection
pub fn chsel1(&mut self) -> CHSEL1_W<'_>
[src]
Bit 1 - Channel-x selection
pub fn chsel0(&mut self) -> CHSEL0_W<'_>
[src]
Bit 0 - Channel-x selection
impl W<u32, Reg<u32, _CCR>>
[src]
pub fn tsen(&mut self) -> TSEN_W<'_>
[src]
Bit 23 - Temperature sensor enable
pub fn vrefen(&mut self) -> VREFEN_W<'_>
[src]
Bit 22 - Temperature sensor and VREFINT enable
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ue(&mut self) -> UE_W<'_>
[src]
Bit 0 - USART enable
pub fn uesm(&mut self) -> UESM_W<'_>
[src]
Bit 1 - USART enable in Stop mode
pub fn re(&mut self) -> RE_W<'_>
[src]
Bit 2 - Receiver enable
pub fn te(&mut self) -> TE_W<'_>
[src]
Bit 3 - Transmitter enable
pub fn idleie(&mut self) -> IDLEIE_W<'_>
[src]
Bit 4 - IDLE interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 5 - RXNE interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transmission complete interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - interrupt enable
pub fn peie(&mut self) -> PEIE_W<'_>
[src]
Bit 8 - PE interrupt enable
pub fn ps(&mut self) -> PS_W<'_>
[src]
Bit 9 - Parity selection
pub fn pce(&mut self) -> PCE_W<'_>
[src]
Bit 10 - Parity control enable
pub fn wake(&mut self) -> WAKE_W<'_>
[src]
Bit 11 - Receiver wakeup method
pub fn m0(&mut self) -> M0_W<'_>
[src]
Bit 12 - Word length
pub fn mme(&mut self) -> MME_W<'_>
[src]
Bit 13 - Mute mode enable
pub fn cmie(&mut self) -> CMIE_W<'_>
[src]
Bit 14 - Character match interrupt enable
pub fn over8(&mut self) -> OVER8_W<'_>
[src]
Bit 15 - Oversampling mode
pub fn dedt(&mut self) -> DEDT_W<'_>
[src]
Bits 16:20 - Driver Enable deassertion time
pub fn deat(&mut self) -> DEAT_W<'_>
[src]
Bits 21:25 - Driver Enable assertion time
pub fn rtoie(&mut self) -> RTOIE_W<'_>
[src]
Bit 26 - Receiver timeout interrupt enable
pub fn eobie(&mut self) -> EOBIE_W<'_>
[src]
Bit 27 - End of Block interrupt enable
pub fn m1(&mut self) -> M1_W<'_>
[src]
Bit 28 - Word length
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rtoen(&mut self) -> RTOEN_W<'_>
[src]
Bit 23 - Receiver timeout enable
pub fn abrmod(&mut self) -> ABRMOD_W<'_>
[src]
Bits 21:22 - Auto baud rate mode
pub fn abren(&mut self) -> ABREN_W<'_>
[src]
Bit 20 - Auto baud rate enable
pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>
[src]
Bit 19 - Most significant bit first
pub fn datainv(&mut self) -> DATAINV_W<'_>
[src]
Bit 18 - Binary data inversion
pub fn txinv(&mut self) -> TXINV_W<'_>
[src]
Bit 17 - TX pin active level inversion
pub fn rxinv(&mut self) -> RXINV_W<'_>
[src]
Bit 16 - RX pin active level inversion
pub fn swap(&mut self) -> SWAP_W<'_>
[src]
Bit 15 - Swap TX/RX pins
pub fn linen(&mut self) -> LINEN_W<'_>
[src]
Bit 14 - LIN mode enable
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bits 12:13 - STOP bits
pub fn clken(&mut self) -> CLKEN_W<'_>
[src]
Bit 11 - Clock enable
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 10 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 9 - Clock phase
pub fn lbcl(&mut self) -> LBCL_W<'_>
[src]
Bit 8 - Last bit clock pulse
pub fn lbdie(&mut self) -> LBDIE_W<'_>
[src]
Bit 6 - LIN break detection interrupt enable
pub fn lbdl(&mut self) -> LBDL_W<'_>
[src]
Bit 5 - LIN break detection length
pub fn addm7(&mut self) -> ADDM7_W<'_>
[src]
Bit 4 - 7-bit Address Detection/4-bit Address Detection
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 24:31 - Address of the USART node
impl W<u32, Reg<u32, _CR3>>
[src]
pub fn wufie(&mut self) -> WUFIE_W<'_>
[src]
Bit 22 - Wakeup from Stop mode interrupt enable
pub fn wus(&mut self) -> WUS_W<'_>
[src]
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
pub fn scarcnt(&mut self) -> SCARCNT_W<'_>
[src]
Bits 17:19 - Smartcard auto-retry count
pub fn dep(&mut self) -> DEP_W<'_>
[src]
Bit 15 - Driver enable polarity selection
pub fn dem(&mut self) -> DEM_W<'_>
[src]
Bit 14 - Driver enable mode
pub fn ddre(&mut self) -> DDRE_W<'_>
[src]
Bit 13 - DMA Disable on Reception Error
pub fn ovrdis(&mut self) -> OVRDIS_W<'_>
[src]
Bit 12 - Overrun Disable
pub fn onebit(&mut self) -> ONEBIT_W<'_>
[src]
Bit 11 - One sample bit method enable
pub fn ctsie(&mut self) -> CTSIE_W<'_>
[src]
Bit 10 - CTS interrupt enable
pub fn ctse(&mut self) -> CTSE_W<'_>
[src]
Bit 9 - CTS enable
pub fn rtse(&mut self) -> RTSE_W<'_>
[src]
Bit 8 - RTS enable
pub fn dmat(&mut self) -> DMAT_W<'_>
[src]
Bit 7 - DMA enable transmitter
pub fn dmar(&mut self) -> DMAR_W<'_>
[src]
Bit 6 - DMA enable receiver
pub fn scen(&mut self) -> SCEN_W<'_>
[src]
Bit 5 - Smartcard mode enable
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 4 - Smartcard NACK enable
pub fn hdsel(&mut self) -> HDSEL_W<'_>
[src]
Bit 3 - Half-duplex selection
pub fn irlp(&mut self) -> IRLP_W<'_>
[src]
Bit 2 - IrDA low-power
pub fn iren(&mut self) -> IREN_W<'_>
[src]
Bit 1 - IrDA mode enable
pub fn eie(&mut self) -> EIE_W<'_>
[src]
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
[src]
impl W<u32, Reg<u32, _GTPR>>
[src]
pub fn gt(&mut self) -> GT_W<'_>
[src]
Bits 8:15 - Guard time value
pub fn psc(&mut self) -> PSC_W<'_>
[src]
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
[src]
pub fn blen(&mut self) -> BLEN_W<'_>
[src]
Bits 24:31 - Block Length
pub fn rto(&mut self) -> RTO_W<'_>
[src]
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
[src]
pub fn txfrq(&mut self) -> TXFRQ_W<'_>
[src]
Bit 4 - Transmit data flush request
pub fn rxfrq(&mut self) -> RXFRQ_W<'_>
[src]
Bit 3 - Receive data flush request
pub fn mmrq(&mut self) -> MMRQ_W<'_>
[src]
Bit 2 - Mute mode request
pub fn sbkrq(&mut self) -> SBKRQ_W<'_>
[src]
Bit 1 - Send break request
pub fn abrrq(&mut self) -> ABRRQ_W<'_>
[src]
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn wucf(&mut self) -> WUCF_W<'_>
[src]
Bit 20 - Wakeup from Stop mode clear flag
pub fn cmcf(&mut self) -> CMCF_W<'_>
[src]
Bit 17 - Character match clear flag
pub fn eobcf(&mut self) -> EOBCF_W<'_>
[src]
Bit 12 - End of timeout clear flag
pub fn rtocf(&mut self) -> RTOCF_W<'_>
[src]
Bit 11 - Receiver timeout clear flag
pub fn ctscf(&mut self) -> CTSCF_W<'_>
[src]
Bit 9 - CTS clear flag
pub fn lbdcf(&mut self) -> LBDCF_W<'_>
[src]
Bit 8 - LIN break detection clear flag
pub fn tccf(&mut self) -> TCCF_W<'_>
[src]
Bit 6 - Transmission complete clear flag
pub fn idlecf(&mut self) -> IDLECF_W<'_>
[src]
Bit 4 - Idle line detected clear flag
pub fn orecf(&mut self) -> ORECF_W<'_>
[src]
Bit 3 - Overrun error clear flag
pub fn ncf(&mut self) -> NCF_W<'_>
[src]
Bit 2 - Noise detected clear flag
pub fn fecf(&mut self) -> FECF_W<'_>
[src]
Bit 1 - Framing error clear flag
pub fn pecf(&mut self) -> PECF_W<'_>
[src]
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _DR>>
[src]
pub fn yt(&mut self) -> YT_W<'_>
[src]
Bits 20:23 - Year tens in BCD format
pub fn yu(&mut self) -> YU_W<'_>
[src]
Bits 16:19 - Year units in BCD format
pub fn wdu(&mut self) -> WDU_W<'_>
[src]
Bits 13:15 - Week day units
pub fn mt(&mut self) -> MT_W<'_>
[src]
Bit 12 - Month tens in BCD format
pub fn mu(&mut self) -> MU_W<'_>
[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 0:3 - Date units in BCD format
impl W<u32, Reg<u32, _CR>>
[src]
pub fn tsedge(&mut self) -> TSEDGE_W<'_>
[src]
Bit 3 - Time-stamp event active edge
pub fn refckon(&mut self) -> REFCKON_W<'_>
[src]
Bit 4 - RTC_REFIN reference clock detection enable (50 or 60 Hz)
pub fn bypshad(&mut self) -> BYPSHAD_W<'_>
[src]
Bit 5 - Bypass the shadow registers
pub fn fmt(&mut self) -> FMT_W<'_>
[src]
Bit 6 - Hour format
pub fn alrae(&mut self) -> ALRAE_W<'_>
[src]
Bit 8 - Alarm A enable
pub fn tse(&mut self) -> TSE_W<'_>
[src]
Bit 11 - timestamp enable
pub fn alraie(&mut self) -> ALRAIE_W<'_>
[src]
Bit 12 - Alarm A interrupt enable
pub fn tsie(&mut self) -> TSIE_W<'_>
[src]
Bit 15 - Time-stamp interrupt enable
pub fn add1h(&mut self) -> ADD1H_W<'_>
[src]
Bit 16 - Add 1 hour (summer time change)
pub fn sub1h(&mut self) -> SUB1H_W<'_>
[src]
Bit 17 - Subtract 1 hour (winter time change)
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 18 - Backup
pub fn cosel(&mut self) -> COSEL_W<'_>
[src]
Bit 19 - Calibration output selection
pub fn pol(&mut self) -> POL_W<'_>
[src]
Bit 20 - Output polarity
pub fn osel(&mut self) -> OSEL_W<'_>
[src]
Bits 21:22 - Output selection
pub fn coe(&mut self) -> COE_W<'_>
[src]
Bit 23 - Calibration output enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn shpf(&mut self) -> SHPF_W<'_>
[src]
Bit 3 - Shift operation pending
pub fn rsf(&mut self) -> RSF_W<'_>
[src]
Bit 5 - Registers synchronization flag
pub fn init(&mut self) -> INIT_W<'_>
[src]
Bit 7 - Initialization mode
pub fn alraf(&mut self) -> ALRAF_W<'_>
[src]
Bit 8 - Alarm A flag
pub fn tsf(&mut self) -> TSF_W<'_>
[src]
Bit 11 - Time-stamp flag
pub fn tsovf(&mut self) -> TSOVF_W<'_>
[src]
Bit 12 - Time-stamp overflow flag
pub fn tamp1f(&mut self) -> TAMP1F_W<'_>
[src]
Bit 13 - RTC_TAMP1 detection flag
pub fn tamp2f(&mut self) -> TAMP2F_W<'_>
[src]
Bit 14 - RTC_TAMP2 detection flag
impl W<u32, Reg<u32, _PRER>>
[src]
pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>
[src]
Bits 16:22 - Asynchronous prescaler factor
pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>
[src]
Bits 0:14 - Synchronous prescaler factor
impl W<u32, Reg<u32, _ALRMAR>>
[src]
pub fn msk4(&mut self) -> MSK4_W<'_>
[src]
Bit 31 - Alarm A date mask
pub fn wdsel(&mut self) -> WDSEL_W<'_>
[src]
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 28:29 - Date tens in BCD format.
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 24:27 - Date units or day in BCD format.
pub fn msk3(&mut self) -> MSK3_W<'_>
[src]
Bit 23 - Alarm A hours mask
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format.
pub fn msk2(&mut self) -> MSK2_W<'_>
[src]
Bit 15 - Alarm A minutes mask
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format.
pub fn msk1(&mut self) -> MSK1_W<'_>
[src]
Bit 7 - Alarm A seconds mask
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format.
impl W<u32, Reg<u32, _WPR>>
[src]
impl W<u32, Reg<u32, _SHIFTR>>
[src]
pub fn add1s(&mut self) -> ADD1S_W<'_>
[src]
Bit 31 - Add one second
pub fn subfs(&mut self) -> SUBFS_W<'_>
[src]
Bits 0:14 - Subtract a fraction of a second
impl W<u32, Reg<u32, _CALR>>
[src]
pub fn calp(&mut self) -> CALP_W<'_>
[src]
Bit 15 - Use an 8-second calibration cycle period
pub fn calw8(&mut self) -> CALW8_W<'_>
[src]
Bit 14 - Use a 16-second calibration cycle period
pub fn calw16(&mut self) -> CALW16_W<'_>
[src]
Bit 13 - Use a 16-second calibration cycle period
pub fn calm(&mut self) -> CALM_W<'_>
[src]
Bits 0:8 - Calibration minus
impl W<u32, Reg<u32, _TAFCR>>
[src]
pub fn pc15mode(&mut self) -> PC15MODE_W<'_>
[src]
Bit 23 - PC15 mode
pub fn pc15value(&mut self) -> PC15VALUE_W<'_>
[src]
Bit 22 - PC15 value
pub fn pc14mode(&mut self) -> PC14MODE_W<'_>
[src]
Bit 21 - PC14 mode
pub fn pc14value(&mut self) -> PC14VALUE_W<'_>
[src]
Bit 20 - PC14 value
pub fn pc13mode(&mut self) -> PC13MODE_W<'_>
[src]
Bit 19 - PC13 mode
pub fn pc13value(&mut self) -> PC13VALUE_W<'_>
[src]
Bit 18 - RTC_ALARM output type/PC13 value
pub fn tamp_pudis(&mut self) -> TAMP_PUDIS_W<'_>
[src]
Bit 15 - RTC_TAMPx pull-up disable
pub fn tamp_prch(&mut self) -> TAMP_PRCH_W<'_>
[src]
Bits 13:14 - RTC_TAMPx precharge duration
pub fn tampflt(&mut self) -> TAMPFLT_W<'_>
[src]
Bits 11:12 - RTC_TAMPx filter count
pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>
[src]
Bits 8:10 - Tamper sampling frequency
pub fn tampts(&mut self) -> TAMPTS_W<'_>
[src]
Bit 7 - Activate timestamp on tamper detection event
pub fn tamp2_trg(&mut self) -> TAMP2_TRG_W<'_>
[src]
Bit 4 - Active level for RTC_TAMP2 input
pub fn tamp2e(&mut self) -> TAMP2E_W<'_>
[src]
Bit 3 - RTC_TAMP2 input detection enable
pub fn tampie(&mut self) -> TAMPIE_W<'_>
[src]
Bit 2 - Tamper interrupt enable
pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>
[src]
Bit 1 - Active level for RTC_TAMP1 input
pub fn tamp1e(&mut self) -> TAMP1E_W<'_>
[src]
Bit 0 - RTC_TAMP1 input detection enable
impl W<u32, Reg<u32, _ALRMASSR>>
[src]
pub fn maskss(&mut self) -> MASKSS_W<'_>
[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
[src]
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _BKPR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _CCR2>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _ACR>>
[src]
pub fn latency(&mut self) -> LATENCY_W<'_>
[src]
Bits 0:2 - LATENCY
pub fn prftbe(&mut self) -> PRFTBE_W<'_>
[src]
Bit 4 - PRFTBE
impl W<u32, Reg<u32, _KEYR>>
[src]
impl W<u32, Reg<u32, _OPTKEYR>>
[src]
impl W<u32, Reg<u32, _SR>>
[src]
pub fn eop(&mut self) -> EOP_W<'_>
[src]
Bit 5 - End of operation
pub fn wrprt(&mut self) -> WRPRT_W<'_>
[src]
Bit 4 - Write protection error
pub fn pgerr(&mut self) -> PGERR_W<'_>
[src]
Bit 2 - Programming error
impl W<u32, Reg<u32, _CR>>
[src]
pub fn force_optload(&mut self) -> FORCE_OPTLOAD_W<'_>
[src]
Bit 13 - Force option byte loading
pub fn eopie(&mut self) -> EOPIE_W<'_>
[src]
Bit 12 - End of operation interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 10 - Error interrupt enable
pub fn optwre(&mut self) -> OPTWRE_W<'_>
[src]
Bit 9 - Option bytes write enable
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bit 7 - Lock
pub fn strt(&mut self) -> STRT_W<'_>
[src]
Bit 6 - Start
pub fn opter(&mut self) -> OPTER_W<'_>
[src]
Bit 5 - Option byte erase
pub fn optpg(&mut self) -> OPTPG_W<'_>
[src]
Bit 4 - Option byte programming
pub fn mer(&mut self) -> MER_W<'_>
[src]
Bit 2 - Mass erase
pub fn per(&mut self) -> PER_W<'_>
[src]
Bit 1 - Page erase
pub fn pg(&mut self) -> PG_W<'_>
[src]
Bit 0 - Programming
impl W<u32, Reg<u32, _AR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>
[src]
Bit 1 - Debug Stop Mode
pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>
[src]
Bit 2 - Debug Standby Mode
impl W<u32, Reg<u32, _APB1_FZ>>
[src]
pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>
[src]
Bit 1 - TIM3 counter stopped when core is halted
pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>
[src]
Bit 4 - TIM6 counter stopped when core is halted
pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>
[src]
Bit 5 - TIM7 counter stopped when core is halted
pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>
[src]
Bit 8 - TIM14 counter stopped when core is halted
pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>
[src]
Bit 11 - Debug window watchdog stopped when core is halted
pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>
[src]
Bit 12 - Debug independent watchdog stopped when core is halted
pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>
[src]
Bit 21 - SMBUS timeout mode stopped when core is halted
impl W<u32, Reg<u32, _APB2_FZ>>
[src]
pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>
[src]
Bit 11 - TIM1 counter stopped when core is halted
pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>
[src]
Bit 16 - TIM15 counter stopped when core is halted
pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>
[src]
Bit 17 - TIM16 counter stopped when core is halted
pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>
[src]
Bit 18 - TIM17 counter stopped when core is halted
impl W<u32, Reg<u32, _EP0R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP1R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP2R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP3R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP4R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP5R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP6R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP7R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _CNTR>>
[src]
pub fn fres(&mut self) -> FRES_W<'_>
[src]
Bit 0 - Force USB Reset
pub fn pdwn(&mut self) -> PDWN_W<'_>
[src]
Bit 1 - Power down
pub fn lpmode(&mut self) -> LPMODE_W<'_>
[src]
Bit 2 - Low-power mode
pub fn fsusp(&mut self) -> FSUSP_W<'_>
[src]
Bit 3 - Force suspend
pub fn resume(&mut self) -> RESUME_W<'_>
[src]
Bit 4 - Resume request
pub fn l1resume(&mut self) -> L1RESUME_W<'_>
[src]
Bit 5 - LPM L1 Resume request
pub fn l1reqm(&mut self) -> L1REQM_W<'_>
[src]
Bit 7 - LPM L1 state request interrupt mask
pub fn esofm(&mut self) -> ESOFM_W<'_>
[src]
Bit 8 - Expected start of frame interrupt mask
pub fn sofm(&mut self) -> SOFM_W<'_>
[src]
Bit 9 - Start of frame interrupt mask
pub fn resetm(&mut self) -> RESETM_W<'_>
[src]
Bit 10 - USB reset interrupt mask
pub fn suspm(&mut self) -> SUSPM_W<'_>
[src]
Bit 11 - Suspend mode interrupt mask
pub fn wkupm(&mut self) -> WKUPM_W<'_>
[src]
Bit 12 - Wakeup interrupt mask
pub fn errm(&mut self) -> ERRM_W<'_>
[src]
Bit 13 - Error interrupt mask
pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>
[src]
Bit 14 - Packet memory area over / underrun interrupt mask
pub fn ctrm(&mut self) -> CTRM_W<'_>
[src]
Bit 15 - Correct transfer interrupt mask
impl W<u32, Reg<u32, _ISTR>>
[src]
pub fn l1req(&mut self) -> L1REQ_W<'_>
[src]
Bit 7 - LPM L1 state request
pub fn esof(&mut self) -> ESOF_W<'_>
[src]
Bit 8 - Expected start frame
pub fn sof(&mut self) -> SOF_W<'_>
[src]
Bit 9 - start of frame
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 10 - reset request
pub fn susp(&mut self) -> SUSP_W<'_>
[src]
Bit 11 - Suspend mode request
pub fn wkup(&mut self) -> WKUP_W<'_>
[src]
Bit 12 - Wakeup
pub fn err(&mut self) -> ERR_W<'_>
[src]
Bit 13 - Error
pub fn pmaovr(&mut self) -> PMAOVR_W<'_>
[src]
Bit 14 - Packet memory area over / underrun
impl W<u32, Reg<u32, _DADDR>>
[src]
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 0:6 - Device address
pub fn ef(&mut self) -> EF_W<'_>
[src]
Bit 7 - Enable function
impl W<u32, Reg<u32, _BTABLE>>
[src]
impl W<u32, Reg<u32, _LPMCSR>>
[src]
pub fn lpmen(&mut self) -> LPMEN_W<'_>
[src]
Bit 0 - LPM support enable
pub fn lpmack(&mut self) -> LPMACK_W<'_>
[src]
Bit 1 - LPM Token acknowledge enable
impl W<u32, Reg<u32, _BCDR>>
[src]
pub fn bcden(&mut self) -> BCDEN_W<'_>
[src]
Bit 0 - Battery charging detector (BCD) enable
pub fn dcden(&mut self) -> DCDEN_W<'_>
[src]
Bit 1 - Data contact detection (DCD) mode enable
pub fn pden(&mut self) -> PDEN_W<'_>
[src]
Bit 2 - Primary detection (PD) mode enable
pub fn sden(&mut self) -> SDEN_W<'_>
[src]
Bit 3 - Secondary detection (SD) mode enable
pub fn dppu(&mut self) -> DPPU_W<'_>
[src]
Bit 15 - DP pull-up control
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn enable(&mut self) -> ENABLE_W<'_>
[src]
Bit 0 - Counter enable
pub fn tickint(&mut self) -> TICKINT_W<'_>
[src]
Bit 1 - SysTick exception request enable
pub fn clksource(&mut self) -> CLKSOURCE_W<'_>
[src]
Bit 2 - Clock source selection
pub fn countflag(&mut self) -> COUNTFLAG_W<'_>
[src]
Bit 16 - COUNTFLAG
impl W<u32, Reg<u32, _RVR>>
[src]
impl W<u32, Reg<u32, _CVR>>
[src]
impl W<u32, Reg<u32, _CALIB>>
[src]
pub fn tenms(&mut self) -> TENMS_W<'_>
[src]
Bits 0:23 - Calibration value
pub fn skew(&mut self) -> SKEW_W<'_>
[src]
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
pub fn noref(&mut self) -> NOREF_W<'_>
[src]
Bit 31 - NOREF flag. Reads as zero
impl W<u32, Reg<u32, _DR>>
[src]
impl W<u32, Reg<u32, _IDR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 0 - reset bit
pub fn polysize(&mut self) -> POLYSIZE_W<'_>
[src]
Bits 3:4 - Polynomial size
pub fn rev_in(&mut self) -> REV_IN_W<'_>
[src]
Bits 5:6 - Reverse input data
pub fn rev_out(&mut self) -> REV_OUT_W<'_>
[src]
Bit 7 - Reverse output data
impl W<u32, Reg<u32, _INIT>>
[src]
impl W<u8, Reg<u8, _DR8>>
[src]
impl W<u16, Reg<u16, _DR16>>
[src]
impl W<u32, Reg<u32, _MODER>>
[src]
pub fn moder15(&mut self) -> MODER15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
[src]
pub fn ot15(&mut self) -> OT15_W<'_>
[src]
Bit 15 - Port x configuration bit 15
pub fn ot14(&mut self) -> OT14_W<'_>
[src]
Bit 14 - Port x configuration bit 14
pub fn ot13(&mut self) -> OT13_W<'_>
[src]
Bit 13 - Port x configuration bit 13
pub fn ot12(&mut self) -> OT12_W<'_>
[src]
Bit 12 - Port x configuration bit 12
pub fn ot11(&mut self) -> OT11_W<'_>
[src]
Bit 11 - Port x configuration bit 11
pub fn ot10(&mut self) -> OT10_W<'_>
[src]
Bit 10 - Port x configuration bit 10
pub fn ot9(&mut self) -> OT9_W<'_>
[src]
Bit 9 - Port x configuration bit 9
pub fn ot8(&mut self) -> OT8_W<'_>
[src]
Bit 8 - Port x configuration bit 8
pub fn ot7(&mut self) -> OT7_W<'_>
[src]
Bit 7 - Port x configuration bit 7
pub fn ot6(&mut self) -> OT6_W<'_>
[src]
Bit 6 - Port x configuration bit 6
pub fn ot5(&mut self) -> OT5_W<'_>
[src]
Bit 5 - Port x configuration bit 5
pub fn ot4(&mut self) -> OT4_W<'_>
[src]
Bit 4 - Port x configuration bit 4
pub fn ot3(&mut self) -> OT3_W<'_>
[src]
Bit 3 - Port x configuration bit 3
pub fn ot2(&mut self) -> OT2_W<'_>
[src]
Bit 2 - Port x configuration bit 2
pub fn ot1(&mut self) -> OT1_W<'_>
[src]
Bit 1 - Port x configuration bit 1
pub fn ot0(&mut self) -> OT0_W<'_>
[src]
Bit 0 - Port x configuration bit 0
impl W<u32, Reg<u32, _OSPEEDR>>
[src]
pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
[src]
pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
[src]
pub fn odr15(&mut self) -> ODR15_W<'_>
[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
[src]
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
[src]
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
[src]
Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
[src]
Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
[src]
Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
[src]
Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
[src]
Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
[src]
Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
[src]
Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
[src]
Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
[src]
Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
[src]
Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
[src]
Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
[src]
Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
[src]
Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
[src]
Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
[src]
Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
[src]
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
[src]
pub fn lckk(&mut self) -> LCKK_W<'_>
[src]
Bit 16 - Port x lock bit y
pub fn lck15(&mut self) -> LCK15_W<'_>
[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
[src]
pub fn afrl7(&mut self) -> AFRL7_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
[src]
pub fn afrh15(&mut self) -> AFRH15_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
[src]
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _MODER>>
[src]
pub fn moder15(&mut self) -> MODER15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
[src]
pub fn ot15(&mut self) -> OT15_W<'_>
[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&mut self) -> OT14_W<'_>
[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&mut self) -> OT13_W<'_>
[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&mut self) -> OT12_W<'_>
[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&mut self) -> OT11_W<'_>
[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&mut self) -> OT10_W<'_>
[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&mut self) -> OT9_W<'_>
[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&mut self) -> OT8_W<'_>
[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&mut self) -> OT7_W<'_>
[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&mut self) -> OT6_W<'_>
[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&mut self) -> OT5_W<'_>
[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&mut self) -> OT4_W<'_>
[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&mut self) -> OT3_W<'_>
[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&mut self) -> OT2_W<'_>
[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&mut self) -> OT1_W<'_>
[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&mut self) -> OT0_W<'_>
[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
[src]
pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
[src]
pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
[src]
pub fn odr15(&mut self) -> ODR15_W<'_>
[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
[src]
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
[src]
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
[src]
Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
[src]
Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
[src]
Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
[src]
Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
[src]
Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
[src]
Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
[src]
Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
[src]
Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
[src]
Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
[src]
Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
[src]
Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
[src]
Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
[src]
Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
[src]
Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
[src]
Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
[src]
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
[src]
pub fn lckk(&mut self) -> LCKK_W<'_>
[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&mut self) -> LCK15_W<'_>
[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
[src]
pub fn afrl7(&mut self) -> AFRL7_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
[src]
pub fn afrh15(&mut self) -> AFRH15_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
[src]
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn bidimode(&mut self) -> BIDIMODE_W<'_>
[src]
Bit 15 - Bidirectional data mode enable
pub fn bidioe(&mut self) -> BIDIOE_W<'_>
[src]
Bit 14 - Output enable in bidirectional mode
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 13 - Hardware CRC calculation enable
pub fn crcnext(&mut self) -> CRCNEXT_W<'_>
[src]
Bit 12 - CRC transfer next
pub fn crcl(&mut self) -> CRCL_W<'_>
[src]
Bit 11 - CRC length
pub fn rxonly(&mut self) -> RXONLY_W<'_>
[src]
Bit 10 - Receive only
pub fn ssm(&mut self) -> SSM_W<'_>
[src]
Bit 9 - Software slave management
pub fn ssi(&mut self) -> SSI_W<'_>
[src]
Bit 8 - Internal slave select
pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>
[src]
Bit 7 - Frame format
pub fn spe(&mut self) -> SPE_W<'_>
[src]
Bit 6 - SPI enable
pub fn br(&mut self) -> BR_W<'_>
[src]
Bits 3:5 - Baud rate control
pub fn mstr(&mut self) -> MSTR_W<'_>
[src]
Bit 2 - Master selection
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 1 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 0 - Clock phase
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 0 - Rx buffer DMA enable
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 1 - Tx buffer DMA enable
pub fn ssoe(&mut self) -> SSOE_W<'_>
[src]
Bit 2 - SS output enable
pub fn nssp(&mut self) -> NSSP_W<'_>
[src]
Bit 3 - NSS pulse management
pub fn frf(&mut self) -> FRF_W<'_>
[src]
Bit 4 - Frame format
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 5 - Error interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 6 - RX buffer not empty interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - Tx buffer empty interrupt enable
pub fn ds(&mut self) -> DS_W<'_>
[src]
Bits 8:11 - Data size
pub fn frxth(&mut self) -> FRXTH_W<'_>
[src]
Bit 12 - FIFO reception threshold
pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>
[src]
Bit 13 - Last DMA transfer for reception
pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>
[src]
Bit 14 - Last DMA transfer for transmission
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _DR>>
[src]
impl W<u32, Reg<u32, _CRCPR>>
[src]
impl W<u32, Reg<u32, _I2SCFGR>>
[src]
pub fn i2smod(&mut self) -> I2SMOD_W<'_>
[src]
Bit 11 - I2S mode selection
pub fn i2se(&mut self) -> I2SE_W<'_>
[src]
Bit 10 - I2S Enable
pub fn i2scfg(&mut self) -> I2SCFG_W<'_>
[src]
Bits 8:9 - I2S configuration mode
pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>
[src]
Bit 7 - PCM frame synchronization
pub fn i2sstd(&mut self) -> I2SSTD_W<'_>
[src]
Bits 4:5 - I2S standard selection
pub fn ckpol(&mut self) -> CKPOL_W<'_>
[src]
Bit 3 - Steady state clock polarity
pub fn datlen(&mut self) -> DATLEN_W<'_>
[src]
Bits 1:2 - Data length to be transferred
pub fn chlen(&mut self) -> CHLEN_W<'_>
[src]
Bit 0 - Channel length (number of bits per audio channel)
impl W<u32, Reg<u32, _I2SPR>>
[src]
pub fn mckoe(&mut self) -> MCKOE_W<'_>
[src]
Bit 9 - Master clock output enable
pub fn odd(&mut self) -> ODD_W<'_>
[src]
Bit 8 - Odd factor for the prescaler
pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>
[src]
Bits 0:7 - I2S Linear prescaler
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbp(&mut self) -> DBP_W<'_>
[src]
Bit 8 - Disable backup domain write protection
pub fn pls(&mut self) -> PLS_W<'_>
[src]
Bits 5:7 - PVD level selection
pub fn pvde(&mut self) -> PVDE_W<'_>
[src]
Bit 4 - Power voltage detector enable
pub fn csbf(&mut self) -> CSBF_W<'_>
[src]
Bit 3 - Clear standby flag
pub fn cwuf(&mut self) -> CWUF_W<'_>
[src]
Bit 2 - Clear wakeup flag
pub fn pdds(&mut self) -> PDDS_W<'_>
[src]
Bit 1 - Power down deepsleep
pub fn lpds(&mut self) -> LPDS_W<'_>
[src]
Bit 0 - Low-power deep sleep
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn ewup1(&mut self) -> EWUP1_W<'_>
[src]
Bit 8 - Enable WKUP pin 1
pub fn ewup2(&mut self) -> EWUP2_W<'_>
[src]
Bit 9 - Enable WKUP pin 2
pub fn ewup3(&mut self) -> EWUP3_W<'_>
[src]
Bit 10 - Enable WKUP pin 3
pub fn ewup4(&mut self) -> EWUP4_W<'_>
[src]
Bit 11 - Enable WKUP pin 4
pub fn ewup5(&mut self) -> EWUP5_W<'_>
[src]
Bit 12 - Enable WKUP pin 5
pub fn ewup6(&mut self) -> EWUP6_W<'_>
[src]
Bit 13 - Enable WKUP pin 6
pub fn ewup7(&mut self) -> EWUP7_W<'_>
[src]
Bit 14 - Enable WKUP pin 7
pub fn ewup8(&mut self) -> EWUP8_W<'_>
[src]
Bit 15 - Enable WKUP pin 8
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn pe(&mut self) -> PE_W<'_>
[src]
Bit 0 - Peripheral enable
pub fn txie(&mut self) -> TXIE_W<'_>
[src]
Bit 1 - TX Interrupt enable
pub fn rxie(&mut self) -> RXIE_W<'_>
[src]
Bit 2 - RX Interrupt enable
pub fn addrie(&mut self) -> ADDRIE_W<'_>
[src]
Bit 3 - Address match interrupt enable (slave only)
pub fn nackie(&mut self) -> NACKIE_W<'_>
[src]
Bit 4 - Not acknowledge received interrupt enable
pub fn stopie(&mut self) -> STOPIE_W<'_>
[src]
Bit 5 - STOP detection Interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transfer Complete interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 7 - Error interrupts enable
pub fn dnf(&mut self) -> DNF_W<'_>
[src]
Bits 8:11 - Digital noise filter
pub fn anfoff(&mut self) -> ANFOFF_W<'_>
[src]
Bit 12 - Analog noise filter OFF
pub fn swrst(&mut self) -> SWRST_W<'_>
[src]
Bit 13 - Software reset
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 14 - DMA transmission requests enable
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 15 - DMA reception requests enable
pub fn sbc(&mut self) -> SBC_W<'_>
[src]
Bit 16 - Slave byte control
pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>
[src]
Bit 17 - Clock stretching disable
pub fn wupen(&mut self) -> WUPEN_W<'_>
[src]
Bit 18 - Wakeup from STOP enable
pub fn gcen(&mut self) -> GCEN_W<'_>
[src]
Bit 19 - General call enable
pub fn smbhen(&mut self) -> SMBHEN_W<'_>
[src]
Bit 20 - SMBus Host address enable
pub fn smbden(&mut self) -> SMBDEN_W<'_>
[src]
Bit 21 - SMBus Device Default address enable
pub fn alerten(&mut self) -> ALERTEN_W<'_>
[src]
Bit 22 - SMBUS alert enable
pub fn pecen(&mut self) -> PECEN_W<'_>
[src]
Bit 23 - PEC enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn pecbyte(&mut self) -> PECBYTE_W<'_>
[src]
Bit 26 - Packet error checking byte
pub fn autoend(&mut self) -> AUTOEND_W<'_>
[src]
Bit 25 - Automatic end mode (master mode)
pub fn reload(&mut self) -> RELOAD_W<'_>
[src]
Bit 24 - NBYTES reload mode
pub fn nbytes(&mut self) -> NBYTES_W<'_>
[src]
Bits 16:23 - Number of bytes
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 15 - NACK generation (slave mode)
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bit 14 - Stop generation (master mode)
pub fn start(&mut self) -> START_W<'_>
[src]
Bit 13 - Start generation
pub fn head10r(&mut self) -> HEAD10R_W<'_>
[src]
Bit 12 - 10-bit address header only read direction (master receiver mode)
pub fn add10(&mut self) -> ADD10_W<'_>
[src]
Bit 11 - 10-bit addressing mode (master mode)
pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>
[src]
Bit 10 - Transfer direction (master mode)
pub fn sadd(&mut self) -> SADD_W<'_>
[src]
Bits 0:9 - Slave address bit 9:8 (master mode)
impl W<u32, Reg<u32, _OAR1>>
[src]
pub fn oa1mode(&mut self) -> OA1MODE_W<'_>
[src]
Bit 10 - Own Address 1 10-bit mode
pub fn oa1en(&mut self) -> OA1EN_W<'_>
[src]
Bit 15 - Own Address 1 enable
pub fn oa1(&mut self) -> OA1_W<'_>
[src]
Bits 0:9 - Interface address
impl W<u32, Reg<u32, _OAR2>>
[src]
pub fn oa2(&mut self) -> OA2_W<'_>
[src]
Bits 1:7 - Interface address
pub fn oa2msk(&mut self) -> OA2MSK_W<'_>
[src]
Bits 8:10 - Own Address 2 masks
pub fn oa2en(&mut self) -> OA2EN_W<'_>
[src]
Bit 15 - Own Address 2 enable
impl W<u32, Reg<u32, _TIMINGR>>
[src]
pub fn scll(&mut self) -> SCLL_W<'_>
[src]
Bits 0:7 - SCL low period (master mode)
pub fn sclh(&mut self) -> SCLH_W<'_>
[src]
Bits 8:15 - SCL high period (master mode)
pub fn sdadel(&mut self) -> SDADEL_W<'_>
[src]
Bits 16:19 - Data hold time
pub fn scldel(&mut self) -> SCLDEL_W<'_>
[src]
Bits 20:23 - Data setup time
pub fn presc(&mut self) -> PRESC_W<'_>
[src]
Bits 28:31 - Timing prescaler
impl W<u32, Reg<u32, _TIMEOUTR>>
[src]
pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>
[src]
Bits 0:11 - Bus timeout A
pub fn tidle(&mut self) -> TIDLE_W<'_>
[src]
Bit 12 - Idle clock timeout detection
pub fn timouten(&mut self) -> TIMOUTEN_W<'_>
[src]
Bit 15 - Clock timeout enable
pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>
[src]
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
[src]
Bit 31 - Extended clock timeout enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn txis(&mut self) -> TXIS_W<'_>
[src]
Bit 1 - Transmit interrupt status (transmitters)
pub fn txe(&mut self) -> TXE_W<'_>
[src]
Bit 0 - Transmit data register empty (transmitters)
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn alertcf(&mut self) -> ALERTCF_W<'_>
[src]
Bit 13 - Alert flag clear
pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>
[src]
Bit 12 - Timeout detection flag clear
pub fn peccf(&mut self) -> PECCF_W<'_>
[src]
Bit 11 - PEC Error flag clear
pub fn ovrcf(&mut self) -> OVRCF_W<'_>
[src]
Bit 10 - Overrun/Underrun flag clear
pub fn arlocf(&mut self) -> ARLOCF_W<'_>
[src]
Bit 9 - Arbitration lost flag clear
pub fn berrcf(&mut self) -> BERRCF_W<'_>
[src]
Bit 8 - Bus error flag clear
pub fn stopcf(&mut self) -> STOPCF_W<'_>
[src]
Bit 5 - Stop detection flag clear
pub fn nackcf(&mut self) -> NACKCF_W<'_>
[src]
Bit 4 - Not Acknowledge flag clear
pub fn addrcf(&mut self) -> ADDRCF_W<'_>
[src]
Bit 3 - Address Matched flag clear
impl W<u32, Reg<u32, _TXDR>>
[src]
impl W<u32, Reg<u32, _KR>>
[src]
impl W<u32, Reg<u32, _PR>>
[src]
impl W<u32, Reg<u32, _RLR>>
[src]
impl W<u32, Reg<u32, _WINR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn wdga(&mut self) -> WDGA_W<'_>
[src]
Bit 7 - Activation bit
pub fn t(&mut self) -> T_W<'_>
[src]
Bits 0:6 - 7-bit counter
impl W<u32, Reg<u32, _CFR>>
[src]
pub fn ewi(&mut self) -> EWI_W<'_>
[src]
Bit 9 - Early wakeup interrupt
pub fn w(&mut self) -> W_W<'_>
[src]
Bits 0:6 - 7-bit window value
pub fn wdgtb(&mut self) -> WDGTB_W<'_>
[src]
Bits 7:8 - Timer base
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois4(&mut self) -> OIS4_W<'_>
[src]
Bit 14 - Output Idle state 4
pub fn ois3n(&mut self) -> OIS3N_W<'_>
[src]
Bit 13 - Output Idle state 3
pub fn ois3(&mut self) -> OIS3_W<'_>
[src]
Bit 12 - Output Idle state 3
pub fn ois2n(&mut self) -> OIS2N_W<'_>
[src]
Bit 11 - Output Idle state 2
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output Compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output Compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3ne(&mut self) -> CC3NE_W<'_>
[src]
Bit 10 - Capture/Compare 3 complementary output enable
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2ne(&mut self) -> CC2NE_W<'_>
[src]
Bit 6 - Capture/Compare 2 complementary output enable
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4np(&mut self) -> CC4NP_W<'_>
[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _OR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _EGR>>
[src]
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _IMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Interrupt Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Interrupt Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Interrupt Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Interrupt Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Interrupt Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Interrupt Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Interrupt Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Interrupt Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Interrupt Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Interrupt Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Interrupt Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Interrupt Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Interrupt Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Interrupt Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Interrupt Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Interrupt Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Interrupt Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Interrupt Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Interrupt Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Interrupt Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Interrupt Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Interrupt Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Interrupt Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Interrupt Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Interrupt Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Interrupt Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Interrupt Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Interrupt Mask on line 27
impl W<u32, Reg<u32, _EMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Event Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Event Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Event Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Event Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Event Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Event Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Event Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Event Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Event Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Event Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Event Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Event Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Event Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Event Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Event Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Event Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Event Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Event Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Event Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Event Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Event Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Event Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Event Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Event Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Event Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Event Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Event Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Event Mask on line 27
impl W<u32, Reg<u32, _RTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Rising trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Rising trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Rising trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Rising trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Rising trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Rising trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Rising trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Rising trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
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Bit 8 - Rising trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
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Bit 9 - Rising trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Rising trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Rising trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Rising trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Rising trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Rising trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Rising trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Rising trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Rising trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Rising trigger event configuration of line 19
impl W<u32, Reg<u32, _FTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Falling trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Falling trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Falling trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Falling trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Falling trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Falling trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Falling trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Falling trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
[src]
Bit 8 - Falling trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
[src]
Bit 9 - Falling trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Falling trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Falling trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Falling trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Falling trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Falling trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Falling trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Falling trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Falling trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Falling trigger event configuration of line 19
impl W<u32, Reg<u32, _SWIER>>
[src]
pub fn swier0(&mut self) -> SWIER0_W<'_>
[src]
Bit 0 - Software Interrupt on line 0
pub fn swier1(&mut self) -> SWIER1_W<'_>
[src]
Bit 1 - Software Interrupt on line 1
pub fn swier2(&mut self) -> SWIER2_W<'_>
[src]
Bit 2 - Software Interrupt on line 2
pub fn swier3(&mut self) -> SWIER3_W<'_>
[src]
Bit 3 - Software Interrupt on line 3
pub fn swier4(&mut self) -> SWIER4_W<'_>
[src]
Bit 4 - Software Interrupt on line 4
pub fn swier5(&mut self) -> SWIER5_W<'_>
[src]
Bit 5 - Software Interrupt on line 5
pub fn swier6(&mut self) -> SWIER6_W<'_>
[src]
Bit 6 - Software Interrupt on line 6
pub fn swier7(&mut self) -> SWIER7_W<'_>
[src]
Bit 7 - Software Interrupt on line 7
pub fn swier8(&mut self) -> SWIER8_W<'_>
[src]
Bit 8 - Software Interrupt on line 8
pub fn swier9(&mut self) -> SWIER9_W<'_>
[src]
Bit 9 - Software Interrupt on line 9
pub fn swier10(&mut self) -> SWIER10_W<'_>
[src]
Bit 10 - Software Interrupt on line 10
pub fn swier11(&mut self) -> SWIER11_W<'_>
[src]
Bit 11 - Software Interrupt on line 11
pub fn swier12(&mut self) -> SWIER12_W<'_>
[src]
Bit 12 - Software Interrupt on line 12
pub fn swier13(&mut self) -> SWIER13_W<'_>
[src]
Bit 13 - Software Interrupt on line 13
pub fn swier14(&mut self) -> SWIER14_W<'_>
[src]
Bit 14 - Software Interrupt on line 14
pub fn swier15(&mut self) -> SWIER15_W<'_>
[src]
Bit 15 - Software Interrupt on line 15
pub fn swier16(&mut self) -> SWIER16_W<'_>
[src]
Bit 16 - Software Interrupt on line 16
pub fn swier17(&mut self) -> SWIER17_W<'_>
[src]
Bit 17 - Software Interrupt on line 17
pub fn swier19(&mut self) -> SWIER19_W<'_>
[src]
Bit 19 - Software Interrupt on line 19
impl W<u32, Reg<u32, _PR>>
[src]
pub fn pr0(&mut self) -> PR0_W<'_>
[src]
Bit 0 - Pending bit 0
pub fn pr1(&mut self) -> PR1_W<'_>
[src]
Bit 1 - Pending bit 1
pub fn pr2(&mut self) -> PR2_W<'_>
[src]
Bit 2 - Pending bit 2
pub fn pr3(&mut self) -> PR3_W<'_>
[src]
Bit 3 - Pending bit 3
pub fn pr4(&mut self) -> PR4_W<'_>
[src]
Bit 4 - Pending bit 4
pub fn pr5(&mut self) -> PR5_W<'_>
[src]
Bit 5 - Pending bit 5
pub fn pr6(&mut self) -> PR6_W<'_>
[src]
Bit 6 - Pending bit 6
pub fn pr7(&mut self) -> PR7_W<'_>
[src]
Bit 7 - Pending bit 7
pub fn pr8(&mut self) -> PR8_W<'_>
[src]
Bit 8 - Pending bit 8
pub fn pr9(&mut self) -> PR9_W<'_>
[src]
Bit 9 - Pending bit 9
pub fn pr10(&mut self) -> PR10_W<'_>
[src]
Bit 10 - Pending bit 10
pub fn pr11(&mut self) -> PR11_W<'_>
[src]
Bit 11 - Pending bit 11
pub fn pr12(&mut self) -> PR12_W<'_>
[src]
Bit 12 - Pending bit 12
pub fn pr13(&mut self) -> PR13_W<'_>
[src]
Bit 13 - Pending bit 13
pub fn pr14(&mut self) -> PR14_W<'_>
[src]
Bit 14 - Pending bit 14
pub fn pr15(&mut self) -> PR15_W<'_>
[src]
Bit 15 - Pending bit 15
pub fn pr16(&mut self) -> PR16_W<'_>
[src]
Bit 16 - Pending bit 16
pub fn pr17(&mut self) -> PR17_W<'_>
[src]
Bit 17 - Pending bit 17
pub fn pr19(&mut self) -> PR19_W<'_>
[src]
Bit 19 - Pending bit 19
impl W<u32, Reg<u32, _CR>>
[src]
pub fn en(&mut self) -> EN_W<'_>
[src]
Bit 0 - Channel enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 1 - Transfer complete interrupt enable
pub fn htie(&mut self) -> HTIE_W<'_>
[src]
Bit 2 - Half Transfer interrupt enable
pub fn teie(&mut self) -> TEIE_W<'_>
[src]
Bit 3 - Transfer error interrupt enable
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Data transfer direction
pub fn circ(&mut self) -> CIRC_W<'_>
[src]
Bit 5 - Circular mode
pub fn pinc(&mut self) -> PINC_W<'_>
[src]
Bit 6 - Peripheral increment mode
pub fn minc(&mut self) -> MINC_W<'_>
[src]
Bit 7 - Memory increment mode
pub fn psize(&mut self) -> PSIZE_W<'_>
[src]
Bits 8:9 - Peripheral size
pub fn msize(&mut self) -> MSIZE_W<'_>
[src]
Bits 10:11 - Memory size
pub fn pl(&mut self) -> PL_W<'_>
[src]
Bits 12:13 - Channel Priority level
pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>
[src]
Bit 14 - Memory to memory mode
impl W<u32, Reg<u32, _NDTR>>
[src]
impl W<u32, Reg<u32, _PAR>>
[src]
impl W<u32, Reg<u32, _MAR>>
[src]
impl W<u32, Reg<u32, _IFCR>>
[src]
pub fn cgif1(&mut self) -> CGIF1_W<'_>
[src]
Bit 0 - Channel 1 Global interrupt clear
pub fn ctcif1(&mut self) -> CTCIF1_W<'_>
[src]
Bit 1 - Channel 1 Transfer Complete clear
pub fn chtif1(&mut self) -> CHTIF1_W<'_>
[src]
Bit 2 - Channel 1 Half Transfer clear
pub fn cteif1(&mut self) -> CTEIF1_W<'_>
[src]
Bit 3 - Channel 1 Transfer Error clear
pub fn cgif2(&mut self) -> CGIF2_W<'_>
[src]
Bit 4 - Channel 2 Global interrupt clear
pub fn ctcif2(&mut self) -> CTCIF2_W<'_>
[src]
Bit 5 - Channel 2 Transfer Complete clear
pub fn chtif2(&mut self) -> CHTIF2_W<'_>
[src]
Bit 6 - Channel 2 Half Transfer clear
pub fn cteif2(&mut self) -> CTEIF2_W<'_>
[src]
Bit 7 - Channel 2 Transfer Error clear
pub fn cgif3(&mut self) -> CGIF3_W<'_>
[src]
Bit 8 - Channel 3 Global interrupt clear
pub fn ctcif3(&mut self) -> CTCIF3_W<'_>
[src]
Bit 9 - Channel 3 Transfer Complete clear
pub fn chtif3(&mut self) -> CHTIF3_W<'_>
[src]
Bit 10 - Channel 3 Half Transfer clear
pub fn cteif3(&mut self) -> CTEIF3_W<'_>
[src]
Bit 11 - Channel 3 Transfer Error clear
pub fn cgif4(&mut self) -> CGIF4_W<'_>
[src]
Bit 12 - Channel 4 Global interrupt clear
pub fn ctcif4(&mut self) -> CTCIF4_W<'_>
[src]
Bit 13 - Channel 4 Transfer Complete clear
pub fn chtif4(&mut self) -> CHTIF4_W<'_>
[src]
Bit 14 - Channel 4 Half Transfer clear
pub fn cteif4(&mut self) -> CTEIF4_W<'_>
[src]
Bit 15 - Channel 4 Transfer Error clear
pub fn cgif5(&mut self) -> CGIF5_W<'_>
[src]
Bit 16 - Channel 5 Global interrupt clear
pub fn ctcif5(&mut self) -> CTCIF5_W<'_>
[src]
Bit 17 - Channel 5 Transfer Complete clear
pub fn chtif5(&mut self) -> CHTIF5_W<'_>
[src]
Bit 18 - Channel 5 Half Transfer clear
pub fn cteif5(&mut self) -> CTEIF5_W<'_>
[src]
Bit 19 - Channel 5 Transfer Error clear
pub fn cgif6(&mut self) -> CGIF6_W<'_>
[src]
Bit 20 - Channel 6 Global interrupt clear
pub fn ctcif6(&mut self) -> CTCIF6_W<'_>
[src]
Bit 21 - Channel 6 Transfer Complete clear
pub fn chtif6(&mut self) -> CHTIF6_W<'_>
[src]
Bit 22 - Channel 6 Half Transfer clear
pub fn cteif6(&mut self) -> CTEIF6_W<'_>
[src]
Bit 23 - Channel 6 Transfer Error clear
pub fn cgif7(&mut self) -> CGIF7_W<'_>
[src]
Bit 24 - Channel 7 Global interrupt clear
pub fn ctcif7(&mut self) -> CTCIF7_W<'_>
[src]
Bit 25 - Channel 7 Transfer Complete clear
pub fn chtif7(&mut self) -> CHTIF7_W<'_>
[src]
Bit 26 - Channel 7 Half Transfer clear
pub fn cteif7(&mut self) -> CTEIF7_W<'_>
[src]
Bit 27 - Channel 7 Transfer Error clear
impl W<u32, Reg<u32, _CR>>
[src]
pub fn hsion(&mut self) -> HSION_W<'_>
[src]
Bit 0 - Internal High Speed clock enable
pub fn hsitrim(&mut self) -> HSITRIM_W<'_>
[src]
Bits 3:7 - Internal High Speed clock trimming
pub fn hseon(&mut self) -> HSEON_W<'_>
[src]
Bit 16 - External High Speed clock enable
pub fn hsebyp(&mut self) -> HSEBYP_W<'_>
[src]
Bit 18 - External High Speed clock Bypass
pub fn csson(&mut self) -> CSSON_W<'_>
[src]
Bit 19 - Clock Security System enable
pub fn pllon(&mut self) -> PLLON_W<'_>
[src]
Bit 24 - PLL enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn sw(&mut self) -> SW_W<'_>
[src]
Bits 0:1 - System clock Switch
pub fn hpre(&mut self) -> HPRE_W<'_>
[src]
Bits 4:7 - AHB prescaler
pub fn ppre(&mut self) -> PPRE_W<'_>
[src]
Bits 8:10 - APB Low speed prescaler (APB1)
pub fn adcpre(&mut self) -> ADCPRE_W<'_>
[src]
Bit 14 - APCPRE is deprecated. See ADC field in CFGR2 register.
pub fn pllsrc(&mut self) -> PLLSRC_W<'_>
[src]
Bits 15:16 - PLL input clock source
pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>
[src]
Bit 17 - HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning
pub fn pllmul(&mut self) -> PLLMUL_W<'_>
[src]
Bits 18:21 - PLL Multiplication Factor
pub fn mco(&mut self) -> MCO_W<'_>
[src]
Bits 24:26 - Microcontroller clock output
pub fn mcopre(&mut self) -> MCOPRE_W<'_>
[src]
Bits 28:30 - Microcontroller Clock Output Prescaler
pub fn pllnodiv(&mut self) -> PLLNODIV_W<'_>
[src]
Bit 31 - PLL clock not divided for MCO
impl W<u32, Reg<u32, _CIR>>
[src]
pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>
[src]
Bit 8 - LSI Ready Interrupt Enable
pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>
[src]
Bit 9 - LSE Ready Interrupt Enable
pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>
[src]
Bit 10 - HSI Ready Interrupt Enable
pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>
[src]
Bit 11 - HSE Ready Interrupt Enable
pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>
[src]
Bit 12 - PLL Ready Interrupt Enable
pub fn hsi14rdyie(&mut self) -> HSI14RDYIE_W<'_>
[src]
Bit 13 - HSI14 ready interrupt enable
pub fn hsi48rdyie(&mut self) -> HSI48RDYIE_W<'_>
[src]
Bit 14 - HSI48 ready interrupt enable
pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>
[src]
Bit 16 - LSI Ready Interrupt Clear
pub fn lserdyc(&mut self) -> LSERDYC_W<'_>
[src]
Bit 17 - LSE Ready Interrupt Clear
pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>
[src]
Bit 18 - HSI Ready Interrupt Clear
pub fn hserdyc(&mut self) -> HSERDYC_W<'_>
[src]
Bit 19 - HSE Ready Interrupt Clear
pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>
[src]
Bit 20 - PLL Ready Interrupt Clear
pub fn hsi14rdyc(&mut self) -> HSI14RDYC_W<'_>
[src]
Bit 21 - HSI 14 MHz Ready Interrupt Clear
pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W<'_>
[src]
Bit 22 - HSI48 Ready Interrupt Clear
pub fn cssc(&mut self) -> CSSC_W<'_>
[src]
Bit 23 - Clock security system interrupt clear
impl W<u32, Reg<u32, _APB2RSTR>>
[src]
pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>
[src]
Bit 0 - SYSCFG and COMP reset
pub fn adcrst(&mut self) -> ADCRST_W<'_>
[src]
Bit 9 - ADC interface reset
pub fn tim1rst(&mut self) -> TIM1RST_W<'_>
[src]
Bit 11 - TIM1 timer reset
pub fn spi1rst(&mut self) -> SPI1RST_W<'_>
[src]
Bit 12 - SPI 1 reset
pub fn usart1rst(&mut self) -> USART1RST_W<'_>
[src]
Bit 14 - USART1 reset
pub fn tim15rst(&mut self) -> TIM15RST_W<'_>
[src]
Bit 16 - TIM15 timer reset
pub fn tim16rst(&mut self) -> TIM16RST_W<'_>
[src]
Bit 17 - TIM16 timer reset
pub fn tim17rst(&mut self) -> TIM17RST_W<'_>
[src]
Bit 18 - TIM17 timer reset
pub fn dbgmcurst(&mut self) -> DBGMCURST_W<'_>
[src]
Bit 22 - Debug MCU reset
pub fn usart6rst(&mut self) -> USART6RST_W<'_>
[src]
Bit 5 - USART6 reset
pub fn usart8rst(&mut self) -> USART8RST_W<'_>
[src]
Bit 7 - USART8 reset
pub fn usart7rst(&mut self) -> USART7RST_W<'_>
[src]
Bit 6 - USART7 reset
impl W<u32, Reg<u32, _APB1RSTR>>
[src]
pub fn tim2rst(&mut self) -> TIM2RST_W<'_>
[src]
Bit 0 - Timer 2 reset
pub fn tim3rst(&mut self) -> TIM3RST_W<'_>
[src]
Bit 1 - Timer 3 reset
pub fn tim6rst(&mut self) -> TIM6RST_W<'_>
[src]
Bit 4 - Timer 6 reset
pub fn tim7rst(&mut self) -> TIM7RST_W<'_>
[src]
Bit 5 - TIM7 timer reset
pub fn tim14rst(&mut self) -> TIM14RST_W<'_>
[src]
Bit 8 - Timer 14 reset
pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>
[src]
Bit 11 - Window watchdog reset
pub fn spi2rst(&mut self) -> SPI2RST_W<'_>
[src]
Bit 14 - SPI2 reset
pub fn usart2rst(&mut self) -> USART2RST_W<'_>
[src]
Bit 17 - USART 2 reset
pub fn usart3rst(&mut self) -> USART3RST_W<'_>
[src]
Bit 18 - USART3 reset
pub fn usart4rst(&mut self) -> USART4RST_W<'_>
[src]
Bit 19 - USART4 reset
pub fn usart5rst(&mut self) -> USART5RST_W<'_>
[src]
Bit 20 - USART5 reset
pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>
[src]
Bit 21 - I2C1 reset
pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>
[src]
Bit 22 - I2C2 reset
pub fn usbrst(&mut self) -> USBRST_W<'_>
[src]
Bit 23 - USB interface reset
pub fn canrst(&mut self) -> CANRST_W<'_>
[src]
Bit 25 - CAN interface reset
pub fn crsrst(&mut self) -> CRSRST_W<'_>
[src]
Bit 27 - Clock Recovery System interface reset
pub fn pwrrst(&mut self) -> PWRRST_W<'_>
[src]
Bit 28 - Power interface reset
pub fn dacrst(&mut self) -> DACRST_W<'_>
[src]
Bit 29 - DAC interface reset
pub fn cecrst(&mut self) -> CECRST_W<'_>
[src]
Bit 30 - HDMI CEC reset
impl W<u32, Reg<u32, _AHBENR>>
[src]
pub fn dma1en(&mut self) -> DMA1EN_W<'_>
[src]
Bit 0 - DMA1 clock enable
pub fn dma2en(&mut self) -> DMA2EN_W<'_>
[src]
Bit 1 - DMA2 clock enable
pub fn sramen(&mut self) -> SRAMEN_W<'_>
[src]
Bit 2 - SRAM interface clock enable
pub fn flitfen(&mut self) -> FLITFEN_W<'_>
[src]
Bit 4 - FLITF clock enable
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 6 - CRC clock enable
pub fn iopaen(&mut self) -> IOPAEN_W<'_>
[src]
Bit 17 - I/O port A clock enable
pub fn iopben(&mut self) -> IOPBEN_W<'_>
[src]
Bit 18 - I/O port B clock enable
pub fn iopcen(&mut self) -> IOPCEN_W<'_>
[src]
Bit 19 - I/O port C clock enable
pub fn iopden(&mut self) -> IOPDEN_W<'_>
[src]
Bit 20 - I/O port D clock enable
pub fn iopfen(&mut self) -> IOPFEN_W<'_>
[src]
Bit 22 - I/O port F clock enable
pub fn tscen(&mut self) -> TSCEN_W<'_>
[src]
Bit 24 - Touch sensing controller clock enable
pub fn iopeen(&mut self) -> IOPEEN_W<'_>
[src]
Bit 21 - I/O port E clock enable
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - DMA clock enable
impl W<u32, Reg<u32, _APB2ENR>>
[src]
pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>
[src]
Bit 0 - SYSCFG clock enable
pub fn adcen(&mut self) -> ADCEN_W<'_>
[src]
Bit 9 - ADC 1 interface clock enable
pub fn tim1en(&mut self) -> TIM1EN_W<'_>
[src]
Bit 11 - TIM1 Timer clock enable
pub fn spi1en(&mut self) -> SPI1EN_W<'_>
[src]
Bit 12 - SPI 1 clock enable
pub fn usart1en(&mut self) -> USART1EN_W<'_>
[src]
Bit 14 - USART1 clock enable
pub fn tim15en(&mut self) -> TIM15EN_W<'_>
[src]
Bit 16 - TIM15 timer clock enable
pub fn tim16en(&mut self) -> TIM16EN_W<'_>
[src]
Bit 17 - TIM16 timer clock enable
pub fn tim17en(&mut self) -> TIM17EN_W<'_>
[src]
Bit 18 - TIM17 timer clock enable
pub fn dbgmcuen(&mut self) -> DBGMCUEN_W<'_>
[src]
Bit 22 - MCU debug module clock enable
pub fn usart6en(&mut self) -> USART6EN_W<'_>
[src]
Bit 5 - USART6 clock enable
pub fn usart8en(&mut self) -> USART8EN_W<'_>
[src]
Bit 7 - USART8 clock enable
pub fn usart7en(&mut self) -> USART7EN_W<'_>
[src]
Bit 6 - USART7 clock enable
impl W<u32, Reg<u32, _APB1ENR>>
[src]
pub fn tim2en(&mut self) -> TIM2EN_W<'_>
[src]
Bit 0 - Timer 2 clock enable
pub fn tim3en(&mut self) -> TIM3EN_W<'_>
[src]
Bit 1 - Timer 3 clock enable
pub fn tim6en(&mut self) -> TIM6EN_W<'_>
[src]
Bit 4 - Timer 6 clock enable
pub fn tim7en(&mut self) -> TIM7EN_W<'_>
[src]
Bit 5 - TIM7 timer clock enable
pub fn tim14en(&mut self) -> TIM14EN_W<'_>
[src]
Bit 8 - Timer 14 clock enable
pub fn wwdgen(&mut self) -> WWDGEN_W<'_>
[src]
Bit 11 - Window watchdog clock enable
pub fn spi2en(&mut self) -> SPI2EN_W<'_>
[src]
Bit 14 - SPI 2 clock enable
pub fn usart2en(&mut self) -> USART2EN_W<'_>
[src]
Bit 17 - USART 2 clock enable
pub fn usart3en(&mut self) -> USART3EN_W<'_>
[src]
Bit 18 - USART3 clock enable
pub fn usart4en(&mut self) -> USART4EN_W<'_>
[src]
Bit 19 - USART4 clock enable
pub fn usart5en(&mut self) -> USART5EN_W<'_>
[src]
Bit 20 - USART5 clock enable
pub fn i2c1en(&mut self) -> I2C1EN_W<'_>
[src]
Bit 21 - I2C 1 clock enable
pub fn i2c2en(&mut self) -> I2C2EN_W<'_>
[src]
Bit 22 - I2C 2 clock enable
pub fn usben(&mut self) -> USBEN_W<'_>
[src]
Bit 23 - USB interface clock enable
pub fn canen(&mut self) -> CANEN_W<'_>
[src]
Bit 25 - CAN interface clock enable
pub fn crsen(&mut self) -> CRSEN_W<'_>
[src]
Bit 27 - Clock Recovery System interface clock enable
pub fn pwren(&mut self) -> PWREN_W<'_>
[src]
Bit 28 - Power interface clock enable
pub fn dacen(&mut self) -> DACEN_W<'_>
[src]
Bit 29 - DAC interface clock enable
pub fn cecen(&mut self) -> CECEN_W<'_>
[src]
Bit 30 - HDMI CEC interface clock enable
impl W<u32, Reg<u32, _BDCR>>
[src]
pub fn lseon(&mut self) -> LSEON_W<'_>
[src]
Bit 0 - External Low Speed oscillator enable
pub fn lsebyp(&mut self) -> LSEBYP_W<'_>
[src]
Bit 2 - External Low Speed oscillator bypass
pub fn lsedrv(&mut self) -> LSEDRV_W<'_>
[src]
Bits 3:4 - LSE oscillator drive capability
pub fn rtcsel(&mut self) -> RTCSEL_W<'_>
[src]
Bits 8:9 - RTC clock source selection
pub fn rtcen(&mut self) -> RTCEN_W<'_>
[src]
Bit 15 - RTC clock enable
pub fn bdrst(&mut self) -> BDRST_W<'_>
[src]
Bit 16 - Backup domain software reset
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn lsion(&mut self) -> LSION_W<'_>
[src]
Bit 0 - Internal low speed oscillator enable
pub fn rmvf(&mut self) -> RMVF_W<'_>
[src]
Bit 24 - Remove reset flag
pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>
[src]
Bit 25 - Option byte loader reset flag
pub fn pinrstf(&mut self) -> PINRSTF_W<'_>
[src]
Bit 26 - PIN reset flag
pub fn porrstf(&mut self) -> PORRSTF_W<'_>
[src]
Bit 27 - POR/PDR reset flag
pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>
[src]
Bit 28 - Software reset flag
pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>
[src]
Bit 29 - Independent watchdog reset flag
pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>
[src]
Bit 30 - Window watchdog reset flag
pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>
[src]
Bit 31 - Low-power reset flag
pub fn v18pwrrstf(&mut self) -> V18PWRRSTF_W<'_>
[src]
Bit 23 - 1.8 V domain reset flag
impl W<u32, Reg<u32, _AHBRSTR>>
[src]
pub fn ioparst(&mut self) -> IOPARST_W<'_>
[src]
Bit 17 - I/O port A reset
pub fn iopbrst(&mut self) -> IOPBRST_W<'_>
[src]
Bit 18 - I/O port B reset
pub fn iopcrst(&mut self) -> IOPCRST_W<'_>
[src]
Bit 19 - I/O port C reset
pub fn iopdrst(&mut self) -> IOPDRST_W<'_>
[src]
Bit 20 - I/O port D reset
pub fn iopfrst(&mut self) -> IOPFRST_W<'_>
[src]
Bit 22 - I/O port F reset
pub fn tscrst(&mut self) -> TSCRST_W<'_>
[src]
Bit 24 - Touch sensing controller reset
pub fn ioperst(&mut self) -> IOPERST_W<'_>
[src]
Bit 21 - I/O port E reset
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _CFGR3>>
[src]
pub fn usart1sw(&mut self) -> USART1SW_W<'_>
[src]
Bits 0:1 - USART1 clock source selection
pub fn i2c1sw(&mut self) -> I2C1SW_W<'_>
[src]
Bit 4 - I2C1 clock source selection
pub fn cecsw(&mut self) -> CECSW_W<'_>
[src]
Bit 6 - HDMI CEC clock source selection
pub fn usbsw(&mut self) -> USBSW_W<'_>
[src]
Bit 7 - USB clock source selection
pub fn adcsw(&mut self) -> ADCSW_W<'_>
[src]
Bit 8 - ADCSW is deprecated. See ADC field in CFGR2 register.
pub fn usart2sw(&mut self) -> USART2SW_W<'_>
[src]
Bits 16:17 - USART2 clock source selection
pub fn usart3sw(&mut self) -> USART3SW_W<'_>
[src]
Bits 18:19 - USART3 clock source
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn hsi14on(&mut self) -> HSI14ON_W<'_>
[src]
Bit 0 - HSI14 clock enable
pub fn hsi14dis(&mut self) -> HSI14DIS_W<'_>
[src]
Bit 2 - HSI14 clock request from ADC disable
pub fn hsi14trim(&mut self) -> HSI14TRIM_W<'_>
[src]
Bits 3:7 - HSI14 clock trimming
pub fn hsi48on(&mut self) -> HSI48ON_W<'_>
[src]
Bit 16 - HSI48 clock enable
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>
[src]
Bits 0:1 - Memory mapping selection bits
pub fn adc_dma_rmp(&mut self) -> ADC_DMA_RMP_W<'_>
[src]
Bit 8 - ADC DMA remapping bit
pub fn usart1_tx_dma_rmp(&mut self) -> USART1_TX_DMA_RMP_W<'_>
[src]
Bit 9 - USART1_TX DMA remapping bit
pub fn usart1_rx_dma_rmp(&mut self) -> USART1_RX_DMA_RMP_W<'_>
[src]
Bit 10 - USART1_RX DMA request remapping bit
pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<'_>
[src]
Bit 11 - TIM16 DMA request remapping bit
pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<'_>
[src]
Bit 12 - TIM17 DMA request remapping bit
pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>
[src]
Bit 16 - Fast Mode Plus (FM plus) driving capability activation bits.
pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>
[src]
Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>
[src]
Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>
[src]
Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>
[src]
Bit 20 - FM+ driving capability activation for I2C1
pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>
[src]
Bit 21 - FM+ driving capability activation for I2C2
pub fn spi2_dma_rmp(&mut self) -> SPI2_DMA_RMP_W<'_>
[src]
Bit 24 - SPI2 DMA request remapping bit
pub fn usart2_dma_rmp(&mut self) -> USART2_DMA_RMP_W<'_>
[src]
Bit 25 - USART2 DMA request remapping bit
pub fn usart3_dma_rmp(&mut self) -> USART3_DMA_RMP_W<'_>
[src]
Bit 26 - USART3 DMA request remapping bit
pub fn i2c1_dma_rmp(&mut self) -> I2C1_DMA_RMP_W<'_>
[src]
Bit 27 - I2C1 DMA request remapping bit
pub fn tim1_dma_rmp(&mut self) -> TIM1_DMA_RMP_W<'_>
[src]
Bit 28 - TIM1 DMA request remapping bit
pub fn tim2_dma_rmp(&mut self) -> TIM2_DMA_RMP_W<'_>
[src]
Bit 29 - TIM2 DMA request remapping bit
pub fn tim3_dma_rmp(&mut self) -> TIM3_DMA_RMP_W<'_>
[src]
Bit 30 - TIM3 DMA request remapping bit
pub fn ir_mod(&mut self) -> IR_MOD_W<'_>
[src]
Bits 6:7 - IR Modulation Envelope signal selection
pub fn tim16_dma_rmp2(&mut self) -> TIM16_DMA_RMP2_W<'_>
[src]
Bit 13 - TIM16 alternate DMA request remapping bit
pub fn tim17_dma_rmp2(&mut self) -> TIM17_DMA_RMP2_W<'_>
[src]
Bit 14 - TIM17 alternate DMA request remapping bit
pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>
[src]
Bit 4 - PA11 and PA12 remapping bit for small packages (28 and 20 pins)
pub fn i2c_pa9_fmp(&mut self) -> I2C_PA9_FMP_W<'_>
[src]
Bit 22 - Fast Mode Plus (FM+) driving capability activation bits
pub fn i2c_pa10_fmp(&mut self) -> I2C_PA10_FMP_W<'_>
[src]
Bit 23 - Fast Mode Plus (FM+) driving capability activation bits
impl W<u32, Reg<u32, _EXTICR1>>
[src]
pub fn exti3(&mut self) -> EXTI3_W<'_>
[src]
Bits 12:15 - EXTI 3 configuration bits
pub fn exti2(&mut self) -> EXTI2_W<'_>
[src]
Bits 8:11 - EXTI 2 configuration bits
pub fn exti1(&mut self) -> EXTI1_W<'_>
[src]
Bits 4:7 - EXTI 1 configuration bits
pub fn exti0(&mut self) -> EXTI0_W<'_>
[src]
Bits 0:3 - EXTI 0 configuration bits
impl W<u32, Reg<u32, _EXTICR2>>
[src]
pub fn exti7(&mut self) -> EXTI7_W<'_>
[src]
Bits 12:15 - EXTI 7 configuration bits
pub fn exti6(&mut self) -> EXTI6_W<'_>
[src]
Bits 8:11 - EXTI 6 configuration bits
pub fn exti5(&mut self) -> EXTI5_W<'_>
[src]
Bits 4:7 - EXTI 5 configuration bits
pub fn exti4(&mut self) -> EXTI4_W<'_>
[src]
Bits 0:3 - EXTI 4 configuration bits
impl W<u32, Reg<u32, _EXTICR3>>
[src]
pub fn exti11(&mut self) -> EXTI11_W<'_>
[src]
Bits 12:15 - EXTI 11 configuration bits
pub fn exti10(&mut self) -> EXTI10_W<'_>
[src]
Bits 8:11 - EXTI 10 configuration bits
pub fn exti9(&mut self) -> EXTI9_W<'_>
[src]
Bits 4:7 - EXTI 9 configuration bits
pub fn exti8(&mut self) -> EXTI8_W<'_>
[src]
Bits 0:3 - EXTI 8 configuration bits
impl W<u32, Reg<u32, _EXTICR4>>
[src]
pub fn exti15(&mut self) -> EXTI15_W<'_>
[src]
Bits 12:15 - EXTI 15 configuration bits
pub fn exti14(&mut self) -> EXTI14_W<'_>
[src]
Bits 8:11 - EXTI 14 configuration bits
pub fn exti13(&mut self) -> EXTI13_W<'_>
[src]
Bits 4:7 - EXTI 13 configuration bits
pub fn exti12(&mut self) -> EXTI12_W<'_>
[src]
Bits 0:3 - EXTI 12 configuration bits
impl W<u32, Reg<u32, _CFGR2>>
[src]
pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>
[src]
Bit 8 - SRAM parity flag
pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>
[src]
Bit 2 - PVD lock enable bit
pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>
[src]
Bit 1 - SRAM parity lock bit
pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>
[src]
Bit 0 - Cortex-M0 LOCKUP bit enable bit
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn awd(&mut self) -> AWD_W<'_>
[src]
Bit 7 - Analog watchdog flag
pub fn ovr(&mut self) -> OVR_W<'_>
[src]
Bit 4 - ADC overrun
pub fn eoseq(&mut self) -> EOSEQ_W<'_>
[src]
Bit 3 - End of sequence flag
pub fn eoc(&mut self) -> EOC_W<'_>
[src]
Bit 2 - End of conversion flag
pub fn eosmp(&mut self) -> EOSMP_W<'_>
[src]
Bit 1 - End of sampling flag
pub fn adrdy(&mut self) -> ADRDY_W<'_>
[src]
Bit 0 - ADC ready
impl W<u32, Reg<u32, _IER>>
[src]
pub fn awdie(&mut self) -> AWDIE_W<'_>
[src]
Bit 7 - Analog watchdog interrupt enable
pub fn ovrie(&mut self) -> OVRIE_W<'_>
[src]
Bit 4 - Overrun interrupt enable
pub fn eoseqie(&mut self) -> EOSEQIE_W<'_>
[src]
Bit 3 - End of conversion sequence interrupt enable
pub fn eocie(&mut self) -> EOCIE_W<'_>
[src]
Bit 2 - End of conversion interrupt enable
pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>
[src]
Bit 1 - End of sampling flag interrupt enable
pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>
[src]
Bit 0 - ADC ready interrupt enable
impl W<u32, Reg<u32, _CR>>
[src]
pub fn adcal(&mut self) -> ADCAL_W<'_>
[src]
Bit 31 - ADC calibration
pub fn adstp(&mut self) -> ADSTP_W<'_>
[src]
Bit 4 - ADC stop conversion command
pub fn adstart(&mut self) -> ADSTART_W<'_>
[src]
Bit 2 - ADC start conversion command
pub fn addis(&mut self) -> ADDIS_W<'_>
[src]
Bit 1 - ADC disable command
pub fn aden(&mut self) -> ADEN_W<'_>
[src]
Bit 0 - ADC enable command
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn awdch(&mut self) -> AWDCH_W<'_>
[src]
Bits 26:30 - Analog watchdog channel selection
pub fn awden(&mut self) -> AWDEN_W<'_>
[src]
Bit 23 - Analog watchdog enable
pub fn awdsgl(&mut self) -> AWDSGL_W<'_>
[src]
Bit 22 - Enable the watchdog on a single channel or on all channels
pub fn discen(&mut self) -> DISCEN_W<'_>
[src]
Bit 16 - Discontinuous mode
pub fn autoff(&mut self) -> AUTOFF_W<'_>
[src]
Bit 15 - Auto-off mode
pub fn autdly(&mut self) -> AUTDLY_W<'_>
[src]
Bit 14 - Auto-delayed conversion mode
pub fn cont(&mut self) -> CONT_W<'_>
[src]
Bit 13 - Single / continuous conversion mode
pub fn ovrmod(&mut self) -> OVRMOD_W<'_>
[src]
Bit 12 - Overrun management mode
pub fn exten(&mut self) -> EXTEN_W<'_>
[src]
Bits 10:11 - External trigger enable and polarity selection
pub fn extsel(&mut self) -> EXTSEL_W<'_>
[src]
Bits 6:8 - External trigger selection
pub fn align(&mut self) -> ALIGN_W<'_>
[src]
Bit 5 - Data alignment
pub fn res(&mut self) -> RES_W<'_>
[src]
Bits 3:4 - Data resolution
pub fn scandir(&mut self) -> SCANDIR_W<'_>
[src]
Bit 2 - Scan sequence direction
pub fn dmacfg(&mut self) -> DMACFG_W<'_>
[src]
Bit 1 - Direct memery access configuration
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - Direct memory access enable
pub fn wait(&mut self) -> WAIT_W<'_>
[src]
Bit 14 - Wait conversion mode
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _SMPR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 16:27 - Analog watchdog higher threshold
pub fn lt(&mut self) -> LT_W<'_>
[src]
Bits 0:11 - Analog watchdog lower threshold
impl W<u32, Reg<u32, _CHSELR>>
[src]
pub fn chsel18(&mut self) -> CHSEL18_W<'_>
[src]
Bit 18 - Channel-x selection
pub fn chsel17(&mut self) -> CHSEL17_W<'_>
[src]
Bit 17 - Channel-x selection
pub fn chsel16(&mut self) -> CHSEL16_W<'_>
[src]
Bit 16 - Channel-x selection
pub fn chsel15(&mut self) -> CHSEL15_W<'_>
[src]
Bit 15 - Channel-x selection
pub fn chsel14(&mut self) -> CHSEL14_W<'_>
[src]
Bit 14 - Channel-x selection
pub fn chsel13(&mut self) -> CHSEL13_W<'_>
[src]
Bit 13 - Channel-x selection
pub fn chsel12(&mut self) -> CHSEL12_W<'_>
[src]
Bit 12 - Channel-x selection
pub fn chsel11(&mut self) -> CHSEL11_W<'_>
[src]
Bit 11 - Channel-x selection
pub fn chsel10(&mut self) -> CHSEL10_W<'_>
[src]
Bit 10 - Channel-x selection
pub fn chsel9(&mut self) -> CHSEL9_W<'_>
[src]
Bit 9 - Channel-x selection
pub fn chsel8(&mut self) -> CHSEL8_W<'_>
[src]
Bit 8 - Channel-x selection
pub fn chsel7(&mut self) -> CHSEL7_W<'_>
[src]
Bit 7 - Channel-x selection
pub fn chsel6(&mut self) -> CHSEL6_W<'_>
[src]
Bit 6 - Channel-x selection
pub fn chsel5(&mut self) -> CHSEL5_W<'_>
[src]
Bit 5 - Channel-x selection
pub fn chsel4(&mut self) -> CHSEL4_W<'_>
[src]
Bit 4 - Channel-x selection
pub fn chsel3(&mut self) -> CHSEL3_W<'_>
[src]
Bit 3 - Channel-x selection
pub fn chsel2(&mut self) -> CHSEL2_W<'_>
[src]
Bit 2 - Channel-x selection
pub fn chsel1(&mut self) -> CHSEL1_W<'_>
[src]
Bit 1 - Channel-x selection
pub fn chsel0(&mut self) -> CHSEL0_W<'_>
[src]
Bit 0 - Channel-x selection
impl W<u32, Reg<u32, _CCR>>
[src]
pub fn vbaten(&mut self) -> VBATEN_W<'_>
[src]
Bit 24 - VBAT enable
pub fn tsen(&mut self) -> TSEN_W<'_>
[src]
Bit 23 - Temperature sensor enable
pub fn vrefen(&mut self) -> VREFEN_W<'_>
[src]
Bit 22 - Temperature sensor and VREFINT enable
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ue(&mut self) -> UE_W<'_>
[src]
Bit 0 - USART enable
pub fn uesm(&mut self) -> UESM_W<'_>
[src]
Bit 1 - USART enable in Stop mode
pub fn re(&mut self) -> RE_W<'_>
[src]
Bit 2 - Receiver enable
pub fn te(&mut self) -> TE_W<'_>
[src]
Bit 3 - Transmitter enable
pub fn idleie(&mut self) -> IDLEIE_W<'_>
[src]
Bit 4 - IDLE interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 5 - RXNE interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transmission complete interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - interrupt enable
pub fn peie(&mut self) -> PEIE_W<'_>
[src]
Bit 8 - PE interrupt enable
pub fn ps(&mut self) -> PS_W<'_>
[src]
Bit 9 - Parity selection
pub fn pce(&mut self) -> PCE_W<'_>
[src]
Bit 10 - Parity control enable
pub fn wake(&mut self) -> WAKE_W<'_>
[src]
Bit 11 - Receiver wakeup method
pub fn m0(&mut self) -> M0_W<'_>
[src]
Bit 12 - Word length
pub fn mme(&mut self) -> MME_W<'_>
[src]
Bit 13 - Mute mode enable
pub fn cmie(&mut self) -> CMIE_W<'_>
[src]
Bit 14 - Character match interrupt enable
pub fn over8(&mut self) -> OVER8_W<'_>
[src]
Bit 15 - Oversampling mode
pub fn dedt(&mut self) -> DEDT_W<'_>
[src]
Bits 16:20 - Driver Enable deassertion time
pub fn deat(&mut self) -> DEAT_W<'_>
[src]
Bits 21:25 - Driver Enable assertion time
pub fn rtoie(&mut self) -> RTOIE_W<'_>
[src]
Bit 26 - Receiver timeout interrupt enable
pub fn eobie(&mut self) -> EOBIE_W<'_>
[src]
Bit 27 - End of Block interrupt enable
pub fn m1(&mut self) -> M1_W<'_>
[src]
Bit 28 - Word length
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rtoen(&mut self) -> RTOEN_W<'_>
[src]
Bit 23 - Receiver timeout enable
pub fn abrmod(&mut self) -> ABRMOD_W<'_>
[src]
Bits 21:22 - Auto baud rate mode
pub fn abren(&mut self) -> ABREN_W<'_>
[src]
Bit 20 - Auto baud rate enable
pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>
[src]
Bit 19 - Most significant bit first
pub fn datainv(&mut self) -> DATAINV_W<'_>
[src]
Bit 18 - Binary data inversion
pub fn txinv(&mut self) -> TXINV_W<'_>
[src]
Bit 17 - TX pin active level inversion
pub fn rxinv(&mut self) -> RXINV_W<'_>
[src]
Bit 16 - RX pin active level inversion
pub fn swap(&mut self) -> SWAP_W<'_>
[src]
Bit 15 - Swap TX/RX pins
pub fn linen(&mut self) -> LINEN_W<'_>
[src]
Bit 14 - LIN mode enable
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bits 12:13 - STOP bits
pub fn clken(&mut self) -> CLKEN_W<'_>
[src]
Bit 11 - Clock enable
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 10 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 9 - Clock phase
pub fn lbcl(&mut self) -> LBCL_W<'_>
[src]
Bit 8 - Last bit clock pulse
pub fn lbdie(&mut self) -> LBDIE_W<'_>
[src]
Bit 6 - LIN break detection interrupt enable
pub fn lbdl(&mut self) -> LBDL_W<'_>
[src]
Bit 5 - LIN break detection length
pub fn addm7(&mut self) -> ADDM7_W<'_>
[src]
Bit 4 - 7-bit Address Detection/4-bit Address Detection
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 24:31 - Address of the USART node
impl W<u32, Reg<u32, _CR3>>
[src]
pub fn wufie(&mut self) -> WUFIE_W<'_>
[src]
Bit 22 - Wakeup from Stop mode interrupt enable
pub fn wus(&mut self) -> WUS_W<'_>
[src]
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
pub fn scarcnt(&mut self) -> SCARCNT_W<'_>
[src]
Bits 17:19 - Smartcard auto-retry count
pub fn dep(&mut self) -> DEP_W<'_>
[src]
Bit 15 - Driver enable polarity selection
pub fn dem(&mut self) -> DEM_W<'_>
[src]
Bit 14 - Driver enable mode
pub fn ddre(&mut self) -> DDRE_W<'_>
[src]
Bit 13 - DMA Disable on Reception Error
pub fn ovrdis(&mut self) -> OVRDIS_W<'_>
[src]
Bit 12 - Overrun Disable
pub fn onebit(&mut self) -> ONEBIT_W<'_>
[src]
Bit 11 - One sample bit method enable
pub fn ctsie(&mut self) -> CTSIE_W<'_>
[src]
Bit 10 - CTS interrupt enable
pub fn ctse(&mut self) -> CTSE_W<'_>
[src]
Bit 9 - CTS enable
pub fn rtse(&mut self) -> RTSE_W<'_>
[src]
Bit 8 - RTS enable
pub fn dmat(&mut self) -> DMAT_W<'_>
[src]
Bit 7 - DMA enable transmitter
pub fn dmar(&mut self) -> DMAR_W<'_>
[src]
Bit 6 - DMA enable receiver
pub fn scen(&mut self) -> SCEN_W<'_>
[src]
Bit 5 - Smartcard mode enable
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 4 - Smartcard NACK enable
pub fn hdsel(&mut self) -> HDSEL_W<'_>
[src]
Bit 3 - Half-duplex selection
pub fn irlp(&mut self) -> IRLP_W<'_>
[src]
Bit 2 - IrDA low-power
pub fn iren(&mut self) -> IREN_W<'_>
[src]
Bit 1 - IrDA mode enable
pub fn eie(&mut self) -> EIE_W<'_>
[src]
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
[src]
impl W<u32, Reg<u32, _GTPR>>
[src]
pub fn gt(&mut self) -> GT_W<'_>
[src]
Bits 8:15 - Guard time value
pub fn psc(&mut self) -> PSC_W<'_>
[src]
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
[src]
pub fn blen(&mut self) -> BLEN_W<'_>
[src]
Bits 24:31 - Block Length
pub fn rto(&mut self) -> RTO_W<'_>
[src]
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
[src]
pub fn txfrq(&mut self) -> TXFRQ_W<'_>
[src]
Bit 4 - Transmit data flush request
pub fn rxfrq(&mut self) -> RXFRQ_W<'_>
[src]
Bit 3 - Receive data flush request
pub fn mmrq(&mut self) -> MMRQ_W<'_>
[src]
Bit 2 - Mute mode request
pub fn sbkrq(&mut self) -> SBKRQ_W<'_>
[src]
Bit 1 - Send break request
pub fn abrrq(&mut self) -> ABRRQ_W<'_>
[src]
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn wucf(&mut self) -> WUCF_W<'_>
[src]
Bit 20 - Wakeup from Stop mode clear flag
pub fn cmcf(&mut self) -> CMCF_W<'_>
[src]
Bit 17 - Character match clear flag
pub fn eobcf(&mut self) -> EOBCF_W<'_>
[src]
Bit 12 - End of timeout clear flag
pub fn rtocf(&mut self) -> RTOCF_W<'_>
[src]
Bit 11 - Receiver timeout clear flag
pub fn ctscf(&mut self) -> CTSCF_W<'_>
[src]
Bit 9 - CTS clear flag
pub fn lbdcf(&mut self) -> LBDCF_W<'_>
[src]
Bit 8 - LIN break detection clear flag
pub fn tccf(&mut self) -> TCCF_W<'_>
[src]
Bit 6 - Transmission complete clear flag
pub fn idlecf(&mut self) -> IDLECF_W<'_>
[src]
Bit 4 - Idle line detected clear flag
pub fn orecf(&mut self) -> ORECF_W<'_>
[src]
Bit 3 - Overrun error clear flag
pub fn ncf(&mut self) -> NCF_W<'_>
[src]
Bit 2 - Noise detected clear flag
pub fn fecf(&mut self) -> FECF_W<'_>
[src]
Bit 1 - Framing error clear flag
pub fn pecf(&mut self) -> PECF_W<'_>
[src]
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _DR>>
[src]
pub fn yt(&mut self) -> YT_W<'_>
[src]
Bits 20:23 - Year tens in BCD format
pub fn yu(&mut self) -> YU_W<'_>
[src]
Bits 16:19 - Year units in BCD format
pub fn wdu(&mut self) -> WDU_W<'_>
[src]
Bits 13:15 - Week day units
pub fn mt(&mut self) -> MT_W<'_>
[src]
Bit 12 - Month tens in BCD format
pub fn mu(&mut self) -> MU_W<'_>
[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 0:3 - Date units in BCD format
impl W<u32, Reg<u32, _CR>>
[src]
pub fn tsedge(&mut self) -> TSEDGE_W<'_>
[src]
Bit 3 - Time-stamp event active edge
pub fn refckon(&mut self) -> REFCKON_W<'_>
[src]
Bit 4 - RTC_REFIN reference clock detection enable (50 or 60 Hz)
pub fn bypshad(&mut self) -> BYPSHAD_W<'_>
[src]
Bit 5 - Bypass the shadow registers
pub fn fmt(&mut self) -> FMT_W<'_>
[src]
Bit 6 - Hour format
pub fn alrae(&mut self) -> ALRAE_W<'_>
[src]
Bit 8 - Alarm A enable
pub fn tse(&mut self) -> TSE_W<'_>
[src]
Bit 11 - timestamp enable
pub fn alraie(&mut self) -> ALRAIE_W<'_>
[src]
Bit 12 - Alarm A interrupt enable
pub fn tsie(&mut self) -> TSIE_W<'_>
[src]
Bit 15 - Time-stamp interrupt enable
pub fn add1h(&mut self) -> ADD1H_W<'_>
[src]
Bit 16 - Add 1 hour (summer time change)
pub fn sub1h(&mut self) -> SUB1H_W<'_>
[src]
Bit 17 - Subtract 1 hour (winter time change)
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 18 - Backup
pub fn cosel(&mut self) -> COSEL_W<'_>
[src]
Bit 19 - Calibration output selection
pub fn pol(&mut self) -> POL_W<'_>
[src]
Bit 20 - Output polarity
pub fn osel(&mut self) -> OSEL_W<'_>
[src]
Bits 21:22 - Output selection
pub fn coe(&mut self) -> COE_W<'_>
[src]
Bit 23 - Calibration output enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn shpf(&mut self) -> SHPF_W<'_>
[src]
Bit 3 - Shift operation pending
pub fn rsf(&mut self) -> RSF_W<'_>
[src]
Bit 5 - Registers synchronization flag
pub fn init(&mut self) -> INIT_W<'_>
[src]
Bit 7 - Initialization mode
pub fn alraf(&mut self) -> ALRAF_W<'_>
[src]
Bit 8 - Alarm A flag
pub fn tsf(&mut self) -> TSF_W<'_>
[src]
Bit 11 - Time-stamp flag
pub fn tsovf(&mut self) -> TSOVF_W<'_>
[src]
Bit 12 - Time-stamp overflow flag
pub fn tamp1f(&mut self) -> TAMP1F_W<'_>
[src]
Bit 13 - RTC_TAMP1 detection flag
pub fn tamp2f(&mut self) -> TAMP2F_W<'_>
[src]
Bit 14 - RTC_TAMP2 detection flag
impl W<u32, Reg<u32, _PRER>>
[src]
pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>
[src]
Bits 16:22 - Asynchronous prescaler factor
pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>
[src]
Bits 0:14 - Synchronous prescaler factor
impl W<u32, Reg<u32, _ALRMAR>>
[src]
pub fn msk4(&mut self) -> MSK4_W<'_>
[src]
Bit 31 - Alarm A date mask
pub fn wdsel(&mut self) -> WDSEL_W<'_>
[src]
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 28:29 - Date tens in BCD format.
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 24:27 - Date units or day in BCD format.
pub fn msk3(&mut self) -> MSK3_W<'_>
[src]
Bit 23 - Alarm A hours mask
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format.
pub fn msk2(&mut self) -> MSK2_W<'_>
[src]
Bit 15 - Alarm A minutes mask
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format.
pub fn msk1(&mut self) -> MSK1_W<'_>
[src]
Bit 7 - Alarm A seconds mask
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format.
impl W<u32, Reg<u32, _WPR>>
[src]
impl W<u32, Reg<u32, _SHIFTR>>
[src]
pub fn add1s(&mut self) -> ADD1S_W<'_>
[src]
Bit 31 - Add one second
pub fn subfs(&mut self) -> SUBFS_W<'_>
[src]
Bits 0:14 - Subtract a fraction of a second
impl W<u32, Reg<u32, _CALR>>
[src]
pub fn calp(&mut self) -> CALP_W<'_>
[src]
Bit 15 - Increase frequency of RTC by 488.5 ppm
pub fn calw8(&mut self) -> CALW8_W<'_>
[src]
Bit 14 - Use an 8-second calibration cycle period
pub fn calw16(&mut self) -> CALW16_W<'_>
[src]
Bit 13 - Use a 16-second calibration cycle period
pub fn calm(&mut self) -> CALM_W<'_>
[src]
Bits 0:8 - Calibration minus
impl W<u32, Reg<u32, _TAFCR>>
[src]
pub fn pc15mode(&mut self) -> PC15MODE_W<'_>
[src]
Bit 23 - PC15 mode
pub fn pc15value(&mut self) -> PC15VALUE_W<'_>
[src]
Bit 22 - PC15 value
pub fn pc14mode(&mut self) -> PC14MODE_W<'_>
[src]
Bit 21 - PC14 mode
pub fn pc14value(&mut self) -> PC14VALUE_W<'_>
[src]
Bit 20 - PC14 value
pub fn pc13mode(&mut self) -> PC13MODE_W<'_>
[src]
Bit 19 - PC13 mode
pub fn pc13value(&mut self) -> PC13VALUE_W<'_>
[src]
Bit 18 - RTC_ALARM output type/PC13 value
pub fn tamp_pudis(&mut self) -> TAMP_PUDIS_W<'_>
[src]
Bit 15 - RTC_TAMPx pull-up disable
pub fn tamp_prch(&mut self) -> TAMP_PRCH_W<'_>
[src]
Bits 13:14 - RTC_TAMPx precharge duration
pub fn tampflt(&mut self) -> TAMPFLT_W<'_>
[src]
Bits 11:12 - RTC_TAMPx filter count
pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>
[src]
Bits 8:10 - Tamper sampling frequency
pub fn tampts(&mut self) -> TAMPTS_W<'_>
[src]
Bit 7 - Activate timestamp on tamper detection event
pub fn tamp2_trg(&mut self) -> TAMP2_TRG_W<'_>
[src]
Bit 4 - Active level for RTC_TAMP2 input
pub fn tamp2e(&mut self) -> TAMP2E_W<'_>
[src]
Bit 3 - RTC_TAMP2 input detection enable
pub fn tampie(&mut self) -> TAMPIE_W<'_>
[src]
Bit 2 - Tamper interrupt enable
pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>
[src]
Bit 1 - Active level for RTC_TAMP1 input
pub fn tamp1e(&mut self) -> TAMP1E_W<'_>
[src]
Bit 0 - RTC_TAMP1 input detection enable
impl W<u32, Reg<u32, _ALRMASSR>>
[src]
pub fn maskss(&mut self) -> MASKSS_W<'_>
[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
[src]
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _BKPR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _CCR2>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn ctph(&mut self) -> CTPH_W<'_>
[src]
Bits 28:31 - Charge transfer pulse high
pub fn ctpl(&mut self) -> CTPL_W<'_>
[src]
Bits 24:27 - Charge transfer pulse low
pub fn ssd(&mut self) -> SSD_W<'_>
[src]
Bits 17:23 - Spread spectrum deviation
pub fn sse(&mut self) -> SSE_W<'_>
[src]
Bit 16 - Spread spectrum enable
pub fn sspsc(&mut self) -> SSPSC_W<'_>
[src]
Bit 15 - Spread spectrum prescaler
pub fn pgpsc(&mut self) -> PGPSC_W<'_>
[src]
Bits 12:14 - pulse generator prescaler
pub fn mcv(&mut self) -> MCV_W<'_>
[src]
Bits 5:7 - Max count value
pub fn iodef(&mut self) -> IODEF_W<'_>
[src]
Bit 4 - I/O Default mode
pub fn syncpol(&mut self) -> SYNCPOL_W<'_>
[src]
Bit 3 - Synchronization pin polarity
pub fn am(&mut self) -> AM_W<'_>
[src]
Bit 2 - Acquisition mode
pub fn start(&mut self) -> START_W<'_>
[src]
Bit 1 - Start a new acquisition
pub fn tsce(&mut self) -> TSCE_W<'_>
[src]
Bit 0 - Touch sensing controller enable
impl W<u32, Reg<u32, _IER>>
[src]
pub fn mceie(&mut self) -> MCEIE_W<'_>
[src]
Bit 1 - Max count error interrupt enable
pub fn eoaie(&mut self) -> EOAIE_W<'_>
[src]
Bit 0 - End of acquisition interrupt enable
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn mceic(&mut self) -> MCEIC_W<'_>
[src]
Bit 1 - Max count error interrupt clear
pub fn eoaic(&mut self) -> EOAIC_W<'_>
[src]
Bit 0 - End of acquisition interrupt clear
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn mcef(&mut self) -> MCEF_W<'_>
[src]
Bit 1 - Max count error flag
pub fn eoaf(&mut self) -> EOAF_W<'_>
[src]
Bit 0 - End of acquisition flag
impl W<u32, Reg<u32, _IOHCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
impl W<u32, Reg<u32, _IOASCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 analog switch enable
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 analog switch enable
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 analog switch enable
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 analog switch enable
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 analog switch enable
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 analog switch enable
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 analog switch enable
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 analog switch enable
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 analog switch enable
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 analog switch enable
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 analog switch enable
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 analog switch enable
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 analog switch enable
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 analog switch enable
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 analog switch enable
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 analog switch enable
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 analog switch enable
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 analog switch enable
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 analog switch enable
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 analog switch enable
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 analog switch enable
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 analog switch enable
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 analog switch enable
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 analog switch enable
impl W<u32, Reg<u32, _IOSCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 sampling mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 sampling mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 sampling mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 sampling mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 sampling mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 sampling mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 sampling mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 sampling mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 sampling mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 sampling mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 sampling mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 sampling mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 sampling mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 sampling mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 sampling mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 sampling mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 sampling mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 sampling mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 sampling mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 sampling mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 sampling mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 sampling mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 sampling mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 sampling mode
impl W<u32, Reg<u32, _IOCCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 channel mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 channel mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 channel mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 channel mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 channel mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 channel mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 channel mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 channel mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 channel mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 channel mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 channel mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 channel mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 channel mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 channel mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 channel mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 channel mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 channel mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 channel mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 channel mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 channel mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 channel mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 channel mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 channel mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 channel mode
impl W<u32, Reg<u32, _IOGCSR>>
[src]
pub fn g8s(&mut self) -> G8S_W<'_>
[src]
Bit 23 - Analog I/O group x status
pub fn g7s(&mut self) -> G7S_W<'_>
[src]
Bit 22 - Analog I/O group x status
pub fn g8e(&mut self) -> G8E_W<'_>
[src]
Bit 7 - Analog I/O group x enable
pub fn g7e(&mut self) -> G7E_W<'_>
[src]
Bit 6 - Analog I/O group x enable
pub fn g6e(&mut self) -> G6E_W<'_>
[src]
Bit 5 - Analog I/O group x enable
pub fn g5e(&mut self) -> G5E_W<'_>
[src]
Bit 4 - Analog I/O group x enable
pub fn g4e(&mut self) -> G4E_W<'_>
[src]
Bit 3 - Analog I/O group x enable
pub fn g3e(&mut self) -> G3E_W<'_>
[src]
Bit 2 - Analog I/O group x enable
pub fn g2e(&mut self) -> G2E_W<'_>
[src]
Bit 1 - Analog I/O group x enable
pub fn g1e(&mut self) -> G1E_W<'_>
[src]
Bit 0 - Analog I/O group x enable
impl W<u32, Reg<u32, _CR>>
[src]
pub fn txeom(&mut self) -> TXEOM_W<'_>
[src]
Bit 2 - Tx End Of Message
pub fn txsom(&mut self) -> TXSOM_W<'_>
[src]
Bit 1 - Tx start of message
pub fn cecen(&mut self) -> CECEN_W<'_>
[src]
Bit 0 - CEC Enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn lbpegen(&mut self) -> LBPEGEN_W<'_>
[src]
Bit 11 - Generate Error-Bit on Long Bit Period Error
pub fn bregen(&mut self) -> BREGEN_W<'_>
[src]
Bit 10 - Generate error-bit on bit rising error
pub fn brestp(&mut self) -> BRESTP_W<'_>
[src]
Bit 9 - Rx-stop on bit rising error
pub fn rxtol(&mut self) -> RXTOL_W<'_>
[src]
Bit 8 - Rx-Tolerance
pub fn sft(&mut self) -> SFT_W<'_>
[src]
Bits 5:7 - Signal Free Time
pub fn lstn(&mut self) -> LSTN_W<'_>
[src]
Bit 4 - Listen mode
pub fn oar(&mut self) -> OAR_W<'_>
[src]
Bits 0:3 - Own Address
impl W<u32, Reg<u32, _TXDR>>
[src]
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn txacke(&mut self) -> TXACKE_W<'_>
[src]
Bit 12 - Tx-Missing acknowledge error
pub fn txerr(&mut self) -> TXERR_W<'_>
[src]
Bit 11 - Tx-Error
pub fn txudr(&mut self) -> TXUDR_W<'_>
[src]
Bit 10 - Tx-Buffer Underrun
pub fn txend(&mut self) -> TXEND_W<'_>
[src]
Bit 9 - End of Transmission
pub fn txbr(&mut self) -> TXBR_W<'_>
[src]
Bit 8 - Tx-Byte Request
pub fn arblst(&mut self) -> ARBLST_W<'_>
[src]
Bit 7 - Arbitration Lost
pub fn rxacke(&mut self) -> RXACKE_W<'_>
[src]
Bit 6 - Rx-Missing Acknowledge
pub fn lbpe(&mut self) -> LBPE_W<'_>
[src]
Bit 5 - Rx-Long Bit Period Error
pub fn sbpe(&mut self) -> SBPE_W<'_>
[src]
Bit 4 - Rx-Short Bit period error
pub fn bre(&mut self) -> BRE_W<'_>
[src]
Bit 3 - Rx-Bit rising error
pub fn rxovr(&mut self) -> RXOVR_W<'_>
[src]
Bit 2 - Rx-Overrun
pub fn rxend(&mut self) -> RXEND_W<'_>
[src]
Bit 1 - End Of Reception
pub fn rxbr(&mut self) -> RXBR_W<'_>
[src]
Bit 0 - Rx-Byte Received
impl W<u32, Reg<u32, _IER>>
[src]
pub fn txackie(&mut self) -> TXACKIE_W<'_>
[src]
Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable
pub fn txerrie(&mut self) -> TXERRIE_W<'_>
[src]
Bit 11 - Tx-Error Interrupt Enable
pub fn txudrie(&mut self) -> TXUDRIE_W<'_>
[src]
Bit 10 - Tx-Underrun interrupt enable
pub fn txendie(&mut self) -> TXENDIE_W<'_>
[src]
Bit 9 - Tx-End of message interrupt enable
pub fn txbrie(&mut self) -> TXBRIE_W<'_>
[src]
Bit 8 - Tx-Byte Request Interrupt Enable
pub fn arblstie(&mut self) -> ARBLSTIE_W<'_>
[src]
Bit 7 - Arbitration Lost Interrupt Enable
pub fn rxackie(&mut self) -> RXACKIE_W<'_>
[src]
Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable
pub fn lbpeie(&mut self) -> LBPEIE_W<'_>
[src]
Bit 5 - Long Bit Period Error Interrupt Enable
pub fn sbpeie(&mut self) -> SBPEIE_W<'_>
[src]
Bit 4 - Short Bit Period Error Interrupt Enable
pub fn breie(&mut self) -> BREIE_W<'_>
[src]
Bit 3 - Bit Rising Error Interrupt Enable
pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>
[src]
Bit 2 - Rx-Buffer Overrun Interrupt Enable
pub fn rxendie(&mut self) -> RXENDIE_W<'_>
[src]
Bit 1 - End Of Reception Interrupt Enable
pub fn rxbrie(&mut self) -> RXBRIE_W<'_>
[src]
Bit 0 - Rx-Byte Received Interrupt Enable
impl W<u32, Reg<u32, _ACR>>
[src]
pub fn latency(&mut self) -> LATENCY_W<'_>
[src]
Bits 0:2 - LATENCY
pub fn prftbe(&mut self) -> PRFTBE_W<'_>
[src]
Bit 4 - PRFTBE
impl W<u32, Reg<u32, _KEYR>>
[src]
impl W<u32, Reg<u32, _OPTKEYR>>
[src]
impl W<u32, Reg<u32, _SR>>
[src]
pub fn eop(&mut self) -> EOP_W<'_>
[src]
Bit 5 - End of operation
pub fn wrprt(&mut self) -> WRPRT_W<'_>
[src]
Bit 4 - Write protection error
pub fn pgerr(&mut self) -> PGERR_W<'_>
[src]
Bit 2 - Programming error
impl W<u32, Reg<u32, _CR>>
[src]
pub fn force_optload(&mut self) -> FORCE_OPTLOAD_W<'_>
[src]
Bit 13 - Force option byte loading
pub fn eopie(&mut self) -> EOPIE_W<'_>
[src]
Bit 12 - End of operation interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 10 - Error interrupt enable
pub fn optwre(&mut self) -> OPTWRE_W<'_>
[src]
Bit 9 - Option bytes write enable
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bit 7 - Lock
pub fn strt(&mut self) -> STRT_W<'_>
[src]
Bit 6 - Start
pub fn opter(&mut self) -> OPTER_W<'_>
[src]
Bit 5 - Option byte erase
pub fn optpg(&mut self) -> OPTPG_W<'_>
[src]
Bit 4 - Option byte programming
pub fn mer(&mut self) -> MER_W<'_>
[src]
Bit 2 - Mass erase
pub fn per(&mut self) -> PER_W<'_>
[src]
Bit 1 - Page erase
pub fn pg(&mut self) -> PG_W<'_>
[src]
Bit 0 - Programming
impl W<u32, Reg<u32, _AR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>
[src]
Bit 1 - Debug Stop Mode
pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>
[src]
Bit 2 - Debug Standby Mode
impl W<u32, Reg<u32, _APB1_FZ>>
[src]
pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>
[src]
Bit 0 - TIM2 counter stopped when core is halted
pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>
[src]
Bit 1 - TIM3 counter stopped when core is halted
pub fn tim3_counter_stopped_when_core_is_halted(
&mut self
) -> TIM3_COUNTER_STOPPED_WHEN_CORE_IS_HALTED_W<'_>
[src]
&mut self
) -> TIM3_COUNTER_STOPPED_WHEN_CORE_IS_HALTED_W<'_>
Bit 4 - TIM6 counter stopped when core is halted
pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>
[src]
Bit 5 - TIM7 counter stopped when core is halted
pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>
[src]
Bit 8 - TIM14 counter stopped when core is halted
pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>
[src]
Bit 10 - Debug RTC stopped when core is halted
pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>
[src]
Bit 11 - Debug window watchdog stopped when core is halted
pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>
[src]
Bit 12 - Debug independent watchdog stopped when core is halted
pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>
[src]
Bit 21 - SMBUS timeout mode stopped when core is halted
pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>
[src]
Bit 25 - CAN stopped when core is halted
impl W<u32, Reg<u32, _APB2_FZ>>
[src]
pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>
[src]
Bit 11 - TIM1 counter stopped when core is halted
pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>
[src]
Bit 16 - TIM15 counter stopped when core is halted
pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>
[src]
Bit 17 - TIM16 counter stopped when core is halted
pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>
[src]
Bit 18 - TIM17 counter stopped when core is halted
impl W<u32, Reg<u32, _EP0R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP1R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP2R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP3R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP4R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP5R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP6R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP7R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _CNTR>>
[src]
pub fn fres(&mut self) -> FRES_W<'_>
[src]
Bit 0 - Force USB Reset
pub fn pdwn(&mut self) -> PDWN_W<'_>
[src]
Bit 1 - Power down
pub fn lpmode(&mut self) -> LPMODE_W<'_>
[src]
Bit 2 - Low-power mode
pub fn fsusp(&mut self) -> FSUSP_W<'_>
[src]
Bit 3 - Force suspend
pub fn resume(&mut self) -> RESUME_W<'_>
[src]
Bit 4 - Resume request
pub fn l1resume(&mut self) -> L1RESUME_W<'_>
[src]
Bit 5 - LPM L1 Resume request
pub fn l1reqm(&mut self) -> L1REQM_W<'_>
[src]
Bit 7 - LPM L1 state request interrupt mask
pub fn esofm(&mut self) -> ESOFM_W<'_>
[src]
Bit 8 - Expected start of frame interrupt mask
pub fn sofm(&mut self) -> SOFM_W<'_>
[src]
Bit 9 - Start of frame interrupt mask
pub fn resetm(&mut self) -> RESETM_W<'_>
[src]
Bit 10 - USB reset interrupt mask
pub fn suspm(&mut self) -> SUSPM_W<'_>
[src]
Bit 11 - Suspend mode interrupt mask
pub fn wkupm(&mut self) -> WKUPM_W<'_>
[src]
Bit 12 - Wakeup interrupt mask
pub fn errm(&mut self) -> ERRM_W<'_>
[src]
Bit 13 - Error interrupt mask
pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>
[src]
Bit 14 - Packet memory area over / underrun interrupt mask
pub fn ctrm(&mut self) -> CTRM_W<'_>
[src]
Bit 15 - Correct transfer interrupt mask
impl W<u32, Reg<u32, _ISTR>>
[src]
pub fn l1req(&mut self) -> L1REQ_W<'_>
[src]
Bit 7 - LPM L1 state request
pub fn esof(&mut self) -> ESOF_W<'_>
[src]
Bit 8 - Expected start frame
pub fn sof(&mut self) -> SOF_W<'_>
[src]
Bit 9 - start of frame
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 10 - reset request
pub fn susp(&mut self) -> SUSP_W<'_>
[src]
Bit 11 - Suspend mode request
pub fn wkup(&mut self) -> WKUP_W<'_>
[src]
Bit 12 - Wakeup
pub fn err(&mut self) -> ERR_W<'_>
[src]
Bit 13 - Error
pub fn pmaovr(&mut self) -> PMAOVR_W<'_>
[src]
Bit 14 - Packet memory area over / underrun
impl W<u32, Reg<u32, _DADDR>>
[src]
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 0:6 - Device address
pub fn ef(&mut self) -> EF_W<'_>
[src]
Bit 7 - Enable function
impl W<u32, Reg<u32, _BTABLE>>
[src]
impl W<u32, Reg<u32, _LPMCSR>>
[src]
pub fn lpmen(&mut self) -> LPMEN_W<'_>
[src]
Bit 0 - LPM support enable
pub fn lpmack(&mut self) -> LPMACK_W<'_>
[src]
Bit 1 - LPM Token acknowledge enable
impl W<u32, Reg<u32, _BCDR>>
[src]
pub fn bcden(&mut self) -> BCDEN_W<'_>
[src]
Bit 0 - Battery charging detector (BCD) enable
pub fn dcden(&mut self) -> DCDEN_W<'_>
[src]
Bit 1 - Data contact detection (DCD) mode enable
pub fn pden(&mut self) -> PDEN_W<'_>
[src]
Bit 2 - Primary detection (PD) mode enable
pub fn sden(&mut self) -> SDEN_W<'_>
[src]
Bit 3 - Secondary detection (SD) mode enable
pub fn dppu(&mut self) -> DPPU_W<'_>
[src]
Bit 15 - DP pull-up control
impl W<u32, Reg<u32, _CR>>
[src]
pub fn trim(&mut self) -> TRIM_W<'_>
[src]
Bits 8:13 - HSI48 oscillator smooth trimming
pub fn swsync(&mut self) -> SWSYNC_W<'_>
[src]
Bit 7 - Generate software SYNC event
pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<'_>
[src]
Bit 6 - Automatic trimming enable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 5 - Frequency error counter enable
pub fn esyncie(&mut self) -> ESYNCIE_W<'_>
[src]
Bit 3 - Expected SYNC interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 2 - Synchronization or trimming error interrupt enable
pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<'_>
[src]
Bit 1 - SYNC warning interrupt enable
pub fn syncokie(&mut self) -> SYNCOKIE_W<'_>
[src]
Bit 0 - SYNC event OK interrupt enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn syncpol(&mut self) -> SYNCPOL_W<'_>
[src]
Bit 31 - SYNC polarity selection
pub fn syncsrc(&mut self) -> SYNCSRC_W<'_>
[src]
Bits 28:29 - SYNC signal source selection
pub fn syncdiv(&mut self) -> SYNCDIV_W<'_>
[src]
Bits 24:26 - SYNC divider
pub fn felim(&mut self) -> FELIM_W<'_>
[src]
Bits 16:23 - Frequency error limit
pub fn reload(&mut self) -> RELOAD_W<'_>
[src]
Bits 0:15 - Counter reload value
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn esyncc(&mut self) -> ESYNCC_W<'_>
[src]
Bit 3 - Expected SYNC clear flag
pub fn errc(&mut self) -> ERRC_W<'_>
[src]
Bit 2 - Error clear flag
pub fn syncwarnc(&mut self) -> SYNCWARNC_W<'_>
[src]
Bit 1 - SYNC warning clear flag
pub fn syncokc(&mut self) -> SYNCOKC_W<'_>
[src]
Bit 0 - SYNC event OK clear flag
impl W<u32, Reg<u32, _TIR>>
[src]
pub fn stid(&mut self) -> STID_W<'_>
[src]
Bits 21:31 - STID
pub fn exid(&mut self) -> EXID_W<'_>
[src]
Bits 3:20 - EXID
pub fn ide(&mut self) -> IDE_W<'_>
[src]
Bit 2 - IDE
pub fn rtr(&mut self) -> RTR_W<'_>
[src]
Bit 1 - RTR
pub fn txrq(&mut self) -> TXRQ_W<'_>
[src]
Bit 0 - TXRQ
impl W<u32, Reg<u32, _TDTR>>
[src]
pub fn time(&mut self) -> TIME_W<'_>
[src]
Bits 16:31 - TIME
pub fn tgt(&mut self) -> TGT_W<'_>
[src]
Bit 8 - TGT
pub fn dlc(&mut self) -> DLC_W<'_>
[src]
Bits 0:3 - DLC
impl W<u32, Reg<u32, _TDLR>>
[src]
pub fn data3(&mut self) -> DATA3_W<'_>
[src]
Bits 24:31 - DATA3
pub fn data2(&mut self) -> DATA2_W<'_>
[src]
Bits 16:23 - DATA2
pub fn data1(&mut self) -> DATA1_W<'_>
[src]
Bits 8:15 - DATA1
pub fn data0(&mut self) -> DATA0_W<'_>
[src]
Bits 0:7 - DATA0
impl W<u32, Reg<u32, _TDHR>>
[src]
pub fn data7(&mut self) -> DATA7_W<'_>
[src]
Bits 24:31 - DATA7
pub fn data6(&mut self) -> DATA6_W<'_>
[src]
Bits 16:23 - DATA6
pub fn data5(&mut self) -> DATA5_W<'_>
[src]
Bits 8:15 - DATA5
pub fn data4(&mut self) -> DATA4_W<'_>
[src]
Bits 0:7 - DATA4
impl W<u32, Reg<u32, _FR1>>
[src]
pub fn fb0(&mut self) -> FB0_W<'_>
[src]
Bit 0 - Filter bits
pub fn fb1(&mut self) -> FB1_W<'_>
[src]
Bit 1 - Filter bits
pub fn fb2(&mut self) -> FB2_W<'_>
[src]
Bit 2 - Filter bits
pub fn fb3(&mut self) -> FB3_W<'_>
[src]
Bit 3 - Filter bits
pub fn fb4(&mut self) -> FB4_W<'_>
[src]
Bit 4 - Filter bits
pub fn fb5(&mut self) -> FB5_W<'_>
[src]
Bit 5 - Filter bits
pub fn fb6(&mut self) -> FB6_W<'_>
[src]
Bit 6 - Filter bits
pub fn fb7(&mut self) -> FB7_W<'_>
[src]
Bit 7 - Filter bits
pub fn fb8(&mut self) -> FB8_W<'_>
[src]
Bit 8 - Filter bits
pub fn fb9(&mut self) -> FB9_W<'_>
[src]
Bit 9 - Filter bits
pub fn fb10(&mut self) -> FB10_W<'_>
[src]
Bit 10 - Filter bits
pub fn fb11(&mut self) -> FB11_W<'_>
[src]
Bit 11 - Filter bits
pub fn fb12(&mut self) -> FB12_W<'_>
[src]
Bit 12 - Filter bits
pub fn fb13(&mut self) -> FB13_W<'_>
[src]
Bit 13 - Filter bits
pub fn fb14(&mut self) -> FB14_W<'_>
[src]
Bit 14 - Filter bits
pub fn fb15(&mut self) -> FB15_W<'_>
[src]
Bit 15 - Filter bits
pub fn fb16(&mut self) -> FB16_W<'_>
[src]
Bit 16 - Filter bits
pub fn fb17(&mut self) -> FB17_W<'_>
[src]
Bit 17 - Filter bits
pub fn fb18(&mut self) -> FB18_W<'_>
[src]
Bit 18 - Filter bits
pub fn fb19(&mut self) -> FB19_W<'_>
[src]
Bit 19 - Filter bits
pub fn fb20(&mut self) -> FB20_W<'_>
[src]
Bit 20 - Filter bits
pub fn fb21(&mut self) -> FB21_W<'_>
[src]
Bit 21 - Filter bits
pub fn fb22(&mut self) -> FB22_W<'_>
[src]
Bit 22 - Filter bits
pub fn fb23(&mut self) -> FB23_W<'_>
[src]
Bit 23 - Filter bits
pub fn fb24(&mut self) -> FB24_W<'_>
[src]
Bit 24 - Filter bits
pub fn fb25(&mut self) -> FB25_W<'_>
[src]
Bit 25 - Filter bits
pub fn fb26(&mut self) -> FB26_W<'_>
[src]
Bit 26 - Filter bits
pub fn fb27(&mut self) -> FB27_W<'_>
[src]
Bit 27 - Filter bits
pub fn fb28(&mut self) -> FB28_W<'_>
[src]
Bit 28 - Filter bits
pub fn fb29(&mut self) -> FB29_W<'_>
[src]
Bit 29 - Filter bits
pub fn fb30(&mut self) -> FB30_W<'_>
[src]
Bit 30 - Filter bits
pub fn fb31(&mut self) -> FB31_W<'_>
[src]
Bit 31 - Filter bits
impl W<u32, Reg<u32, _FR2>>
[src]
pub fn fb0(&mut self) -> FB0_W<'_>
[src]
Bit 0 - Filter bits
pub fn fb1(&mut self) -> FB1_W<'_>
[src]
Bit 1 - Filter bits
pub fn fb2(&mut self) -> FB2_W<'_>
[src]
Bit 2 - Filter bits
pub fn fb3(&mut self) -> FB3_W<'_>
[src]
Bit 3 - Filter bits
pub fn fb4(&mut self) -> FB4_W<'_>
[src]
Bit 4 - Filter bits
pub fn fb5(&mut self) -> FB5_W<'_>
[src]
Bit 5 - Filter bits
pub fn fb6(&mut self) -> FB6_W<'_>
[src]
Bit 6 - Filter bits
pub fn fb7(&mut self) -> FB7_W<'_>
[src]
Bit 7 - Filter bits
pub fn fb8(&mut self) -> FB8_W<'_>
[src]
Bit 8 - Filter bits
pub fn fb9(&mut self) -> FB9_W<'_>
[src]
Bit 9 - Filter bits
pub fn fb10(&mut self) -> FB10_W<'_>
[src]
Bit 10 - Filter bits
pub fn fb11(&mut self) -> FB11_W<'_>
[src]
Bit 11 - Filter bits
pub fn fb12(&mut self) -> FB12_W<'_>
[src]
Bit 12 - Filter bits
pub fn fb13(&mut self) -> FB13_W<'_>
[src]
Bit 13 - Filter bits
pub fn fb14(&mut self) -> FB14_W<'_>
[src]
Bit 14 - Filter bits
pub fn fb15(&mut self) -> FB15_W<'_>
[src]
Bit 15 - Filter bits
pub fn fb16(&mut self) -> FB16_W<'_>
[src]
Bit 16 - Filter bits
pub fn fb17(&mut self) -> FB17_W<'_>
[src]
Bit 17 - Filter bits
pub fn fb18(&mut self) -> FB18_W<'_>
[src]
Bit 18 - Filter bits
pub fn fb19(&mut self) -> FB19_W<'_>
[src]
Bit 19 - Filter bits
pub fn fb20(&mut self) -> FB20_W<'_>
[src]
Bit 20 - Filter bits
pub fn fb21(&mut self) -> FB21_W<'_>
[src]
Bit 21 - Filter bits
pub fn fb22(&mut self) -> FB22_W<'_>
[src]
Bit 22 - Filter bits
pub fn fb23(&mut self) -> FB23_W<'_>
[src]
Bit 23 - Filter bits
pub fn fb24(&mut self) -> FB24_W<'_>
[src]
Bit 24 - Filter bits
pub fn fb25(&mut self) -> FB25_W<'_>
[src]
Bit 25 - Filter bits
pub fn fb26(&mut self) -> FB26_W<'_>
[src]
Bit 26 - Filter bits
pub fn fb27(&mut self) -> FB27_W<'_>
[src]
Bit 27 - Filter bits
pub fn fb28(&mut self) -> FB28_W<'_>
[src]
Bit 28 - Filter bits
pub fn fb29(&mut self) -> FB29_W<'_>
[src]
Bit 29 - Filter bits
pub fn fb30(&mut self) -> FB30_W<'_>
[src]
Bit 30 - Filter bits
pub fn fb31(&mut self) -> FB31_W<'_>
[src]
Bit 31 - Filter bits
impl W<u32, Reg<u32, _MCR>>
[src]
pub fn dbf(&mut self) -> DBF_W<'_>
[src]
Bit 16 - DBF
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 15 - RESET
pub fn ttcm(&mut self) -> TTCM_W<'_>
[src]
Bit 7 - TTCM
pub fn abom(&mut self) -> ABOM_W<'_>
[src]
Bit 6 - ABOM
pub fn awum(&mut self) -> AWUM_W<'_>
[src]
Bit 5 - AWUM
pub fn nart(&mut self) -> NART_W<'_>
[src]
Bit 4 - NART
pub fn rflm(&mut self) -> RFLM_W<'_>
[src]
Bit 3 - RFLM
pub fn txfp(&mut self) -> TXFP_W<'_>
[src]
Bit 2 - TXFP
pub fn sleep(&mut self) -> SLEEP_W<'_>
[src]
Bit 1 - SLEEP
pub fn inrq(&mut self) -> INRQ_W<'_>
[src]
Bit 0 - INRQ
impl W<u32, Reg<u32, _MSR>>
[src]
pub fn slaki(&mut self) -> SLAKI_W<'_>
[src]
Bit 4 - SLAKI
pub fn wkui(&mut self) -> WKUI_W<'_>
[src]
Bit 3 - WKUI
pub fn erri(&mut self) -> ERRI_W<'_>
[src]
Bit 2 - ERRI
impl W<u32, Reg<u32, _TSR>>
[src]
pub fn abrq2(&mut self) -> ABRQ2_W<'_>
[src]
Bit 23 - ABRQ2
pub fn terr2(&mut self) -> TERR2_W<'_>
[src]
Bit 19 - TERR2
pub fn alst2(&mut self) -> ALST2_W<'_>
[src]
Bit 18 - ALST2
pub fn txok2(&mut self) -> TXOK2_W<'_>
[src]
Bit 17 - TXOK2
pub fn rqcp2(&mut self) -> RQCP2_W<'_>
[src]
Bit 16 - RQCP2
pub fn abrq1(&mut self) -> ABRQ1_W<'_>
[src]
Bit 15 - ABRQ1
pub fn terr1(&mut self) -> TERR1_W<'_>
[src]
Bit 11 - TERR1
pub fn alst1(&mut self) -> ALST1_W<'_>
[src]
Bit 10 - ALST1
pub fn txok1(&mut self) -> TXOK1_W<'_>
[src]
Bit 9 - TXOK1
pub fn rqcp1(&mut self) -> RQCP1_W<'_>
[src]
Bit 8 - RQCP1
pub fn abrq0(&mut self) -> ABRQ0_W<'_>
[src]
Bit 7 - ABRQ0
pub fn terr0(&mut self) -> TERR0_W<'_>
[src]
Bit 3 - TERR0
pub fn alst0(&mut self) -> ALST0_W<'_>
[src]
Bit 2 - ALST0
pub fn txok0(&mut self) -> TXOK0_W<'_>
[src]
Bit 1 - TXOK0
pub fn rqcp0(&mut self) -> RQCP0_W<'_>
[src]
Bit 0 - RQCP0
impl W<u32, Reg<u32, _RFR>>
[src]
pub fn rfom(&mut self) -> RFOM_W<'_>
[src]
Bit 5 - RFOM0
pub fn fovr(&mut self) -> FOVR_W<'_>
[src]
Bit 4 - FOVR0
pub fn full(&mut self) -> FULL_W<'_>
[src]
Bit 3 - FULL0
impl W<u32, Reg<u32, _IER>>
[src]
pub fn slkie(&mut self) -> SLKIE_W<'_>
[src]
Bit 17 - SLKIE
pub fn wkuie(&mut self) -> WKUIE_W<'_>
[src]
Bit 16 - WKUIE
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 15 - ERRIE
pub fn lecie(&mut self) -> LECIE_W<'_>
[src]
Bit 11 - LECIE
pub fn bofie(&mut self) -> BOFIE_W<'_>
[src]
Bit 10 - BOFIE
pub fn epvie(&mut self) -> EPVIE_W<'_>
[src]
Bit 9 - EPVIE
pub fn ewgie(&mut self) -> EWGIE_W<'_>
[src]
Bit 8 - EWGIE
pub fn fovie1(&mut self) -> FOVIE1_W<'_>
[src]
Bit 6 - FOVIE1
pub fn ffie1(&mut self) -> FFIE1_W<'_>
[src]
Bit 5 - FFIE1
pub fn fmpie1(&mut self) -> FMPIE1_W<'_>
[src]
Bit 4 - FMPIE1
pub fn fovie0(&mut self) -> FOVIE0_W<'_>
[src]
Bit 3 - FOVIE0
pub fn ffie0(&mut self) -> FFIE0_W<'_>
[src]
Bit 2 - FFIE0
pub fn fmpie0(&mut self) -> FMPIE0_W<'_>
[src]
Bit 1 - FMPIE0
pub fn tmeie(&mut self) -> TMEIE_W<'_>
[src]
Bit 0 - TMEIE
impl W<u32, Reg<u32, _ESR>>
[src]
impl W<u32, Reg<u32, _BTR>>
[src]
pub fn silm(&mut self) -> SILM_W<'_>
[src]
Bit 31 - SILM
pub fn lbkm(&mut self) -> LBKM_W<'_>
[src]
Bit 30 - LBKM
pub fn sjw(&mut self) -> SJW_W<'_>
[src]
Bits 24:25 - SJW
pub fn ts2(&mut self) -> TS2_W<'_>
[src]
Bits 20:22 - TS2
pub fn ts1(&mut self) -> TS1_W<'_>
[src]
Bits 16:19 - TS1
pub fn brp(&mut self) -> BRP_W<'_>
[src]
Bits 0:9 - BRP
impl W<u32, Reg<u32, _FMR>>
[src]
pub fn can2sb(&mut self) -> CAN2SB_W<'_>
[src]
Bits 8:13 - CAN2SB
pub fn finit(&mut self) -> FINIT_W<'_>
[src]
Bit 0 - FINIT
impl W<u32, Reg<u32, _FM1R>>
[src]
pub fn fbm0(&mut self) -> FBM0_W<'_>
[src]
Bit 0 - Filter mode
pub fn fbm1(&mut self) -> FBM1_W<'_>
[src]
Bit 1 - Filter mode
pub fn fbm2(&mut self) -> FBM2_W<'_>
[src]
Bit 2 - Filter mode
pub fn fbm3(&mut self) -> FBM3_W<'_>
[src]
Bit 3 - Filter mode
pub fn fbm4(&mut self) -> FBM4_W<'_>
[src]
Bit 4 - Filter mode
pub fn fbm5(&mut self) -> FBM5_W<'_>
[src]
Bit 5 - Filter mode
pub fn fbm6(&mut self) -> FBM6_W<'_>
[src]
Bit 6 - Filter mode
pub fn fbm7(&mut self) -> FBM7_W<'_>
[src]
Bit 7 - Filter mode
pub fn fbm8(&mut self) -> FBM8_W<'_>
[src]
Bit 8 - Filter mode
pub fn fbm9(&mut self) -> FBM9_W<'_>
[src]
Bit 9 - Filter mode
pub fn fbm10(&mut self) -> FBM10_W<'_>
[src]
Bit 10 - Filter mode
pub fn fbm11(&mut self) -> FBM11_W<'_>
[src]
Bit 11 - Filter mode
pub fn fbm12(&mut self) -> FBM12_W<'_>
[src]
Bit 12 - Filter mode
pub fn fbm13(&mut self) -> FBM13_W<'_>
[src]
Bit 13 - Filter mode
pub fn fbm14(&mut self) -> FBM14_W<'_>
[src]
Bit 14 - Filter mode
pub fn fbm15(&mut self) -> FBM15_W<'_>
[src]
Bit 15 - Filter mode
pub fn fbm16(&mut self) -> FBM16_W<'_>
[src]
Bit 16 - Filter mode
pub fn fbm17(&mut self) -> FBM17_W<'_>
[src]
Bit 17 - Filter mode
pub fn fbm18(&mut self) -> FBM18_W<'_>
[src]
Bit 18 - Filter mode
pub fn fbm19(&mut self) -> FBM19_W<'_>
[src]
Bit 19 - Filter mode
pub fn fbm20(&mut self) -> FBM20_W<'_>
[src]
Bit 20 - Filter mode
pub fn fbm21(&mut self) -> FBM21_W<'_>
[src]
Bit 21 - Filter mode
pub fn fbm22(&mut self) -> FBM22_W<'_>
[src]
Bit 22 - Filter mode
pub fn fbm23(&mut self) -> FBM23_W<'_>
[src]
Bit 23 - Filter mode
pub fn fbm24(&mut self) -> FBM24_W<'_>
[src]
Bit 24 - Filter mode
pub fn fbm25(&mut self) -> FBM25_W<'_>
[src]
Bit 25 - Filter mode
pub fn fbm26(&mut self) -> FBM26_W<'_>
[src]
Bit 26 - Filter mode
pub fn fbm27(&mut self) -> FBM27_W<'_>
[src]
Bit 27 - Filter mode
impl W<u32, Reg<u32, _FS1R>>
[src]
pub fn fsc0(&mut self) -> FSC0_W<'_>
[src]
Bit 0 - Filter scale configuration
pub fn fsc1(&mut self) -> FSC1_W<'_>
[src]
Bit 1 - Filter scale configuration
pub fn fsc2(&mut self) -> FSC2_W<'_>
[src]
Bit 2 - Filter scale configuration
pub fn fsc3(&mut self) -> FSC3_W<'_>
[src]
Bit 3 - Filter scale configuration
pub fn fsc4(&mut self) -> FSC4_W<'_>
[src]
Bit 4 - Filter scale configuration
pub fn fsc5(&mut self) -> FSC5_W<'_>
[src]
Bit 5 - Filter scale configuration
pub fn fsc6(&mut self) -> FSC6_W<'_>
[src]
Bit 6 - Filter scale configuration
pub fn fsc7(&mut self) -> FSC7_W<'_>
[src]
Bit 7 - Filter scale configuration
pub fn fsc8(&mut self) -> FSC8_W<'_>
[src]
Bit 8 - Filter scale configuration
pub fn fsc9(&mut self) -> FSC9_W<'_>
[src]
Bit 9 - Filter scale configuration
pub fn fsc10(&mut self) -> FSC10_W<'_>
[src]
Bit 10 - Filter scale configuration
pub fn fsc11(&mut self) -> FSC11_W<'_>
[src]
Bit 11 - Filter scale configuration
pub fn fsc12(&mut self) -> FSC12_W<'_>
[src]
Bit 12 - Filter scale configuration
pub fn fsc13(&mut self) -> FSC13_W<'_>
[src]
Bit 13 - Filter scale configuration
pub fn fsc14(&mut self) -> FSC14_W<'_>
[src]
Bit 14 - Filter scale configuration
pub fn fsc15(&mut self) -> FSC15_W<'_>
[src]
Bit 15 - Filter scale configuration
pub fn fsc16(&mut self) -> FSC16_W<'_>
[src]
Bit 16 - Filter scale configuration
pub fn fsc17(&mut self) -> FSC17_W<'_>
[src]
Bit 17 - Filter scale configuration
pub fn fsc18(&mut self) -> FSC18_W<'_>
[src]
Bit 18 - Filter scale configuration
pub fn fsc19(&mut self) -> FSC19_W<'_>
[src]
Bit 19 - Filter scale configuration
pub fn fsc20(&mut self) -> FSC20_W<'_>
[src]
Bit 20 - Filter scale configuration
pub fn fsc21(&mut self) -> FSC21_W<'_>
[src]
Bit 21 - Filter scale configuration
pub fn fsc22(&mut self) -> FSC22_W<'_>
[src]
Bit 22 - Filter scale configuration
pub fn fsc23(&mut self) -> FSC23_W<'_>
[src]
Bit 23 - Filter scale configuration
pub fn fsc24(&mut self) -> FSC24_W<'_>
[src]
Bit 24 - Filter scale configuration
pub fn fsc25(&mut self) -> FSC25_W<'_>
[src]
Bit 25 - Filter scale configuration
pub fn fsc26(&mut self) -> FSC26_W<'_>
[src]
Bit 26 - Filter scale configuration
pub fn fsc27(&mut self) -> FSC27_W<'_>
[src]
Bit 27 - Filter scale configuration
impl W<u32, Reg<u32, _FFA1R>>
[src]
pub fn ffa0(&mut self) -> FFA0_W<'_>
[src]
Bit 0 - Filter FIFO assignment for filter 0
pub fn ffa1(&mut self) -> FFA1_W<'_>
[src]
Bit 1 - Filter FIFO assignment for filter 1
pub fn ffa2(&mut self) -> FFA2_W<'_>
[src]
Bit 2 - Filter FIFO assignment for filter 2
pub fn ffa3(&mut self) -> FFA3_W<'_>
[src]
Bit 3 - Filter FIFO assignment for filter 3
pub fn ffa4(&mut self) -> FFA4_W<'_>
[src]
Bit 4 - Filter FIFO assignment for filter 4
pub fn ffa5(&mut self) -> FFA5_W<'_>
[src]
Bit 5 - Filter FIFO assignment for filter 5
pub fn ffa6(&mut self) -> FFA6_W<'_>
[src]
Bit 6 - Filter FIFO assignment for filter 6
pub fn ffa7(&mut self) -> FFA7_W<'_>
[src]
Bit 7 - Filter FIFO assignment for filter 7
pub fn ffa8(&mut self) -> FFA8_W<'_>
[src]
Bit 8 - Filter FIFO assignment for filter 8
pub fn ffa9(&mut self) -> FFA9_W<'_>
[src]
Bit 9 - Filter FIFO assignment for filter 9
pub fn ffa10(&mut self) -> FFA10_W<'_>
[src]
Bit 10 - Filter FIFO assignment for filter 10
pub fn ffa11(&mut self) -> FFA11_W<'_>
[src]
Bit 11 - Filter FIFO assignment for filter 11
pub fn ffa12(&mut self) -> FFA12_W<'_>
[src]
Bit 12 - Filter FIFO assignment for filter 12
pub fn ffa13(&mut self) -> FFA13_W<'_>
[src]
Bit 13 - Filter FIFO assignment for filter 13
pub fn ffa14(&mut self) -> FFA14_W<'_>
[src]
Bit 14 - Filter FIFO assignment for filter 14
pub fn ffa15(&mut self) -> FFA15_W<'_>
[src]
Bit 15 - Filter FIFO assignment for filter 15
pub fn ffa16(&mut self) -> FFA16_W<'_>
[src]
Bit 16 - Filter FIFO assignment for filter 16
pub fn ffa17(&mut self) -> FFA17_W<'_>
[src]
Bit 17 - Filter FIFO assignment for filter 17
pub fn ffa18(&mut self) -> FFA18_W<'_>
[src]
Bit 18 - Filter FIFO assignment for filter 18
pub fn ffa19(&mut self) -> FFA19_W<'_>
[src]
Bit 19 - Filter FIFO assignment for filter 19
pub fn ffa20(&mut self) -> FFA20_W<'_>
[src]
Bit 20 - Filter FIFO assignment for filter 20
pub fn ffa21(&mut self) -> FFA21_W<'_>
[src]
Bit 21 - Filter FIFO assignment for filter 21
pub fn ffa22(&mut self) -> FFA22_W<'_>
[src]
Bit 22 - Filter FIFO assignment for filter 22
pub fn ffa23(&mut self) -> FFA23_W<'_>
[src]
Bit 23 - Filter FIFO assignment for filter 23
pub fn ffa24(&mut self) -> FFA24_W<'_>
[src]
Bit 24 - Filter FIFO assignment for filter 24
pub fn ffa25(&mut self) -> FFA25_W<'_>
[src]
Bit 25 - Filter FIFO assignment for filter 25
pub fn ffa26(&mut self) -> FFA26_W<'_>
[src]
Bit 26 - Filter FIFO assignment for filter 26
pub fn ffa27(&mut self) -> FFA27_W<'_>
[src]
Bit 27 - Filter FIFO assignment for filter 27
impl W<u32, Reg<u32, _FA1R>>
[src]
pub fn fact0(&mut self) -> FACT0_W<'_>
[src]
Bit 0 - Filter active
pub fn fact1(&mut self) -> FACT1_W<'_>
[src]
Bit 1 - Filter active
pub fn fact2(&mut self) -> FACT2_W<'_>
[src]
Bit 2 - Filter active
pub fn fact3(&mut self) -> FACT3_W<'_>
[src]
Bit 3 - Filter active
pub fn fact4(&mut self) -> FACT4_W<'_>
[src]
Bit 4 - Filter active
pub fn fact5(&mut self) -> FACT5_W<'_>
[src]
Bit 5 - Filter active
pub fn fact6(&mut self) -> FACT6_W<'_>
[src]
Bit 6 - Filter active
pub fn fact7(&mut self) -> FACT7_W<'_>
[src]
Bit 7 - Filter active
pub fn fact8(&mut self) -> FACT8_W<'_>
[src]
Bit 8 - Filter active
pub fn fact9(&mut self) -> FACT9_W<'_>
[src]
Bit 9 - Filter active
pub fn fact10(&mut self) -> FACT10_W<'_>
[src]
Bit 10 - Filter active
pub fn fact11(&mut self) -> FACT11_W<'_>
[src]
Bit 11 - Filter active
pub fn fact12(&mut self) -> FACT12_W<'_>
[src]
Bit 12 - Filter active
pub fn fact13(&mut self) -> FACT13_W<'_>
[src]
Bit 13 - Filter active
pub fn fact14(&mut self) -> FACT14_W<'_>
[src]
Bit 14 - Filter active
pub fn fact15(&mut self) -> FACT15_W<'_>
[src]
Bit 15 - Filter active
pub fn fact16(&mut self) -> FACT16_W<'_>
[src]
Bit 16 - Filter active
pub fn fact17(&mut self) -> FACT17_W<'_>
[src]
Bit 17 - Filter active
pub fn fact18(&mut self) -> FACT18_W<'_>
[src]
Bit 18 - Filter active
pub fn fact19(&mut self) -> FACT19_W<'_>
[src]
Bit 19 - Filter active
pub fn fact20(&mut self) -> FACT20_W<'_>
[src]
Bit 20 - Filter active
pub fn fact21(&mut self) -> FACT21_W<'_>
[src]
Bit 21 - Filter active
pub fn fact22(&mut self) -> FACT22_W<'_>
[src]
Bit 22 - Filter active
pub fn fact23(&mut self) -> FACT23_W<'_>
[src]
Bit 23 - Filter active
pub fn fact24(&mut self) -> FACT24_W<'_>
[src]
Bit 24 - Filter active
pub fn fact25(&mut self) -> FACT25_W<'_>
[src]
Bit 25 - Filter active
pub fn fact26(&mut self) -> FACT26_W<'_>
[src]
Bit 26 - Filter active
pub fn fact27(&mut self) -> FACT27_W<'_>
[src]
Bit 27 - Filter active
impl W<u32, Reg<u32, _CR>>
[src]
pub fn en1(&mut self) -> EN1_W<'_>
[src]
Bit 0 - DAC channel1 enable
pub fn boff1(&mut self) -> BOFF1_W<'_>
[src]
Bit 1 - DAC channel1 output buffer disable
pub fn ten1(&mut self) -> TEN1_W<'_>
[src]
Bit 2 - DAC channel1 trigger enable
pub fn tsel1(&mut self) -> TSEL1_W<'_>
[src]
Bits 3:5 - DAC channel1 trigger selection
pub fn wave1(&mut self) -> WAVE1_W<'_>
[src]
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
pub fn mamp1(&mut self) -> MAMP1_W<'_>
[src]
Bits 8:11 - DAC channel1 mask/amplitude selector
pub fn dmaen1(&mut self) -> DMAEN1_W<'_>
[src]
Bit 12 - DAC channel1 DMA enable
pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>
[src]
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
pub fn en2(&mut self) -> EN2_W<'_>
[src]
Bit 16 - DAC channel2 enable
pub fn boff2(&mut self) -> BOFF2_W<'_>
[src]
Bit 17 - DAC channel2 output buffer disable
pub fn ten2(&mut self) -> TEN2_W<'_>
[src]
Bit 18 - DAC channel2 trigger enable
pub fn tsel2(&mut self) -> TSEL2_W<'_>
[src]
Bits 19:21 - DAC channel2 trigger selection
pub fn wave2(&mut self) -> WAVE2_W<'_>
[src]
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
pub fn mamp2(&mut self) -> MAMP2_W<'_>
[src]
Bits 24:27 - DAC channel2 mask/amplitude selector
pub fn dmaen2(&mut self) -> DMAEN2_W<'_>
[src]
Bit 28 - DAC channel2 DMA enable
pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>
[src]
Bit 29 - DAC channel2 DMA underrun interrupt enable
impl W<u32, Reg<u32, _SWTRIGR>>
[src]
pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>
[src]
Bit 0 - DAC channel1 software trigger
pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>
[src]
Bit 1 - DAC channel2 software trigger
impl W<u32, Reg<u32, _DHR12R1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _SR>>
[src]
pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>
[src]
Bit 29 - DAC channel2 DMA underrun flag
pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>
[src]
Bit 13 - DAC channel1 DMA underrun flag
impl W<u32, Reg<u32, _DHR12R2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl W<u32, Reg<u32, _DHR12RD>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 16:27 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12LD>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 20:31 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8RD>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 8:15 - DAC channel2 8-bit right-aligned data
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn enable(&mut self) -> ENABLE_W<'_>
[src]
Bit 0 - Counter enable
pub fn tickint(&mut self) -> TICKINT_W<'_>
[src]
Bit 1 - SysTick exception request enable
pub fn clksource(&mut self) -> CLKSOURCE_W<'_>
[src]
Bit 2 - Clock source selection
pub fn countflag(&mut self) -> COUNTFLAG_W<'_>
[src]
Bit 16 - COUNTFLAG
impl W<u32, Reg<u32, _RVR>>
[src]
impl W<u32, Reg<u32, _CVR>>
[src]
impl W<u32, Reg<u32, _CALIB>>
[src]
pub fn tenms(&mut self) -> TENMS_W<'_>
[src]
Bits 0:23 - Calibration value
pub fn skew(&mut self) -> SKEW_W<'_>
[src]
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
pub fn noref(&mut self) -> NOREF_W<'_>
[src]
Bit 31 - NOREF flag. Reads as zero
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4np(&mut self) -> CC4NP_W<'_>
[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
pub fn cnt_h(&mut self) -> CNT_H_W<'_>
[src]
Bits 16:31 - High counter value (TIM2 only)
pub fn cnt(&mut self) -> CNT_W<'_>
[src]
Bits 0:15 - Counter value
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
pub fn arr_h(&mut self) -> ARR_H_W<'_>
[src]
Bits 16:31 - High Auto-reload value (TIM2 only)
pub fn arr(&mut self) -> ARR_W<'_>
[src]
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
[src]
pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>
[src]
Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
pub fn ccr(&mut self) -> CCR_W<'_>
[src]
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn comp1en(&mut self) -> COMP1EN_W<'_>
[src]
Bit 0 - Comparator 1 enable
pub fn comp1mode(&mut self) -> COMP1MODE_W<'_>
[src]
Bits 2:3 - Comparator 1 mode
pub fn comp1insel(&mut self) -> COMP1INSEL_W<'_>
[src]
Bits 4:6 - Comparator 1 inverting input selection
pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<'_>
[src]
Bits 8:10 - Comparator 1 output selection
pub fn comp1pol(&mut self) -> COMP1POL_W<'_>
[src]
Bit 11 - Comparator 1 output polarity
pub fn comp1hyst(&mut self) -> COMP1HYST_W<'_>
[src]
Bits 12:13 - Comparator 1 hysteresis
pub fn comp1lock(&mut self) -> COMP1LOCK_W<'_>
[src]
Bit 15 - Comparator 1 lock
pub fn comp2en(&mut self) -> COMP2EN_W<'_>
[src]
Bit 16 - Comparator 2 enable
pub fn comp2mode(&mut self) -> COMP2MODE_W<'_>
[src]
Bits 18:19 - Comparator 2 mode
pub fn comp2insel(&mut self) -> COMP2INSEL_W<'_>
[src]
Bits 20:22 - Comparator 2 inverting input selection
pub fn wndwen(&mut self) -> WNDWEN_W<'_>
[src]
Bit 23 - Window mode enable
pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<'_>
[src]
Bits 24:26 - Comparator 2 output selection
pub fn comp2pol(&mut self) -> COMP2POL_W<'_>
[src]
Bit 27 - Comparator 2 output polarity
pub fn comp2hyst(&mut self) -> COMP2HYST_W<'_>
[src]
Bits 28:29 - Comparator 2 hysteresis
pub fn comp2lock(&mut self) -> COMP2LOCK_W<'_>
[src]
Bit 31 - Comparator 2 lock
pub fn comp1sw1(&mut self) -> COMP1SW1_W<'_>
[src]
Bit 1 - Comparator 1 non inverting input DAC switch
impl W<u32, Reg<u32, _DR>>
[src]
impl W<u32, Reg<u32, _IDR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 0 - reset bit
pub fn polysize(&mut self) -> POLYSIZE_W<'_>
[src]
Bits 3:4 - Polynomial size
pub fn rev_in(&mut self) -> REV_IN_W<'_>
[src]
Bits 5:6 - Reverse input data
pub fn rev_out(&mut self) -> REV_OUT_W<'_>
[src]
Bit 7 - Reverse output data
impl W<u32, Reg<u32, _INIT>>
[src]
impl W<u8, Reg<u8, _DR8>>
[src]
impl W<u16, Reg<u16, _DR16>>
[src]
impl W<u32, Reg<u32, _MODER>>
[src]
pub fn moder15(&mut self) -> MODER15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
[src]
pub fn ot15(&mut self) -> OT15_W<'_>
[src]
Bit 15 - Port x configuration bit 15
pub fn ot14(&mut self) -> OT14_W<'_>
[src]
Bit 14 - Port x configuration bit 14
pub fn ot13(&mut self) -> OT13_W<'_>
[src]
Bit 13 - Port x configuration bit 13
pub fn ot12(&mut self) -> OT12_W<'_>
[src]
Bit 12 - Port x configuration bit 12
pub fn ot11(&mut self) -> OT11_W<'_>
[src]
Bit 11 - Port x configuration bit 11
pub fn ot10(&mut self) -> OT10_W<'_>
[src]
Bit 10 - Port x configuration bit 10
pub fn ot9(&mut self) -> OT9_W<'_>
[src]
Bit 9 - Port x configuration bit 9
pub fn ot8(&mut self) -> OT8_W<'_>
[src]
Bit 8 - Port x configuration bit 8
pub fn ot7(&mut self) -> OT7_W<'_>
[src]
Bit 7 - Port x configuration bit 7
pub fn ot6(&mut self) -> OT6_W<'_>
[src]
Bit 6 - Port x configuration bit 6
pub fn ot5(&mut self) -> OT5_W<'_>
[src]
Bit 5 - Port x configuration bit 5
pub fn ot4(&mut self) -> OT4_W<'_>
[src]
Bit 4 - Port x configuration bit 4
pub fn ot3(&mut self) -> OT3_W<'_>
[src]
Bit 3 - Port x configuration bit 3
pub fn ot2(&mut self) -> OT2_W<'_>
[src]
Bit 2 - Port x configuration bit 2
pub fn ot1(&mut self) -> OT1_W<'_>
[src]
Bit 1 - Port x configuration bit 1
pub fn ot0(&mut self) -> OT0_W<'_>
[src]
Bit 0 - Port x configuration bit 0
impl W<u32, Reg<u32, _OSPEEDR>>
[src]
pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
[src]
pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
[src]
pub fn odr15(&mut self) -> ODR15_W<'_>
[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
[src]
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
[src]
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
[src]
Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
[src]
Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
[src]
Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
[src]
Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
[src]
Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
[src]
Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
[src]
Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
[src]
Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
[src]
Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
[src]
Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
[src]
Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
[src]
Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
[src]
Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
[src]
Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
[src]
Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
[src]
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
[src]
pub fn lckk(&mut self) -> LCKK_W<'_>
[src]
Bit 16 - Port x lock bit y
pub fn lck15(&mut self) -> LCK15_W<'_>
[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
[src]
pub fn afrl7(&mut self) -> AFRL7_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
[src]
pub fn afrh15(&mut self) -> AFRH15_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
[src]
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _MODER>>
[src]
pub fn moder15(&mut self) -> MODER15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
[src]
pub fn ot15(&mut self) -> OT15_W<'_>
[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&mut self) -> OT14_W<'_>
[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&mut self) -> OT13_W<'_>
[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&mut self) -> OT12_W<'_>
[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&mut self) -> OT11_W<'_>
[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&mut self) -> OT10_W<'_>
[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&mut self) -> OT9_W<'_>
[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&mut self) -> OT8_W<'_>
[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&mut self) -> OT7_W<'_>
[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&mut self) -> OT6_W<'_>
[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&mut self) -> OT5_W<'_>
[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&mut self) -> OT4_W<'_>
[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&mut self) -> OT3_W<'_>
[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&mut self) -> OT2_W<'_>
[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&mut self) -> OT1_W<'_>
[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&mut self) -> OT0_W<'_>
[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
[src]
pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
[src]
pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
[src]
pub fn odr15(&mut self) -> ODR15_W<'_>
[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
[src]
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
[src]
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
[src]
Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
[src]
Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
[src]
Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
[src]
Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
[src]
Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
[src]
Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
[src]
Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
[src]
Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
[src]
Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
[src]
Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
[src]
Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
[src]
Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
[src]
Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
[src]
Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
[src]
Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
[src]
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
[src]
pub fn lckk(&mut self) -> LCKK_W<'_>
[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&mut self) -> LCK15_W<'_>
[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
[src]
pub fn afrl7(&mut self) -> AFRL7_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
[src]
pub fn afrh15(&mut self) -> AFRH15_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
[src]
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn bidimode(&mut self) -> BIDIMODE_W<'_>
[src]
Bit 15 - Bidirectional data mode enable
pub fn bidioe(&mut self) -> BIDIOE_W<'_>
[src]
Bit 14 - Output enable in bidirectional mode
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 13 - Hardware CRC calculation enable
pub fn crcnext(&mut self) -> CRCNEXT_W<'_>
[src]
Bit 12 - CRC transfer next
pub fn crcl(&mut self) -> CRCL_W<'_>
[src]
Bit 11 - CRC length
pub fn rxonly(&mut self) -> RXONLY_W<'_>
[src]
Bit 10 - Receive only
pub fn ssm(&mut self) -> SSM_W<'_>
[src]
Bit 9 - Software slave management
pub fn ssi(&mut self) -> SSI_W<'_>
[src]
Bit 8 - Internal slave select
pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>
[src]
Bit 7 - Frame format
pub fn spe(&mut self) -> SPE_W<'_>
[src]
Bit 6 - SPI enable
pub fn br(&mut self) -> BR_W<'_>
[src]
Bits 3:5 - Baud rate control
pub fn mstr(&mut self) -> MSTR_W<'_>
[src]
Bit 2 - Master selection
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 1 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 0 - Clock phase
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 0 - Rx buffer DMA enable
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 1 - Tx buffer DMA enable
pub fn ssoe(&mut self) -> SSOE_W<'_>
[src]
Bit 2 - SS output enable
pub fn nssp(&mut self) -> NSSP_W<'_>
[src]
Bit 3 - NSS pulse management
pub fn frf(&mut self) -> FRF_W<'_>
[src]
Bit 4 - Frame format
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 5 - Error interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 6 - RX buffer not empty interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - Tx buffer empty interrupt enable
pub fn ds(&mut self) -> DS_W<'_>
[src]
Bits 8:11 - Data size
pub fn frxth(&mut self) -> FRXTH_W<'_>
[src]
Bit 12 - FIFO reception threshold
pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>
[src]
Bit 13 - Last DMA transfer for reception
pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>
[src]
Bit 14 - Last DMA transfer for transmission
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _DR>>
[src]
impl W<u32, Reg<u32, _CRCPR>>
[src]
impl W<u32, Reg<u32, _I2SCFGR>>
[src]
pub fn i2smod(&mut self) -> I2SMOD_W<'_>
[src]
Bit 11 - I2S mode selection
pub fn i2se(&mut self) -> I2SE_W<'_>
[src]
Bit 10 - I2S Enable
pub fn i2scfg(&mut self) -> I2SCFG_W<'_>
[src]
Bits 8:9 - I2S configuration mode
pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>
[src]
Bit 7 - PCM frame synchronization
pub fn i2sstd(&mut self) -> I2SSTD_W<'_>
[src]
Bits 4:5 - I2S standard selection
pub fn ckpol(&mut self) -> CKPOL_W<'_>
[src]
Bit 3 - Steady state clock polarity
pub fn datlen(&mut self) -> DATLEN_W<'_>
[src]
Bits 1:2 - Data length to be transferred
pub fn chlen(&mut self) -> CHLEN_W<'_>
[src]
Bit 0 - Channel length (number of bits per audio channel)
impl W<u32, Reg<u32, _I2SPR>>
[src]
pub fn mckoe(&mut self) -> MCKOE_W<'_>
[src]
Bit 9 - Master clock output enable
pub fn odd(&mut self) -> ODD_W<'_>
[src]
Bit 8 - Odd factor for the prescaler
pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>
[src]
Bits 0:7 - I2S Linear prescaler
impl W<u32, Reg<u32, _CR>>
[src]
pub fn en1(&mut self) -> EN1_W<'_>
[src]
Bit 0 - DAC channel1 enable
pub fn boff1(&mut self) -> BOFF1_W<'_>
[src]
Bit 1 - DAC channel1 output buffer disable
pub fn ten1(&mut self) -> TEN1_W<'_>
[src]
Bit 2 - DAC channel1 trigger enable
pub fn tsel1(&mut self) -> TSEL1_W<'_>
[src]
Bits 3:5 - DAC channel1 trigger selection
pub fn wave1(&mut self) -> WAVE1_W<'_>
[src]
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
pub fn mamp1(&mut self) -> MAMP1_W<'_>
[src]
Bits 8:11 - DAC channel1 mask/amplitude selector
pub fn dmaen1(&mut self) -> DMAEN1_W<'_>
[src]
Bit 12 - DAC channel1 DMA enable
pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>
[src]
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
pub fn en2(&mut self) -> EN2_W<'_>
[src]
Bit 16 - DAC channel2 enable
pub fn boff2(&mut self) -> BOFF2_W<'_>
[src]
Bit 17 - DAC channel2 output buffer disable
pub fn ten2(&mut self) -> TEN2_W<'_>
[src]
Bit 18 - DAC channel2 trigger enable
pub fn tsel2(&mut self) -> TSEL2_W<'_>
[src]
Bits 19:21 - DAC channel2 trigger selection
pub fn wave2(&mut self) -> WAVE2_W<'_>
[src]
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
pub fn mamp2(&mut self) -> MAMP2_W<'_>
[src]
Bits 24:27 - DAC channel2 mask/amplitude selector
pub fn dmaen2(&mut self) -> DMAEN2_W<'_>
[src]
Bit 28 - DAC channel2 DMA enable
pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>
[src]
Bit 29 - DAC channel2 DMA underrun interrupt enable
impl W<u32, Reg<u32, _SWTRIGR>>
[src]
pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>
[src]
Bit 0 - DAC channel1 software trigger
pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>
[src]
Bit 1 - DAC channel2 software trigger
impl W<u32, Reg<u32, _DHR12R1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _SR>>
[src]
pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>
[src]
Bit 29 - DAC channel2 DMA underrun flag
pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>
[src]
Bit 13 - DAC channel1 DMA underrun flag
impl W<u32, Reg<u32, _DHR12R2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl W<u32, Reg<u32, _DHR12RD>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 16:27 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12LD>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 20:31 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8RD>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 8:15 - DAC channel2 8-bit right-aligned data
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbp(&mut self) -> DBP_W<'_>
[src]
Bit 8 - Disable backup domain write protection
pub fn pls(&mut self) -> PLS_W<'_>
[src]
Bits 5:7 - PVD level selection
pub fn pvde(&mut self) -> PVDE_W<'_>
[src]
Bit 4 - Power voltage detector enable
pub fn csbf(&mut self) -> CSBF_W<'_>
[src]
Bit 3 - Clear standby flag
pub fn cwuf(&mut self) -> CWUF_W<'_>
[src]
Bit 2 - Clear wakeup flag
pub fn pdds(&mut self) -> PDDS_W<'_>
[src]
Bit 1 - Power down deepsleep
pub fn lpds(&mut self) -> LPDS_W<'_>
[src]
Bit 0 - Low-power deep sleep
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn ewup1(&mut self) -> EWUP1_W<'_>
[src]
Bit 8 - Enable WKUP pin 1
pub fn ewup2(&mut self) -> EWUP2_W<'_>
[src]
Bit 9 - Enable WKUP pin 2
pub fn ewup3(&mut self) -> EWUP3_W<'_>
[src]
Bit 10 - Enable WKUP pin 3
pub fn ewup4(&mut self) -> EWUP4_W<'_>
[src]
Bit 11 - Enable WKUP pin 4
pub fn ewup5(&mut self) -> EWUP5_W<'_>
[src]
Bit 12 - Enable WKUP pin 5
pub fn ewup6(&mut self) -> EWUP6_W<'_>
[src]
Bit 13 - Enable WKUP pin 6
pub fn ewup7(&mut self) -> EWUP7_W<'_>
[src]
Bit 14 - Enable WKUP pin 7
pub fn ewup8(&mut self) -> EWUP8_W<'_>
[src]
Bit 15 - Enable WKUP pin 8
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn pe(&mut self) -> PE_W<'_>
[src]
Bit 0 - Peripheral enable
pub fn txie(&mut self) -> TXIE_W<'_>
[src]
Bit 1 - TX Interrupt enable
pub fn rxie(&mut self) -> RXIE_W<'_>
[src]
Bit 2 - RX Interrupt enable
pub fn addrie(&mut self) -> ADDRIE_W<'_>
[src]
Bit 3 - Address match interrupt enable (slave only)
pub fn nackie(&mut self) -> NACKIE_W<'_>
[src]
Bit 4 - Not acknowledge received interrupt enable
pub fn stopie(&mut self) -> STOPIE_W<'_>
[src]
Bit 5 - STOP detection Interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transfer Complete interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 7 - Error interrupts enable
pub fn dnf(&mut self) -> DNF_W<'_>
[src]
Bits 8:11 - Digital noise filter
pub fn anfoff(&mut self) -> ANFOFF_W<'_>
[src]
Bit 12 - Analog noise filter OFF
pub fn swrst(&mut self) -> SWRST_W<'_>
[src]
Bit 13 - Software reset
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 14 - DMA transmission requests enable
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 15 - DMA reception requests enable
pub fn sbc(&mut self) -> SBC_W<'_>
[src]
Bit 16 - Slave byte control
pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>
[src]
Bit 17 - Clock stretching disable
pub fn wupen(&mut self) -> WUPEN_W<'_>
[src]
Bit 18 - Wakeup from STOP enable
pub fn gcen(&mut self) -> GCEN_W<'_>
[src]
Bit 19 - General call enable
pub fn smbhen(&mut self) -> SMBHEN_W<'_>
[src]
Bit 20 - SMBus Host address enable
pub fn smbden(&mut self) -> SMBDEN_W<'_>
[src]
Bit 21 - SMBus Device Default address enable
pub fn alerten(&mut self) -> ALERTEN_W<'_>
[src]
Bit 22 - SMBUS alert enable
pub fn pecen(&mut self) -> PECEN_W<'_>
[src]
Bit 23 - PEC enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn pecbyte(&mut self) -> PECBYTE_W<'_>
[src]
Bit 26 - Packet error checking byte
pub fn autoend(&mut self) -> AUTOEND_W<'_>
[src]
Bit 25 - Automatic end mode (master mode)
pub fn reload(&mut self) -> RELOAD_W<'_>
[src]
Bit 24 - NBYTES reload mode
pub fn nbytes(&mut self) -> NBYTES_W<'_>
[src]
Bits 16:23 - Number of bytes
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 15 - NACK generation (slave mode)
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bit 14 - Stop generation (master mode)
pub fn start(&mut self) -> START_W<'_>
[src]
Bit 13 - Start generation
pub fn head10r(&mut self) -> HEAD10R_W<'_>
[src]
Bit 12 - 10-bit address header only read direction (master receiver mode)
pub fn add10(&mut self) -> ADD10_W<'_>
[src]
Bit 11 - 10-bit addressing mode (master mode)
pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>
[src]
Bit 10 - Transfer direction (master mode)
pub fn sadd(&mut self) -> SADD_W<'_>
[src]
Bits 0:9 - Slave address bit 9:8 (master mode)
impl W<u32, Reg<u32, _OAR1>>
[src]
pub fn oa1mode(&mut self) -> OA1MODE_W<'_>
[src]
Bit 10 - Own Address 1 10-bit mode
pub fn oa1en(&mut self) -> OA1EN_W<'_>
[src]
Bit 15 - Own Address 1 enable
pub fn oa1(&mut self) -> OA1_W<'_>
[src]
Bits 0:9 - Interface address
impl W<u32, Reg<u32, _OAR2>>
[src]
pub fn oa2(&mut self) -> OA2_W<'_>
[src]
Bits 1:7 - Interface address
pub fn oa2msk(&mut self) -> OA2MSK_W<'_>
[src]
Bits 8:10 - Own Address 2 masks
pub fn oa2en(&mut self) -> OA2EN_W<'_>
[src]
Bit 15 - Own Address 2 enable
impl W<u32, Reg<u32, _TIMINGR>>
[src]
pub fn scll(&mut self) -> SCLL_W<'_>
[src]
Bits 0:7 - SCL low period (master mode)
pub fn sclh(&mut self) -> SCLH_W<'_>
[src]
Bits 8:15 - SCL high period (master mode)
pub fn sdadel(&mut self) -> SDADEL_W<'_>
[src]
Bits 16:19 - Data hold time
pub fn scldel(&mut self) -> SCLDEL_W<'_>
[src]
Bits 20:23 - Data setup time
pub fn presc(&mut self) -> PRESC_W<'_>
[src]
Bits 28:31 - Timing prescaler
impl W<u32, Reg<u32, _TIMEOUTR>>
[src]
pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>
[src]
Bits 0:11 - Bus timeout A
pub fn tidle(&mut self) -> TIDLE_W<'_>
[src]
Bit 12 - Idle clock timeout detection
pub fn timouten(&mut self) -> TIMOUTEN_W<'_>
[src]
Bit 15 - Clock timeout enable
pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>
[src]
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
[src]
Bit 31 - Extended clock timeout enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn txis(&mut self) -> TXIS_W<'_>
[src]
Bit 1 - Transmit interrupt status (transmitters)
pub fn txe(&mut self) -> TXE_W<'_>
[src]
Bit 0 - Transmit data register empty (transmitters)
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn alertcf(&mut self) -> ALERTCF_W<'_>
[src]
Bit 13 - Alert flag clear
pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>
[src]
Bit 12 - Timeout detection flag clear
pub fn peccf(&mut self) -> PECCF_W<'_>
[src]
Bit 11 - PEC Error flag clear
pub fn ovrcf(&mut self) -> OVRCF_W<'_>
[src]
Bit 10 - Overrun/Underrun flag clear
pub fn arlocf(&mut self) -> ARLOCF_W<'_>
[src]
Bit 9 - Arbitration lost flag clear
pub fn berrcf(&mut self) -> BERRCF_W<'_>
[src]
Bit 8 - Bus error flag clear
pub fn stopcf(&mut self) -> STOPCF_W<'_>
[src]
Bit 5 - Stop detection flag clear
pub fn nackcf(&mut self) -> NACKCF_W<'_>
[src]
Bit 4 - Not Acknowledge flag clear
pub fn addrcf(&mut self) -> ADDRCF_W<'_>
[src]
Bit 3 - Address Matched flag clear
impl W<u32, Reg<u32, _TXDR>>
[src]
impl W<u32, Reg<u32, _KR>>
[src]
impl W<u32, Reg<u32, _PR>>
[src]
impl W<u32, Reg<u32, _RLR>>
[src]
impl W<u32, Reg<u32, _WINR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn wdga(&mut self) -> WDGA_W<'_>
[src]
Bit 7 - Activation bit
pub fn t(&mut self) -> T_W<'_>
[src]
Bits 0:6 - 7-bit counter
impl W<u32, Reg<u32, _CFR>>
[src]
pub fn ewi(&mut self) -> EWI_W<'_>
[src]
Bit 9 - Early wakeup interrupt
pub fn w(&mut self) -> W_W<'_>
[src]
Bits 0:6 - 7-bit window value
pub fn wdgtb(&mut self) -> WDGTB_W<'_>
[src]
Bits 7:8 - Timer base
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois4(&mut self) -> OIS4_W<'_>
[src]
Bit 14 - Output Idle state 4
pub fn ois3n(&mut self) -> OIS3N_W<'_>
[src]
Bit 13 - Output Idle state 3
pub fn ois3(&mut self) -> OIS3_W<'_>
[src]
Bit 12 - Output Idle state 3
pub fn ois2n(&mut self) -> OIS2N_W<'_>
[src]
Bit 11 - Output Idle state 2
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output Compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output Compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3ne(&mut self) -> CC3NE_W<'_>
[src]
Bit 10 - Capture/Compare 3 complementary output enable
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2ne(&mut self) -> CC2NE_W<'_>
[src]
Bit 6 - Capture/Compare 2 complementary output enable
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4np(&mut self) -> CC4NP_W<'_>
[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _OR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _EGR>>
[src]
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _IMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Interrupt Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Interrupt Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Interrupt Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Interrupt Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Interrupt Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Interrupt Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Interrupt Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Interrupt Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Interrupt Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Interrupt Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Interrupt Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Interrupt Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Interrupt Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Interrupt Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Interrupt Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Interrupt Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Interrupt Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Interrupt Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Interrupt Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Interrupt Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Interrupt Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Interrupt Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Interrupt Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Interrupt Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Interrupt Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Interrupt Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Interrupt Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Interrupt Mask on line 27
impl W<u32, Reg<u32, _EMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Event Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Event Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Event Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Event Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Event Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Event Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Event Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Event Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Event Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Event Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Event Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Event Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Event Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Event Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Event Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Event Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Event Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Event Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Event Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Event Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Event Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Event Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Event Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Event Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Event Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Event Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Event Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Event Mask on line 27
impl W<u32, Reg<u32, _RTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Rising trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Rising trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Rising trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Rising trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Rising trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Rising trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Rising trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Rising trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
[src]
Bit 8 - Rising trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
[src]
Bit 9 - Rising trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Rising trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Rising trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Rising trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Rising trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Rising trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Rising trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Rising trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Rising trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Rising trigger event configuration of line 19
impl W<u32, Reg<u32, _FTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Falling trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Falling trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Falling trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Falling trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Falling trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Falling trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Falling trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Falling trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
[src]
Bit 8 - Falling trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
[src]
Bit 9 - Falling trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Falling trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Falling trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Falling trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Falling trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Falling trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Falling trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Falling trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Falling trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Falling trigger event configuration of line 19
impl W<u32, Reg<u32, _SWIER>>
[src]
pub fn swier0(&mut self) -> SWIER0_W<'_>
[src]
Bit 0 - Software Interrupt on line 0
pub fn swier1(&mut self) -> SWIER1_W<'_>
[src]
Bit 1 - Software Interrupt on line 1
pub fn swier2(&mut self) -> SWIER2_W<'_>
[src]
Bit 2 - Software Interrupt on line 2
pub fn swier3(&mut self) -> SWIER3_W<'_>
[src]
Bit 3 - Software Interrupt on line 3
pub fn swier4(&mut self) -> SWIER4_W<'_>
[src]
Bit 4 - Software Interrupt on line 4
pub fn swier5(&mut self) -> SWIER5_W<'_>
[src]
Bit 5 - Software Interrupt on line 5
pub fn swier6(&mut self) -> SWIER6_W<'_>
[src]
Bit 6 - Software Interrupt on line 6
pub fn swier7(&mut self) -> SWIER7_W<'_>
[src]
Bit 7 - Software Interrupt on line 7
pub fn swier8(&mut self) -> SWIER8_W<'_>
[src]
Bit 8 - Software Interrupt on line 8
pub fn swier9(&mut self) -> SWIER9_W<'_>
[src]
Bit 9 - Software Interrupt on line 9
pub fn swier10(&mut self) -> SWIER10_W<'_>
[src]
Bit 10 - Software Interrupt on line 10
pub fn swier11(&mut self) -> SWIER11_W<'_>
[src]
Bit 11 - Software Interrupt on line 11
pub fn swier12(&mut self) -> SWIER12_W<'_>
[src]
Bit 12 - Software Interrupt on line 12
pub fn swier13(&mut self) -> SWIER13_W<'_>
[src]
Bit 13 - Software Interrupt on line 13
pub fn swier14(&mut self) -> SWIER14_W<'_>
[src]
Bit 14 - Software Interrupt on line 14
pub fn swier15(&mut self) -> SWIER15_W<'_>
[src]
Bit 15 - Software Interrupt on line 15
pub fn swier16(&mut self) -> SWIER16_W<'_>
[src]
Bit 16 - Software Interrupt on line 16
pub fn swier17(&mut self) -> SWIER17_W<'_>
[src]
Bit 17 - Software Interrupt on line 17
pub fn swier19(&mut self) -> SWIER19_W<'_>
[src]
Bit 19 - Software Interrupt on line 19
impl W<u32, Reg<u32, _PR>>
[src]
pub fn pif31(&mut self) -> PIF31_W<'_>
[src]
Bit 31 - Pending interrupt flag on line 31
pub fn pif22(&mut self) -> PIF22_W<'_>
[src]
Bit 22 - Pending interrupt flag on line 22
pub fn pif21(&mut self) -> PIF21_W<'_>
[src]
Bit 21 - Pending interrupt flag on line 21
pub fn pif20(&mut self) -> PIF20_W<'_>
[src]
Bit 20 - Pending interrupt flag on line 20
pub fn pif19(&mut self) -> PIF19_W<'_>
[src]
Bit 19 - Pending interrupt flag on line 19
pub fn pif17(&mut self) -> PIF17_W<'_>
[src]
Bit 17 - Pending interrupt flag on line 17
pub fn pif16(&mut self) -> PIF16_W<'_>
[src]
Bit 16 - Pending interrupt flag on line 16
pub fn pif15(&mut self) -> PIF15_W<'_>
[src]
Bit 15 - Pending interrupt flag on line 15
pub fn pif14(&mut self) -> PIF14_W<'_>
[src]
Bit 14 - Pending interrupt flag on line 14
pub fn pif13(&mut self) -> PIF13_W<'_>
[src]
Bit 13 - Pending interrupt flag on line 13
pub fn pif12(&mut self) -> PIF12_W<'_>
[src]
Bit 12 - Pending interrupt flag on line 12
pub fn pif11(&mut self) -> PIF11_W<'_>
[src]
Bit 11 - Pending interrupt flag on line 11
pub fn pif10(&mut self) -> PIF10_W<'_>
[src]
Bit 10 - Pending interrupt flag on line 10
pub fn pif9(&mut self) -> PIF9_W<'_>
[src]
Bit 9 - Pending interrupt flag on line 9
pub fn pif8(&mut self) -> PIF8_W<'_>
[src]
Bit 8 - Pending interrupt flag on line 8
pub fn pif7(&mut self) -> PIF7_W<'_>
[src]
Bit 7 - Pending interrupt flag on line 7
pub fn pif6(&mut self) -> PIF6_W<'_>
[src]
Bit 6 - Pending interrupt flag on line 6
pub fn pif5(&mut self) -> PIF5_W<'_>
[src]
Bit 5 - Pending interrupt flag on line 5
pub fn pif4(&mut self) -> PIF4_W<'_>
[src]
Bit 4 - Pending interrupt flag on line 4
pub fn pif3(&mut self) -> PIF3_W<'_>
[src]
Bit 3 - Pending interrupt flag on line 3
pub fn pif2(&mut self) -> PIF2_W<'_>
[src]
Bit 2 - Pending interrupt flag on line 2
pub fn pif1(&mut self) -> PIF1_W<'_>
[src]
Bit 1 - Pending interrupt flag on line 1
pub fn pif0(&mut self) -> PIF0_W<'_>
[src]
Bit 0 - Pending interrupt flag on line 0
impl W<u32, Reg<u32, _CR>>
[src]
pub fn en(&mut self) -> EN_W<'_>
[src]
Bit 0 - Channel enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 1 - Transfer complete interrupt enable
pub fn htie(&mut self) -> HTIE_W<'_>
[src]
Bit 2 - Half Transfer interrupt enable
pub fn teie(&mut self) -> TEIE_W<'_>
[src]
Bit 3 - Transfer error interrupt enable
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Data transfer direction
pub fn circ(&mut self) -> CIRC_W<'_>
[src]
Bit 5 - Circular mode
pub fn pinc(&mut self) -> PINC_W<'_>
[src]
Bit 6 - Peripheral increment mode
pub fn minc(&mut self) -> MINC_W<'_>
[src]
Bit 7 - Memory increment mode
pub fn psize(&mut self) -> PSIZE_W<'_>
[src]
Bits 8:9 - Peripheral size
pub fn msize(&mut self) -> MSIZE_W<'_>
[src]
Bits 10:11 - Memory size
pub fn pl(&mut self) -> PL_W<'_>
[src]
Bits 12:13 - Channel Priority level
pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>
[src]
Bit 14 - Memory to memory mode
impl W<u32, Reg<u32, _NDTR>>
[src]
impl W<u32, Reg<u32, _PAR>>
[src]
impl W<u32, Reg<u32, _MAR>>
[src]
impl W<u32, Reg<u32, _IFCR>>
[src]
pub fn cgif1(&mut self) -> CGIF1_W<'_>
[src]
Bit 0 - Channel 1 Global interrupt clear
pub fn ctcif1(&mut self) -> CTCIF1_W<'_>
[src]
Bit 1 - Channel 1 Transfer Complete clear
pub fn chtif1(&mut self) -> CHTIF1_W<'_>
[src]
Bit 2 - Channel 1 Half Transfer clear
pub fn cteif1(&mut self) -> CTEIF1_W<'_>
[src]
Bit 3 - Channel 1 Transfer Error clear
pub fn cgif2(&mut self) -> CGIF2_W<'_>
[src]
Bit 4 - Channel 2 Global interrupt clear
pub fn ctcif2(&mut self) -> CTCIF2_W<'_>
[src]
Bit 5 - Channel 2 Transfer Complete clear
pub fn chtif2(&mut self) -> CHTIF2_W<'_>
[src]
Bit 6 - Channel 2 Half Transfer clear
pub fn cteif2(&mut self) -> CTEIF2_W<'_>
[src]
Bit 7 - Channel 2 Transfer Error clear
pub fn cgif3(&mut self) -> CGIF3_W<'_>
[src]
Bit 8 - Channel 3 Global interrupt clear
pub fn ctcif3(&mut self) -> CTCIF3_W<'_>
[src]
Bit 9 - Channel 3 Transfer Complete clear
pub fn chtif3(&mut self) -> CHTIF3_W<'_>
[src]
Bit 10 - Channel 3 Half Transfer clear
pub fn cteif3(&mut self) -> CTEIF3_W<'_>
[src]
Bit 11 - Channel 3 Transfer Error clear
pub fn cgif4(&mut self) -> CGIF4_W<'_>
[src]
Bit 12 - Channel 4 Global interrupt clear
pub fn ctcif4(&mut self) -> CTCIF4_W<'_>
[src]
Bit 13 - Channel 4 Transfer Complete clear
pub fn chtif4(&mut self) -> CHTIF4_W<'_>
[src]
Bit 14 - Channel 4 Half Transfer clear
pub fn cteif4(&mut self) -> CTEIF4_W<'_>
[src]
Bit 15 - Channel 4 Transfer Error clear
pub fn cgif5(&mut self) -> CGIF5_W<'_>
[src]
Bit 16 - Channel 5 Global interrupt clear
pub fn ctcif5(&mut self) -> CTCIF5_W<'_>
[src]
Bit 17 - Channel 5 Transfer Complete clear
pub fn chtif5(&mut self) -> CHTIF5_W<'_>
[src]
Bit 18 - Channel 5 Half Transfer clear
pub fn cteif5(&mut self) -> CTEIF5_W<'_>
[src]
Bit 19 - Channel 5 Transfer Error clear
pub fn cgif6(&mut self) -> CGIF6_W<'_>
[src]
Bit 20 - Channel 6 Global interrupt clear
pub fn ctcif6(&mut self) -> CTCIF6_W<'_>
[src]
Bit 21 - Channel 6 Transfer Complete clear
pub fn chtif6(&mut self) -> CHTIF6_W<'_>
[src]
Bit 22 - Channel 6 Half Transfer clear
pub fn cteif6(&mut self) -> CTEIF6_W<'_>
[src]
Bit 23 - Channel 6 Transfer Error clear
pub fn cgif7(&mut self) -> CGIF7_W<'_>
[src]
Bit 24 - Channel 7 Global interrupt clear
pub fn ctcif7(&mut self) -> CTCIF7_W<'_>
[src]
Bit 25 - Channel 7 Transfer Complete clear
pub fn chtif7(&mut self) -> CHTIF7_W<'_>
[src]
Bit 26 - Channel 7 Half Transfer clear
pub fn cteif7(&mut self) -> CTEIF7_W<'_>
[src]
Bit 27 - Channel 7 Transfer Error clear
impl W<u32, Reg<u32, _CR>>
[src]
pub fn hsion(&mut self) -> HSION_W<'_>
[src]
Bit 0 - Internal High Speed clock enable
pub fn hsitrim(&mut self) -> HSITRIM_W<'_>
[src]
Bits 3:7 - Internal High Speed clock trimming
pub fn hseon(&mut self) -> HSEON_W<'_>
[src]
Bit 16 - External High Speed clock enable
pub fn hsebyp(&mut self) -> HSEBYP_W<'_>
[src]
Bit 18 - External High Speed clock Bypass
pub fn csson(&mut self) -> CSSON_W<'_>
[src]
Bit 19 - Clock Security System enable
pub fn pllon(&mut self) -> PLLON_W<'_>
[src]
Bit 24 - PLL enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn sw(&mut self) -> SW_W<'_>
[src]
Bits 0:1 - System clock Switch
pub fn hpre(&mut self) -> HPRE_W<'_>
[src]
Bits 4:7 - AHB prescaler
pub fn ppre(&mut self) -> PPRE_W<'_>
[src]
Bits 8:10 - APB Low speed prescaler (APB1)
pub fn adcpre(&mut self) -> ADCPRE_W<'_>
[src]
Bit 14 - APCPRE is deprecated. See ADC field in CFGR2 register.
pub fn pllsrc(&mut self) -> PLLSRC_W<'_>
[src]
Bits 15:16 - PLL input clock source
pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>
[src]
Bit 17 - HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning
pub fn pllmul(&mut self) -> PLLMUL_W<'_>
[src]
Bits 18:21 - PLL Multiplication Factor
pub fn mco(&mut self) -> MCO_W<'_>
[src]
Bits 24:26 - Microcontroller clock output
pub fn mcopre(&mut self) -> MCOPRE_W<'_>
[src]
Bits 28:30 - Microcontroller Clock Output Prescaler
pub fn pllnodiv(&mut self) -> PLLNODIV_W<'_>
[src]
Bit 31 - PLL clock not divided for MCO
impl W<u32, Reg<u32, _CIR>>
[src]
pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>
[src]
Bit 8 - LSI Ready Interrupt Enable
pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>
[src]
Bit 9 - LSE Ready Interrupt Enable
pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>
[src]
Bit 10 - HSI Ready Interrupt Enable
pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>
[src]
Bit 11 - HSE Ready Interrupt Enable
pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>
[src]
Bit 12 - PLL Ready Interrupt Enable
pub fn hsi14rdyie(&mut self) -> HSI14RDYIE_W<'_>
[src]
Bit 13 - HSI14 ready interrupt enable
pub fn hsi48rdyie(&mut self) -> HSI48RDYIE_W<'_>
[src]
Bit 14 - HSI48 ready interrupt enable
pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>
[src]
Bit 16 - LSI Ready Interrupt Clear
pub fn lserdyc(&mut self) -> LSERDYC_W<'_>
[src]
Bit 17 - LSE Ready Interrupt Clear
pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>
[src]
Bit 18 - HSI Ready Interrupt Clear
pub fn hserdyc(&mut self) -> HSERDYC_W<'_>
[src]
Bit 19 - HSE Ready Interrupt Clear
pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>
[src]
Bit 20 - PLL Ready Interrupt Clear
pub fn hsi14rdyc(&mut self) -> HSI14RDYC_W<'_>
[src]
Bit 21 - HSI 14 MHz Ready Interrupt Clear
pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W<'_>
[src]
Bit 22 - HSI48 Ready Interrupt Clear
pub fn cssc(&mut self) -> CSSC_W<'_>
[src]
Bit 23 - Clock security system interrupt clear
impl W<u32, Reg<u32, _APB2RSTR>>
[src]
pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>
[src]
Bit 0 - SYSCFG and COMP reset
pub fn adcrst(&mut self) -> ADCRST_W<'_>
[src]
Bit 9 - ADC interface reset
pub fn tim1rst(&mut self) -> TIM1RST_W<'_>
[src]
Bit 11 - TIM1 timer reset
pub fn spi1rst(&mut self) -> SPI1RST_W<'_>
[src]
Bit 12 - SPI 1 reset
pub fn usart1rst(&mut self) -> USART1RST_W<'_>
[src]
Bit 14 - USART1 reset
pub fn tim15rst(&mut self) -> TIM15RST_W<'_>
[src]
Bit 16 - TIM15 timer reset
pub fn tim16rst(&mut self) -> TIM16RST_W<'_>
[src]
Bit 17 - TIM16 timer reset
pub fn tim17rst(&mut self) -> TIM17RST_W<'_>
[src]
Bit 18 - TIM17 timer reset
pub fn dbgmcurst(&mut self) -> DBGMCURST_W<'_>
[src]
Bit 22 - Debug MCU reset
pub fn usart6rst(&mut self) -> USART6RST_W<'_>
[src]
Bit 5 - USART6 reset
impl W<u32, Reg<u32, _APB1RSTR>>
[src]
pub fn tim2rst(&mut self) -> TIM2RST_W<'_>
[src]
Bit 0 - Timer 2 reset
pub fn tim3rst(&mut self) -> TIM3RST_W<'_>
[src]
Bit 1 - Timer 3 reset
pub fn tim6rst(&mut self) -> TIM6RST_W<'_>
[src]
Bit 4 - Timer 6 reset
pub fn tim7rst(&mut self) -> TIM7RST_W<'_>
[src]
Bit 5 - TIM7 timer reset
pub fn tim14rst(&mut self) -> TIM14RST_W<'_>
[src]
Bit 8 - Timer 14 reset
pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>
[src]
Bit 11 - Window watchdog reset
pub fn spi2rst(&mut self) -> SPI2RST_W<'_>
[src]
Bit 14 - SPI2 reset
pub fn usart2rst(&mut self) -> USART2RST_W<'_>
[src]
Bit 17 - USART 2 reset
pub fn usart3rst(&mut self) -> USART3RST_W<'_>
[src]
Bit 18 - USART3 reset
pub fn usart4rst(&mut self) -> USART4RST_W<'_>
[src]
Bit 19 - USART4 reset
pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>
[src]
Bit 21 - I2C1 reset
pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>
[src]
Bit 22 - I2C2 reset
pub fn usbrst(&mut self) -> USBRST_W<'_>
[src]
Bit 23 - USB interface reset
pub fn canrst(&mut self) -> CANRST_W<'_>
[src]
Bit 25 - CAN interface reset
pub fn crsrst(&mut self) -> CRSRST_W<'_>
[src]
Bit 27 - Clock Recovery System interface reset
pub fn pwrrst(&mut self) -> PWRRST_W<'_>
[src]
Bit 28 - Power interface reset
pub fn dacrst(&mut self) -> DACRST_W<'_>
[src]
Bit 29 - DAC interface reset
pub fn cecrst(&mut self) -> CECRST_W<'_>
[src]
Bit 30 - HDMI CEC reset
pub fn usart5rst(&mut self) -> USART5RST_W<'_>
[src]
Bit 20 - USART5 reset
impl W<u32, Reg<u32, _AHBENR>>
[src]
pub fn dma1en(&mut self) -> DMA1EN_W<'_>
[src]
Bit 0 - DMA1 clock enable
pub fn sramen(&mut self) -> SRAMEN_W<'_>
[src]
Bit 2 - SRAM interface clock enable
pub fn flitfen(&mut self) -> FLITFEN_W<'_>
[src]
Bit 4 - FLITF clock enable
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 6 - CRC clock enable
pub fn iopaen(&mut self) -> IOPAEN_W<'_>
[src]
Bit 17 - I/O port A clock enable
pub fn iopben(&mut self) -> IOPBEN_W<'_>
[src]
Bit 18 - I/O port B clock enable
pub fn iopcen(&mut self) -> IOPCEN_W<'_>
[src]
Bit 19 - I/O port C clock enable
pub fn iopden(&mut self) -> IOPDEN_W<'_>
[src]
Bit 20 - I/O port D clock enable
pub fn iopfen(&mut self) -> IOPFEN_W<'_>
[src]
Bit 22 - I/O port F clock enable
pub fn tscen(&mut self) -> TSCEN_W<'_>
[src]
Bit 24 - Touch sensing controller clock enable
pub fn iopeen(&mut self) -> IOPEEN_W<'_>
[src]
Bit 21 - I/O port E clock enable
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - DMA clock enable
impl W<u32, Reg<u32, _APB2ENR>>
[src]
pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>
[src]
Bit 0 - SYSCFG clock enable
pub fn adcen(&mut self) -> ADCEN_W<'_>
[src]
Bit 9 - ADC 1 interface clock enable
pub fn tim1en(&mut self) -> TIM1EN_W<'_>
[src]
Bit 11 - TIM1 Timer clock enable
pub fn spi1en(&mut self) -> SPI1EN_W<'_>
[src]
Bit 12 - SPI 1 clock enable
pub fn usart1en(&mut self) -> USART1EN_W<'_>
[src]
Bit 14 - USART1 clock enable
pub fn tim15en(&mut self) -> TIM15EN_W<'_>
[src]
Bit 16 - TIM15 timer clock enable
pub fn tim16en(&mut self) -> TIM16EN_W<'_>
[src]
Bit 17 - TIM16 timer clock enable
pub fn tim17en(&mut self) -> TIM17EN_W<'_>
[src]
Bit 18 - TIM17 timer clock enable
pub fn dbgmcuen(&mut self) -> DBGMCUEN_W<'_>
[src]
Bit 22 - MCU debug module clock enable
pub fn usart6en(&mut self) -> USART6EN_W<'_>
[src]
Bit 5 - USART6 clock enable
impl W<u32, Reg<u32, _APB1ENR>>
[src]
pub fn tim2en(&mut self) -> TIM2EN_W<'_>
[src]
Bit 0 - Timer 2 clock enable
pub fn tim3en(&mut self) -> TIM3EN_W<'_>
[src]
Bit 1 - Timer 3 clock enable
pub fn tim6en(&mut self) -> TIM6EN_W<'_>
[src]
Bit 4 - Timer 6 clock enable
pub fn tim7en(&mut self) -> TIM7EN_W<'_>
[src]
Bit 5 - TIM7 timer clock enable
pub fn tim14en(&mut self) -> TIM14EN_W<'_>
[src]
Bit 8 - Timer 14 clock enable
pub fn wwdgen(&mut self) -> WWDGEN_W<'_>
[src]
Bit 11 - Window watchdog clock enable
pub fn spi2en(&mut self) -> SPI2EN_W<'_>
[src]
Bit 14 - SPI 2 clock enable
pub fn usart2en(&mut self) -> USART2EN_W<'_>
[src]
Bit 17 - USART 2 clock enable
pub fn usart3en(&mut self) -> USART3EN_W<'_>
[src]
Bit 18 - USART3 clock enable
pub fn usart4en(&mut self) -> USART4EN_W<'_>
[src]
Bit 19 - USART4 clock enable
pub fn i2c1en(&mut self) -> I2C1EN_W<'_>
[src]
Bit 21 - I2C 1 clock enable
pub fn i2c2en(&mut self) -> I2C2EN_W<'_>
[src]
Bit 22 - I2C 2 clock enable
pub fn usben(&mut self) -> USBEN_W<'_>
[src]
Bit 23 - USB interface clock enable
pub fn canen(&mut self) -> CANEN_W<'_>
[src]
Bit 25 - CAN interface clock enable
pub fn crsen(&mut self) -> CRSEN_W<'_>
[src]
Bit 27 - Clock Recovery System interface clock enable
pub fn pwren(&mut self) -> PWREN_W<'_>
[src]
Bit 28 - Power interface clock enable
pub fn dacen(&mut self) -> DACEN_W<'_>
[src]
Bit 29 - DAC interface clock enable
pub fn cecen(&mut self) -> CECEN_W<'_>
[src]
Bit 30 - HDMI CEC interface clock enable
pub fn usart5en(&mut self) -> USART5EN_W<'_>
[src]
Bit 20 - USART5 clock enable
impl W<u32, Reg<u32, _BDCR>>
[src]
pub fn lseon(&mut self) -> LSEON_W<'_>
[src]
Bit 0 - External Low Speed oscillator enable
pub fn lsebyp(&mut self) -> LSEBYP_W<'_>
[src]
Bit 2 - External Low Speed oscillator bypass
pub fn lsedrv(&mut self) -> LSEDRV_W<'_>
[src]
Bits 3:4 - LSE oscillator drive capability
pub fn rtcsel(&mut self) -> RTCSEL_W<'_>
[src]
Bits 8:9 - RTC clock source selection
pub fn rtcen(&mut self) -> RTCEN_W<'_>
[src]
Bit 15 - RTC clock enable
pub fn bdrst(&mut self) -> BDRST_W<'_>
[src]
Bit 16 - Backup domain software reset
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn lsion(&mut self) -> LSION_W<'_>
[src]
Bit 0 - Internal low speed oscillator enable
pub fn rmvf(&mut self) -> RMVF_W<'_>
[src]
Bit 24 - Remove reset flag
pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>
[src]
Bit 25 - Option byte loader reset flag
pub fn pinrstf(&mut self) -> PINRSTF_W<'_>
[src]
Bit 26 - PIN reset flag
pub fn porrstf(&mut self) -> PORRSTF_W<'_>
[src]
Bit 27 - POR/PDR reset flag
pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>
[src]
Bit 28 - Software reset flag
pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>
[src]
Bit 29 - Independent watchdog reset flag
pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>
[src]
Bit 30 - Window watchdog reset flag
pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>
[src]
Bit 31 - Low-power reset flag
pub fn v18pwrrstf(&mut self) -> V18PWRRSTF_W<'_>
[src]
Bit 23 - 1.8 V domain reset flag
impl W<u32, Reg<u32, _AHBRSTR>>
[src]
pub fn ioparst(&mut self) -> IOPARST_W<'_>
[src]
Bit 17 - I/O port A reset
pub fn iopbrst(&mut self) -> IOPBRST_W<'_>
[src]
Bit 18 - I/O port B reset
pub fn iopcrst(&mut self) -> IOPCRST_W<'_>
[src]
Bit 19 - I/O port C reset
pub fn iopdrst(&mut self) -> IOPDRST_W<'_>
[src]
Bit 20 - I/O port D reset
pub fn iopfrst(&mut self) -> IOPFRST_W<'_>
[src]
Bit 22 - I/O port F reset
pub fn tscrst(&mut self) -> TSCRST_W<'_>
[src]
Bit 24 - Touch sensing controller reset
pub fn ioperst(&mut self) -> IOPERST_W<'_>
[src]
Bit 21 - I/O port E reset
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _CFGR3>>
[src]
pub fn usart1sw(&mut self) -> USART1SW_W<'_>
[src]
Bits 0:1 - USART1 clock source selection
pub fn i2c1sw(&mut self) -> I2C1SW_W<'_>
[src]
Bit 4 - I2C1 clock source selection
pub fn cecsw(&mut self) -> CECSW_W<'_>
[src]
Bit 6 - HDMI CEC clock source selection
pub fn usbsw(&mut self) -> USBSW_W<'_>
[src]
Bit 7 - USB clock source selection
pub fn adcsw(&mut self) -> ADCSW_W<'_>
[src]
Bit 8 - ADCSW is deprecated. See ADC field in CFGR2 register.
pub fn usart2sw(&mut self) -> USART2SW_W<'_>
[src]
Bits 16:17 - USART2 clock source selection
pub fn usart3sw(&mut self) -> USART3SW_W<'_>
[src]
Bits 18:19 - USART3 clock source
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn hsi14on(&mut self) -> HSI14ON_W<'_>
[src]
Bit 0 - HSI14 clock enable
pub fn hsi14dis(&mut self) -> HSI14DIS_W<'_>
[src]
Bit 2 - HSI14 clock request from ADC disable
pub fn hsi14trim(&mut self) -> HSI14TRIM_W<'_>
[src]
Bits 3:7 - HSI14 clock trimming
pub fn hsi48on(&mut self) -> HSI48ON_W<'_>
[src]
Bit 16 - HSI48 clock enable
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>
[src]
Bits 0:1 - Memory mapping selection bits
pub fn adc_dma_rmp(&mut self) -> ADC_DMA_RMP_W<'_>
[src]
Bit 8 - ADC DMA remapping bit
pub fn usart1_tx_dma_rmp(&mut self) -> USART1_TX_DMA_RMP_W<'_>
[src]
Bit 9 - USART1_TX DMA remapping bit
pub fn usart1_rx_dma_rmp(&mut self) -> USART1_RX_DMA_RMP_W<'_>
[src]
Bit 10 - USART1_RX DMA request remapping bit
pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<'_>
[src]
Bit 11 - TIM16 DMA request remapping bit
pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<'_>
[src]
Bit 12 - TIM17 DMA request remapping bit
pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>
[src]
Bit 16 - Fast Mode Plus (FM plus) driving capability activation bits.
pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>
[src]
Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>
[src]
Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>
[src]
Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>
[src]
Bit 20 - FM+ driving capability activation for I2C1
pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>
[src]
Bit 21 - FM+ driving capability activation for I2C2
pub fn spi2_dma_rmp(&mut self) -> SPI2_DMA_RMP_W<'_>
[src]
Bit 24 - SPI2 DMA request remapping bit
pub fn usart2_dma_rmp(&mut self) -> USART2_DMA_RMP_W<'_>
[src]
Bit 25 - USART2 DMA request remapping bit
pub fn usart3_dma_rmp(&mut self) -> USART3_DMA_RMP_W<'_>
[src]
Bit 26 - USART3 DMA request remapping bit
pub fn i2c1_dma_rmp(&mut self) -> I2C1_DMA_RMP_W<'_>
[src]
Bit 27 - I2C1 DMA request remapping bit
pub fn tim1_dma_rmp(&mut self) -> TIM1_DMA_RMP_W<'_>
[src]
Bit 28 - TIM1 DMA request remapping bit
pub fn tim2_dma_rmp(&mut self) -> TIM2_DMA_RMP_W<'_>
[src]
Bit 29 - TIM2 DMA request remapping bit
pub fn tim3_dma_rmp(&mut self) -> TIM3_DMA_RMP_W<'_>
[src]
Bit 30 - TIM3 DMA request remapping bit
pub fn ir_mod(&mut self) -> IR_MOD_W<'_>
[src]
Bits 6:7 - IR Modulation Envelope signal selection
pub fn tim16_dma_rmp2(&mut self) -> TIM16_DMA_RMP2_W<'_>
[src]
Bit 13 - TIM16 alternate DMA request remapping bit
pub fn tim17_dma_rmp2(&mut self) -> TIM17_DMA_RMP2_W<'_>
[src]
Bit 14 - TIM17 alternate DMA request remapping bit
pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>
[src]
Bit 4 - PA11 and PA12 remapping bit for small packages (28 and 20 pins)
pub fn i2c_pa9_fmp(&mut self) -> I2C_PA9_FMP_W<'_>
[src]
Bit 22 - Fast Mode Plus (FM+) driving capability activation bits
pub fn i2c_pa10_fmp(&mut self) -> I2C_PA10_FMP_W<'_>
[src]
Bit 23 - Fast Mode Plus (FM+) driving capability activation bits
impl W<u32, Reg<u32, _EXTICR1>>
[src]
pub fn exti3(&mut self) -> EXTI3_W<'_>
[src]
Bits 12:15 - EXTI 3 configuration bits
pub fn exti2(&mut self) -> EXTI2_W<'_>
[src]
Bits 8:11 - EXTI 2 configuration bits
pub fn exti1(&mut self) -> EXTI1_W<'_>
[src]
Bits 4:7 - EXTI 1 configuration bits
pub fn exti0(&mut self) -> EXTI0_W<'_>
[src]
Bits 0:3 - EXTI 0 configuration bits
impl W<u32, Reg<u32, _EXTICR2>>
[src]
pub fn exti7(&mut self) -> EXTI7_W<'_>
[src]
Bits 12:15 - EXTI 7 configuration bits
pub fn exti6(&mut self) -> EXTI6_W<'_>
[src]
Bits 8:11 - EXTI 6 configuration bits
pub fn exti5(&mut self) -> EXTI5_W<'_>
[src]
Bits 4:7 - EXTI 5 configuration bits
pub fn exti4(&mut self) -> EXTI4_W<'_>
[src]
Bits 0:3 - EXTI 4 configuration bits
impl W<u32, Reg<u32, _EXTICR3>>
[src]
pub fn exti11(&mut self) -> EXTI11_W<'_>
[src]
Bits 12:15 - EXTI 11 configuration bits
pub fn exti10(&mut self) -> EXTI10_W<'_>
[src]
Bits 8:11 - EXTI 10 configuration bits
pub fn exti9(&mut self) -> EXTI9_W<'_>
[src]
Bits 4:7 - EXTI 9 configuration bits
pub fn exti8(&mut self) -> EXTI8_W<'_>
[src]
Bits 0:3 - EXTI 8 configuration bits
impl W<u32, Reg<u32, _EXTICR4>>
[src]
pub fn exti15(&mut self) -> EXTI15_W<'_>
[src]
Bits 12:15 - EXTI 15 configuration bits
pub fn exti14(&mut self) -> EXTI14_W<'_>
[src]
Bits 8:11 - EXTI 14 configuration bits
pub fn exti13(&mut self) -> EXTI13_W<'_>
[src]
Bits 4:7 - EXTI 13 configuration bits
pub fn exti12(&mut self) -> EXTI12_W<'_>
[src]
Bits 0:3 - EXTI 12 configuration bits
impl W<u32, Reg<u32, _CFGR2>>
[src]
pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>
[src]
Bit 8 - SRAM parity flag
pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>
[src]
Bit 2 - PVD lock enable bit
pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>
[src]
Bit 1 - SRAM parity lock bit
pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>
[src]
Bit 0 - Cortex-M0 LOCKUP bit enable bit
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn awd(&mut self) -> AWD_W<'_>
[src]
Bit 7 - Analog watchdog flag
pub fn ovr(&mut self) -> OVR_W<'_>
[src]
Bit 4 - ADC overrun
pub fn eoseq(&mut self) -> EOSEQ_W<'_>
[src]
Bit 3 - End of sequence flag
pub fn eoc(&mut self) -> EOC_W<'_>
[src]
Bit 2 - End of conversion flag
pub fn eosmp(&mut self) -> EOSMP_W<'_>
[src]
Bit 1 - End of sampling flag
pub fn adrdy(&mut self) -> ADRDY_W<'_>
[src]
Bit 0 - ADC ready
impl W<u32, Reg<u32, _IER>>
[src]
pub fn awdie(&mut self) -> AWDIE_W<'_>
[src]
Bit 7 - Analog watchdog interrupt enable
pub fn ovrie(&mut self) -> OVRIE_W<'_>
[src]
Bit 4 - Overrun interrupt enable
pub fn eoseqie(&mut self) -> EOSEQIE_W<'_>
[src]
Bit 3 - End of conversion sequence interrupt enable
pub fn eocie(&mut self) -> EOCIE_W<'_>
[src]
Bit 2 - End of conversion interrupt enable
pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>
[src]
Bit 1 - End of sampling flag interrupt enable
pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>
[src]
Bit 0 - ADC ready interrupt enable
impl W<u32, Reg<u32, _CR>>
[src]
pub fn adcal(&mut self) -> ADCAL_W<'_>
[src]
Bit 31 - ADC calibration
pub fn adstp(&mut self) -> ADSTP_W<'_>
[src]
Bit 4 - ADC stop conversion command
pub fn adstart(&mut self) -> ADSTART_W<'_>
[src]
Bit 2 - ADC start conversion command
pub fn addis(&mut self) -> ADDIS_W<'_>
[src]
Bit 1 - ADC disable command
pub fn aden(&mut self) -> ADEN_W<'_>
[src]
Bit 0 - ADC enable command
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn awdch(&mut self) -> AWDCH_W<'_>
[src]
Bits 26:30 - Analog watchdog channel selection
pub fn awden(&mut self) -> AWDEN_W<'_>
[src]
Bit 23 - Analog watchdog enable
pub fn awdsgl(&mut self) -> AWDSGL_W<'_>
[src]
Bit 22 - Enable the watchdog on a single channel or on all channels
pub fn discen(&mut self) -> DISCEN_W<'_>
[src]
Bit 16 - Discontinuous mode
pub fn autoff(&mut self) -> AUTOFF_W<'_>
[src]
Bit 15 - Auto-off mode
pub fn autdly(&mut self) -> AUTDLY_W<'_>
[src]
Bit 14 - Auto-delayed conversion mode
pub fn cont(&mut self) -> CONT_W<'_>
[src]
Bit 13 - Single / continuous conversion mode
pub fn ovrmod(&mut self) -> OVRMOD_W<'_>
[src]
Bit 12 - Overrun management mode
pub fn exten(&mut self) -> EXTEN_W<'_>
[src]
Bits 10:11 - External trigger enable and polarity selection
pub fn extsel(&mut self) -> EXTSEL_W<'_>
[src]
Bits 6:8 - External trigger selection
pub fn align(&mut self) -> ALIGN_W<'_>
[src]
Bit 5 - Data alignment
pub fn res(&mut self) -> RES_W<'_>
[src]
Bits 3:4 - Data resolution
pub fn scandir(&mut self) -> SCANDIR_W<'_>
[src]
Bit 2 - Scan sequence direction
pub fn dmacfg(&mut self) -> DMACFG_W<'_>
[src]
Bit 1 - Direct memery access configuration
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - Direct memory access enable
pub fn wait(&mut self) -> WAIT_W<'_>
[src]
Bit 14 - Wait conversion mode
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _SMPR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 16:27 - Analog watchdog higher threshold
pub fn lt(&mut self) -> LT_W<'_>
[src]
Bits 0:11 - Analog watchdog lower threshold
impl W<u32, Reg<u32, _CHSELR>>
[src]
pub fn chsel18(&mut self) -> CHSEL18_W<'_>
[src]
Bit 18 - Channel-x selection
pub fn chsel17(&mut self) -> CHSEL17_W<'_>
[src]
Bit 17 - Channel-x selection
pub fn chsel16(&mut self) -> CHSEL16_W<'_>
[src]
Bit 16 - Channel-x selection
pub fn chsel15(&mut self) -> CHSEL15_W<'_>
[src]
Bit 15 - Channel-x selection
pub fn chsel14(&mut self) -> CHSEL14_W<'_>
[src]
Bit 14 - Channel-x selection
pub fn chsel13(&mut self) -> CHSEL13_W<'_>
[src]
Bit 13 - Channel-x selection
pub fn chsel12(&mut self) -> CHSEL12_W<'_>
[src]
Bit 12 - Channel-x selection
pub fn chsel11(&mut self) -> CHSEL11_W<'_>
[src]
Bit 11 - Channel-x selection
pub fn chsel10(&mut self) -> CHSEL10_W<'_>
[src]
Bit 10 - Channel-x selection
pub fn chsel9(&mut self) -> CHSEL9_W<'_>
[src]
Bit 9 - Channel-x selection
pub fn chsel8(&mut self) -> CHSEL8_W<'_>
[src]
Bit 8 - Channel-x selection
pub fn chsel7(&mut self) -> CHSEL7_W<'_>
[src]
Bit 7 - Channel-x selection
pub fn chsel6(&mut self) -> CHSEL6_W<'_>
[src]
Bit 6 - Channel-x selection
pub fn chsel5(&mut self) -> CHSEL5_W<'_>
[src]
Bit 5 - Channel-x selection
pub fn chsel4(&mut self) -> CHSEL4_W<'_>
[src]
Bit 4 - Channel-x selection
pub fn chsel3(&mut self) -> CHSEL3_W<'_>
[src]
Bit 3 - Channel-x selection
pub fn chsel2(&mut self) -> CHSEL2_W<'_>
[src]
Bit 2 - Channel-x selection
pub fn chsel1(&mut self) -> CHSEL1_W<'_>
[src]
Bit 1 - Channel-x selection
pub fn chsel0(&mut self) -> CHSEL0_W<'_>
[src]
Bit 0 - Channel-x selection
impl W<u32, Reg<u32, _CCR>>
[src]
pub fn vbaten(&mut self) -> VBATEN_W<'_>
[src]
Bit 24 - VBAT enable
pub fn tsen(&mut self) -> TSEN_W<'_>
[src]
Bit 23 - Temperature sensor enable
pub fn vrefen(&mut self) -> VREFEN_W<'_>
[src]
Bit 22 - Temperature sensor and VREFINT enable
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ue(&mut self) -> UE_W<'_>
[src]
Bit 0 - USART enable
pub fn uesm(&mut self) -> UESM_W<'_>
[src]
Bit 1 - USART enable in Stop mode
pub fn re(&mut self) -> RE_W<'_>
[src]
Bit 2 - Receiver enable
pub fn te(&mut self) -> TE_W<'_>
[src]
Bit 3 - Transmitter enable
pub fn idleie(&mut self) -> IDLEIE_W<'_>
[src]
Bit 4 - IDLE interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 5 - RXNE interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transmission complete interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - interrupt enable
pub fn peie(&mut self) -> PEIE_W<'_>
[src]
Bit 8 - PE interrupt enable
pub fn ps(&mut self) -> PS_W<'_>
[src]
Bit 9 - Parity selection
pub fn pce(&mut self) -> PCE_W<'_>
[src]
Bit 10 - Parity control enable
pub fn wake(&mut self) -> WAKE_W<'_>
[src]
Bit 11 - Receiver wakeup method
pub fn m0(&mut self) -> M0_W<'_>
[src]
Bit 12 - Word length
pub fn mme(&mut self) -> MME_W<'_>
[src]
Bit 13 - Mute mode enable
pub fn cmie(&mut self) -> CMIE_W<'_>
[src]
Bit 14 - Character match interrupt enable
pub fn over8(&mut self) -> OVER8_W<'_>
[src]
Bit 15 - Oversampling mode
pub fn dedt(&mut self) -> DEDT_W<'_>
[src]
Bits 16:20 - Driver Enable deassertion time
pub fn deat(&mut self) -> DEAT_W<'_>
[src]
Bits 21:25 - Driver Enable assertion time
pub fn rtoie(&mut self) -> RTOIE_W<'_>
[src]
Bit 26 - Receiver timeout interrupt enable
pub fn eobie(&mut self) -> EOBIE_W<'_>
[src]
Bit 27 - End of Block interrupt enable
pub fn m1(&mut self) -> M1_W<'_>
[src]
Bit 28 - Word length
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rtoen(&mut self) -> RTOEN_W<'_>
[src]
Bit 23 - Receiver timeout enable
pub fn abrmod(&mut self) -> ABRMOD_W<'_>
[src]
Bits 21:22 - Auto baud rate mode
pub fn abren(&mut self) -> ABREN_W<'_>
[src]
Bit 20 - Auto baud rate enable
pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>
[src]
Bit 19 - Most significant bit first
pub fn datainv(&mut self) -> DATAINV_W<'_>
[src]
Bit 18 - Binary data inversion
pub fn txinv(&mut self) -> TXINV_W<'_>
[src]
Bit 17 - TX pin active level inversion
pub fn rxinv(&mut self) -> RXINV_W<'_>
[src]
Bit 16 - RX pin active level inversion
pub fn swap(&mut self) -> SWAP_W<'_>
[src]
Bit 15 - Swap TX/RX pins
pub fn linen(&mut self) -> LINEN_W<'_>
[src]
Bit 14 - LIN mode enable
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bits 12:13 - STOP bits
pub fn clken(&mut self) -> CLKEN_W<'_>
[src]
Bit 11 - Clock enable
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 10 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 9 - Clock phase
pub fn lbcl(&mut self) -> LBCL_W<'_>
[src]
Bit 8 - Last bit clock pulse
pub fn lbdie(&mut self) -> LBDIE_W<'_>
[src]
Bit 6 - LIN break detection interrupt enable
pub fn lbdl(&mut self) -> LBDL_W<'_>
[src]
Bit 5 - LIN break detection length
pub fn addm7(&mut self) -> ADDM7_W<'_>
[src]
Bit 4 - 7-bit Address Detection/4-bit Address Detection
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 24:31 - Address of the USART node
impl W<u32, Reg<u32, _CR3>>
[src]
pub fn wufie(&mut self) -> WUFIE_W<'_>
[src]
Bit 22 - Wakeup from Stop mode interrupt enable
pub fn wus(&mut self) -> WUS_W<'_>
[src]
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
pub fn scarcnt(&mut self) -> SCARCNT_W<'_>
[src]
Bits 17:19 - Smartcard auto-retry count
pub fn dep(&mut self) -> DEP_W<'_>
[src]
Bit 15 - Driver enable polarity selection
pub fn dem(&mut self) -> DEM_W<'_>
[src]
Bit 14 - Driver enable mode
pub fn ddre(&mut self) -> DDRE_W<'_>
[src]
Bit 13 - DMA Disable on Reception Error
pub fn ovrdis(&mut self) -> OVRDIS_W<'_>
[src]
Bit 12 - Overrun Disable
pub fn onebit(&mut self) -> ONEBIT_W<'_>
[src]
Bit 11 - One sample bit method enable
pub fn ctsie(&mut self) -> CTSIE_W<'_>
[src]
Bit 10 - CTS interrupt enable
pub fn ctse(&mut self) -> CTSE_W<'_>
[src]
Bit 9 - CTS enable
pub fn rtse(&mut self) -> RTSE_W<'_>
[src]
Bit 8 - RTS enable
pub fn dmat(&mut self) -> DMAT_W<'_>
[src]
Bit 7 - DMA enable transmitter
pub fn dmar(&mut self) -> DMAR_W<'_>
[src]
Bit 6 - DMA enable receiver
pub fn scen(&mut self) -> SCEN_W<'_>
[src]
Bit 5 - Smartcard mode enable
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 4 - Smartcard NACK enable
pub fn hdsel(&mut self) -> HDSEL_W<'_>
[src]
Bit 3 - Half-duplex selection
pub fn irlp(&mut self) -> IRLP_W<'_>
[src]
Bit 2 - IrDA low-power
pub fn iren(&mut self) -> IREN_W<'_>
[src]
Bit 1 - IrDA mode enable
pub fn eie(&mut self) -> EIE_W<'_>
[src]
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
[src]
impl W<u32, Reg<u32, _GTPR>>
[src]
pub fn gt(&mut self) -> GT_W<'_>
[src]
Bits 8:15 - Guard time value
pub fn psc(&mut self) -> PSC_W<'_>
[src]
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
[src]
pub fn blen(&mut self) -> BLEN_W<'_>
[src]
Bits 24:31 - Block Length
pub fn rto(&mut self) -> RTO_W<'_>
[src]
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
[src]
pub fn txfrq(&mut self) -> TXFRQ_W<'_>
[src]
Bit 4 - Transmit data flush request
pub fn rxfrq(&mut self) -> RXFRQ_W<'_>
[src]
Bit 3 - Receive data flush request
pub fn mmrq(&mut self) -> MMRQ_W<'_>
[src]
Bit 2 - Mute mode request
pub fn sbkrq(&mut self) -> SBKRQ_W<'_>
[src]
Bit 1 - Send break request
pub fn abrrq(&mut self) -> ABRRQ_W<'_>
[src]
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn wucf(&mut self) -> WUCF_W<'_>
[src]
Bit 20 - Wakeup from Stop mode clear flag
pub fn cmcf(&mut self) -> CMCF_W<'_>
[src]
Bit 17 - Character match clear flag
pub fn eobcf(&mut self) -> EOBCF_W<'_>
[src]
Bit 12 - End of timeout clear flag
pub fn rtocf(&mut self) -> RTOCF_W<'_>
[src]
Bit 11 - Receiver timeout clear flag
pub fn ctscf(&mut self) -> CTSCF_W<'_>
[src]
Bit 9 - CTS clear flag
pub fn lbdcf(&mut self) -> LBDCF_W<'_>
[src]
Bit 8 - LIN break detection clear flag
pub fn tccf(&mut self) -> TCCF_W<'_>
[src]
Bit 6 - Transmission complete clear flag
pub fn idlecf(&mut self) -> IDLECF_W<'_>
[src]
Bit 4 - Idle line detected clear flag
pub fn orecf(&mut self) -> ORECF_W<'_>
[src]
Bit 3 - Overrun error clear flag
pub fn ncf(&mut self) -> NCF_W<'_>
[src]
Bit 2 - Noise detected clear flag
pub fn fecf(&mut self) -> FECF_W<'_>
[src]
Bit 1 - Framing error clear flag
pub fn pecf(&mut self) -> PECF_W<'_>
[src]
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _DR>>
[src]
pub fn yt(&mut self) -> YT_W<'_>
[src]
Bits 20:23 - Year tens in BCD format
pub fn yu(&mut self) -> YU_W<'_>
[src]
Bits 16:19 - Year units in BCD format
pub fn wdu(&mut self) -> WDU_W<'_>
[src]
Bits 13:15 - Week day units
pub fn mt(&mut self) -> MT_W<'_>
[src]
Bit 12 - Month tens in BCD format
pub fn mu(&mut self) -> MU_W<'_>
[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 0:3 - Date units in BCD format
impl W<u32, Reg<u32, _CR>>
[src]
pub fn tsedge(&mut self) -> TSEDGE_W<'_>
[src]
Bit 3 - Time-stamp event active edge
pub fn refckon(&mut self) -> REFCKON_W<'_>
[src]
Bit 4 - RTC_REFIN reference clock detection enable (50 or 60 Hz)
pub fn bypshad(&mut self) -> BYPSHAD_W<'_>
[src]
Bit 5 - Bypass the shadow registers
pub fn fmt(&mut self) -> FMT_W<'_>
[src]
Bit 6 - Hour format
pub fn alrae(&mut self) -> ALRAE_W<'_>
[src]
Bit 8 - Alarm A enable
pub fn tse(&mut self) -> TSE_W<'_>
[src]
Bit 11 - timestamp enable
pub fn alraie(&mut self) -> ALRAIE_W<'_>
[src]
Bit 12 - Alarm A interrupt enable
pub fn tsie(&mut self) -> TSIE_W<'_>
[src]
Bit 15 - Time-stamp interrupt enable
pub fn add1h(&mut self) -> ADD1H_W<'_>
[src]
Bit 16 - Add 1 hour (summer time change)
pub fn sub1h(&mut self) -> SUB1H_W<'_>
[src]
Bit 17 - Subtract 1 hour (winter time change)
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 18 - Backup
pub fn cosel(&mut self) -> COSEL_W<'_>
[src]
Bit 19 - Calibration output selection
pub fn pol(&mut self) -> POL_W<'_>
[src]
Bit 20 - Output polarity
pub fn osel(&mut self) -> OSEL_W<'_>
[src]
Bits 21:22 - Output selection
pub fn coe(&mut self) -> COE_W<'_>
[src]
Bit 23 - Calibration output enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn shpf(&mut self) -> SHPF_W<'_>
[src]
Bit 3 - Shift operation pending
pub fn rsf(&mut self) -> RSF_W<'_>
[src]
Bit 5 - Registers synchronization flag
pub fn init(&mut self) -> INIT_W<'_>
[src]
Bit 7 - Initialization mode
pub fn alraf(&mut self) -> ALRAF_W<'_>
[src]
Bit 8 - Alarm A flag
pub fn tsf(&mut self) -> TSF_W<'_>
[src]
Bit 11 - Time-stamp flag
pub fn tsovf(&mut self) -> TSOVF_W<'_>
[src]
Bit 12 - Time-stamp overflow flag
pub fn tamp1f(&mut self) -> TAMP1F_W<'_>
[src]
Bit 13 - RTC_TAMP1 detection flag
pub fn tamp2f(&mut self) -> TAMP2F_W<'_>
[src]
Bit 14 - RTC_TAMP2 detection flag
impl W<u32, Reg<u32, _PRER>>
[src]
pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>
[src]
Bits 16:22 - Asynchronous prescaler factor
pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>
[src]
Bits 0:14 - Synchronous prescaler factor
impl W<u32, Reg<u32, _ALRMAR>>
[src]
pub fn msk4(&mut self) -> MSK4_W<'_>
[src]
Bit 31 - Alarm A date mask
pub fn wdsel(&mut self) -> WDSEL_W<'_>
[src]
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 28:29 - Date tens in BCD format.
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 24:27 - Date units or day in BCD format.
pub fn msk3(&mut self) -> MSK3_W<'_>
[src]
Bit 23 - Alarm A hours mask
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format.
pub fn msk2(&mut self) -> MSK2_W<'_>
[src]
Bit 15 - Alarm A minutes mask
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format.
pub fn msk1(&mut self) -> MSK1_W<'_>
[src]
Bit 7 - Alarm A seconds mask
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format.
impl W<u32, Reg<u32, _WPR>>
[src]
impl W<u32, Reg<u32, _SHIFTR>>
[src]
pub fn add1s(&mut self) -> ADD1S_W<'_>
[src]
Bit 31 - Add one second
pub fn subfs(&mut self) -> SUBFS_W<'_>
[src]
Bits 0:14 - Subtract a fraction of a second
impl W<u32, Reg<u32, _CALR>>
[src]
pub fn calp(&mut self) -> CALP_W<'_>
[src]
Bit 15 - Increase frequency of RTC by 488.5 ppm
pub fn calw8(&mut self) -> CALW8_W<'_>
[src]
Bit 14 - Use an 8-second calibration cycle period
pub fn calw16(&mut self) -> CALW16_W<'_>
[src]
Bit 13 - Use a 16-second calibration cycle period
pub fn calm(&mut self) -> CALM_W<'_>
[src]
Bits 0:8 - Calibration minus
impl W<u32, Reg<u32, _TAFCR>>
[src]
pub fn pc15mode(&mut self) -> PC15MODE_W<'_>
[src]
Bit 23 - PC15 mode
pub fn pc15value(&mut self) -> PC15VALUE_W<'_>
[src]
Bit 22 - PC15 value
pub fn pc14mode(&mut self) -> PC14MODE_W<'_>
[src]
Bit 21 - PC14 mode
pub fn pc14value(&mut self) -> PC14VALUE_W<'_>
[src]
Bit 20 - PC14 value
pub fn pc13mode(&mut self) -> PC13MODE_W<'_>
[src]
Bit 19 - PC13 mode
pub fn pc13value(&mut self) -> PC13VALUE_W<'_>
[src]
Bit 18 - RTC_ALARM output type/PC13 value
pub fn tamp_pudis(&mut self) -> TAMP_PUDIS_W<'_>
[src]
Bit 15 - RTC_TAMPx pull-up disable
pub fn tamp_prch(&mut self) -> TAMP_PRCH_W<'_>
[src]
Bits 13:14 - RTC_TAMPx precharge duration
pub fn tampflt(&mut self) -> TAMPFLT_W<'_>
[src]
Bits 11:12 - RTC_TAMPx filter count
pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>
[src]
Bits 8:10 - Tamper sampling frequency
pub fn tampts(&mut self) -> TAMPTS_W<'_>
[src]
Bit 7 - Activate timestamp on tamper detection event
pub fn tamp2_trg(&mut self) -> TAMP2_TRG_W<'_>
[src]
Bit 4 - Active level for RTC_TAMP2 input
pub fn tamp2e(&mut self) -> TAMP2E_W<'_>
[src]
Bit 3 - RTC_TAMP2 input detection enable
pub fn tampie(&mut self) -> TAMPIE_W<'_>
[src]
Bit 2 - Tamper interrupt enable
pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>
[src]
Bit 1 - Active level for RTC_TAMP1 input
pub fn tamp1e(&mut self) -> TAMP1E_W<'_>
[src]
Bit 0 - RTC_TAMP1 input detection enable
impl W<u32, Reg<u32, _ALRMASSR>>
[src]
pub fn maskss(&mut self) -> MASKSS_W<'_>
[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
[src]
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _BKPR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _CCR2>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn ctph(&mut self) -> CTPH_W<'_>
[src]
Bits 28:31 - Charge transfer pulse high
pub fn ctpl(&mut self) -> CTPL_W<'_>
[src]
Bits 24:27 - Charge transfer pulse low
pub fn ssd(&mut self) -> SSD_W<'_>
[src]
Bits 17:23 - Spread spectrum deviation
pub fn sse(&mut self) -> SSE_W<'_>
[src]
Bit 16 - Spread spectrum enable
pub fn sspsc(&mut self) -> SSPSC_W<'_>
[src]
Bit 15 - Spread spectrum prescaler
pub fn pgpsc(&mut self) -> PGPSC_W<'_>
[src]
Bits 12:14 - pulse generator prescaler
pub fn mcv(&mut self) -> MCV_W<'_>
[src]
Bits 5:7 - Max count value
pub fn iodef(&mut self) -> IODEF_W<'_>
[src]
Bit 4 - I/O Default mode
pub fn syncpol(&mut self) -> SYNCPOL_W<'_>
[src]
Bit 3 - Synchronization pin polarity
pub fn am(&mut self) -> AM_W<'_>
[src]
Bit 2 - Acquisition mode
pub fn start(&mut self) -> START_W<'_>
[src]
Bit 1 - Start a new acquisition
pub fn tsce(&mut self) -> TSCE_W<'_>
[src]
Bit 0 - Touch sensing controller enable
impl W<u32, Reg<u32, _IER>>
[src]
pub fn mceie(&mut self) -> MCEIE_W<'_>
[src]
Bit 1 - Max count error interrupt enable
pub fn eoaie(&mut self) -> EOAIE_W<'_>
[src]
Bit 0 - End of acquisition interrupt enable
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn mceic(&mut self) -> MCEIC_W<'_>
[src]
Bit 1 - Max count error interrupt clear
pub fn eoaic(&mut self) -> EOAIC_W<'_>
[src]
Bit 0 - End of acquisition interrupt clear
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn mcef(&mut self) -> MCEF_W<'_>
[src]
Bit 1 - Max count error flag
pub fn eoaf(&mut self) -> EOAF_W<'_>
[src]
Bit 0 - End of acquisition flag
impl W<u32, Reg<u32, _IOHCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
impl W<u32, Reg<u32, _IOASCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 analog switch enable
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 analog switch enable
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 analog switch enable
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 analog switch enable
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 analog switch enable
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 analog switch enable
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 analog switch enable
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 analog switch enable
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 analog switch enable
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 analog switch enable
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 analog switch enable
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 analog switch enable
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 analog switch enable
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 analog switch enable
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 analog switch enable
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 analog switch enable
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 analog switch enable
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 analog switch enable
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 analog switch enable
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 analog switch enable
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 analog switch enable
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 analog switch enable
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 analog switch enable
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 analog switch enable
impl W<u32, Reg<u32, _IOSCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 sampling mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 sampling mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 sampling mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 sampling mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 sampling mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 sampling mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 sampling mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 sampling mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 sampling mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 sampling mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 sampling mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 sampling mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 sampling mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 sampling mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 sampling mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 sampling mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 sampling mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 sampling mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 sampling mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 sampling mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 sampling mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 sampling mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 sampling mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 sampling mode
impl W<u32, Reg<u32, _IOCCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 channel mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 channel mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 channel mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 channel mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 channel mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 channel mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 channel mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 channel mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 channel mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 channel mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 channel mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 channel mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 channel mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 channel mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 channel mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 channel mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 channel mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 channel mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 channel mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 channel mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 channel mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 channel mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 channel mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 channel mode
impl W<u32, Reg<u32, _IOGCSR>>
[src]
pub fn g8s(&mut self) -> G8S_W<'_>
[src]
Bit 23 - Analog I/O group x status
pub fn g7s(&mut self) -> G7S_W<'_>
[src]
Bit 22 - Analog I/O group x status
pub fn g8e(&mut self) -> G8E_W<'_>
[src]
Bit 7 - Analog I/O group x enable
pub fn g7e(&mut self) -> G7E_W<'_>
[src]
Bit 6 - Analog I/O group x enable
pub fn g6e(&mut self) -> G6E_W<'_>
[src]
Bit 5 - Analog I/O group x enable
pub fn g5e(&mut self) -> G5E_W<'_>
[src]
Bit 4 - Analog I/O group x enable
pub fn g4e(&mut self) -> G4E_W<'_>
[src]
Bit 3 - Analog I/O group x enable
pub fn g3e(&mut self) -> G3E_W<'_>
[src]
Bit 2 - Analog I/O group x enable
pub fn g2e(&mut self) -> G2E_W<'_>
[src]
Bit 1 - Analog I/O group x enable
pub fn g1e(&mut self) -> G1E_W<'_>
[src]
Bit 0 - Analog I/O group x enable
impl W<u32, Reg<u32, _CR>>
[src]
pub fn txeom(&mut self) -> TXEOM_W<'_>
[src]
Bit 2 - Tx End Of Message
pub fn txsom(&mut self) -> TXSOM_W<'_>
[src]
Bit 1 - Tx start of message
pub fn cecen(&mut self) -> CECEN_W<'_>
[src]
Bit 0 - CEC Enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn lbpegen(&mut self) -> LBPEGEN_W<'_>
[src]
Bit 11 - Generate Error-Bit on Long Bit Period Error
pub fn bregen(&mut self) -> BREGEN_W<'_>
[src]
Bit 10 - Generate error-bit on bit rising error
pub fn brestp(&mut self) -> BRESTP_W<'_>
[src]
Bit 9 - Rx-stop on bit rising error
pub fn rxtol(&mut self) -> RXTOL_W<'_>
[src]
Bit 8 - Rx-Tolerance
pub fn sft(&mut self) -> SFT_W<'_>
[src]
Bits 5:7 - Signal Free Time
pub fn lstn(&mut self) -> LSTN_W<'_>
[src]
Bit 4 - Listen mode
pub fn oar(&mut self) -> OAR_W<'_>
[src]
Bits 0:3 - Own Address
impl W<u32, Reg<u32, _TXDR>>
[src]
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn txacke(&mut self) -> TXACKE_W<'_>
[src]
Bit 12 - Tx-Missing acknowledge error
pub fn txerr(&mut self) -> TXERR_W<'_>
[src]
Bit 11 - Tx-Error
pub fn txudr(&mut self) -> TXUDR_W<'_>
[src]
Bit 10 - Tx-Buffer Underrun
pub fn txend(&mut self) -> TXEND_W<'_>
[src]
Bit 9 - End of Transmission
pub fn txbr(&mut self) -> TXBR_W<'_>
[src]
Bit 8 - Tx-Byte Request
pub fn arblst(&mut self) -> ARBLST_W<'_>
[src]
Bit 7 - Arbitration Lost
pub fn rxacke(&mut self) -> RXACKE_W<'_>
[src]
Bit 6 - Rx-Missing Acknowledge
pub fn lbpe(&mut self) -> LBPE_W<'_>
[src]
Bit 5 - Rx-Long Bit Period Error
pub fn sbpe(&mut self) -> SBPE_W<'_>
[src]
Bit 4 - Rx-Short Bit period error
pub fn bre(&mut self) -> BRE_W<'_>
[src]
Bit 3 - Rx-Bit rising error
pub fn rxovr(&mut self) -> RXOVR_W<'_>
[src]
Bit 2 - Rx-Overrun
pub fn rxend(&mut self) -> RXEND_W<'_>
[src]
Bit 1 - End Of Reception
pub fn rxbr(&mut self) -> RXBR_W<'_>
[src]
Bit 0 - Rx-Byte Received
impl W<u32, Reg<u32, _IER>>
[src]
pub fn txackie(&mut self) -> TXACKIE_W<'_>
[src]
Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable
pub fn txerrie(&mut self) -> TXERRIE_W<'_>
[src]
Bit 11 - Tx-Error Interrupt Enable
pub fn txudrie(&mut self) -> TXUDRIE_W<'_>
[src]
Bit 10 - Tx-Underrun interrupt enable
pub fn txendie(&mut self) -> TXENDIE_W<'_>
[src]
Bit 9 - Tx-End of message interrupt enable
pub fn txbrie(&mut self) -> TXBRIE_W<'_>
[src]
Bit 8 - Tx-Byte Request Interrupt Enable
pub fn arblstie(&mut self) -> ARBLSTIE_W<'_>
[src]
Bit 7 - Arbitration Lost Interrupt Enable
pub fn rxackie(&mut self) -> RXACKIE_W<'_>
[src]
Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable
pub fn lbpeie(&mut self) -> LBPEIE_W<'_>
[src]
Bit 5 - Long Bit Period Error Interrupt Enable
pub fn sbpeie(&mut self) -> SBPEIE_W<'_>
[src]
Bit 4 - Short Bit Period Error Interrupt Enable
pub fn breie(&mut self) -> BREIE_W<'_>
[src]
Bit 3 - Bit Rising Error Interrupt Enable
pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>
[src]
Bit 2 - Rx-Buffer Overrun Interrupt Enable
pub fn rxendie(&mut self) -> RXENDIE_W<'_>
[src]
Bit 1 - End Of Reception Interrupt Enable
pub fn rxbrie(&mut self) -> RXBRIE_W<'_>
[src]
Bit 0 - Rx-Byte Received Interrupt Enable
impl W<u32, Reg<u32, _ACR>>
[src]
pub fn latency(&mut self) -> LATENCY_W<'_>
[src]
Bits 0:2 - LATENCY
pub fn prftbe(&mut self) -> PRFTBE_W<'_>
[src]
Bit 4 - PRFTBE
impl W<u32, Reg<u32, _KEYR>>
[src]
impl W<u32, Reg<u32, _OPTKEYR>>
[src]
impl W<u32, Reg<u32, _SR>>
[src]
pub fn eop(&mut self) -> EOP_W<'_>
[src]
Bit 5 - End of operation
pub fn wrprt(&mut self) -> WRPRT_W<'_>
[src]
Bit 4 - Write protection error
pub fn pgerr(&mut self) -> PGERR_W<'_>
[src]
Bit 2 - Programming error
impl W<u32, Reg<u32, _CR>>
[src]
pub fn force_optload(&mut self) -> FORCE_OPTLOAD_W<'_>
[src]
Bit 13 - Force option byte loading
pub fn eopie(&mut self) -> EOPIE_W<'_>
[src]
Bit 12 - End of operation interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 10 - Error interrupt enable
pub fn optwre(&mut self) -> OPTWRE_W<'_>
[src]
Bit 9 - Option bytes write enable
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bit 7 - Lock
pub fn strt(&mut self) -> STRT_W<'_>
[src]
Bit 6 - Start
pub fn opter(&mut self) -> OPTER_W<'_>
[src]
Bit 5 - Option byte erase
pub fn optpg(&mut self) -> OPTPG_W<'_>
[src]
Bit 4 - Option byte programming
pub fn mer(&mut self) -> MER_W<'_>
[src]
Bit 2 - Mass erase
pub fn per(&mut self) -> PER_W<'_>
[src]
Bit 1 - Page erase
pub fn pg(&mut self) -> PG_W<'_>
[src]
Bit 0 - Programming
impl W<u32, Reg<u32, _AR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>
[src]
Bit 1 - Debug Stop Mode
pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>
[src]
Bit 2 - Debug Standby Mode
impl W<u32, Reg<u32, _APB1_FZ>>
[src]
pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>
[src]
Bit 0 - TIM2 counter stopped when core is halted
pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>
[src]
Bit 1 - TIM3 counter stopped when core is halted
pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>
[src]
Bit 4 - TIM6 counter stopped when core is halted
pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>
[src]
Bit 5 - TIM7 counter stopped when core is halted
pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>
[src]
Bit 8 - TIM14 counter stopped when core is halted
pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>
[src]
Bit 10 - Debug RTC stopped when core is halted
pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>
[src]
Bit 11 - Debug window watchdog stopped when core is halted
pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>
[src]
Bit 12 - Debug independent watchdog stopped when core is halted
pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>
[src]
Bit 21 - SMBUS timeout mode stopped when core is halted
pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>
[src]
Bit 25 - CAN stopped when core is halted
impl W<u32, Reg<u32, _APB2_FZ>>
[src]
pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>
[src]
Bit 11 - TIM1 counter stopped when core is halted
pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>
[src]
Bit 16 - TIM15 counter stopped when core is halted
pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>
[src]
Bit 17 - TIM16 counter stopped when core is halted
pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>
[src]
Bit 18 - TIM17 counter stopped when core is halted
impl W<u32, Reg<u32, _EPR>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _CNTR>>
[src]
pub fn fres(&mut self) -> FRES_W<'_>
[src]
Bit 0 - Force USB Reset
pub fn pdwn(&mut self) -> PDWN_W<'_>
[src]
Bit 1 - Power down
pub fn lpmode(&mut self) -> LPMODE_W<'_>
[src]
Bit 2 - Low-power mode
pub fn fsusp(&mut self) -> FSUSP_W<'_>
[src]
Bit 3 - Force suspend
pub fn resume(&mut self) -> RESUME_W<'_>
[src]
Bit 4 - Resume request
pub fn l1resume(&mut self) -> L1RESUME_W<'_>
[src]
Bit 5 - LPM L1 Resume request
pub fn l1reqm(&mut self) -> L1REQM_W<'_>
[src]
Bit 7 - LPM L1 state request interrupt mask
pub fn esofm(&mut self) -> ESOFM_W<'_>
[src]
Bit 8 - Expected start of frame interrupt mask
pub fn sofm(&mut self) -> SOFM_W<'_>
[src]
Bit 9 - Start of frame interrupt mask
pub fn resetm(&mut self) -> RESETM_W<'_>
[src]
Bit 10 - USB reset interrupt mask
pub fn suspm(&mut self) -> SUSPM_W<'_>
[src]
Bit 11 - Suspend mode interrupt mask
pub fn wkupm(&mut self) -> WKUPM_W<'_>
[src]
Bit 12 - Wakeup interrupt mask
pub fn errm(&mut self) -> ERRM_W<'_>
[src]
Bit 13 - Error interrupt mask
pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>
[src]
Bit 14 - Packet memory area over / underrun interrupt mask
pub fn ctrm(&mut self) -> CTRM_W<'_>
[src]
Bit 15 - Correct transfer interrupt mask
impl W<u32, Reg<u32, _ISTR>>
[src]
pub fn l1req(&mut self) -> L1REQ_W<'_>
[src]
Bit 7 - LPM L1 state request
pub fn esof(&mut self) -> ESOF_W<'_>
[src]
Bit 8 - Expected start frame
pub fn sof(&mut self) -> SOF_W<'_>
[src]
Bit 9 - start of frame
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 10 - reset request
pub fn susp(&mut self) -> SUSP_W<'_>
[src]
Bit 11 - Suspend mode request
pub fn wkup(&mut self) -> WKUP_W<'_>
[src]
Bit 12 - Wakeup
pub fn err(&mut self) -> ERR_W<'_>
[src]
Bit 13 - Error
pub fn pmaovr(&mut self) -> PMAOVR_W<'_>
[src]
Bit 14 - Packet memory area over / underrun
impl W<u32, Reg<u32, _DADDR>>
[src]
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 0:6 - Device address
pub fn ef(&mut self) -> EF_W<'_>
[src]
Bit 7 - Enable function
impl W<u32, Reg<u32, _BTABLE>>
[src]
impl W<u32, Reg<u32, _LPMCSR>>
[src]
pub fn lpmen(&mut self) -> LPMEN_W<'_>
[src]
Bit 0 - LPM support enable
pub fn lpmack(&mut self) -> LPMACK_W<'_>
[src]
Bit 1 - LPM Token acknowledge enable
impl W<u32, Reg<u32, _BCDR>>
[src]
pub fn bcden(&mut self) -> BCDEN_W<'_>
[src]
Bit 0 - Battery charging detector (BCD) enable
pub fn dcden(&mut self) -> DCDEN_W<'_>
[src]
Bit 1 - Data contact detection (DCD) mode enable
pub fn pden(&mut self) -> PDEN_W<'_>
[src]
Bit 2 - Primary detection (PD) mode enable
pub fn sden(&mut self) -> SDEN_W<'_>
[src]
Bit 3 - Secondary detection (SD) mode enable
pub fn dppu(&mut self) -> DPPU_W<'_>
[src]
Bit 15 - DP pull-up control
impl W<u32, Reg<u32, _CR>>
[src]
pub fn trim(&mut self) -> TRIM_W<'_>
[src]
Bits 8:13 - HSI48 oscillator smooth trimming
pub fn swsync(&mut self) -> SWSYNC_W<'_>
[src]
Bit 7 - Generate software SYNC event
pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<'_>
[src]
Bit 6 - Automatic trimming enable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 5 - Frequency error counter enable
pub fn esyncie(&mut self) -> ESYNCIE_W<'_>
[src]
Bit 3 - Expected SYNC interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 2 - Synchronization or trimming error interrupt enable
pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<'_>
[src]
Bit 1 - SYNC warning interrupt enable
pub fn syncokie(&mut self) -> SYNCOKIE_W<'_>
[src]
Bit 0 - SYNC event OK interrupt enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn syncpol(&mut self) -> SYNCPOL_W<'_>
[src]
Bit 31 - SYNC polarity selection
pub fn syncsrc(&mut self) -> SYNCSRC_W<'_>
[src]
Bits 28:29 - SYNC signal source selection
pub fn syncdiv(&mut self) -> SYNCDIV_W<'_>
[src]
Bits 24:26 - SYNC divider
pub fn felim(&mut self) -> FELIM_W<'_>
[src]
Bits 16:23 - Frequency error limit
pub fn reload(&mut self) -> RELOAD_W<'_>
[src]
Bits 0:15 - Counter reload value
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn esyncc(&mut self) -> ESYNCC_W<'_>
[src]
Bit 3 - Expected SYNC clear flag
pub fn errc(&mut self) -> ERRC_W<'_>
[src]
Bit 2 - Error clear flag
pub fn syncwarnc(&mut self) -> SYNCWARNC_W<'_>
[src]
Bit 1 - SYNC warning clear flag
pub fn syncokc(&mut self) -> SYNCOKC_W<'_>
[src]
Bit 0 - SYNC event OK clear flag
impl W<u32, Reg<u32, _TIR>>
[src]
pub fn stid(&mut self) -> STID_W<'_>
[src]
Bits 21:31 - STID
pub fn exid(&mut self) -> EXID_W<'_>
[src]
Bits 3:20 - EXID
pub fn ide(&mut self) -> IDE_W<'_>
[src]
Bit 2 - IDE
pub fn rtr(&mut self) -> RTR_W<'_>
[src]
Bit 1 - RTR
pub fn txrq(&mut self) -> TXRQ_W<'_>
[src]
Bit 0 - TXRQ
impl W<u32, Reg<u32, _TDTR>>
[src]
pub fn time(&mut self) -> TIME_W<'_>
[src]
Bits 16:31 - TIME
pub fn tgt(&mut self) -> TGT_W<'_>
[src]
Bit 8 - TGT
pub fn dlc(&mut self) -> DLC_W<'_>
[src]
Bits 0:3 - DLC
impl W<u32, Reg<u32, _TDLR>>
[src]
pub fn data3(&mut self) -> DATA3_W<'_>
[src]
Bits 24:31 - DATA3
pub fn data2(&mut self) -> DATA2_W<'_>
[src]
Bits 16:23 - DATA2
pub fn data1(&mut self) -> DATA1_W<'_>
[src]
Bits 8:15 - DATA1
pub fn data0(&mut self) -> DATA0_W<'_>
[src]
Bits 0:7 - DATA0
impl W<u32, Reg<u32, _TDHR>>
[src]
pub fn data7(&mut self) -> DATA7_W<'_>
[src]
Bits 24:31 - DATA7
pub fn data6(&mut self) -> DATA6_W<'_>
[src]
Bits 16:23 - DATA6
pub fn data5(&mut self) -> DATA5_W<'_>
[src]
Bits 8:15 - DATA5
pub fn data4(&mut self) -> DATA4_W<'_>
[src]
Bits 0:7 - DATA4
impl W<u32, Reg<u32, _FR1>>
[src]
pub fn fb0(&mut self) -> FB0_W<'_>
[src]
Bit 0 - Filter bits
pub fn fb1(&mut self) -> FB1_W<'_>
[src]
Bit 1 - Filter bits
pub fn fb2(&mut self) -> FB2_W<'_>
[src]
Bit 2 - Filter bits
pub fn fb3(&mut self) -> FB3_W<'_>
[src]
Bit 3 - Filter bits
pub fn fb4(&mut self) -> FB4_W<'_>
[src]
Bit 4 - Filter bits
pub fn fb5(&mut self) -> FB5_W<'_>
[src]
Bit 5 - Filter bits
pub fn fb6(&mut self) -> FB6_W<'_>
[src]
Bit 6 - Filter bits
pub fn fb7(&mut self) -> FB7_W<'_>
[src]
Bit 7 - Filter bits
pub fn fb8(&mut self) -> FB8_W<'_>
[src]
Bit 8 - Filter bits
pub fn fb9(&mut self) -> FB9_W<'_>
[src]
Bit 9 - Filter bits
pub fn fb10(&mut self) -> FB10_W<'_>
[src]
Bit 10 - Filter bits
pub fn fb11(&mut self) -> FB11_W<'_>
[src]
Bit 11 - Filter bits
pub fn fb12(&mut self) -> FB12_W<'_>
[src]
Bit 12 - Filter bits
pub fn fb13(&mut self) -> FB13_W<'_>
[src]
Bit 13 - Filter bits
pub fn fb14(&mut self) -> FB14_W<'_>
[src]
Bit 14 - Filter bits
pub fn fb15(&mut self) -> FB15_W<'_>
[src]
Bit 15 - Filter bits
pub fn fb16(&mut self) -> FB16_W<'_>
[src]
Bit 16 - Filter bits
pub fn fb17(&mut self) -> FB17_W<'_>
[src]
Bit 17 - Filter bits
pub fn fb18(&mut self) -> FB18_W<'_>
[src]
Bit 18 - Filter bits
pub fn fb19(&mut self) -> FB19_W<'_>
[src]
Bit 19 - Filter bits
pub fn fb20(&mut self) -> FB20_W<'_>
[src]
Bit 20 - Filter bits
pub fn fb21(&mut self) -> FB21_W<'_>
[src]
Bit 21 - Filter bits
pub fn fb22(&mut self) -> FB22_W<'_>
[src]
Bit 22 - Filter bits
pub fn fb23(&mut self) -> FB23_W<'_>
[src]
Bit 23 - Filter bits
pub fn fb24(&mut self) -> FB24_W<'_>
[src]
Bit 24 - Filter bits
pub fn fb25(&mut self) -> FB25_W<'_>
[src]
Bit 25 - Filter bits
pub fn fb26(&mut self) -> FB26_W<'_>
[src]
Bit 26 - Filter bits
pub fn fb27(&mut self) -> FB27_W<'_>
[src]
Bit 27 - Filter bits
pub fn fb28(&mut self) -> FB28_W<'_>
[src]
Bit 28 - Filter bits
pub fn fb29(&mut self) -> FB29_W<'_>
[src]
Bit 29 - Filter bits
pub fn fb30(&mut self) -> FB30_W<'_>
[src]
Bit 30 - Filter bits
pub fn fb31(&mut self) -> FB31_W<'_>
[src]
Bit 31 - Filter bits
impl W<u32, Reg<u32, _FR2>>
[src]
pub fn fb0(&mut self) -> FB0_W<'_>
[src]
Bit 0 - Filter bits
pub fn fb1(&mut self) -> FB1_W<'_>
[src]
Bit 1 - Filter bits
pub fn fb2(&mut self) -> FB2_W<'_>
[src]
Bit 2 - Filter bits
pub fn fb3(&mut self) -> FB3_W<'_>
[src]
Bit 3 - Filter bits
pub fn fb4(&mut self) -> FB4_W<'_>
[src]
Bit 4 - Filter bits
pub fn fb5(&mut self) -> FB5_W<'_>
[src]
Bit 5 - Filter bits
pub fn fb6(&mut self) -> FB6_W<'_>
[src]
Bit 6 - Filter bits
pub fn fb7(&mut self) -> FB7_W<'_>
[src]
Bit 7 - Filter bits
pub fn fb8(&mut self) -> FB8_W<'_>
[src]
Bit 8 - Filter bits
pub fn fb9(&mut self) -> FB9_W<'_>
[src]
Bit 9 - Filter bits
pub fn fb10(&mut self) -> FB10_W<'_>
[src]
Bit 10 - Filter bits
pub fn fb11(&mut self) -> FB11_W<'_>
[src]
Bit 11 - Filter bits
pub fn fb12(&mut self) -> FB12_W<'_>
[src]
Bit 12 - Filter bits
pub fn fb13(&mut self) -> FB13_W<'_>
[src]
Bit 13 - Filter bits
pub fn fb14(&mut self) -> FB14_W<'_>
[src]
Bit 14 - Filter bits
pub fn fb15(&mut self) -> FB15_W<'_>
[src]
Bit 15 - Filter bits
pub fn fb16(&mut self) -> FB16_W<'_>
[src]
Bit 16 - Filter bits
pub fn fb17(&mut self) -> FB17_W<'_>
[src]
Bit 17 - Filter bits
pub fn fb18(&mut self) -> FB18_W<'_>
[src]
Bit 18 - Filter bits
pub fn fb19(&mut self) -> FB19_W<'_>
[src]
Bit 19 - Filter bits
pub fn fb20(&mut self) -> FB20_W<'_>
[src]
Bit 20 - Filter bits
pub fn fb21(&mut self) -> FB21_W<'_>
[src]
Bit 21 - Filter bits
pub fn fb22(&mut self) -> FB22_W<'_>
[src]
Bit 22 - Filter bits
pub fn fb23(&mut self) -> FB23_W<'_>
[src]
Bit 23 - Filter bits
pub fn fb24(&mut self) -> FB24_W<'_>
[src]
Bit 24 - Filter bits
pub fn fb25(&mut self) -> FB25_W<'_>
[src]
Bit 25 - Filter bits
pub fn fb26(&mut self) -> FB26_W<'_>
[src]
Bit 26 - Filter bits
pub fn fb27(&mut self) -> FB27_W<'_>
[src]
Bit 27 - Filter bits
pub fn fb28(&mut self) -> FB28_W<'_>
[src]
Bit 28 - Filter bits
pub fn fb29(&mut self) -> FB29_W<'_>
[src]
Bit 29 - Filter bits
pub fn fb30(&mut self) -> FB30_W<'_>
[src]
Bit 30 - Filter bits
pub fn fb31(&mut self) -> FB31_W<'_>
[src]
Bit 31 - Filter bits
impl W<u32, Reg<u32, _MCR>>
[src]
pub fn dbf(&mut self) -> DBF_W<'_>
[src]
Bit 16 - DBF
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 15 - RESET
pub fn ttcm(&mut self) -> TTCM_W<'_>
[src]
Bit 7 - TTCM
pub fn abom(&mut self) -> ABOM_W<'_>
[src]
Bit 6 - ABOM
pub fn awum(&mut self) -> AWUM_W<'_>
[src]
Bit 5 - AWUM
pub fn nart(&mut self) -> NART_W<'_>
[src]
Bit 4 - NART
pub fn rflm(&mut self) -> RFLM_W<'_>
[src]
Bit 3 - RFLM
pub fn txfp(&mut self) -> TXFP_W<'_>
[src]
Bit 2 - TXFP
pub fn sleep(&mut self) -> SLEEP_W<'_>
[src]
Bit 1 - SLEEP
pub fn inrq(&mut self) -> INRQ_W<'_>
[src]
Bit 0 - INRQ
impl W<u32, Reg<u32, _MSR>>
[src]
pub fn slaki(&mut self) -> SLAKI_W<'_>
[src]
Bit 4 - SLAKI
pub fn wkui(&mut self) -> WKUI_W<'_>
[src]
Bit 3 - WKUI
pub fn erri(&mut self) -> ERRI_W<'_>
[src]
Bit 2 - ERRI
impl W<u32, Reg<u32, _TSR>>
[src]
pub fn abrq2(&mut self) -> ABRQ2_W<'_>
[src]
Bit 23 - ABRQ2
pub fn terr2(&mut self) -> TERR2_W<'_>
[src]
Bit 19 - TERR2
pub fn alst2(&mut self) -> ALST2_W<'_>
[src]
Bit 18 - ALST2
pub fn txok2(&mut self) -> TXOK2_W<'_>
[src]
Bit 17 - TXOK2
pub fn rqcp2(&mut self) -> RQCP2_W<'_>
[src]
Bit 16 - RQCP2
pub fn abrq1(&mut self) -> ABRQ1_W<'_>
[src]
Bit 15 - ABRQ1
pub fn terr1(&mut self) -> TERR1_W<'_>
[src]
Bit 11 - TERR1
pub fn alst1(&mut self) -> ALST1_W<'_>
[src]
Bit 10 - ALST1
pub fn txok1(&mut self) -> TXOK1_W<'_>
[src]
Bit 9 - TXOK1
pub fn rqcp1(&mut self) -> RQCP1_W<'_>
[src]
Bit 8 - RQCP1
pub fn abrq0(&mut self) -> ABRQ0_W<'_>
[src]
Bit 7 - ABRQ0
pub fn terr0(&mut self) -> TERR0_W<'_>
[src]
Bit 3 - TERR0
pub fn alst0(&mut self) -> ALST0_W<'_>
[src]
Bit 2 - ALST0
pub fn txok0(&mut self) -> TXOK0_W<'_>
[src]
Bit 1 - TXOK0
pub fn rqcp0(&mut self) -> RQCP0_W<'_>
[src]
Bit 0 - RQCP0
impl W<u32, Reg<u32, _RFR>>
[src]
pub fn rfom(&mut self) -> RFOM_W<'_>
[src]
Bit 5 - RFOM0
pub fn fovr(&mut self) -> FOVR_W<'_>
[src]
Bit 4 - FOVR0
pub fn full(&mut self) -> FULL_W<'_>
[src]
Bit 3 - FULL0
impl W<u32, Reg<u32, _IER>>
[src]
pub fn slkie(&mut self) -> SLKIE_W<'_>
[src]
Bit 17 - SLKIE
pub fn wkuie(&mut self) -> WKUIE_W<'_>
[src]
Bit 16 - WKUIE
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 15 - ERRIE
pub fn lecie(&mut self) -> LECIE_W<'_>
[src]
Bit 11 - LECIE
pub fn bofie(&mut self) -> BOFIE_W<'_>
[src]
Bit 10 - BOFIE
pub fn epvie(&mut self) -> EPVIE_W<'_>
[src]
Bit 9 - EPVIE
pub fn ewgie(&mut self) -> EWGIE_W<'_>
[src]
Bit 8 - EWGIE
pub fn fovie1(&mut self) -> FOVIE1_W<'_>
[src]
Bit 6 - FOVIE1
pub fn ffie1(&mut self) -> FFIE1_W<'_>
[src]
Bit 5 - FFIE1
pub fn fmpie1(&mut self) -> FMPIE1_W<'_>
[src]
Bit 4 - FMPIE1
pub fn fovie0(&mut self) -> FOVIE0_W<'_>
[src]
Bit 3 - FOVIE0
pub fn ffie0(&mut self) -> FFIE0_W<'_>
[src]
Bit 2 - FFIE0
pub fn fmpie0(&mut self) -> FMPIE0_W<'_>
[src]
Bit 1 - FMPIE0
pub fn tmeie(&mut self) -> TMEIE_W<'_>
[src]
Bit 0 - TMEIE
impl W<u32, Reg<u32, _ESR>>
[src]
impl W<u32, Reg<u32, _BTR>>
[src]
pub fn silm(&mut self) -> SILM_W<'_>
[src]
Bit 31 - SILM
pub fn lbkm(&mut self) -> LBKM_W<'_>
[src]
Bit 30 - LBKM
pub fn sjw(&mut self) -> SJW_W<'_>
[src]
Bits 24:25 - SJW
pub fn ts2(&mut self) -> TS2_W<'_>
[src]
Bits 20:22 - TS2
pub fn ts1(&mut self) -> TS1_W<'_>
[src]
Bits 16:19 - TS1
pub fn brp(&mut self) -> BRP_W<'_>
[src]
Bits 0:9 - BRP
impl W<u32, Reg<u32, _FMR>>
[src]
pub fn can2sb(&mut self) -> CAN2SB_W<'_>
[src]
Bits 8:13 - CAN2SB
pub fn finit(&mut self) -> FINIT_W<'_>
[src]
Bit 0 - FINIT
impl W<u32, Reg<u32, _FM1R>>
[src]
pub fn fbm0(&mut self) -> FBM0_W<'_>
[src]
Bit 0 - Filter mode
pub fn fbm1(&mut self) -> FBM1_W<'_>
[src]
Bit 1 - Filter mode
pub fn fbm2(&mut self) -> FBM2_W<'_>
[src]
Bit 2 - Filter mode
pub fn fbm3(&mut self) -> FBM3_W<'_>
[src]
Bit 3 - Filter mode
pub fn fbm4(&mut self) -> FBM4_W<'_>
[src]
Bit 4 - Filter mode
pub fn fbm5(&mut self) -> FBM5_W<'_>
[src]
Bit 5 - Filter mode
pub fn fbm6(&mut self) -> FBM6_W<'_>
[src]
Bit 6 - Filter mode
pub fn fbm7(&mut self) -> FBM7_W<'_>
[src]
Bit 7 - Filter mode
pub fn fbm8(&mut self) -> FBM8_W<'_>
[src]
Bit 8 - Filter mode
pub fn fbm9(&mut self) -> FBM9_W<'_>
[src]
Bit 9 - Filter mode
pub fn fbm10(&mut self) -> FBM10_W<'_>
[src]
Bit 10 - Filter mode
pub fn fbm11(&mut self) -> FBM11_W<'_>
[src]
Bit 11 - Filter mode
pub fn fbm12(&mut self) -> FBM12_W<'_>
[src]
Bit 12 - Filter mode
pub fn fbm13(&mut self) -> FBM13_W<'_>
[src]
Bit 13 - Filter mode
pub fn fbm14(&mut self) -> FBM14_W<'_>
[src]
Bit 14 - Filter mode
pub fn fbm15(&mut self) -> FBM15_W<'_>
[src]
Bit 15 - Filter mode
pub fn fbm16(&mut self) -> FBM16_W<'_>
[src]
Bit 16 - Filter mode
pub fn fbm17(&mut self) -> FBM17_W<'_>
[src]
Bit 17 - Filter mode
pub fn fbm18(&mut self) -> FBM18_W<'_>
[src]
Bit 18 - Filter mode
pub fn fbm19(&mut self) -> FBM19_W<'_>
[src]
Bit 19 - Filter mode
pub fn fbm20(&mut self) -> FBM20_W<'_>
[src]
Bit 20 - Filter mode
pub fn fbm21(&mut self) -> FBM21_W<'_>
[src]
Bit 21 - Filter mode
pub fn fbm22(&mut self) -> FBM22_W<'_>
[src]
Bit 22 - Filter mode
pub fn fbm23(&mut self) -> FBM23_W<'_>
[src]
Bit 23 - Filter mode
pub fn fbm24(&mut self) -> FBM24_W<'_>
[src]
Bit 24 - Filter mode
pub fn fbm25(&mut self) -> FBM25_W<'_>
[src]
Bit 25 - Filter mode
pub fn fbm26(&mut self) -> FBM26_W<'_>
[src]
Bit 26 - Filter mode
pub fn fbm27(&mut self) -> FBM27_W<'_>
[src]
Bit 27 - Filter mode
impl W<u32, Reg<u32, _FS1R>>
[src]
pub fn fsc0(&mut self) -> FSC0_W<'_>
[src]
Bit 0 - Filter scale configuration
pub fn fsc1(&mut self) -> FSC1_W<'_>
[src]
Bit 1 - Filter scale configuration
pub fn fsc2(&mut self) -> FSC2_W<'_>
[src]
Bit 2 - Filter scale configuration
pub fn fsc3(&mut self) -> FSC3_W<'_>
[src]
Bit 3 - Filter scale configuration
pub fn fsc4(&mut self) -> FSC4_W<'_>
[src]
Bit 4 - Filter scale configuration
pub fn fsc5(&mut self) -> FSC5_W<'_>
[src]
Bit 5 - Filter scale configuration
pub fn fsc6(&mut self) -> FSC6_W<'_>
[src]
Bit 6 - Filter scale configuration
pub fn fsc7(&mut self) -> FSC7_W<'_>
[src]
Bit 7 - Filter scale configuration
pub fn fsc8(&mut self) -> FSC8_W<'_>
[src]
Bit 8 - Filter scale configuration
pub fn fsc9(&mut self) -> FSC9_W<'_>
[src]
Bit 9 - Filter scale configuration
pub fn fsc10(&mut self) -> FSC10_W<'_>
[src]
Bit 10 - Filter scale configuration
pub fn fsc11(&mut self) -> FSC11_W<'_>
[src]
Bit 11 - Filter scale configuration
pub fn fsc12(&mut self) -> FSC12_W<'_>
[src]
Bit 12 - Filter scale configuration
pub fn fsc13(&mut self) -> FSC13_W<'_>
[src]
Bit 13 - Filter scale configuration
pub fn fsc14(&mut self) -> FSC14_W<'_>
[src]
Bit 14 - Filter scale configuration
pub fn fsc15(&mut self) -> FSC15_W<'_>
[src]
Bit 15 - Filter scale configuration
pub fn fsc16(&mut self) -> FSC16_W<'_>
[src]
Bit 16 - Filter scale configuration
pub fn fsc17(&mut self) -> FSC17_W<'_>
[src]
Bit 17 - Filter scale configuration
pub fn fsc18(&mut self) -> FSC18_W<'_>
[src]
Bit 18 - Filter scale configuration
pub fn fsc19(&mut self) -> FSC19_W<'_>
[src]
Bit 19 - Filter scale configuration
pub fn fsc20(&mut self) -> FSC20_W<'_>
[src]
Bit 20 - Filter scale configuration
pub fn fsc21(&mut self) -> FSC21_W<'_>
[src]
Bit 21 - Filter scale configuration
pub fn fsc22(&mut self) -> FSC22_W<'_>
[src]
Bit 22 - Filter scale configuration
pub fn fsc23(&mut self) -> FSC23_W<'_>
[src]
Bit 23 - Filter scale configuration
pub fn fsc24(&mut self) -> FSC24_W<'_>
[src]
Bit 24 - Filter scale configuration
pub fn fsc25(&mut self) -> FSC25_W<'_>
[src]
Bit 25 - Filter scale configuration
pub fn fsc26(&mut self) -> FSC26_W<'_>
[src]
Bit 26 - Filter scale configuration
pub fn fsc27(&mut self) -> FSC27_W<'_>
[src]
Bit 27 - Filter scale configuration
impl W<u32, Reg<u32, _FFA1R>>
[src]
pub fn ffa0(&mut self) -> FFA0_W<'_>
[src]
Bit 0 - Filter FIFO assignment for filter 0
pub fn ffa1(&mut self) -> FFA1_W<'_>
[src]
Bit 1 - Filter FIFO assignment for filter 1
pub fn ffa2(&mut self) -> FFA2_W<'_>
[src]
Bit 2 - Filter FIFO assignment for filter 2
pub fn ffa3(&mut self) -> FFA3_W<'_>
[src]
Bit 3 - Filter FIFO assignment for filter 3
pub fn ffa4(&mut self) -> FFA4_W<'_>
[src]
Bit 4 - Filter FIFO assignment for filter 4
pub fn ffa5(&mut self) -> FFA5_W<'_>
[src]
Bit 5 - Filter FIFO assignment for filter 5
pub fn ffa6(&mut self) -> FFA6_W<'_>
[src]
Bit 6 - Filter FIFO assignment for filter 6
pub fn ffa7(&mut self) -> FFA7_W<'_>
[src]
Bit 7 - Filter FIFO assignment for filter 7
pub fn ffa8(&mut self) -> FFA8_W<'_>
[src]
Bit 8 - Filter FIFO assignment for filter 8
pub fn ffa9(&mut self) -> FFA9_W<'_>
[src]
Bit 9 - Filter FIFO assignment for filter 9
pub fn ffa10(&mut self) -> FFA10_W<'_>
[src]
Bit 10 - Filter FIFO assignment for filter 10
pub fn ffa11(&mut self) -> FFA11_W<'_>
[src]
Bit 11 - Filter FIFO assignment for filter 11
pub fn ffa12(&mut self) -> FFA12_W<'_>
[src]
Bit 12 - Filter FIFO assignment for filter 12
pub fn ffa13(&mut self) -> FFA13_W<'_>
[src]
Bit 13 - Filter FIFO assignment for filter 13
pub fn ffa14(&mut self) -> FFA14_W<'_>
[src]
Bit 14 - Filter FIFO assignment for filter 14
pub fn ffa15(&mut self) -> FFA15_W<'_>
[src]
Bit 15 - Filter FIFO assignment for filter 15
pub fn ffa16(&mut self) -> FFA16_W<'_>
[src]
Bit 16 - Filter FIFO assignment for filter 16
pub fn ffa17(&mut self) -> FFA17_W<'_>
[src]
Bit 17 - Filter FIFO assignment for filter 17
pub fn ffa18(&mut self) -> FFA18_W<'_>
[src]
Bit 18 - Filter FIFO assignment for filter 18
pub fn ffa19(&mut self) -> FFA19_W<'_>
[src]
Bit 19 - Filter FIFO assignment for filter 19
pub fn ffa20(&mut self) -> FFA20_W<'_>
[src]
Bit 20 - Filter FIFO assignment for filter 20
pub fn ffa21(&mut self) -> FFA21_W<'_>
[src]
Bit 21 - Filter FIFO assignment for filter 21
pub fn ffa22(&mut self) -> FFA22_W<'_>
[src]
Bit 22 - Filter FIFO assignment for filter 22
pub fn ffa23(&mut self) -> FFA23_W<'_>
[src]
Bit 23 - Filter FIFO assignment for filter 23
pub fn ffa24(&mut self) -> FFA24_W<'_>
[src]
Bit 24 - Filter FIFO assignment for filter 24
pub fn ffa25(&mut self) -> FFA25_W<'_>
[src]
Bit 25 - Filter FIFO assignment for filter 25
pub fn ffa26(&mut self) -> FFA26_W<'_>
[src]
Bit 26 - Filter FIFO assignment for filter 26
pub fn ffa27(&mut self) -> FFA27_W<'_>
[src]
Bit 27 - Filter FIFO assignment for filter 27
impl W<u32, Reg<u32, _FA1R>>
[src]
pub fn fact0(&mut self) -> FACT0_W<'_>
[src]
Bit 0 - Filter active
pub fn fact1(&mut self) -> FACT1_W<'_>
[src]
Bit 1 - Filter active
pub fn fact2(&mut self) -> FACT2_W<'_>
[src]
Bit 2 - Filter active
pub fn fact3(&mut self) -> FACT3_W<'_>
[src]
Bit 3 - Filter active
pub fn fact4(&mut self) -> FACT4_W<'_>
[src]
Bit 4 - Filter active
pub fn fact5(&mut self) -> FACT5_W<'_>
[src]
Bit 5 - Filter active
pub fn fact6(&mut self) -> FACT6_W<'_>
[src]
Bit 6 - Filter active
pub fn fact7(&mut self) -> FACT7_W<'_>
[src]
Bit 7 - Filter active
pub fn fact8(&mut self) -> FACT8_W<'_>
[src]
Bit 8 - Filter active
pub fn fact9(&mut self) -> FACT9_W<'_>
[src]
Bit 9 - Filter active
pub fn fact10(&mut self) -> FACT10_W<'_>
[src]
Bit 10 - Filter active
pub fn fact11(&mut self) -> FACT11_W<'_>
[src]
Bit 11 - Filter active
pub fn fact12(&mut self) -> FACT12_W<'_>
[src]
Bit 12 - Filter active
pub fn fact13(&mut self) -> FACT13_W<'_>
[src]
Bit 13 - Filter active
pub fn fact14(&mut self) -> FACT14_W<'_>
[src]
Bit 14 - Filter active
pub fn fact15(&mut self) -> FACT15_W<'_>
[src]
Bit 15 - Filter active
pub fn fact16(&mut self) -> FACT16_W<'_>
[src]
Bit 16 - Filter active
pub fn fact17(&mut self) -> FACT17_W<'_>
[src]
Bit 17 - Filter active
pub fn fact18(&mut self) -> FACT18_W<'_>
[src]
Bit 18 - Filter active
pub fn fact19(&mut self) -> FACT19_W<'_>
[src]
Bit 19 - Filter active
pub fn fact20(&mut self) -> FACT20_W<'_>
[src]
Bit 20 - Filter active
pub fn fact21(&mut self) -> FACT21_W<'_>
[src]
Bit 21 - Filter active
pub fn fact22(&mut self) -> FACT22_W<'_>
[src]
Bit 22 - Filter active
pub fn fact23(&mut self) -> FACT23_W<'_>
[src]
Bit 23 - Filter active
pub fn fact24(&mut self) -> FACT24_W<'_>
[src]
Bit 24 - Filter active
pub fn fact25(&mut self) -> FACT25_W<'_>
[src]
Bit 25 - Filter active
pub fn fact26(&mut self) -> FACT26_W<'_>
[src]
Bit 26 - Filter active
pub fn fact27(&mut self) -> FACT27_W<'_>
[src]
Bit 27 - Filter active
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn enable(&mut self) -> ENABLE_W<'_>
[src]
Bit 0 - Counter enable
pub fn tickint(&mut self) -> TICKINT_W<'_>
[src]
Bit 1 - SysTick exception request enable
pub fn clksource(&mut self) -> CLKSOURCE_W<'_>
[src]
Bit 2 - Clock source selection
pub fn countflag(&mut self) -> COUNTFLAG_W<'_>
[src]
Bit 16 - COUNTFLAG
impl W<u32, Reg<u32, _RVR>>
[src]
impl W<u32, Reg<u32, _CVR>>
[src]
impl W<u32, Reg<u32, _CALIB>>
[src]
pub fn tenms(&mut self) -> TENMS_W<'_>
[src]
Bits 0:23 - Calibration value
pub fn skew(&mut self) -> SKEW_W<'_>
[src]
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
pub fn noref(&mut self) -> NOREF_W<'_>
[src]
Bit 31 - NOREF flag. Reads as zero
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4np(&mut self) -> CC4NP_W<'_>
[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
pub fn cnt_h(&mut self) -> CNT_H_W<'_>
[src]
Bits 16:31 - High counter value (TIM2 only)
pub fn cnt(&mut self) -> CNT_W<'_>
[src]
Bits 0:15 - Counter value
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
pub fn arr_h(&mut self) -> ARR_H_W<'_>
[src]
Bits 16:31 - High Auto-reload value (TIM2 only)
pub fn arr(&mut self) -> ARR_W<'_>
[src]
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
[src]
pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>
[src]
Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
pub fn ccr(&mut self) -> CCR_W<'_>
[src]
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn comp1en(&mut self) -> COMP1EN_W<'_>
[src]
Bit 0 - Comparator 1 enable
pub fn comp1mode(&mut self) -> COMP1MODE_W<'_>
[src]
Bits 2:3 - Comparator 1 mode
pub fn comp1insel(&mut self) -> COMP1INSEL_W<'_>
[src]
Bits 4:6 - Comparator 1 inverting input selection
pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<'_>
[src]
Bits 8:10 - Comparator 1 output selection
pub fn comp1pol(&mut self) -> COMP1POL_W<'_>
[src]
Bit 11 - Comparator 1 output polarity
pub fn comp1hyst(&mut self) -> COMP1HYST_W<'_>
[src]
Bits 12:13 - Comparator 1 hysteresis
pub fn comp1lock(&mut self) -> COMP1LOCK_W<'_>
[src]
Bit 15 - Comparator 1 lock
pub fn comp2en(&mut self) -> COMP2EN_W<'_>
[src]
Bit 16 - Comparator 2 enable
pub fn comp2mode(&mut self) -> COMP2MODE_W<'_>
[src]
Bits 18:19 - Comparator 2 mode
pub fn comp2insel(&mut self) -> COMP2INSEL_W<'_>
[src]
Bits 20:22 - Comparator 2 inverting input selection
pub fn wndwen(&mut self) -> WNDWEN_W<'_>
[src]
Bit 23 - Window mode enable
pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<'_>
[src]
Bits 24:26 - Comparator 2 output selection
pub fn comp2pol(&mut self) -> COMP2POL_W<'_>
[src]
Bit 27 - Comparator 2 output polarity
pub fn comp2hyst(&mut self) -> COMP2HYST_W<'_>
[src]
Bits 28:29 - Comparator 2 hysteresis
pub fn comp2lock(&mut self) -> COMP2LOCK_W<'_>
[src]
Bit 31 - Comparator 2 lock
pub fn comp1sw1(&mut self) -> COMP1SW1_W<'_>
[src]
Bit 1 - Comparator 1 non inverting input DAC switch
impl W<u32, Reg<u32, _DR>>
[src]
impl W<u32, Reg<u32, _IDR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 0 - reset bit
pub fn polysize(&mut self) -> POLYSIZE_W<'_>
[src]
Bits 3:4 - Polynomial size
pub fn rev_in(&mut self) -> REV_IN_W<'_>
[src]
Bits 5:6 - Reverse input data
pub fn rev_out(&mut self) -> REV_OUT_W<'_>
[src]
Bit 7 - Reverse output data
impl W<u32, Reg<u32, _INIT>>
[src]
impl W<u8, Reg<u8, _DR8>>
[src]
impl W<u16, Reg<u16, _DR16>>
[src]
impl W<u32, Reg<u32, _MODER>>
[src]
pub fn moder15(&mut self) -> MODER15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
[src]
pub fn ot15(&mut self) -> OT15_W<'_>
[src]
Bit 15 - Port x configuration bit 15
pub fn ot14(&mut self) -> OT14_W<'_>
[src]
Bit 14 - Port x configuration bit 14
pub fn ot13(&mut self) -> OT13_W<'_>
[src]
Bit 13 - Port x configuration bit 13
pub fn ot12(&mut self) -> OT12_W<'_>
[src]
Bit 12 - Port x configuration bit 12
pub fn ot11(&mut self) -> OT11_W<'_>
[src]
Bit 11 - Port x configuration bit 11
pub fn ot10(&mut self) -> OT10_W<'_>
[src]
Bit 10 - Port x configuration bit 10
pub fn ot9(&mut self) -> OT9_W<'_>
[src]
Bit 9 - Port x configuration bit 9
pub fn ot8(&mut self) -> OT8_W<'_>
[src]
Bit 8 - Port x configuration bit 8
pub fn ot7(&mut self) -> OT7_W<'_>
[src]
Bit 7 - Port x configuration bit 7
pub fn ot6(&mut self) -> OT6_W<'_>
[src]
Bit 6 - Port x configuration bit 6
pub fn ot5(&mut self) -> OT5_W<'_>
[src]
Bit 5 - Port x configuration bit 5
pub fn ot4(&mut self) -> OT4_W<'_>
[src]
Bit 4 - Port x configuration bit 4
pub fn ot3(&mut self) -> OT3_W<'_>
[src]
Bit 3 - Port x configuration bit 3
pub fn ot2(&mut self) -> OT2_W<'_>
[src]
Bit 2 - Port x configuration bit 2
pub fn ot1(&mut self) -> OT1_W<'_>
[src]
Bit 1 - Port x configuration bit 1
pub fn ot0(&mut self) -> OT0_W<'_>
[src]
Bit 0 - Port x configuration bit 0
impl W<u32, Reg<u32, _OSPEEDR>>
[src]
pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
[src]
pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
[src]
pub fn odr15(&mut self) -> ODR15_W<'_>
[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
[src]
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
[src]
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
[src]
Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
[src]
Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
[src]
Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
[src]
Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
[src]
Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
[src]
Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
[src]
Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
[src]
Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
[src]
Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
[src]
Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
[src]
Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
[src]
Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
[src]
Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
[src]
Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
[src]
Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
[src]
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
[src]
pub fn lckk(&mut self) -> LCKK_W<'_>
[src]
Bit 16 - Port x lock bit y
pub fn lck15(&mut self) -> LCK15_W<'_>
[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
[src]
pub fn afrl7(&mut self) -> AFRL7_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
[src]
pub fn afrh15(&mut self) -> AFRH15_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
[src]
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _MODER>>
[src]
pub fn moder15(&mut self) -> MODER15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&mut self) -> MODER14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&mut self) -> MODER13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&mut self) -> MODER12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&mut self) -> MODER11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&mut self) -> MODER10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&mut self) -> MODER9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&mut self) -> MODER8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&mut self) -> MODER7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&mut self) -> MODER6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&mut self) -> MODER5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&mut self) -> MODER4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&mut self) -> MODER3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&mut self) -> MODER2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&mut self) -> MODER1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&mut self) -> MODER0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
[src]
pub fn ot15(&mut self) -> OT15_W<'_>
[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&mut self) -> OT14_W<'_>
[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&mut self) -> OT13_W<'_>
[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&mut self) -> OT12_W<'_>
[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&mut self) -> OT11_W<'_>
[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&mut self) -> OT10_W<'_>
[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&mut self) -> OT9_W<'_>
[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&mut self) -> OT8_W<'_>
[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&mut self) -> OT7_W<'_>
[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&mut self) -> OT6_W<'_>
[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&mut self) -> OT5_W<'_>
[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&mut self) -> OT4_W<'_>
[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&mut self) -> OT3_W<'_>
[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&mut self) -> OT2_W<'_>
[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&mut self) -> OT1_W<'_>
[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&mut self) -> OT0_W<'_>
[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
[src]
pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
[src]
pub fn pupdr15(&mut self) -> PUPDR15_W<'_>
[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&mut self) -> PUPDR14_W<'_>
[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&mut self) -> PUPDR13_W<'_>
[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&mut self) -> PUPDR12_W<'_>
[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&mut self) -> PUPDR11_W<'_>
[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&mut self) -> PUPDR10_W<'_>
[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&mut self) -> PUPDR9_W<'_>
[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&mut self) -> PUPDR8_W<'_>
[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&mut self) -> PUPDR7_W<'_>
[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&mut self) -> PUPDR6_W<'_>
[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&mut self) -> PUPDR5_W<'_>
[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&mut self) -> PUPDR4_W<'_>
[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&mut self) -> PUPDR3_W<'_>
[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&mut self) -> PUPDR2_W<'_>
[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&mut self) -> PUPDR1_W<'_>
[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&mut self) -> PUPDR0_W<'_>
[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
[src]
pub fn odr15(&mut self) -> ODR15_W<'_>
[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&mut self) -> ODR14_W<'_>
[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&mut self) -> ODR13_W<'_>
[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&mut self) -> ODR12_W<'_>
[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&mut self) -> ODR11_W<'_>
[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&mut self) -> ODR10_W<'_>
[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&mut self) -> ODR9_W<'_>
[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&mut self) -> ODR8_W<'_>
[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&mut self) -> ODR7_W<'_>
[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&mut self) -> ODR6_W<'_>
[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&mut self) -> ODR5_W<'_>
[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&mut self) -> ODR4_W<'_>
[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&mut self) -> ODR3_W<'_>
[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&mut self) -> ODR2_W<'_>
[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&mut self) -> ODR1_W<'_>
[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&mut self) -> ODR0_W<'_>
[src]
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
[src]
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 31 - Port x reset bit y (y = 0..15)
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 30 - Port x reset bit y (y = 0..15)
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 29 - Port x reset bit y (y = 0..15)
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 28 - Port x reset bit y (y = 0..15)
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 27 - Port x reset bit y (y = 0..15)
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 26 - Port x reset bit y (y = 0..15)
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 25 - Port x reset bit y (y = 0..15)
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 24 - Port x reset bit y (y = 0..15)
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 23 - Port x reset bit y (y = 0..15)
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 22 - Port x reset bit y (y = 0..15)
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 21 - Port x reset bit y (y = 0..15)
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 20 - Port x reset bit y (y = 0..15)
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 19 - Port x reset bit y (y = 0..15)
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 18 - Port x reset bit y (y = 0..15)
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 17 - Port x reset bit y (y = 0..15)
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 16 - Port x set bit y (y= 0..15)
pub fn bs15(&mut self) -> BS15_W<'_>
[src]
Bit 15 - Port x set bit y (y= 0..15)
pub fn bs14(&mut self) -> BS14_W<'_>
[src]
Bit 14 - Port x set bit y (y= 0..15)
pub fn bs13(&mut self) -> BS13_W<'_>
[src]
Bit 13 - Port x set bit y (y= 0..15)
pub fn bs12(&mut self) -> BS12_W<'_>
[src]
Bit 12 - Port x set bit y (y= 0..15)
pub fn bs11(&mut self) -> BS11_W<'_>
[src]
Bit 11 - Port x set bit y (y= 0..15)
pub fn bs10(&mut self) -> BS10_W<'_>
[src]
Bit 10 - Port x set bit y (y= 0..15)
pub fn bs9(&mut self) -> BS9_W<'_>
[src]
Bit 9 - Port x set bit y (y= 0..15)
pub fn bs8(&mut self) -> BS8_W<'_>
[src]
Bit 8 - Port x set bit y (y= 0..15)
pub fn bs7(&mut self) -> BS7_W<'_>
[src]
Bit 7 - Port x set bit y (y= 0..15)
pub fn bs6(&mut self) -> BS6_W<'_>
[src]
Bit 6 - Port x set bit y (y= 0..15)
pub fn bs5(&mut self) -> BS5_W<'_>
[src]
Bit 5 - Port x set bit y (y= 0..15)
pub fn bs4(&mut self) -> BS4_W<'_>
[src]
Bit 4 - Port x set bit y (y= 0..15)
pub fn bs3(&mut self) -> BS3_W<'_>
[src]
Bit 3 - Port x set bit y (y= 0..15)
pub fn bs2(&mut self) -> BS2_W<'_>
[src]
Bit 2 - Port x set bit y (y= 0..15)
pub fn bs1(&mut self) -> BS1_W<'_>
[src]
Bit 1 - Port x set bit y (y= 0..15)
pub fn bs0(&mut self) -> BS0_W<'_>
[src]
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
[src]
pub fn lckk(&mut self) -> LCKK_W<'_>
[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&mut self) -> LCK15_W<'_>
[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&mut self) -> LCK14_W<'_>
[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&mut self) -> LCK13_W<'_>
[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&mut self) -> LCK12_W<'_>
[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&mut self) -> LCK11_W<'_>
[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&mut self) -> LCK10_W<'_>
[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&mut self) -> LCK9_W<'_>
[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&mut self) -> LCK8_W<'_>
[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&mut self) -> LCK7_W<'_>
[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&mut self) -> LCK6_W<'_>
[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&mut self) -> LCK5_W<'_>
[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&mut self) -> LCK4_W<'_>
[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&mut self) -> LCK3_W<'_>
[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&mut self) -> LCK2_W<'_>
[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&mut self) -> LCK1_W<'_>
[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&mut self) -> LCK0_W<'_>
[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
[src]
pub fn afrl7(&mut self) -> AFRL7_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&mut self) -> AFRL6_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&mut self) -> AFRL5_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&mut self) -> AFRL4_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&mut self) -> AFRL3_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&mut self) -> AFRL2_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&mut self) -> AFRL1_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&mut self) -> AFRL0_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
[src]
pub fn afrh15(&mut self) -> AFRH15_W<'_>
[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&mut self) -> AFRH14_W<'_>
[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&mut self) -> AFRH13_W<'_>
[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&mut self) -> AFRH12_W<'_>
[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&mut self) -> AFRH11_W<'_>
[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&mut self) -> AFRH10_W<'_>
[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&mut self) -> AFRH9_W<'_>
[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&mut self) -> AFRH8_W<'_>
[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _BRR>>
[src]
pub fn br0(&mut self) -> BR0_W<'_>
[src]
Bit 0 - Port x Reset bit y
pub fn br1(&mut self) -> BR1_W<'_>
[src]
Bit 1 - Port x Reset bit y
pub fn br2(&mut self) -> BR2_W<'_>
[src]
Bit 2 - Port x Reset bit y
pub fn br3(&mut self) -> BR3_W<'_>
[src]
Bit 3 - Port x Reset bit y
pub fn br4(&mut self) -> BR4_W<'_>
[src]
Bit 4 - Port x Reset bit y
pub fn br5(&mut self) -> BR5_W<'_>
[src]
Bit 5 - Port x Reset bit y
pub fn br6(&mut self) -> BR6_W<'_>
[src]
Bit 6 - Port x Reset bit y
pub fn br7(&mut self) -> BR7_W<'_>
[src]
Bit 7 - Port x Reset bit y
pub fn br8(&mut self) -> BR8_W<'_>
[src]
Bit 8 - Port x Reset bit y
pub fn br9(&mut self) -> BR9_W<'_>
[src]
Bit 9 - Port x Reset bit y
pub fn br10(&mut self) -> BR10_W<'_>
[src]
Bit 10 - Port x Reset bit y
pub fn br11(&mut self) -> BR11_W<'_>
[src]
Bit 11 - Port x Reset bit y
pub fn br12(&mut self) -> BR12_W<'_>
[src]
Bit 12 - Port x Reset bit y
pub fn br13(&mut self) -> BR13_W<'_>
[src]
Bit 13 - Port x Reset bit y
pub fn br14(&mut self) -> BR14_W<'_>
[src]
Bit 14 - Port x Reset bit y
pub fn br15(&mut self) -> BR15_W<'_>
[src]
Bit 15 - Port x Reset bit y
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn bidimode(&mut self) -> BIDIMODE_W<'_>
[src]
Bit 15 - Bidirectional data mode enable
pub fn bidioe(&mut self) -> BIDIOE_W<'_>
[src]
Bit 14 - Output enable in bidirectional mode
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 13 - Hardware CRC calculation enable
pub fn crcnext(&mut self) -> CRCNEXT_W<'_>
[src]
Bit 12 - CRC transfer next
pub fn crcl(&mut self) -> CRCL_W<'_>
[src]
Bit 11 - CRC length
pub fn rxonly(&mut self) -> RXONLY_W<'_>
[src]
Bit 10 - Receive only
pub fn ssm(&mut self) -> SSM_W<'_>
[src]
Bit 9 - Software slave management
pub fn ssi(&mut self) -> SSI_W<'_>
[src]
Bit 8 - Internal slave select
pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>
[src]
Bit 7 - Frame format
pub fn spe(&mut self) -> SPE_W<'_>
[src]
Bit 6 - SPI enable
pub fn br(&mut self) -> BR_W<'_>
[src]
Bits 3:5 - Baud rate control
pub fn mstr(&mut self) -> MSTR_W<'_>
[src]
Bit 2 - Master selection
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 1 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 0 - Clock phase
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 0 - Rx buffer DMA enable
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 1 - Tx buffer DMA enable
pub fn ssoe(&mut self) -> SSOE_W<'_>
[src]
Bit 2 - SS output enable
pub fn nssp(&mut self) -> NSSP_W<'_>
[src]
Bit 3 - NSS pulse management
pub fn frf(&mut self) -> FRF_W<'_>
[src]
Bit 4 - Frame format
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 5 - Error interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 6 - RX buffer not empty interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - Tx buffer empty interrupt enable
pub fn ds(&mut self) -> DS_W<'_>
[src]
Bits 8:11 - Data size
pub fn frxth(&mut self) -> FRXTH_W<'_>
[src]
Bit 12 - FIFO reception threshold
pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>
[src]
Bit 13 - Last DMA transfer for reception
pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>
[src]
Bit 14 - Last DMA transfer for transmission
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _DR>>
[src]
impl W<u32, Reg<u32, _CRCPR>>
[src]
impl W<u32, Reg<u32, _I2SCFGR>>
[src]
pub fn i2smod(&mut self) -> I2SMOD_W<'_>
[src]
Bit 11 - I2S mode selection
pub fn i2se(&mut self) -> I2SE_W<'_>
[src]
Bit 10 - I2S Enable
pub fn i2scfg(&mut self) -> I2SCFG_W<'_>
[src]
Bits 8:9 - I2S configuration mode
pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>
[src]
Bit 7 - PCM frame synchronization
pub fn i2sstd(&mut self) -> I2SSTD_W<'_>
[src]
Bits 4:5 - I2S standard selection
pub fn ckpol(&mut self) -> CKPOL_W<'_>
[src]
Bit 3 - Steady state clock polarity
pub fn datlen(&mut self) -> DATLEN_W<'_>
[src]
Bits 1:2 - Data length to be transferred
pub fn chlen(&mut self) -> CHLEN_W<'_>
[src]
Bit 0 - Channel length (number of bits per audio channel)
impl W<u32, Reg<u32, _I2SPR>>
[src]
pub fn mckoe(&mut self) -> MCKOE_W<'_>
[src]
Bit 9 - Master clock output enable
pub fn odd(&mut self) -> ODD_W<'_>
[src]
Bit 8 - Odd factor for the prescaler
pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>
[src]
Bits 0:7 - I2S Linear prescaler
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbp(&mut self) -> DBP_W<'_>
[src]
Bit 8 - Disable backup domain write protection
pub fn pls(&mut self) -> PLS_W<'_>
[src]
Bits 5:7 - PVD level selection
pub fn pvde(&mut self) -> PVDE_W<'_>
[src]
Bit 4 - Power voltage detector enable
pub fn csbf(&mut self) -> CSBF_W<'_>
[src]
Bit 3 - Clear standby flag
pub fn cwuf(&mut self) -> CWUF_W<'_>
[src]
Bit 2 - Clear wakeup flag
pub fn pdds(&mut self) -> PDDS_W<'_>
[src]
Bit 1 - Power down deepsleep
pub fn lpds(&mut self) -> LPDS_W<'_>
[src]
Bit 0 - Low-power deep sleep
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn ewup1(&mut self) -> EWUP1_W<'_>
[src]
Bit 8 - Enable WKUP pin 1
pub fn ewup2(&mut self) -> EWUP2_W<'_>
[src]
Bit 9 - Enable WKUP pin 2
pub fn ewup3(&mut self) -> EWUP3_W<'_>
[src]
Bit 10 - Enable WKUP pin 3
pub fn ewup4(&mut self) -> EWUP4_W<'_>
[src]
Bit 11 - Enable WKUP pin 4
pub fn ewup5(&mut self) -> EWUP5_W<'_>
[src]
Bit 12 - Enable WKUP pin 5
pub fn ewup6(&mut self) -> EWUP6_W<'_>
[src]
Bit 13 - Enable WKUP pin 6
pub fn ewup7(&mut self) -> EWUP7_W<'_>
[src]
Bit 14 - Enable WKUP pin 7
pub fn ewup8(&mut self) -> EWUP8_W<'_>
[src]
Bit 15 - Enable WKUP pin 8
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn pe(&mut self) -> PE_W<'_>
[src]
Bit 0 - Peripheral enable
pub fn txie(&mut self) -> TXIE_W<'_>
[src]
Bit 1 - TX Interrupt enable
pub fn rxie(&mut self) -> RXIE_W<'_>
[src]
Bit 2 - RX Interrupt enable
pub fn addrie(&mut self) -> ADDRIE_W<'_>
[src]
Bit 3 - Address match interrupt enable (slave only)
pub fn nackie(&mut self) -> NACKIE_W<'_>
[src]
Bit 4 - Not acknowledge received interrupt enable
pub fn stopie(&mut self) -> STOPIE_W<'_>
[src]
Bit 5 - STOP detection Interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transfer Complete interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 7 - Error interrupts enable
pub fn dnf(&mut self) -> DNF_W<'_>
[src]
Bits 8:11 - Digital noise filter
pub fn anfoff(&mut self) -> ANFOFF_W<'_>
[src]
Bit 12 - Analog noise filter OFF
pub fn swrst(&mut self) -> SWRST_W<'_>
[src]
Bit 13 - Software reset
pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>
[src]
Bit 14 - DMA transmission requests enable
pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>
[src]
Bit 15 - DMA reception requests enable
pub fn sbc(&mut self) -> SBC_W<'_>
[src]
Bit 16 - Slave byte control
pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>
[src]
Bit 17 - Clock stretching disable
pub fn wupen(&mut self) -> WUPEN_W<'_>
[src]
Bit 18 - Wakeup from STOP enable
pub fn gcen(&mut self) -> GCEN_W<'_>
[src]
Bit 19 - General call enable
pub fn smbhen(&mut self) -> SMBHEN_W<'_>
[src]
Bit 20 - SMBus Host address enable
pub fn smbden(&mut self) -> SMBDEN_W<'_>
[src]
Bit 21 - SMBus Device Default address enable
pub fn alerten(&mut self) -> ALERTEN_W<'_>
[src]
Bit 22 - SMBUS alert enable
pub fn pecen(&mut self) -> PECEN_W<'_>
[src]
Bit 23 - PEC enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn pecbyte(&mut self) -> PECBYTE_W<'_>
[src]
Bit 26 - Packet error checking byte
pub fn autoend(&mut self) -> AUTOEND_W<'_>
[src]
Bit 25 - Automatic end mode (master mode)
pub fn reload(&mut self) -> RELOAD_W<'_>
[src]
Bit 24 - NBYTES reload mode
pub fn nbytes(&mut self) -> NBYTES_W<'_>
[src]
Bits 16:23 - Number of bytes
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 15 - NACK generation (slave mode)
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bit 14 - Stop generation (master mode)
pub fn start(&mut self) -> START_W<'_>
[src]
Bit 13 - Start generation
pub fn head10r(&mut self) -> HEAD10R_W<'_>
[src]
Bit 12 - 10-bit address header only read direction (master receiver mode)
pub fn add10(&mut self) -> ADD10_W<'_>
[src]
Bit 11 - 10-bit addressing mode (master mode)
pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>
[src]
Bit 10 - Transfer direction (master mode)
pub fn sadd(&mut self) -> SADD_W<'_>
[src]
Bits 0:9 - Slave address bit 9:8 (master mode)
impl W<u32, Reg<u32, _OAR1>>
[src]
pub fn oa1mode(&mut self) -> OA1MODE_W<'_>
[src]
Bit 10 - Own Address 1 10-bit mode
pub fn oa1en(&mut self) -> OA1EN_W<'_>
[src]
Bit 15 - Own Address 1 enable
pub fn oa1(&mut self) -> OA1_W<'_>
[src]
Bits 0:9 - Interface address
impl W<u32, Reg<u32, _OAR2>>
[src]
pub fn oa2(&mut self) -> OA2_W<'_>
[src]
Bits 1:7 - Interface address
pub fn oa2msk(&mut self) -> OA2MSK_W<'_>
[src]
Bits 8:10 - Own Address 2 masks
pub fn oa2en(&mut self) -> OA2EN_W<'_>
[src]
Bit 15 - Own Address 2 enable
impl W<u32, Reg<u32, _TIMINGR>>
[src]
pub fn scll(&mut self) -> SCLL_W<'_>
[src]
Bits 0:7 - SCL low period (master mode)
pub fn sclh(&mut self) -> SCLH_W<'_>
[src]
Bits 8:15 - SCL high period (master mode)
pub fn sdadel(&mut self) -> SDADEL_W<'_>
[src]
Bits 16:19 - Data hold time
pub fn scldel(&mut self) -> SCLDEL_W<'_>
[src]
Bits 20:23 - Data setup time
pub fn presc(&mut self) -> PRESC_W<'_>
[src]
Bits 28:31 - Timing prescaler
impl W<u32, Reg<u32, _TIMEOUTR>>
[src]
pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>
[src]
Bits 0:11 - Bus timeout A
pub fn tidle(&mut self) -> TIDLE_W<'_>
[src]
Bit 12 - Idle clock timeout detection
pub fn timouten(&mut self) -> TIMOUTEN_W<'_>
[src]
Bit 15 - Clock timeout enable
pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>
[src]
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
[src]
Bit 31 - Extended clock timeout enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn txis(&mut self) -> TXIS_W<'_>
[src]
Bit 1 - Transmit interrupt status (transmitters)
pub fn txe(&mut self) -> TXE_W<'_>
[src]
Bit 0 - Transmit data register empty (transmitters)
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn alertcf(&mut self) -> ALERTCF_W<'_>
[src]
Bit 13 - Alert flag clear
pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>
[src]
Bit 12 - Timeout detection flag clear
pub fn peccf(&mut self) -> PECCF_W<'_>
[src]
Bit 11 - PEC Error flag clear
pub fn ovrcf(&mut self) -> OVRCF_W<'_>
[src]
Bit 10 - Overrun/Underrun flag clear
pub fn arlocf(&mut self) -> ARLOCF_W<'_>
[src]
Bit 9 - Arbitration lost flag clear
pub fn berrcf(&mut self) -> BERRCF_W<'_>
[src]
Bit 8 - Bus error flag clear
pub fn stopcf(&mut self) -> STOPCF_W<'_>
[src]
Bit 5 - Stop detection flag clear
pub fn nackcf(&mut self) -> NACKCF_W<'_>
[src]
Bit 4 - Not Acknowledge flag clear
pub fn addrcf(&mut self) -> ADDRCF_W<'_>
[src]
Bit 3 - Address Matched flag clear
impl W<u32, Reg<u32, _TXDR>>
[src]
impl W<u32, Reg<u32, _KR>>
[src]
impl W<u32, Reg<u32, _PR>>
[src]
impl W<u32, Reg<u32, _RLR>>
[src]
impl W<u32, Reg<u32, _WINR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn wdga(&mut self) -> WDGA_W<'_>
[src]
Bit 7 - Activation bit
pub fn t(&mut self) -> T_W<'_>
[src]
Bits 0:6 - 7-bit counter
impl W<u32, Reg<u32, _CFR>>
[src]
pub fn ewi(&mut self) -> EWI_W<'_>
[src]
Bit 9 - Early wakeup interrupt
pub fn w(&mut self) -> W_W<'_>
[src]
Bits 0:6 - 7-bit window value
pub fn wdgtb(&mut self) -> WDGTB_W<'_>
[src]
Bits 7:8 - Timer base
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois4(&mut self) -> OIS4_W<'_>
[src]
Bit 14 - Output Idle state 4
pub fn ois3n(&mut self) -> OIS3N_W<'_>
[src]
Bit 13 - Output Idle state 3
pub fn ois3(&mut self) -> OIS3_W<'_>
[src]
Bit 12 - Output Idle state 3
pub fn ois2n(&mut self) -> OIS2N_W<'_>
[src]
Bit 11 - Output Idle state 2
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output Compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output Compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3ne(&mut self) -> CC3NE_W<'_>
[src]
Bit 10 - Capture/Compare 3 complementary output enable
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2ne(&mut self) -> CC2NE_W<'_>
[src]
Bit 6 - Capture/Compare 2 complementary output enable
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
[src]
pub fn oc4ce(&mut self) -> OC4CE_W<'_>
[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
[src]
pub fn ic4f(&mut self) -> IC4F_W<'_>
[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
[src]
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc4np(&mut self) -> CC4NP_W<'_>
[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&mut self) -> CC4P_W<'_>
[src]
Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&mut self) -> CC3P_W<'_>
[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output compare 1 fast enable
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _CCR>>
[src]
impl W<u32, Reg<u32, _OR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
impl W<u32, Reg<u32, _EGR>>
[src]
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _IMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Interrupt Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Interrupt Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Interrupt Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Interrupt Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Interrupt Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Interrupt Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Interrupt Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Interrupt Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Interrupt Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Interrupt Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Interrupt Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Interrupt Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Interrupt Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Interrupt Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Interrupt Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Interrupt Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Interrupt Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Interrupt Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Interrupt Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Interrupt Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Interrupt Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Interrupt Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Interrupt Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Interrupt Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Interrupt Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Interrupt Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Interrupt Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Interrupt Mask on line 27
impl W<u32, Reg<u32, _EMR>>
[src]
pub fn mr0(&mut self) -> MR0_W<'_>
[src]
Bit 0 - Event Mask on line 0
pub fn mr1(&mut self) -> MR1_W<'_>
[src]
Bit 1 - Event Mask on line 1
pub fn mr2(&mut self) -> MR2_W<'_>
[src]
Bit 2 - Event Mask on line 2
pub fn mr3(&mut self) -> MR3_W<'_>
[src]
Bit 3 - Event Mask on line 3
pub fn mr4(&mut self) -> MR4_W<'_>
[src]
Bit 4 - Event Mask on line 4
pub fn mr5(&mut self) -> MR5_W<'_>
[src]
Bit 5 - Event Mask on line 5
pub fn mr6(&mut self) -> MR6_W<'_>
[src]
Bit 6 - Event Mask on line 6
pub fn mr7(&mut self) -> MR7_W<'_>
[src]
Bit 7 - Event Mask on line 7
pub fn mr8(&mut self) -> MR8_W<'_>
[src]
Bit 8 - Event Mask on line 8
pub fn mr9(&mut self) -> MR9_W<'_>
[src]
Bit 9 - Event Mask on line 9
pub fn mr10(&mut self) -> MR10_W<'_>
[src]
Bit 10 - Event Mask on line 10
pub fn mr11(&mut self) -> MR11_W<'_>
[src]
Bit 11 - Event Mask on line 11
pub fn mr12(&mut self) -> MR12_W<'_>
[src]
Bit 12 - Event Mask on line 12
pub fn mr13(&mut self) -> MR13_W<'_>
[src]
Bit 13 - Event Mask on line 13
pub fn mr14(&mut self) -> MR14_W<'_>
[src]
Bit 14 - Event Mask on line 14
pub fn mr15(&mut self) -> MR15_W<'_>
[src]
Bit 15 - Event Mask on line 15
pub fn mr16(&mut self) -> MR16_W<'_>
[src]
Bit 16 - Event Mask on line 16
pub fn mr17(&mut self) -> MR17_W<'_>
[src]
Bit 17 - Event Mask on line 17
pub fn mr18(&mut self) -> MR18_W<'_>
[src]
Bit 18 - Event Mask on line 18
pub fn mr19(&mut self) -> MR19_W<'_>
[src]
Bit 19 - Event Mask on line 19
pub fn mr20(&mut self) -> MR20_W<'_>
[src]
Bit 20 - Event Mask on line 20
pub fn mr21(&mut self) -> MR21_W<'_>
[src]
Bit 21 - Event Mask on line 21
pub fn mr22(&mut self) -> MR22_W<'_>
[src]
Bit 22 - Event Mask on line 22
pub fn mr23(&mut self) -> MR23_W<'_>
[src]
Bit 23 - Event Mask on line 23
pub fn mr24(&mut self) -> MR24_W<'_>
[src]
Bit 24 - Event Mask on line 24
pub fn mr25(&mut self) -> MR25_W<'_>
[src]
Bit 25 - Event Mask on line 25
pub fn mr26(&mut self) -> MR26_W<'_>
[src]
Bit 26 - Event Mask on line 26
pub fn mr27(&mut self) -> MR27_W<'_>
[src]
Bit 27 - Event Mask on line 27
impl W<u32, Reg<u32, _RTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Rising trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Rising trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Rising trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Rising trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Rising trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Rising trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Rising trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Rising trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
[src]
Bit 8 - Rising trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
[src]
Bit 9 - Rising trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Rising trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Rising trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Rising trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Rising trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Rising trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Rising trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Rising trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Rising trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Rising trigger event configuration of line 19
impl W<u32, Reg<u32, _FTSR>>
[src]
pub fn tr0(&mut self) -> TR0_W<'_>
[src]
Bit 0 - Falling trigger event configuration of line 0
pub fn tr1(&mut self) -> TR1_W<'_>
[src]
Bit 1 - Falling trigger event configuration of line 1
pub fn tr2(&mut self) -> TR2_W<'_>
[src]
Bit 2 - Falling trigger event configuration of line 2
pub fn tr3(&mut self) -> TR3_W<'_>
[src]
Bit 3 - Falling trigger event configuration of line 3
pub fn tr4(&mut self) -> TR4_W<'_>
[src]
Bit 4 - Falling trigger event configuration of line 4
pub fn tr5(&mut self) -> TR5_W<'_>
[src]
Bit 5 - Falling trigger event configuration of line 5
pub fn tr6(&mut self) -> TR6_W<'_>
[src]
Bit 6 - Falling trigger event configuration of line 6
pub fn tr7(&mut self) -> TR7_W<'_>
[src]
Bit 7 - Falling trigger event configuration of line 7
pub fn tr8(&mut self) -> TR8_W<'_>
[src]
Bit 8 - Falling trigger event configuration of line 8
pub fn tr9(&mut self) -> TR9_W<'_>
[src]
Bit 9 - Falling trigger event configuration of line 9
pub fn tr10(&mut self) -> TR10_W<'_>
[src]
Bit 10 - Falling trigger event configuration of line 10
pub fn tr11(&mut self) -> TR11_W<'_>
[src]
Bit 11 - Falling trigger event configuration of line 11
pub fn tr12(&mut self) -> TR12_W<'_>
[src]
Bit 12 - Falling trigger event configuration of line 12
pub fn tr13(&mut self) -> TR13_W<'_>
[src]
Bit 13 - Falling trigger event configuration of line 13
pub fn tr14(&mut self) -> TR14_W<'_>
[src]
Bit 14 - Falling trigger event configuration of line 14
pub fn tr15(&mut self) -> TR15_W<'_>
[src]
Bit 15 - Falling trigger event configuration of line 15
pub fn tr16(&mut self) -> TR16_W<'_>
[src]
Bit 16 - Falling trigger event configuration of line 16
pub fn tr17(&mut self) -> TR17_W<'_>
[src]
Bit 17 - Falling trigger event configuration of line 17
pub fn tr19(&mut self) -> TR19_W<'_>
[src]
Bit 19 - Falling trigger event configuration of line 19
impl W<u32, Reg<u32, _SWIER>>
[src]
pub fn swier0(&mut self) -> SWIER0_W<'_>
[src]
Bit 0 - Software Interrupt on line 0
pub fn swier1(&mut self) -> SWIER1_W<'_>
[src]
Bit 1 - Software Interrupt on line 1
pub fn swier2(&mut self) -> SWIER2_W<'_>
[src]
Bit 2 - Software Interrupt on line 2
pub fn swier3(&mut self) -> SWIER3_W<'_>
[src]
Bit 3 - Software Interrupt on line 3
pub fn swier4(&mut self) -> SWIER4_W<'_>
[src]
Bit 4 - Software Interrupt on line 4
pub fn swier5(&mut self) -> SWIER5_W<'_>
[src]
Bit 5 - Software Interrupt on line 5
pub fn swier6(&mut self) -> SWIER6_W<'_>
[src]
Bit 6 - Software Interrupt on line 6
pub fn swier7(&mut self) -> SWIER7_W<'_>
[src]
Bit 7 - Software Interrupt on line 7
pub fn swier8(&mut self) -> SWIER8_W<'_>
[src]
Bit 8 - Software Interrupt on line 8
pub fn swier9(&mut self) -> SWIER9_W<'_>
[src]
Bit 9 - Software Interrupt on line 9
pub fn swier10(&mut self) -> SWIER10_W<'_>
[src]
Bit 10 - Software Interrupt on line 10
pub fn swier11(&mut self) -> SWIER11_W<'_>
[src]
Bit 11 - Software Interrupt on line 11
pub fn swier12(&mut self) -> SWIER12_W<'_>
[src]
Bit 12 - Software Interrupt on line 12
pub fn swier13(&mut self) -> SWIER13_W<'_>
[src]
Bit 13 - Software Interrupt on line 13
pub fn swier14(&mut self) -> SWIER14_W<'_>
[src]
Bit 14 - Software Interrupt on line 14
pub fn swier15(&mut self) -> SWIER15_W<'_>
[src]
Bit 15 - Software Interrupt on line 15
pub fn swier16(&mut self) -> SWIER16_W<'_>
[src]
Bit 16 - Software Interrupt on line 16
pub fn swier17(&mut self) -> SWIER17_W<'_>
[src]
Bit 17 - Software Interrupt on line 17
pub fn swier19(&mut self) -> SWIER19_W<'_>
[src]
Bit 19 - Software Interrupt on line 19
impl W<u32, Reg<u32, _PR>>
[src]
pub fn pr0(&mut self) -> PR0_W<'_>
[src]
Bit 0 - Pending bit 0
pub fn pr1(&mut self) -> PR1_W<'_>
[src]
Bit 1 - Pending bit 1
pub fn pr2(&mut self) -> PR2_W<'_>
[src]
Bit 2 - Pending bit 2
pub fn pr3(&mut self) -> PR3_W<'_>
[src]
Bit 3 - Pending bit 3
pub fn pr4(&mut self) -> PR4_W<'_>
[src]
Bit 4 - Pending bit 4
pub fn pr5(&mut self) -> PR5_W<'_>
[src]
Bit 5 - Pending bit 5
pub fn pr6(&mut self) -> PR6_W<'_>
[src]
Bit 6 - Pending bit 6
pub fn pr7(&mut self) -> PR7_W<'_>
[src]
Bit 7 - Pending bit 7
pub fn pr8(&mut self) -> PR8_W<'_>
[src]
Bit 8 - Pending bit 8
pub fn pr9(&mut self) -> PR9_W<'_>
[src]
Bit 9 - Pending bit 9
pub fn pr10(&mut self) -> PR10_W<'_>
[src]
Bit 10 - Pending bit 10
pub fn pr11(&mut self) -> PR11_W<'_>
[src]
Bit 11 - Pending bit 11
pub fn pr12(&mut self) -> PR12_W<'_>
[src]
Bit 12 - Pending bit 12
pub fn pr13(&mut self) -> PR13_W<'_>
[src]
Bit 13 - Pending bit 13
pub fn pr14(&mut self) -> PR14_W<'_>
[src]
Bit 14 - Pending bit 14
pub fn pr15(&mut self) -> PR15_W<'_>
[src]
Bit 15 - Pending bit 15
pub fn pr16(&mut self) -> PR16_W<'_>
[src]
Bit 16 - Pending bit 16
pub fn pr17(&mut self) -> PR17_W<'_>
[src]
Bit 17 - Pending bit 17
pub fn pr19(&mut self) -> PR19_W<'_>
[src]
Bit 19 - Pending bit 19
impl W<u32, Reg<u32, _CR>>
[src]
pub fn en(&mut self) -> EN_W<'_>
[src]
Bit 0 - Channel enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 1 - Transfer complete interrupt enable
pub fn htie(&mut self) -> HTIE_W<'_>
[src]
Bit 2 - Half Transfer interrupt enable
pub fn teie(&mut self) -> TEIE_W<'_>
[src]
Bit 3 - Transfer error interrupt enable
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Data transfer direction
pub fn circ(&mut self) -> CIRC_W<'_>
[src]
Bit 5 - Circular mode
pub fn pinc(&mut self) -> PINC_W<'_>
[src]
Bit 6 - Peripheral increment mode
pub fn minc(&mut self) -> MINC_W<'_>
[src]
Bit 7 - Memory increment mode
pub fn psize(&mut self) -> PSIZE_W<'_>
[src]
Bits 8:9 - Peripheral size
pub fn msize(&mut self) -> MSIZE_W<'_>
[src]
Bits 10:11 - Memory size
pub fn pl(&mut self) -> PL_W<'_>
[src]
Bits 12:13 - Channel Priority level
pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>
[src]
Bit 14 - Memory to memory mode
impl W<u32, Reg<u32, _NDTR>>
[src]
impl W<u32, Reg<u32, _PAR>>
[src]
impl W<u32, Reg<u32, _MAR>>
[src]
impl W<u32, Reg<u32, _IFCR>>
[src]
pub fn cgif1(&mut self) -> CGIF1_W<'_>
[src]
Bit 0 - Channel 1 Global interrupt clear
pub fn ctcif1(&mut self) -> CTCIF1_W<'_>
[src]
Bit 1 - Channel 1 Transfer Complete clear
pub fn chtif1(&mut self) -> CHTIF1_W<'_>
[src]
Bit 2 - Channel 1 Half Transfer clear
pub fn cteif1(&mut self) -> CTEIF1_W<'_>
[src]
Bit 3 - Channel 1 Transfer Error clear
pub fn cgif2(&mut self) -> CGIF2_W<'_>
[src]
Bit 4 - Channel 2 Global interrupt clear
pub fn ctcif2(&mut self) -> CTCIF2_W<'_>
[src]
Bit 5 - Channel 2 Transfer Complete clear
pub fn chtif2(&mut self) -> CHTIF2_W<'_>
[src]
Bit 6 - Channel 2 Half Transfer clear
pub fn cteif2(&mut self) -> CTEIF2_W<'_>
[src]
Bit 7 - Channel 2 Transfer Error clear
pub fn cgif3(&mut self) -> CGIF3_W<'_>
[src]
Bit 8 - Channel 3 Global interrupt clear
pub fn ctcif3(&mut self) -> CTCIF3_W<'_>
[src]
Bit 9 - Channel 3 Transfer Complete clear
pub fn chtif3(&mut self) -> CHTIF3_W<'_>
[src]
Bit 10 - Channel 3 Half Transfer clear
pub fn cteif3(&mut self) -> CTEIF3_W<'_>
[src]
Bit 11 - Channel 3 Transfer Error clear
pub fn cgif4(&mut self) -> CGIF4_W<'_>
[src]
Bit 12 - Channel 4 Global interrupt clear
pub fn ctcif4(&mut self) -> CTCIF4_W<'_>
[src]
Bit 13 - Channel 4 Transfer Complete clear
pub fn chtif4(&mut self) -> CHTIF4_W<'_>
[src]
Bit 14 - Channel 4 Half Transfer clear
pub fn cteif4(&mut self) -> CTEIF4_W<'_>
[src]
Bit 15 - Channel 4 Transfer Error clear
pub fn cgif5(&mut self) -> CGIF5_W<'_>
[src]
Bit 16 - Channel 5 Global interrupt clear
pub fn ctcif5(&mut self) -> CTCIF5_W<'_>
[src]
Bit 17 - Channel 5 Transfer Complete clear
pub fn chtif5(&mut self) -> CHTIF5_W<'_>
[src]
Bit 18 - Channel 5 Half Transfer clear
pub fn cteif5(&mut self) -> CTEIF5_W<'_>
[src]
Bit 19 - Channel 5 Transfer Error clear
pub fn cgif6(&mut self) -> CGIF6_W<'_>
[src]
Bit 20 - Channel 6 Global interrupt clear
pub fn ctcif6(&mut self) -> CTCIF6_W<'_>
[src]
Bit 21 - Channel 6 Transfer Complete clear
pub fn chtif6(&mut self) -> CHTIF6_W<'_>
[src]
Bit 22 - Channel 6 Half Transfer clear
pub fn cteif6(&mut self) -> CTEIF6_W<'_>
[src]
Bit 23 - Channel 6 Transfer Error clear
pub fn cgif7(&mut self) -> CGIF7_W<'_>
[src]
Bit 24 - Channel 7 Global interrupt clear
pub fn ctcif7(&mut self) -> CTCIF7_W<'_>
[src]
Bit 25 - Channel 7 Transfer Complete clear
pub fn chtif7(&mut self) -> CHTIF7_W<'_>
[src]
Bit 26 - Channel 7 Half Transfer clear
pub fn cteif7(&mut self) -> CTEIF7_W<'_>
[src]
Bit 27 - Channel 7 Transfer Error clear
impl W<u32, Reg<u32, _CR>>
[src]
pub fn hsion(&mut self) -> HSION_W<'_>
[src]
Bit 0 - Internal High Speed clock enable
pub fn hsitrim(&mut self) -> HSITRIM_W<'_>
[src]
Bits 3:7 - Internal High Speed clock trimming
pub fn hseon(&mut self) -> HSEON_W<'_>
[src]
Bit 16 - External High Speed clock enable
pub fn hsebyp(&mut self) -> HSEBYP_W<'_>
[src]
Bit 18 - External High Speed clock Bypass
pub fn csson(&mut self) -> CSSON_W<'_>
[src]
Bit 19 - Clock Security System enable
pub fn pllon(&mut self) -> PLLON_W<'_>
[src]
Bit 24 - PLL enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn sw(&mut self) -> SW_W<'_>
[src]
Bits 0:1 - System clock Switch
pub fn hpre(&mut self) -> HPRE_W<'_>
[src]
Bits 4:7 - AHB prescaler
pub fn ppre(&mut self) -> PPRE_W<'_>
[src]
Bits 8:10 - APB Low speed prescaler (APB1)
pub fn adcpre(&mut self) -> ADCPRE_W<'_>
[src]
Bit 14 - APCPRE is deprecated. See ADC field in CFGR2 register.
pub fn pllsrc(&mut self) -> PLLSRC_W<'_>
[src]
Bits 15:16 - PLL input clock source
pub fn pllxtpre(&mut self) -> PLLXTPRE_W<'_>
[src]
Bit 17 - HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning
pub fn pllmul(&mut self) -> PLLMUL_W<'_>
[src]
Bits 18:21 - PLL Multiplication Factor
pub fn mco(&mut self) -> MCO_W<'_>
[src]
Bits 24:26 - Microcontroller clock output
pub fn mcopre(&mut self) -> MCOPRE_W<'_>
[src]
Bits 28:30 - Microcontroller Clock Output Prescaler
pub fn pllnodiv(&mut self) -> PLLNODIV_W<'_>
[src]
Bit 31 - PLL clock not divided for MCO
impl W<u32, Reg<u32, _CIR>>
[src]
pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>
[src]
Bit 8 - LSI Ready Interrupt Enable
pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>
[src]
Bit 9 - LSE Ready Interrupt Enable
pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>
[src]
Bit 10 - HSI Ready Interrupt Enable
pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>
[src]
Bit 11 - HSE Ready Interrupt Enable
pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>
[src]
Bit 12 - PLL Ready Interrupt Enable
pub fn hsi14rdyie(&mut self) -> HSI14RDYIE_W<'_>
[src]
Bit 13 - HSI14 ready interrupt enable
pub fn hsi48rdyie(&mut self) -> HSI48RDYIE_W<'_>
[src]
Bit 14 - HSI48 ready interrupt enable
pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>
[src]
Bit 16 - LSI Ready Interrupt Clear
pub fn lserdyc(&mut self) -> LSERDYC_W<'_>
[src]
Bit 17 - LSE Ready Interrupt Clear
pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>
[src]
Bit 18 - HSI Ready Interrupt Clear
pub fn hserdyc(&mut self) -> HSERDYC_W<'_>
[src]
Bit 19 - HSE Ready Interrupt Clear
pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>
[src]
Bit 20 - PLL Ready Interrupt Clear
pub fn hsi14rdyc(&mut self) -> HSI14RDYC_W<'_>
[src]
Bit 21 - HSI 14 MHz Ready Interrupt Clear
pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W<'_>
[src]
Bit 22 - HSI48 Ready Interrupt Clear
pub fn cssc(&mut self) -> CSSC_W<'_>
[src]
Bit 23 - Clock security system interrupt clear
impl W<u32, Reg<u32, _APB2RSTR>>
[src]
pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>
[src]
Bit 0 - SYSCFG and COMP reset
pub fn adcrst(&mut self) -> ADCRST_W<'_>
[src]
Bit 9 - ADC interface reset
pub fn tim1rst(&mut self) -> TIM1RST_W<'_>
[src]
Bit 11 - TIM1 timer reset
pub fn spi1rst(&mut self) -> SPI1RST_W<'_>
[src]
Bit 12 - SPI 1 reset
pub fn usart1rst(&mut self) -> USART1RST_W<'_>
[src]
Bit 14 - USART1 reset
pub fn tim15rst(&mut self) -> TIM15RST_W<'_>
[src]
Bit 16 - TIM15 timer reset
pub fn tim16rst(&mut self) -> TIM16RST_W<'_>
[src]
Bit 17 - TIM16 timer reset
pub fn tim17rst(&mut self) -> TIM17RST_W<'_>
[src]
Bit 18 - TIM17 timer reset
pub fn dbgmcurst(&mut self) -> DBGMCURST_W<'_>
[src]
Bit 22 - Debug MCU reset
pub fn usart6rst(&mut self) -> USART6RST_W<'_>
[src]
Bit 5 - USART6 reset
pub fn usart8rst(&mut self) -> USART8RST_W<'_>
[src]
Bit 7 - USART8 reset
pub fn usart7rst(&mut self) -> USART7RST_W<'_>
[src]
Bit 6 - USART7 reset
impl W<u32, Reg<u32, _APB1RSTR>>
[src]
pub fn tim2rst(&mut self) -> TIM2RST_W<'_>
[src]
Bit 0 - Timer 2 reset
pub fn tim3rst(&mut self) -> TIM3RST_W<'_>
[src]
Bit 1 - Timer 3 reset
pub fn tim6rst(&mut self) -> TIM6RST_W<'_>
[src]
Bit 4 - Timer 6 reset
pub fn tim7rst(&mut self) -> TIM7RST_W<'_>
[src]
Bit 5 - TIM7 timer reset
pub fn tim14rst(&mut self) -> TIM14RST_W<'_>
[src]
Bit 8 - Timer 14 reset
pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>
[src]
Bit 11 - Window watchdog reset
pub fn spi2rst(&mut self) -> SPI2RST_W<'_>
[src]
Bit 14 - SPI2 reset
pub fn usart2rst(&mut self) -> USART2RST_W<'_>
[src]
Bit 17 - USART 2 reset
pub fn usart3rst(&mut self) -> USART3RST_W<'_>
[src]
Bit 18 - USART3 reset
pub fn usart4rst(&mut self) -> USART4RST_W<'_>
[src]
Bit 19 - USART4 reset
pub fn usart5rst(&mut self) -> USART5RST_W<'_>
[src]
Bit 20 - USART5 reset
pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>
[src]
Bit 21 - I2C1 reset
pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>
[src]
Bit 22 - I2C2 reset
pub fn usbrst(&mut self) -> USBRST_W<'_>
[src]
Bit 23 - USB interface reset
pub fn canrst(&mut self) -> CANRST_W<'_>
[src]
Bit 25 - CAN interface reset
pub fn crsrst(&mut self) -> CRSRST_W<'_>
[src]
Bit 27 - Clock Recovery System interface reset
pub fn pwrrst(&mut self) -> PWRRST_W<'_>
[src]
Bit 28 - Power interface reset
pub fn dacrst(&mut self) -> DACRST_W<'_>
[src]
Bit 29 - DAC interface reset
pub fn cecrst(&mut self) -> CECRST_W<'_>
[src]
Bit 30 - HDMI CEC reset
impl W<u32, Reg<u32, _AHBENR>>
[src]
pub fn dma1en(&mut self) -> DMA1EN_W<'_>
[src]
Bit 0 - DMA1 clock enable
pub fn dma2en(&mut self) -> DMA2EN_W<'_>
[src]
Bit 1 - DMA2 clock enable
pub fn sramen(&mut self) -> SRAMEN_W<'_>
[src]
Bit 2 - SRAM interface clock enable
pub fn flitfen(&mut self) -> FLITFEN_W<'_>
[src]
Bit 4 - FLITF clock enable
pub fn crcen(&mut self) -> CRCEN_W<'_>
[src]
Bit 6 - CRC clock enable
pub fn iopaen(&mut self) -> IOPAEN_W<'_>
[src]
Bit 17 - I/O port A clock enable
pub fn iopben(&mut self) -> IOPBEN_W<'_>
[src]
Bit 18 - I/O port B clock enable
pub fn iopcen(&mut self) -> IOPCEN_W<'_>
[src]
Bit 19 - I/O port C clock enable
pub fn iopden(&mut self) -> IOPDEN_W<'_>
[src]
Bit 20 - I/O port D clock enable
pub fn iopfen(&mut self) -> IOPFEN_W<'_>
[src]
Bit 22 - I/O port F clock enable
pub fn tscen(&mut self) -> TSCEN_W<'_>
[src]
Bit 24 - Touch sensing controller clock enable
pub fn iopeen(&mut self) -> IOPEEN_W<'_>
[src]
Bit 21 - I/O port E clock enable
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - DMA clock enable
impl W<u32, Reg<u32, _APB2ENR>>
[src]
pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>
[src]
Bit 0 - SYSCFG clock enable
pub fn adcen(&mut self) -> ADCEN_W<'_>
[src]
Bit 9 - ADC 1 interface clock enable
pub fn tim1en(&mut self) -> TIM1EN_W<'_>
[src]
Bit 11 - TIM1 Timer clock enable
pub fn spi1en(&mut self) -> SPI1EN_W<'_>
[src]
Bit 12 - SPI 1 clock enable
pub fn usart1en(&mut self) -> USART1EN_W<'_>
[src]
Bit 14 - USART1 clock enable
pub fn tim15en(&mut self) -> TIM15EN_W<'_>
[src]
Bit 16 - TIM15 timer clock enable
pub fn tim16en(&mut self) -> TIM16EN_W<'_>
[src]
Bit 17 - TIM16 timer clock enable
pub fn tim17en(&mut self) -> TIM17EN_W<'_>
[src]
Bit 18 - TIM17 timer clock enable
pub fn dbgmcuen(&mut self) -> DBGMCUEN_W<'_>
[src]
Bit 22 - MCU debug module clock enable
pub fn usart6en(&mut self) -> USART6EN_W<'_>
[src]
Bit 5 - USART6 clock enable
pub fn usart8en(&mut self) -> USART8EN_W<'_>
[src]
Bit 7 - USART8 clock enable
pub fn usart7en(&mut self) -> USART7EN_W<'_>
[src]
Bit 6 - USART7 clock enable
impl W<u32, Reg<u32, _APB1ENR>>
[src]
pub fn tim2en(&mut self) -> TIM2EN_W<'_>
[src]
Bit 0 - Timer 2 clock enable
pub fn tim3en(&mut self) -> TIM3EN_W<'_>
[src]
Bit 1 - Timer 3 clock enable
pub fn tim6en(&mut self) -> TIM6EN_W<'_>
[src]
Bit 4 - Timer 6 clock enable
pub fn tim7en(&mut self) -> TIM7EN_W<'_>
[src]
Bit 5 - TIM7 timer clock enable
pub fn tim14en(&mut self) -> TIM14EN_W<'_>
[src]
Bit 8 - Timer 14 clock enable
pub fn wwdgen(&mut self) -> WWDGEN_W<'_>
[src]
Bit 11 - Window watchdog clock enable
pub fn spi2en(&mut self) -> SPI2EN_W<'_>
[src]
Bit 14 - SPI 2 clock enable
pub fn usart2en(&mut self) -> USART2EN_W<'_>
[src]
Bit 17 - USART 2 clock enable
pub fn usart3en(&mut self) -> USART3EN_W<'_>
[src]
Bit 18 - USART3 clock enable
pub fn usart4en(&mut self) -> USART4EN_W<'_>
[src]
Bit 19 - USART4 clock enable
pub fn usart5en(&mut self) -> USART5EN_W<'_>
[src]
Bit 20 - USART5 clock enable
pub fn i2c1en(&mut self) -> I2C1EN_W<'_>
[src]
Bit 21 - I2C 1 clock enable
pub fn i2c2en(&mut self) -> I2C2EN_W<'_>
[src]
Bit 22 - I2C 2 clock enable
pub fn usben(&mut self) -> USBEN_W<'_>
[src]
Bit 23 - USB interface clock enable
pub fn canen(&mut self) -> CANEN_W<'_>
[src]
Bit 25 - CAN interface clock enable
pub fn crsen(&mut self) -> CRSEN_W<'_>
[src]
Bit 27 - Clock Recovery System interface clock enable
pub fn pwren(&mut self) -> PWREN_W<'_>
[src]
Bit 28 - Power interface clock enable
pub fn dacen(&mut self) -> DACEN_W<'_>
[src]
Bit 29 - DAC interface clock enable
pub fn cecen(&mut self) -> CECEN_W<'_>
[src]
Bit 30 - HDMI CEC interface clock enable
impl W<u32, Reg<u32, _BDCR>>
[src]
pub fn lseon(&mut self) -> LSEON_W<'_>
[src]
Bit 0 - External Low Speed oscillator enable
pub fn lsebyp(&mut self) -> LSEBYP_W<'_>
[src]
Bit 2 - External Low Speed oscillator bypass
pub fn lsedrv(&mut self) -> LSEDRV_W<'_>
[src]
Bits 3:4 - LSE oscillator drive capability
pub fn rtcsel(&mut self) -> RTCSEL_W<'_>
[src]
Bits 8:9 - RTC clock source selection
pub fn rtcen(&mut self) -> RTCEN_W<'_>
[src]
Bit 15 - RTC clock enable
pub fn bdrst(&mut self) -> BDRST_W<'_>
[src]
Bit 16 - Backup domain software reset
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn lsion(&mut self) -> LSION_W<'_>
[src]
Bit 0 - Internal low speed oscillator enable
pub fn rmvf(&mut self) -> RMVF_W<'_>
[src]
Bit 24 - Remove reset flag
pub fn oblrstf(&mut self) -> OBLRSTF_W<'_>
[src]
Bit 25 - Option byte loader reset flag
pub fn pinrstf(&mut self) -> PINRSTF_W<'_>
[src]
Bit 26 - PIN reset flag
pub fn porrstf(&mut self) -> PORRSTF_W<'_>
[src]
Bit 27 - POR/PDR reset flag
pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>
[src]
Bit 28 - Software reset flag
pub fn iwdgrstf(&mut self) -> IWDGRSTF_W<'_>
[src]
Bit 29 - Independent watchdog reset flag
pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>
[src]
Bit 30 - Window watchdog reset flag
pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>
[src]
Bit 31 - Low-power reset flag
pub fn v18pwrrstf(&mut self) -> V18PWRRSTF_W<'_>
[src]
Bit 23 - 1.8 V domain reset flag
impl W<u32, Reg<u32, _AHBRSTR>>
[src]
pub fn ioparst(&mut self) -> IOPARST_W<'_>
[src]
Bit 17 - I/O port A reset
pub fn iopbrst(&mut self) -> IOPBRST_W<'_>
[src]
Bit 18 - I/O port B reset
pub fn iopcrst(&mut self) -> IOPCRST_W<'_>
[src]
Bit 19 - I/O port C reset
pub fn iopdrst(&mut self) -> IOPDRST_W<'_>
[src]
Bit 20 - I/O port D reset
pub fn iopfrst(&mut self) -> IOPFRST_W<'_>
[src]
Bit 22 - I/O port F reset
pub fn tscrst(&mut self) -> TSCRST_W<'_>
[src]
Bit 24 - Touch sensing controller reset
pub fn ioperst(&mut self) -> IOPERST_W<'_>
[src]
Bit 21 - I/O port E reset
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _CFGR3>>
[src]
pub fn usart1sw(&mut self) -> USART1SW_W<'_>
[src]
Bits 0:1 - USART1 clock source selection
pub fn i2c1sw(&mut self) -> I2C1SW_W<'_>
[src]
Bit 4 - I2C1 clock source selection
pub fn cecsw(&mut self) -> CECSW_W<'_>
[src]
Bit 6 - HDMI CEC clock source selection
pub fn usbsw(&mut self) -> USBSW_W<'_>
[src]
Bit 7 - USB clock source selection
pub fn adcsw(&mut self) -> ADCSW_W<'_>
[src]
Bit 8 - ADCSW is deprecated. See ADC field in CFGR2 register.
pub fn usart2sw(&mut self) -> USART2SW_W<'_>
[src]
Bits 16:17 - USART2 clock source selection
pub fn usart3sw(&mut self) -> USART3SW_W<'_>
[src]
Bits 18:19 - USART3 clock source
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn hsi14on(&mut self) -> HSI14ON_W<'_>
[src]
Bit 0 - HSI14 clock enable
pub fn hsi14dis(&mut self) -> HSI14DIS_W<'_>
[src]
Bit 2 - HSI14 clock request from ADC disable
pub fn hsi14trim(&mut self) -> HSI14TRIM_W<'_>
[src]
Bits 3:7 - HSI14 clock trimming
pub fn hsi48on(&mut self) -> HSI48ON_W<'_>
[src]
Bit 16 - HSI48 clock enable
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>
[src]
Bits 0:1 - Memory mapping selection bits
pub fn adc_dma_rmp(&mut self) -> ADC_DMA_RMP_W<'_>
[src]
Bit 8 - ADC DMA remapping bit
pub fn usart1_tx_dma_rmp(&mut self) -> USART1_TX_DMA_RMP_W<'_>
[src]
Bit 9 - USART1_TX DMA remapping bit
pub fn usart1_rx_dma_rmp(&mut self) -> USART1_RX_DMA_RMP_W<'_>
[src]
Bit 10 - USART1_RX DMA request remapping bit
pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<'_>
[src]
Bit 11 - TIM16 DMA request remapping bit
pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<'_>
[src]
Bit 12 - TIM17 DMA request remapping bit
pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>
[src]
Bit 16 - Fast Mode Plus (FM plus) driving capability activation bits.
pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>
[src]
Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>
[src]
Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>
[src]
Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>
[src]
Bit 20 - FM+ driving capability activation for I2C1
pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>
[src]
Bit 21 - FM+ driving capability activation for I2C2
pub fn spi2_dma_rmp(&mut self) -> SPI2_DMA_RMP_W<'_>
[src]
Bit 24 - SPI2 DMA request remapping bit
pub fn usart2_dma_rmp(&mut self) -> USART2_DMA_RMP_W<'_>
[src]
Bit 25 - USART2 DMA request remapping bit
pub fn usart3_dma_rmp(&mut self) -> USART3_DMA_RMP_W<'_>
[src]
Bit 26 - USART3 DMA request remapping bit
pub fn i2c1_dma_rmp(&mut self) -> I2C1_DMA_RMP_W<'_>
[src]
Bit 27 - I2C1 DMA request remapping bit
pub fn tim1_dma_rmp(&mut self) -> TIM1_DMA_RMP_W<'_>
[src]
Bit 28 - TIM1 DMA request remapping bit
pub fn tim2_dma_rmp(&mut self) -> TIM2_DMA_RMP_W<'_>
[src]
Bit 29 - TIM2 DMA request remapping bit
pub fn tim3_dma_rmp(&mut self) -> TIM3_DMA_RMP_W<'_>
[src]
Bit 30 - TIM3 DMA request remapping bit
pub fn ir_mod(&mut self) -> IR_MOD_W<'_>
[src]
Bits 6:7 - IR Modulation Envelope signal selection
pub fn tim16_dma_rmp2(&mut self) -> TIM16_DMA_RMP2_W<'_>
[src]
Bit 13 - TIM16 alternate DMA request remapping bit
pub fn tim17_dma_rmp2(&mut self) -> TIM17_DMA_RMP2_W<'_>
[src]
Bit 14 - TIM17 alternate DMA request remapping bit
pub fn pa11_pa12_rmp(&mut self) -> PA11_PA12_RMP_W<'_>
[src]
Bit 4 - PA11 and PA12 remapping bit for small packages (28 and 20 pins)
pub fn i2c_pa9_fmp(&mut self) -> I2C_PA9_FMP_W<'_>
[src]
Bit 22 - Fast Mode Plus (FM+) driving capability activation bits
pub fn i2c_pa10_fmp(&mut self) -> I2C_PA10_FMP_W<'_>
[src]
Bit 23 - Fast Mode Plus (FM+) driving capability activation bits
impl W<u32, Reg<u32, _EXTICR1>>
[src]
pub fn exti3(&mut self) -> EXTI3_W<'_>
[src]
Bits 12:15 - EXTI 3 configuration bits
pub fn exti2(&mut self) -> EXTI2_W<'_>
[src]
Bits 8:11 - EXTI 2 configuration bits
pub fn exti1(&mut self) -> EXTI1_W<'_>
[src]
Bits 4:7 - EXTI 1 configuration bits
pub fn exti0(&mut self) -> EXTI0_W<'_>
[src]
Bits 0:3 - EXTI 0 configuration bits
impl W<u32, Reg<u32, _EXTICR2>>
[src]
pub fn exti7(&mut self) -> EXTI7_W<'_>
[src]
Bits 12:15 - EXTI 7 configuration bits
pub fn exti6(&mut self) -> EXTI6_W<'_>
[src]
Bits 8:11 - EXTI 6 configuration bits
pub fn exti5(&mut self) -> EXTI5_W<'_>
[src]
Bits 4:7 - EXTI 5 configuration bits
pub fn exti4(&mut self) -> EXTI4_W<'_>
[src]
Bits 0:3 - EXTI 4 configuration bits
impl W<u32, Reg<u32, _EXTICR3>>
[src]
pub fn exti11(&mut self) -> EXTI11_W<'_>
[src]
Bits 12:15 - EXTI 11 configuration bits
pub fn exti10(&mut self) -> EXTI10_W<'_>
[src]
Bits 8:11 - EXTI 10 configuration bits
pub fn exti9(&mut self) -> EXTI9_W<'_>
[src]
Bits 4:7 - EXTI 9 configuration bits
pub fn exti8(&mut self) -> EXTI8_W<'_>
[src]
Bits 0:3 - EXTI 8 configuration bits
impl W<u32, Reg<u32, _EXTICR4>>
[src]
pub fn exti15(&mut self) -> EXTI15_W<'_>
[src]
Bits 12:15 - EXTI 15 configuration bits
pub fn exti14(&mut self) -> EXTI14_W<'_>
[src]
Bits 8:11 - EXTI 14 configuration bits
pub fn exti13(&mut self) -> EXTI13_W<'_>
[src]
Bits 4:7 - EXTI 13 configuration bits
pub fn exti12(&mut self) -> EXTI12_W<'_>
[src]
Bits 0:3 - EXTI 12 configuration bits
impl W<u32, Reg<u32, _CFGR2>>
[src]
pub fn sram_pef(&mut self) -> SRAM_PEF_W<'_>
[src]
Bit 8 - SRAM parity flag
pub fn pvd_lock(&mut self) -> PVD_LOCK_W<'_>
[src]
Bit 2 - PVD lock enable bit
pub fn sram_parity_lock(&mut self) -> SRAM_PARITY_LOCK_W<'_>
[src]
Bit 1 - SRAM parity lock bit
pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<'_>
[src]
Bit 0 - Cortex-M0 LOCKUP bit enable bit
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn awd(&mut self) -> AWD_W<'_>
[src]
Bit 7 - Analog watchdog flag
pub fn ovr(&mut self) -> OVR_W<'_>
[src]
Bit 4 - ADC overrun
pub fn eoseq(&mut self) -> EOSEQ_W<'_>
[src]
Bit 3 - End of sequence flag
pub fn eoc(&mut self) -> EOC_W<'_>
[src]
Bit 2 - End of conversion flag
pub fn eosmp(&mut self) -> EOSMP_W<'_>
[src]
Bit 1 - End of sampling flag
pub fn adrdy(&mut self) -> ADRDY_W<'_>
[src]
Bit 0 - ADC ready
impl W<u32, Reg<u32, _IER>>
[src]
pub fn awdie(&mut self) -> AWDIE_W<'_>
[src]
Bit 7 - Analog watchdog interrupt enable
pub fn ovrie(&mut self) -> OVRIE_W<'_>
[src]
Bit 4 - Overrun interrupt enable
pub fn eoseqie(&mut self) -> EOSEQIE_W<'_>
[src]
Bit 3 - End of conversion sequence interrupt enable
pub fn eocie(&mut self) -> EOCIE_W<'_>
[src]
Bit 2 - End of conversion interrupt enable
pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>
[src]
Bit 1 - End of sampling flag interrupt enable
pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>
[src]
Bit 0 - ADC ready interrupt enable
impl W<u32, Reg<u32, _CR>>
[src]
pub fn adcal(&mut self) -> ADCAL_W<'_>
[src]
Bit 31 - ADC calibration
pub fn adstp(&mut self) -> ADSTP_W<'_>
[src]
Bit 4 - ADC stop conversion command
pub fn adstart(&mut self) -> ADSTART_W<'_>
[src]
Bit 2 - ADC start conversion command
pub fn addis(&mut self) -> ADDIS_W<'_>
[src]
Bit 1 - ADC disable command
pub fn aden(&mut self) -> ADEN_W<'_>
[src]
Bit 0 - ADC enable command
impl W<u32, Reg<u32, _CFGR1>>
[src]
pub fn awdch(&mut self) -> AWDCH_W<'_>
[src]
Bits 26:30 - Analog watchdog channel selection
pub fn awden(&mut self) -> AWDEN_W<'_>
[src]
Bit 23 - Analog watchdog enable
pub fn awdsgl(&mut self) -> AWDSGL_W<'_>
[src]
Bit 22 - Enable the watchdog on a single channel or on all channels
pub fn discen(&mut self) -> DISCEN_W<'_>
[src]
Bit 16 - Discontinuous mode
pub fn autoff(&mut self) -> AUTOFF_W<'_>
[src]
Bit 15 - Auto-off mode
pub fn autdly(&mut self) -> AUTDLY_W<'_>
[src]
Bit 14 - Auto-delayed conversion mode
pub fn cont(&mut self) -> CONT_W<'_>
[src]
Bit 13 - Single / continuous conversion mode
pub fn ovrmod(&mut self) -> OVRMOD_W<'_>
[src]
Bit 12 - Overrun management mode
pub fn exten(&mut self) -> EXTEN_W<'_>
[src]
Bits 10:11 - External trigger enable and polarity selection
pub fn extsel(&mut self) -> EXTSEL_W<'_>
[src]
Bits 6:8 - External trigger selection
pub fn align(&mut self) -> ALIGN_W<'_>
[src]
Bit 5 - Data alignment
pub fn res(&mut self) -> RES_W<'_>
[src]
Bits 3:4 - Data resolution
pub fn scandir(&mut self) -> SCANDIR_W<'_>
[src]
Bit 2 - Scan sequence direction
pub fn dmacfg(&mut self) -> DMACFG_W<'_>
[src]
Bit 1 - Direct memery access configuration
pub fn dmaen(&mut self) -> DMAEN_W<'_>
[src]
Bit 0 - Direct memory access enable
pub fn wait(&mut self) -> WAIT_W<'_>
[src]
Bit 14 - Wait conversion mode
impl W<u32, Reg<u32, _CFGR2>>
[src]
impl W<u32, Reg<u32, _SMPR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 16:27 - Analog watchdog higher threshold
pub fn lt(&mut self) -> LT_W<'_>
[src]
Bits 0:11 - Analog watchdog lower threshold
impl W<u32, Reg<u32, _CHSELR>>
[src]
pub fn chsel18(&mut self) -> CHSEL18_W<'_>
[src]
Bit 18 - Channel-x selection
pub fn chsel17(&mut self) -> CHSEL17_W<'_>
[src]
Bit 17 - Channel-x selection
pub fn chsel16(&mut self) -> CHSEL16_W<'_>
[src]
Bit 16 - Channel-x selection
pub fn chsel15(&mut self) -> CHSEL15_W<'_>
[src]
Bit 15 - Channel-x selection
pub fn chsel14(&mut self) -> CHSEL14_W<'_>
[src]
Bit 14 - Channel-x selection
pub fn chsel13(&mut self) -> CHSEL13_W<'_>
[src]
Bit 13 - Channel-x selection
pub fn chsel12(&mut self) -> CHSEL12_W<'_>
[src]
Bit 12 - Channel-x selection
pub fn chsel11(&mut self) -> CHSEL11_W<'_>
[src]
Bit 11 - Channel-x selection
pub fn chsel10(&mut self) -> CHSEL10_W<'_>
[src]
Bit 10 - Channel-x selection
pub fn chsel9(&mut self) -> CHSEL9_W<'_>
[src]
Bit 9 - Channel-x selection
pub fn chsel8(&mut self) -> CHSEL8_W<'_>
[src]
Bit 8 - Channel-x selection
pub fn chsel7(&mut self) -> CHSEL7_W<'_>
[src]
Bit 7 - Channel-x selection
pub fn chsel6(&mut self) -> CHSEL6_W<'_>
[src]
Bit 6 - Channel-x selection
pub fn chsel5(&mut self) -> CHSEL5_W<'_>
[src]
Bit 5 - Channel-x selection
pub fn chsel4(&mut self) -> CHSEL4_W<'_>
[src]
Bit 4 - Channel-x selection
pub fn chsel3(&mut self) -> CHSEL3_W<'_>
[src]
Bit 3 - Channel-x selection
pub fn chsel2(&mut self) -> CHSEL2_W<'_>
[src]
Bit 2 - Channel-x selection
pub fn chsel1(&mut self) -> CHSEL1_W<'_>
[src]
Bit 1 - Channel-x selection
pub fn chsel0(&mut self) -> CHSEL0_W<'_>
[src]
Bit 0 - Channel-x selection
impl W<u32, Reg<u32, _CCR>>
[src]
pub fn vbaten(&mut self) -> VBATEN_W<'_>
[src]
Bit 24 - VBAT enable
pub fn tsen(&mut self) -> TSEN_W<'_>
[src]
Bit 23 - Temperature sensor enable
pub fn vrefen(&mut self) -> VREFEN_W<'_>
[src]
Bit 22 - Temperature sensor and VREFINT enable
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ue(&mut self) -> UE_W<'_>
[src]
Bit 0 - USART enable
pub fn uesm(&mut self) -> UESM_W<'_>
[src]
Bit 1 - USART enable in Stop mode
pub fn re(&mut self) -> RE_W<'_>
[src]
Bit 2 - Receiver enable
pub fn te(&mut self) -> TE_W<'_>
[src]
Bit 3 - Transmitter enable
pub fn idleie(&mut self) -> IDLEIE_W<'_>
[src]
Bit 4 - IDLE interrupt enable
pub fn rxneie(&mut self) -> RXNEIE_W<'_>
[src]
Bit 5 - RXNE interrupt enable
pub fn tcie(&mut self) -> TCIE_W<'_>
[src]
Bit 6 - Transmission complete interrupt enable
pub fn txeie(&mut self) -> TXEIE_W<'_>
[src]
Bit 7 - interrupt enable
pub fn peie(&mut self) -> PEIE_W<'_>
[src]
Bit 8 - PE interrupt enable
pub fn ps(&mut self) -> PS_W<'_>
[src]
Bit 9 - Parity selection
pub fn pce(&mut self) -> PCE_W<'_>
[src]
Bit 10 - Parity control enable
pub fn wake(&mut self) -> WAKE_W<'_>
[src]
Bit 11 - Receiver wakeup method
pub fn m0(&mut self) -> M0_W<'_>
[src]
Bit 12 - Word length
pub fn mme(&mut self) -> MME_W<'_>
[src]
Bit 13 - Mute mode enable
pub fn cmie(&mut self) -> CMIE_W<'_>
[src]
Bit 14 - Character match interrupt enable
pub fn over8(&mut self) -> OVER8_W<'_>
[src]
Bit 15 - Oversampling mode
pub fn dedt(&mut self) -> DEDT_W<'_>
[src]
Bits 16:20 - Driver Enable deassertion time
pub fn deat(&mut self) -> DEAT_W<'_>
[src]
Bits 21:25 - Driver Enable assertion time
pub fn rtoie(&mut self) -> RTOIE_W<'_>
[src]
Bit 26 - Receiver timeout interrupt enable
pub fn eobie(&mut self) -> EOBIE_W<'_>
[src]
Bit 27 - End of Block interrupt enable
pub fn m1(&mut self) -> M1_W<'_>
[src]
Bit 28 - Word length
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn rtoen(&mut self) -> RTOEN_W<'_>
[src]
Bit 23 - Receiver timeout enable
pub fn abrmod(&mut self) -> ABRMOD_W<'_>
[src]
Bits 21:22 - Auto baud rate mode
pub fn abren(&mut self) -> ABREN_W<'_>
[src]
Bit 20 - Auto baud rate enable
pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>
[src]
Bit 19 - Most significant bit first
pub fn datainv(&mut self) -> DATAINV_W<'_>
[src]
Bit 18 - Binary data inversion
pub fn txinv(&mut self) -> TXINV_W<'_>
[src]
Bit 17 - TX pin active level inversion
pub fn rxinv(&mut self) -> RXINV_W<'_>
[src]
Bit 16 - RX pin active level inversion
pub fn swap(&mut self) -> SWAP_W<'_>
[src]
Bit 15 - Swap TX/RX pins
pub fn linen(&mut self) -> LINEN_W<'_>
[src]
Bit 14 - LIN mode enable
pub fn stop(&mut self) -> STOP_W<'_>
[src]
Bits 12:13 - STOP bits
pub fn clken(&mut self) -> CLKEN_W<'_>
[src]
Bit 11 - Clock enable
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 10 - Clock polarity
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 9 - Clock phase
pub fn lbcl(&mut self) -> LBCL_W<'_>
[src]
Bit 8 - Last bit clock pulse
pub fn lbdie(&mut self) -> LBDIE_W<'_>
[src]
Bit 6 - LIN break detection interrupt enable
pub fn lbdl(&mut self) -> LBDL_W<'_>
[src]
Bit 5 - LIN break detection length
pub fn addm7(&mut self) -> ADDM7_W<'_>
[src]
Bit 4 - 7-bit Address Detection/4-bit Address Detection
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 24:31 - Address of the USART node
impl W<u32, Reg<u32, _CR3>>
[src]
pub fn wufie(&mut self) -> WUFIE_W<'_>
[src]
Bit 22 - Wakeup from Stop mode interrupt enable
pub fn wus(&mut self) -> WUS_W<'_>
[src]
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
pub fn scarcnt(&mut self) -> SCARCNT_W<'_>
[src]
Bits 17:19 - Smartcard auto-retry count
pub fn dep(&mut self) -> DEP_W<'_>
[src]
Bit 15 - Driver enable polarity selection
pub fn dem(&mut self) -> DEM_W<'_>
[src]
Bit 14 - Driver enable mode
pub fn ddre(&mut self) -> DDRE_W<'_>
[src]
Bit 13 - DMA Disable on Reception Error
pub fn ovrdis(&mut self) -> OVRDIS_W<'_>
[src]
Bit 12 - Overrun Disable
pub fn onebit(&mut self) -> ONEBIT_W<'_>
[src]
Bit 11 - One sample bit method enable
pub fn ctsie(&mut self) -> CTSIE_W<'_>
[src]
Bit 10 - CTS interrupt enable
pub fn ctse(&mut self) -> CTSE_W<'_>
[src]
Bit 9 - CTS enable
pub fn rtse(&mut self) -> RTSE_W<'_>
[src]
Bit 8 - RTS enable
pub fn dmat(&mut self) -> DMAT_W<'_>
[src]
Bit 7 - DMA enable transmitter
pub fn dmar(&mut self) -> DMAR_W<'_>
[src]
Bit 6 - DMA enable receiver
pub fn scen(&mut self) -> SCEN_W<'_>
[src]
Bit 5 - Smartcard mode enable
pub fn nack(&mut self) -> NACK_W<'_>
[src]
Bit 4 - Smartcard NACK enable
pub fn hdsel(&mut self) -> HDSEL_W<'_>
[src]
Bit 3 - Half-duplex selection
pub fn irlp(&mut self) -> IRLP_W<'_>
[src]
Bit 2 - IrDA low-power
pub fn iren(&mut self) -> IREN_W<'_>
[src]
Bit 1 - IrDA mode enable
pub fn eie(&mut self) -> EIE_W<'_>
[src]
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
[src]
impl W<u32, Reg<u32, _GTPR>>
[src]
pub fn gt(&mut self) -> GT_W<'_>
[src]
Bits 8:15 - Guard time value
pub fn psc(&mut self) -> PSC_W<'_>
[src]
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
[src]
pub fn blen(&mut self) -> BLEN_W<'_>
[src]
Bits 24:31 - Block Length
pub fn rto(&mut self) -> RTO_W<'_>
[src]
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
[src]
pub fn txfrq(&mut self) -> TXFRQ_W<'_>
[src]
Bit 4 - Transmit data flush request
pub fn rxfrq(&mut self) -> RXFRQ_W<'_>
[src]
Bit 3 - Receive data flush request
pub fn mmrq(&mut self) -> MMRQ_W<'_>
[src]
Bit 2 - Mute mode request
pub fn sbkrq(&mut self) -> SBKRQ_W<'_>
[src]
Bit 1 - Send break request
pub fn abrrq(&mut self) -> ABRRQ_W<'_>
[src]
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn wucf(&mut self) -> WUCF_W<'_>
[src]
Bit 20 - Wakeup from Stop mode clear flag
pub fn cmcf(&mut self) -> CMCF_W<'_>
[src]
Bit 17 - Character match clear flag
pub fn eobcf(&mut self) -> EOBCF_W<'_>
[src]
Bit 12 - End of timeout clear flag
pub fn rtocf(&mut self) -> RTOCF_W<'_>
[src]
Bit 11 - Receiver timeout clear flag
pub fn ctscf(&mut self) -> CTSCF_W<'_>
[src]
Bit 9 - CTS clear flag
pub fn lbdcf(&mut self) -> LBDCF_W<'_>
[src]
Bit 8 - LIN break detection clear flag
pub fn tccf(&mut self) -> TCCF_W<'_>
[src]
Bit 6 - Transmission complete clear flag
pub fn idlecf(&mut self) -> IDLECF_W<'_>
[src]
Bit 4 - Idle line detected clear flag
pub fn orecf(&mut self) -> ORECF_W<'_>
[src]
Bit 3 - Overrun error clear flag
pub fn ncf(&mut self) -> NCF_W<'_>
[src]
Bit 2 - Noise detected clear flag
pub fn fecf(&mut self) -> FECF_W<'_>
[src]
Bit 1 - Framing error clear flag
pub fn pecf(&mut self) -> PECF_W<'_>
[src]
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
[src]
impl W<u32, Reg<u32, _TR>>
[src]
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _DR>>
[src]
pub fn yt(&mut self) -> YT_W<'_>
[src]
Bits 20:23 - Year tens in BCD format
pub fn yu(&mut self) -> YU_W<'_>
[src]
Bits 16:19 - Year units in BCD format
pub fn wdu(&mut self) -> WDU_W<'_>
[src]
Bits 13:15 - Week day units
pub fn mt(&mut self) -> MT_W<'_>
[src]
Bit 12 - Month tens in BCD format
pub fn mu(&mut self) -> MU_W<'_>
[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 0:3 - Date units in BCD format
impl W<u32, Reg<u32, _CR>>
[src]
pub fn wucksel(&mut self) -> WUCKSEL_W<'_>
[src]
Bits 0:2 - Wakeup clock selection
pub fn tsedge(&mut self) -> TSEDGE_W<'_>
[src]
Bit 3 - Time-stamp event active edge
pub fn refckon(&mut self) -> REFCKON_W<'_>
[src]
Bit 4 - RTC_REFIN reference clock detection enable (50 or 60 Hz)
pub fn bypshad(&mut self) -> BYPSHAD_W<'_>
[src]
Bit 5 - Bypass the shadow registers
pub fn fmt(&mut self) -> FMT_W<'_>
[src]
Bit 6 - Hour format
pub fn alrae(&mut self) -> ALRAE_W<'_>
[src]
Bit 8 - Alarm A enable
pub fn wute(&mut self) -> WUTE_W<'_>
[src]
Bit 10 - Wakeup timer enable
pub fn tse(&mut self) -> TSE_W<'_>
[src]
Bit 11 - timestamp enable
pub fn alraie(&mut self) -> ALRAIE_W<'_>
[src]
Bit 12 - Alarm A interrupt enable
pub fn wutie(&mut self) -> WUTIE_W<'_>
[src]
Bit 14 - Wakeup timer interrupt enable
pub fn tsie(&mut self) -> TSIE_W<'_>
[src]
Bit 15 - Time-stamp interrupt enable
pub fn add1h(&mut self) -> ADD1H_W<'_>
[src]
Bit 16 - Add 1 hour (summer time change)
pub fn sub1h(&mut self) -> SUB1H_W<'_>
[src]
Bit 17 - Subtract 1 hour (winter time change)
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 18 - Backup
pub fn cosel(&mut self) -> COSEL_W<'_>
[src]
Bit 19 - Calibration output selection
pub fn pol(&mut self) -> POL_W<'_>
[src]
Bit 20 - Output polarity
pub fn osel(&mut self) -> OSEL_W<'_>
[src]
Bits 21:22 - Output selection
pub fn coe(&mut self) -> COE_W<'_>
[src]
Bit 23 - Calibration output enable
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn shpf(&mut self) -> SHPF_W<'_>
[src]
Bit 3 - Shift operation pending
pub fn rsf(&mut self) -> RSF_W<'_>
[src]
Bit 5 - Registers synchronization flag
pub fn init(&mut self) -> INIT_W<'_>
[src]
Bit 7 - Initialization mode
pub fn alraf(&mut self) -> ALRAF_W<'_>
[src]
Bit 8 - Alarm A flag
pub fn wutf(&mut self) -> WUTF_W<'_>
[src]
Bit 10 - Wakeup timer flag
pub fn tsf(&mut self) -> TSF_W<'_>
[src]
Bit 11 - Time-stamp flag
pub fn tsovf(&mut self) -> TSOVF_W<'_>
[src]
Bit 12 - Time-stamp overflow flag
pub fn tamp1f(&mut self) -> TAMP1F_W<'_>
[src]
Bit 13 - RTC_TAMP1 detection flag
pub fn tamp2f(&mut self) -> TAMP2F_W<'_>
[src]
Bit 14 - RTC_TAMP2 detection flag
pub fn tamp3f(&mut self) -> TAMP3F_W<'_>
[src]
Bit 15 - RTC_TAMP3 detection flag
impl W<u32, Reg<u32, _PRER>>
[src]
pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>
[src]
Bits 16:22 - Asynchronous prescaler factor
pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>
[src]
Bits 0:14 - Synchronous prescaler factor
impl W<u32, Reg<u32, _ALRMAR>>
[src]
pub fn msk4(&mut self) -> MSK4_W<'_>
[src]
Bit 31 - Alarm A date mask
pub fn wdsel(&mut self) -> WDSEL_W<'_>
[src]
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
[src]
Bits 28:29 - Date tens in BCD format.
pub fn du(&mut self) -> DU_W<'_>
[src]
Bits 24:27 - Date units or day in BCD format.
pub fn msk3(&mut self) -> MSK3_W<'_>
[src]
Bit 23 - Alarm A hours mask
pub fn pm(&mut self) -> PM_W<'_>
[src]
Bit 22 - AM/PM notation
pub fn ht(&mut self) -> HT_W<'_>
[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&mut self) -> HU_W<'_>
[src]
Bits 16:19 - Hour units in BCD format.
pub fn msk2(&mut self) -> MSK2_W<'_>
[src]
Bit 15 - Alarm A minutes mask
pub fn mnt(&mut self) -> MNT_W<'_>
[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&mut self) -> MNU_W<'_>
[src]
Bits 8:11 - Minute units in BCD format.
pub fn msk1(&mut self) -> MSK1_W<'_>
[src]
Bit 7 - Alarm A seconds mask
pub fn st(&mut self) -> ST_W<'_>
[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&mut self) -> SU_W<'_>
[src]
Bits 0:3 - Second units in BCD format.
impl W<u32, Reg<u32, _WPR>>
[src]
impl W<u32, Reg<u32, _SHIFTR>>
[src]
pub fn add1s(&mut self) -> ADD1S_W<'_>
[src]
Bit 31 - Add one second
pub fn subfs(&mut self) -> SUBFS_W<'_>
[src]
Bits 0:14 - Subtract a fraction of a second
impl W<u32, Reg<u32, _CALR>>
[src]
pub fn calp(&mut self) -> CALP_W<'_>
[src]
Bit 15 - Increase frequency of RTC by 488.5 ppm
pub fn calw8(&mut self) -> CALW8_W<'_>
[src]
Bit 14 - Use an 8-second calibration cycle period
pub fn calw16(&mut self) -> CALW16_W<'_>
[src]
Bit 13 - Use a 16-second calibration cycle period
pub fn calm(&mut self) -> CALM_W<'_>
[src]
Bits 0:8 - Calibration minus
impl W<u32, Reg<u32, _TAFCR>>
[src]
pub fn pc15mode(&mut self) -> PC15MODE_W<'_>
[src]
Bit 23 - PC15 mode
pub fn pc15value(&mut self) -> PC15VALUE_W<'_>
[src]
Bit 22 - PC15 value
pub fn pc14mode(&mut self) -> PC14MODE_W<'_>
[src]
Bit 21 - PC14 mode
pub fn pc14value(&mut self) -> PC14VALUE_W<'_>
[src]
Bit 20 - PC14 value
pub fn pc13mode(&mut self) -> PC13MODE_W<'_>
[src]
Bit 19 - PC13 mode
pub fn pc13value(&mut self) -> PC13VALUE_W<'_>
[src]
Bit 18 - RTC_ALARM output type/PC13 value
pub fn tamp_pudis(&mut self) -> TAMP_PUDIS_W<'_>
[src]
Bit 15 - RTC_TAMPx pull-up disable
pub fn tamp_prch(&mut self) -> TAMP_PRCH_W<'_>
[src]
Bits 13:14 - RTC_TAMPx precharge duration
pub fn tampflt(&mut self) -> TAMPFLT_W<'_>
[src]
Bits 11:12 - RTC_TAMPx filter count
pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>
[src]
Bits 8:10 - Tamper sampling frequency
pub fn tampts(&mut self) -> TAMPTS_W<'_>
[src]
Bit 7 - Activate timestamp on tamper detection event
pub fn tamp3trg(&mut self) -> TAMP3TRG_W<'_>
[src]
Bit 6 - Active level for RTC_TAMP3 input
pub fn tamp3e(&mut self) -> TAMP3E_W<'_>
[src]
Bit 5 - RTC_TAMP3 detection enable
pub fn tamp2_trg(&mut self) -> TAMP2_TRG_W<'_>
[src]
Bit 4 - Active level for RTC_TAMP2 input
pub fn tamp2e(&mut self) -> TAMP2E_W<'_>
[src]
Bit 3 - RTC_TAMP2 input detection enable
pub fn tampie(&mut self) -> TAMPIE_W<'_>
[src]
Bit 2 - Tamper interrupt enable
pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>
[src]
Bit 1 - Active level for RTC_TAMP1 input
pub fn tamp1e(&mut self) -> TAMP1E_W<'_>
[src]
Bit 0 - RTC_TAMP1 input detection enable
impl W<u32, Reg<u32, _ALRMASSR>>
[src]
pub fn maskss(&mut self) -> MASKSS_W<'_>
[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
[src]
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _BKPR>>
[src]
impl W<u32, Reg<u32, _WUTR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois2(&mut self) -> OIS2_W<'_>
[src]
Bit 10 - Output Idle state 2
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output Compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output Compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output Compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic2f(&mut self) -> IC2F_W<'_>
[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc2np(&mut self) -> CC2NP_W<'_>
[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _CCR2>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ois1n(&mut self) -> OIS1N_W<'_>
[src]
Bit 9 - Output Idle state 1
pub fn ois1(&mut self) -> OIS1_W<'_>
[src]
Bit 8 - Output Idle state 1
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
pub fn ccus(&mut self) -> CCUS_W<'_>
[src]
Bit 2 - Capture/compare control update selection
pub fn ccpc(&mut self) -> CCPC_W<'_>
[src]
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn bie(&mut self) -> BIE_W<'_>
[src]
Bit 7 - Break interrupt enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn comie(&mut self) -> COMIE_W<'_>
[src]
Bit 5 - COM interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn bif(&mut self) -> BIF_W<'_>
[src]
Bit 7 - Break interrupt flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn comif(&mut self) -> COMIF_W<'_>
[src]
Bit 5 - COM interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn bg(&mut self) -> BG_W<'_>
[src]
Bit 7 - Break generation
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn comg(&mut self) -> COMG_W<'_>
[src]
Bit 5 - Capture/Compare control update generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc1m(&mut self) -> OC1M_W<'_>
[src]
Bits 4:6 - Output Compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
[src]
Bit 3 - Output Compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
[src]
Bit 2 - Output Compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
[src]
pub fn ic1f(&mut self) -> IC1F_W<'_>
[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
[src]
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
[src]
pub fn cc1np(&mut self) -> CC1NP_W<'_>
[src]
Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1ne(&mut self) -> CC1NE_W<'_>
[src]
Bit 2 - Capture/Compare 1 complementary output enable
pub fn cc1p(&mut self) -> CC1P_W<'_>
[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
[src]
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _PSC>>
[src]
impl W<u32, Reg<u32, _ARR>>
[src]
impl W<u32, Reg<u32, _RCR>>
[src]
impl W<u32, Reg<u32, _CCR1>>
[src]
impl W<u32, Reg<u32, _BDTR>>
[src]
pub fn moe(&mut self) -> MOE_W<'_>
[src]
Bit 15 - Main output enable
pub fn aoe(&mut self) -> AOE_W<'_>
[src]
Bit 14 - Automatic output enable
pub fn bkp(&mut self) -> BKP_W<'_>
[src]
Bit 13 - Break polarity
pub fn bke(&mut self) -> BKE_W<'_>
[src]
Bit 12 - Break enable
pub fn ossr(&mut self) -> OSSR_W<'_>
[src]
Bit 11 - Off-state selection for Run mode
pub fn ossi(&mut self) -> OSSI_W<'_>
[src]
Bit 10 - Off-state selection for Idle mode
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bits 8:9 - Lock configuration
pub fn dtg(&mut self) -> DTG_W<'_>
[src]
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
[src]
pub fn dbl(&mut self) -> DBL_W<'_>
[src]
Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
[src]
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn ctph(&mut self) -> CTPH_W<'_>
[src]
Bits 28:31 - Charge transfer pulse high
pub fn ctpl(&mut self) -> CTPL_W<'_>
[src]
Bits 24:27 - Charge transfer pulse low
pub fn ssd(&mut self) -> SSD_W<'_>
[src]
Bits 17:23 - Spread spectrum deviation
pub fn sse(&mut self) -> SSE_W<'_>
[src]
Bit 16 - Spread spectrum enable
pub fn sspsc(&mut self) -> SSPSC_W<'_>
[src]
Bit 15 - Spread spectrum prescaler
pub fn pgpsc(&mut self) -> PGPSC_W<'_>
[src]
Bits 12:14 - pulse generator prescaler
pub fn mcv(&mut self) -> MCV_W<'_>
[src]
Bits 5:7 - Max count value
pub fn iodef(&mut self) -> IODEF_W<'_>
[src]
Bit 4 - I/O Default mode
pub fn syncpol(&mut self) -> SYNCPOL_W<'_>
[src]
Bit 3 - Synchronization pin polarity
pub fn am(&mut self) -> AM_W<'_>
[src]
Bit 2 - Acquisition mode
pub fn start(&mut self) -> START_W<'_>
[src]
Bit 1 - Start a new acquisition
pub fn tsce(&mut self) -> TSCE_W<'_>
[src]
Bit 0 - Touch sensing controller enable
impl W<u32, Reg<u32, _IER>>
[src]
pub fn mceie(&mut self) -> MCEIE_W<'_>
[src]
Bit 1 - Max count error interrupt enable
pub fn eoaie(&mut self) -> EOAIE_W<'_>
[src]
Bit 0 - End of acquisition interrupt enable
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn mceic(&mut self) -> MCEIC_W<'_>
[src]
Bit 1 - Max count error interrupt clear
pub fn eoaic(&mut self) -> EOAIC_W<'_>
[src]
Bit 0 - End of acquisition interrupt clear
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn mcef(&mut self) -> MCEF_W<'_>
[src]
Bit 1 - Max count error flag
pub fn eoaf(&mut self) -> EOAF_W<'_>
[src]
Bit 0 - End of acquisition flag
impl W<u32, Reg<u32, _IOHCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
impl W<u32, Reg<u32, _IOASCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 analog switch enable
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 analog switch enable
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 analog switch enable
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 analog switch enable
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 analog switch enable
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 analog switch enable
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 analog switch enable
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 analog switch enable
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 analog switch enable
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 analog switch enable
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 analog switch enable
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 analog switch enable
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 analog switch enable
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 analog switch enable
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 analog switch enable
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 analog switch enable
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 analog switch enable
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 analog switch enable
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 analog switch enable
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 analog switch enable
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 analog switch enable
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 analog switch enable
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 analog switch enable
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 analog switch enable
impl W<u32, Reg<u32, _IOSCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 sampling mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 sampling mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 sampling mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 sampling mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 sampling mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 sampling mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 sampling mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 sampling mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 sampling mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 sampling mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 sampling mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 sampling mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 sampling mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 sampling mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 sampling mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 sampling mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 sampling mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 sampling mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 sampling mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 sampling mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 sampling mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 sampling mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 sampling mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 sampling mode
impl W<u32, Reg<u32, _IOCCR>>
[src]
pub fn g6_io4(&mut self) -> G6_IO4_W<'_>
[src]
Bit 23 - G6_IO4 channel mode
pub fn g6_io3(&mut self) -> G6_IO3_W<'_>
[src]
Bit 22 - G6_IO3 channel mode
pub fn g6_io2(&mut self) -> G6_IO2_W<'_>
[src]
Bit 21 - G6_IO2 channel mode
pub fn g6_io1(&mut self) -> G6_IO1_W<'_>
[src]
Bit 20 - G6_IO1 channel mode
pub fn g5_io4(&mut self) -> G5_IO4_W<'_>
[src]
Bit 19 - G5_IO4 channel mode
pub fn g5_io3(&mut self) -> G5_IO3_W<'_>
[src]
Bit 18 - G5_IO3 channel mode
pub fn g5_io2(&mut self) -> G5_IO2_W<'_>
[src]
Bit 17 - G5_IO2 channel mode
pub fn g5_io1(&mut self) -> G5_IO1_W<'_>
[src]
Bit 16 - G5_IO1 channel mode
pub fn g4_io4(&mut self) -> G4_IO4_W<'_>
[src]
Bit 15 - G4_IO4 channel mode
pub fn g4_io3(&mut self) -> G4_IO3_W<'_>
[src]
Bit 14 - G4_IO3 channel mode
pub fn g4_io2(&mut self) -> G4_IO2_W<'_>
[src]
Bit 13 - G4_IO2 channel mode
pub fn g4_io1(&mut self) -> G4_IO1_W<'_>
[src]
Bit 12 - G4_IO1 channel mode
pub fn g3_io4(&mut self) -> G3_IO4_W<'_>
[src]
Bit 11 - G3_IO4 channel mode
pub fn g3_io3(&mut self) -> G3_IO3_W<'_>
[src]
Bit 10 - G3_IO3 channel mode
pub fn g3_io2(&mut self) -> G3_IO2_W<'_>
[src]
Bit 9 - G3_IO2 channel mode
pub fn g3_io1(&mut self) -> G3_IO1_W<'_>
[src]
Bit 8 - G3_IO1 channel mode
pub fn g2_io4(&mut self) -> G2_IO4_W<'_>
[src]
Bit 7 - G2_IO4 channel mode
pub fn g2_io3(&mut self) -> G2_IO3_W<'_>
[src]
Bit 6 - G2_IO3 channel mode
pub fn g2_io2(&mut self) -> G2_IO2_W<'_>
[src]
Bit 5 - G2_IO2 channel mode
pub fn g2_io1(&mut self) -> G2_IO1_W<'_>
[src]
Bit 4 - G2_IO1 channel mode
pub fn g1_io4(&mut self) -> G1_IO4_W<'_>
[src]
Bit 3 - G1_IO4 channel mode
pub fn g1_io3(&mut self) -> G1_IO3_W<'_>
[src]
Bit 2 - G1_IO3 channel mode
pub fn g1_io2(&mut self) -> G1_IO2_W<'_>
[src]
Bit 1 - G1_IO2 channel mode
pub fn g1_io1(&mut self) -> G1_IO1_W<'_>
[src]
Bit 0 - G1_IO1 channel mode
impl W<u32, Reg<u32, _IOGCSR>>
[src]
pub fn g8s(&mut self) -> G8S_W<'_>
[src]
Bit 23 - Analog I/O group x status
pub fn g7s(&mut self) -> G7S_W<'_>
[src]
Bit 22 - Analog I/O group x status
pub fn g8e(&mut self) -> G8E_W<'_>
[src]
Bit 7 - Analog I/O group x enable
pub fn g7e(&mut self) -> G7E_W<'_>
[src]
Bit 6 - Analog I/O group x enable
pub fn g6e(&mut self) -> G6E_W<'_>
[src]
Bit 5 - Analog I/O group x enable
pub fn g5e(&mut self) -> G5E_W<'_>
[src]
Bit 4 - Analog I/O group x enable
pub fn g4e(&mut self) -> G4E_W<'_>
[src]
Bit 3 - Analog I/O group x enable
pub fn g3e(&mut self) -> G3E_W<'_>
[src]
Bit 2 - Analog I/O group x enable
pub fn g2e(&mut self) -> G2E_W<'_>
[src]
Bit 1 - Analog I/O group x enable
pub fn g1e(&mut self) -> G1E_W<'_>
[src]
Bit 0 - Analog I/O group x enable
impl W<u32, Reg<u32, _CR>>
[src]
pub fn txeom(&mut self) -> TXEOM_W<'_>
[src]
Bit 2 - Tx End Of Message
pub fn txsom(&mut self) -> TXSOM_W<'_>
[src]
Bit 1 - Tx start of message
pub fn cecen(&mut self) -> CECEN_W<'_>
[src]
Bit 0 - CEC Enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn lbpegen(&mut self) -> LBPEGEN_W<'_>
[src]
Bit 11 - Generate Error-Bit on Long Bit Period Error
pub fn bregen(&mut self) -> BREGEN_W<'_>
[src]
Bit 10 - Generate error-bit on bit rising error
pub fn brestp(&mut self) -> BRESTP_W<'_>
[src]
Bit 9 - Rx-stop on bit rising error
pub fn rxtol(&mut self) -> RXTOL_W<'_>
[src]
Bit 8 - Rx-Tolerance
pub fn sft(&mut self) -> SFT_W<'_>
[src]
Bits 5:7 - Signal Free Time
pub fn lstn(&mut self) -> LSTN_W<'_>
[src]
Bit 4 - Listen mode
pub fn oar(&mut self) -> OAR_W<'_>
[src]
Bits 0:3 - Own Address
impl W<u32, Reg<u32, _TXDR>>
[src]
impl W<u32, Reg<u32, _ISR>>
[src]
pub fn txacke(&mut self) -> TXACKE_W<'_>
[src]
Bit 12 - Tx-Missing acknowledge error
pub fn txerr(&mut self) -> TXERR_W<'_>
[src]
Bit 11 - Tx-Error
pub fn txudr(&mut self) -> TXUDR_W<'_>
[src]
Bit 10 - Tx-Buffer Underrun
pub fn txend(&mut self) -> TXEND_W<'_>
[src]
Bit 9 - End of Transmission
pub fn txbr(&mut self) -> TXBR_W<'_>
[src]
Bit 8 - Tx-Byte Request
pub fn arblst(&mut self) -> ARBLST_W<'_>
[src]
Bit 7 - Arbitration Lost
pub fn rxacke(&mut self) -> RXACKE_W<'_>
[src]
Bit 6 - Rx-Missing Acknowledge
pub fn lbpe(&mut self) -> LBPE_W<'_>
[src]
Bit 5 - Rx-Long Bit Period Error
pub fn sbpe(&mut self) -> SBPE_W<'_>
[src]
Bit 4 - Rx-Short Bit period error
pub fn bre(&mut self) -> BRE_W<'_>
[src]
Bit 3 - Rx-Bit rising error
pub fn rxovr(&mut self) -> RXOVR_W<'_>
[src]
Bit 2 - Rx-Overrun
pub fn rxend(&mut self) -> RXEND_W<'_>
[src]
Bit 1 - End Of Reception
pub fn rxbr(&mut self) -> RXBR_W<'_>
[src]
Bit 0 - Rx-Byte Received
impl W<u32, Reg<u32, _IER>>
[src]
pub fn txackie(&mut self) -> TXACKIE_W<'_>
[src]
Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable
pub fn txerrie(&mut self) -> TXERRIE_W<'_>
[src]
Bit 11 - Tx-Error Interrupt Enable
pub fn txudrie(&mut self) -> TXUDRIE_W<'_>
[src]
Bit 10 - Tx-Underrun interrupt enable
pub fn txendie(&mut self) -> TXENDIE_W<'_>
[src]
Bit 9 - Tx-End of message interrupt enable
pub fn txbrie(&mut self) -> TXBRIE_W<'_>
[src]
Bit 8 - Tx-Byte Request Interrupt Enable
pub fn arblstie(&mut self) -> ARBLSTIE_W<'_>
[src]
Bit 7 - Arbitration Lost Interrupt Enable
pub fn rxackie(&mut self) -> RXACKIE_W<'_>
[src]
Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable
pub fn lbpeie(&mut self) -> LBPEIE_W<'_>
[src]
Bit 5 - Long Bit Period Error Interrupt Enable
pub fn sbpeie(&mut self) -> SBPEIE_W<'_>
[src]
Bit 4 - Short Bit Period Error Interrupt Enable
pub fn breie(&mut self) -> BREIE_W<'_>
[src]
Bit 3 - Bit Rising Error Interrupt Enable
pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>
[src]
Bit 2 - Rx-Buffer Overrun Interrupt Enable
pub fn rxendie(&mut self) -> RXENDIE_W<'_>
[src]
Bit 1 - End Of Reception Interrupt Enable
pub fn rxbrie(&mut self) -> RXBRIE_W<'_>
[src]
Bit 0 - Rx-Byte Received Interrupt Enable
impl W<u32, Reg<u32, _ACR>>
[src]
pub fn latency(&mut self) -> LATENCY_W<'_>
[src]
Bits 0:2 - LATENCY
pub fn prftbe(&mut self) -> PRFTBE_W<'_>
[src]
Bit 4 - PRFTBE
impl W<u32, Reg<u32, _KEYR>>
[src]
impl W<u32, Reg<u32, _OPTKEYR>>
[src]
impl W<u32, Reg<u32, _SR>>
[src]
pub fn eop(&mut self) -> EOP_W<'_>
[src]
Bit 5 - End of operation
pub fn wrprt(&mut self) -> WRPRT_W<'_>
[src]
Bit 4 - Write protection error
pub fn pgerr(&mut self) -> PGERR_W<'_>
[src]
Bit 2 - Programming error
impl W<u32, Reg<u32, _CR>>
[src]
pub fn force_optload(&mut self) -> FORCE_OPTLOAD_W<'_>
[src]
Bit 13 - Force option byte loading
pub fn eopie(&mut self) -> EOPIE_W<'_>
[src]
Bit 12 - End of operation interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 10 - Error interrupt enable
pub fn optwre(&mut self) -> OPTWRE_W<'_>
[src]
Bit 9 - Option bytes write enable
pub fn lock(&mut self) -> LOCK_W<'_>
[src]
Bit 7 - Lock
pub fn strt(&mut self) -> STRT_W<'_>
[src]
Bit 6 - Start
pub fn opter(&mut self) -> OPTER_W<'_>
[src]
Bit 5 - Option byte erase
pub fn optpg(&mut self) -> OPTPG_W<'_>
[src]
Bit 4 - Option byte programming
pub fn mer(&mut self) -> MER_W<'_>
[src]
Bit 2 - Mass erase
pub fn per(&mut self) -> PER_W<'_>
[src]
Bit 1 - Page erase
pub fn pg(&mut self) -> PG_W<'_>
[src]
Bit 0 - Programming
impl W<u32, Reg<u32, _AR>>
[src]
impl W<u32, Reg<u32, _CR>>
[src]
pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>
[src]
Bit 1 - Debug Stop Mode
pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>
[src]
Bit 2 - Debug Standby Mode
impl W<u32, Reg<u32, _APB1_FZ>>
[src]
pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>
[src]
Bit 0 - TIM2 counter stopped when core is halted
pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>
[src]
Bit 1 - TIM3 counter stopped when core is halted
pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>
[src]
Bit 4 - TIM6 counter stopped when core is halted
pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>
[src]
Bit 5 - TIM7 counter stopped when core is halted
pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>
[src]
Bit 8 - TIM14 counter stopped when core is halted
pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>
[src]
Bit 10 - Debug RTC stopped when core is halted
pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>
[src]
Bit 11 - Debug window watchdog stopped when core is halted
pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>
[src]
Bit 12 - Debug independent watchdog stopped when core is halted
pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>
[src]
Bit 21 - SMBUS timeout mode stopped when core is halted
pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>
[src]
Bit 25 - CAN stopped when core is halted
impl W<u32, Reg<u32, _APB2_FZ>>
[src]
pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>
[src]
Bit 11 - TIM1 counter stopped when core is halted
pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>
[src]
Bit 16 - TIM15 counter stopped when core is halted
pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>
[src]
Bit 17 - TIM16 counter stopped when core is halted
pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>
[src]
Bit 18 - TIM17 counter stopped when core is halted
impl W<u32, Reg<u32, _EP0R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP1R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP2R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP3R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP4R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP5R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP6R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP7R>>
[src]
pub fn ea(&mut self) -> EA_W<'_>
[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&mut self) -> STAT_TX_W<'_>
[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>
[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>
[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&mut self) -> EP_KIND_W<'_>
[src]
Bit 8 - Endpoint kind
pub fn ep_type(&mut self) -> EP_TYPE_W<'_>
[src]
Bits 9:10 - Endpoint type
pub fn setup(&mut self) -> SETUP_W<'_>
[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&mut self) -> STAT_RX_W<'_>
[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>
[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>
[src]
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _CNTR>>
[src]
pub fn fres(&mut self) -> FRES_W<'_>
[src]
Bit 0 - Force USB Reset
pub fn pdwn(&mut self) -> PDWN_W<'_>
[src]
Bit 1 - Power down
pub fn lpmode(&mut self) -> LPMODE_W<'_>
[src]
Bit 2 - Low-power mode
pub fn fsusp(&mut self) -> FSUSP_W<'_>
[src]
Bit 3 - Force suspend
pub fn resume(&mut self) -> RESUME_W<'_>
[src]
Bit 4 - Resume request
pub fn l1resume(&mut self) -> L1RESUME_W<'_>
[src]
Bit 5 - LPM L1 Resume request
pub fn l1reqm(&mut self) -> L1REQM_W<'_>
[src]
Bit 7 - LPM L1 state request interrupt mask
pub fn esofm(&mut self) -> ESOFM_W<'_>
[src]
Bit 8 - Expected start of frame interrupt mask
pub fn sofm(&mut self) -> SOFM_W<'_>
[src]
Bit 9 - Start of frame interrupt mask
pub fn resetm(&mut self) -> RESETM_W<'_>
[src]
Bit 10 - USB reset interrupt mask
pub fn suspm(&mut self) -> SUSPM_W<'_>
[src]
Bit 11 - Suspend mode interrupt mask
pub fn wkupm(&mut self) -> WKUPM_W<'_>
[src]
Bit 12 - Wakeup interrupt mask
pub fn errm(&mut self) -> ERRM_W<'_>
[src]
Bit 13 - Error interrupt mask
pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>
[src]
Bit 14 - Packet memory area over / underrun interrupt mask
pub fn ctrm(&mut self) -> CTRM_W<'_>
[src]
Bit 15 - Correct transfer interrupt mask
impl W<u32, Reg<u32, _ISTR>>
[src]
pub fn l1req(&mut self) -> L1REQ_W<'_>
[src]
Bit 7 - LPM L1 state request
pub fn esof(&mut self) -> ESOF_W<'_>
[src]
Bit 8 - Expected start frame
pub fn sof(&mut self) -> SOF_W<'_>
[src]
Bit 9 - start of frame
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 10 - reset request
pub fn susp(&mut self) -> SUSP_W<'_>
[src]
Bit 11 - Suspend mode request
pub fn wkup(&mut self) -> WKUP_W<'_>
[src]
Bit 12 - Wakeup
pub fn err(&mut self) -> ERR_W<'_>
[src]
Bit 13 - Error
pub fn pmaovr(&mut self) -> PMAOVR_W<'_>
[src]
Bit 14 - Packet memory area over / underrun
impl W<u32, Reg<u32, _DADDR>>
[src]
pub fn add(&mut self) -> ADD_W<'_>
[src]
Bits 0:6 - Device address
pub fn ef(&mut self) -> EF_W<'_>
[src]
Bit 7 - Enable function
impl W<u32, Reg<u32, _BTABLE>>
[src]
impl W<u32, Reg<u32, _LPMCSR>>
[src]
pub fn lpmen(&mut self) -> LPMEN_W<'_>
[src]
Bit 0 - LPM support enable
pub fn lpmack(&mut self) -> LPMACK_W<'_>
[src]
Bit 1 - LPM Token acknowledge enable
impl W<u32, Reg<u32, _BCDR>>
[src]
pub fn bcden(&mut self) -> BCDEN_W<'_>
[src]
Bit 0 - Battery charging detector (BCD) enable
pub fn dcden(&mut self) -> DCDEN_W<'_>
[src]
Bit 1 - Data contact detection (DCD) mode enable
pub fn pden(&mut self) -> PDEN_W<'_>
[src]
Bit 2 - Primary detection (PD) mode enable
pub fn sden(&mut self) -> SDEN_W<'_>
[src]
Bit 3 - Secondary detection (SD) mode enable
pub fn dppu(&mut self) -> DPPU_W<'_>
[src]
Bit 15 - DP pull-up control
impl W<u32, Reg<u32, _CR>>
[src]
pub fn trim(&mut self) -> TRIM_W<'_>
[src]
Bits 8:13 - HSI48 oscillator smooth trimming
pub fn swsync(&mut self) -> SWSYNC_W<'_>
[src]
Bit 7 - Generate software SYNC event
pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<'_>
[src]
Bit 6 - Automatic trimming enable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 5 - Frequency error counter enable
pub fn esyncie(&mut self) -> ESYNCIE_W<'_>
[src]
Bit 3 - Expected SYNC interrupt enable
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 2 - Synchronization or trimming error interrupt enable
pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<'_>
[src]
Bit 1 - SYNC warning interrupt enable
pub fn syncokie(&mut self) -> SYNCOKIE_W<'_>
[src]
Bit 0 - SYNC event OK interrupt enable
impl W<u32, Reg<u32, _CFGR>>
[src]
pub fn syncpol(&mut self) -> SYNCPOL_W<'_>
[src]
Bit 31 - SYNC polarity selection
pub fn syncsrc(&mut self) -> SYNCSRC_W<'_>
[src]
Bits 28:29 - SYNC signal source selection
pub fn syncdiv(&mut self) -> SYNCDIV_W<'_>
[src]
Bits 24:26 - SYNC divider
pub fn felim(&mut self) -> FELIM_W<'_>
[src]
Bits 16:23 - Frequency error limit
pub fn reload(&mut self) -> RELOAD_W<'_>
[src]
Bits 0:15 - Counter reload value
impl W<u32, Reg<u32, _ICR>>
[src]
pub fn esyncc(&mut self) -> ESYNCC_W<'_>
[src]
Bit 3 - Expected SYNC clear flag
pub fn errc(&mut self) -> ERRC_W<'_>
[src]
Bit 2 - Error clear flag
pub fn syncwarnc(&mut self) -> SYNCWARNC_W<'_>
[src]
Bit 1 - SYNC warning clear flag
pub fn syncokc(&mut self) -> SYNCOKC_W<'_>
[src]
Bit 0 - SYNC event OK clear flag
impl W<u32, Reg<u32, _TIR>>
[src]
pub fn stid(&mut self) -> STID_W<'_>
[src]
Bits 21:31 - STID
pub fn exid(&mut self) -> EXID_W<'_>
[src]
Bits 3:20 - EXID
pub fn ide(&mut self) -> IDE_W<'_>
[src]
Bit 2 - IDE
pub fn rtr(&mut self) -> RTR_W<'_>
[src]
Bit 1 - RTR
pub fn txrq(&mut self) -> TXRQ_W<'_>
[src]
Bit 0 - TXRQ
impl W<u32, Reg<u32, _TDTR>>
[src]
pub fn time(&mut self) -> TIME_W<'_>
[src]
Bits 16:31 - TIME
pub fn tgt(&mut self) -> TGT_W<'_>
[src]
Bit 8 - TGT
pub fn dlc(&mut self) -> DLC_W<'_>
[src]
Bits 0:3 - DLC
impl W<u32, Reg<u32, _TDLR>>
[src]
pub fn data3(&mut self) -> DATA3_W<'_>
[src]
Bits 24:31 - DATA3
pub fn data2(&mut self) -> DATA2_W<'_>
[src]
Bits 16:23 - DATA2
pub fn data1(&mut self) -> DATA1_W<'_>
[src]
Bits 8:15 - DATA1
pub fn data0(&mut self) -> DATA0_W<'_>
[src]
Bits 0:7 - DATA0
impl W<u32, Reg<u32, _TDHR>>
[src]
pub fn data7(&mut self) -> DATA7_W<'_>
[src]
Bits 24:31 - DATA7
pub fn data6(&mut self) -> DATA6_W<'_>
[src]
Bits 16:23 - DATA6
pub fn data5(&mut self) -> DATA5_W<'_>
[src]
Bits 8:15 - DATA5
pub fn data4(&mut self) -> DATA4_W<'_>
[src]
Bits 0:7 - DATA4
impl W<u32, Reg<u32, _FR1>>
[src]
pub fn fb0(&mut self) -> FB0_W<'_>
[src]
Bit 0 - Filter bits
pub fn fb1(&mut self) -> FB1_W<'_>
[src]
Bit 1 - Filter bits
pub fn fb2(&mut self) -> FB2_W<'_>
[src]
Bit 2 - Filter bits
pub fn fb3(&mut self) -> FB3_W<'_>
[src]
Bit 3 - Filter bits
pub fn fb4(&mut self) -> FB4_W<'_>
[src]
Bit 4 - Filter bits
pub fn fb5(&mut self) -> FB5_W<'_>
[src]
Bit 5 - Filter bits
pub fn fb6(&mut self) -> FB6_W<'_>
[src]
Bit 6 - Filter bits
pub fn fb7(&mut self) -> FB7_W<'_>
[src]
Bit 7 - Filter bits
pub fn fb8(&mut self) -> FB8_W<'_>
[src]
Bit 8 - Filter bits
pub fn fb9(&mut self) -> FB9_W<'_>
[src]
Bit 9 - Filter bits
pub fn fb10(&mut self) -> FB10_W<'_>
[src]
Bit 10 - Filter bits
pub fn fb11(&mut self) -> FB11_W<'_>
[src]
Bit 11 - Filter bits
pub fn fb12(&mut self) -> FB12_W<'_>
[src]
Bit 12 - Filter bits
pub fn fb13(&mut self) -> FB13_W<'_>
[src]
Bit 13 - Filter bits
pub fn fb14(&mut self) -> FB14_W<'_>
[src]
Bit 14 - Filter bits
pub fn fb15(&mut self) -> FB15_W<'_>
[src]
Bit 15 - Filter bits
pub fn fb16(&mut self) -> FB16_W<'_>
[src]
Bit 16 - Filter bits
pub fn fb17(&mut self) -> FB17_W<'_>
[src]
Bit 17 - Filter bits
pub fn fb18(&mut self) -> FB18_W<'_>
[src]
Bit 18 - Filter bits
pub fn fb19(&mut self) -> FB19_W<'_>
[src]
Bit 19 - Filter bits
pub fn fb20(&mut self) -> FB20_W<'_>
[src]
Bit 20 - Filter bits
pub fn fb21(&mut self) -> FB21_W<'_>
[src]
Bit 21 - Filter bits
pub fn fb22(&mut self) -> FB22_W<'_>
[src]
Bit 22 - Filter bits
pub fn fb23(&mut self) -> FB23_W<'_>
[src]
Bit 23 - Filter bits
pub fn fb24(&mut self) -> FB24_W<'_>
[src]
Bit 24 - Filter bits
pub fn fb25(&mut self) -> FB25_W<'_>
[src]
Bit 25 - Filter bits
pub fn fb26(&mut self) -> FB26_W<'_>
[src]
Bit 26 - Filter bits
pub fn fb27(&mut self) -> FB27_W<'_>
[src]
Bit 27 - Filter bits
pub fn fb28(&mut self) -> FB28_W<'_>
[src]
Bit 28 - Filter bits
pub fn fb29(&mut self) -> FB29_W<'_>
[src]
Bit 29 - Filter bits
pub fn fb30(&mut self) -> FB30_W<'_>
[src]
Bit 30 - Filter bits
pub fn fb31(&mut self) -> FB31_W<'_>
[src]
Bit 31 - Filter bits
impl W<u32, Reg<u32, _FR2>>
[src]
pub fn fb0(&mut self) -> FB0_W<'_>
[src]
Bit 0 - Filter bits
pub fn fb1(&mut self) -> FB1_W<'_>
[src]
Bit 1 - Filter bits
pub fn fb2(&mut self) -> FB2_W<'_>
[src]
Bit 2 - Filter bits
pub fn fb3(&mut self) -> FB3_W<'_>
[src]
Bit 3 - Filter bits
pub fn fb4(&mut self) -> FB4_W<'_>
[src]
Bit 4 - Filter bits
pub fn fb5(&mut self) -> FB5_W<'_>
[src]
Bit 5 - Filter bits
pub fn fb6(&mut self) -> FB6_W<'_>
[src]
Bit 6 - Filter bits
pub fn fb7(&mut self) -> FB7_W<'_>
[src]
Bit 7 - Filter bits
pub fn fb8(&mut self) -> FB8_W<'_>
[src]
Bit 8 - Filter bits
pub fn fb9(&mut self) -> FB9_W<'_>
[src]
Bit 9 - Filter bits
pub fn fb10(&mut self) -> FB10_W<'_>
[src]
Bit 10 - Filter bits
pub fn fb11(&mut self) -> FB11_W<'_>
[src]
Bit 11 - Filter bits
pub fn fb12(&mut self) -> FB12_W<'_>
[src]
Bit 12 - Filter bits
pub fn fb13(&mut self) -> FB13_W<'_>
[src]
Bit 13 - Filter bits
pub fn fb14(&mut self) -> FB14_W<'_>
[src]
Bit 14 - Filter bits
pub fn fb15(&mut self) -> FB15_W<'_>
[src]
Bit 15 - Filter bits
pub fn fb16(&mut self) -> FB16_W<'_>
[src]
Bit 16 - Filter bits
pub fn fb17(&mut self) -> FB17_W<'_>
[src]
Bit 17 - Filter bits
pub fn fb18(&mut self) -> FB18_W<'_>
[src]
Bit 18 - Filter bits
pub fn fb19(&mut self) -> FB19_W<'_>
[src]
Bit 19 - Filter bits
pub fn fb20(&mut self) -> FB20_W<'_>
[src]
Bit 20 - Filter bits
pub fn fb21(&mut self) -> FB21_W<'_>
[src]
Bit 21 - Filter bits
pub fn fb22(&mut self) -> FB22_W<'_>
[src]
Bit 22 - Filter bits
pub fn fb23(&mut self) -> FB23_W<'_>
[src]
Bit 23 - Filter bits
pub fn fb24(&mut self) -> FB24_W<'_>
[src]
Bit 24 - Filter bits
pub fn fb25(&mut self) -> FB25_W<'_>
[src]
Bit 25 - Filter bits
pub fn fb26(&mut self) -> FB26_W<'_>
[src]
Bit 26 - Filter bits
pub fn fb27(&mut self) -> FB27_W<'_>
[src]
Bit 27 - Filter bits
pub fn fb28(&mut self) -> FB28_W<'_>
[src]
Bit 28 - Filter bits
pub fn fb29(&mut self) -> FB29_W<'_>
[src]
Bit 29 - Filter bits
pub fn fb30(&mut self) -> FB30_W<'_>
[src]
Bit 30 - Filter bits
pub fn fb31(&mut self) -> FB31_W<'_>
[src]
Bit 31 - Filter bits
impl W<u32, Reg<u32, _MCR>>
[src]
pub fn dbf(&mut self) -> DBF_W<'_>
[src]
Bit 16 - DBF
pub fn reset(&mut self) -> RESET_W<'_>
[src]
Bit 15 - RESET
pub fn ttcm(&mut self) -> TTCM_W<'_>
[src]
Bit 7 - TTCM
pub fn abom(&mut self) -> ABOM_W<'_>
[src]
Bit 6 - ABOM
pub fn awum(&mut self) -> AWUM_W<'_>
[src]
Bit 5 - AWUM
pub fn nart(&mut self) -> NART_W<'_>
[src]
Bit 4 - NART
pub fn rflm(&mut self) -> RFLM_W<'_>
[src]
Bit 3 - RFLM
pub fn txfp(&mut self) -> TXFP_W<'_>
[src]
Bit 2 - TXFP
pub fn sleep(&mut self) -> SLEEP_W<'_>
[src]
Bit 1 - SLEEP
pub fn inrq(&mut self) -> INRQ_W<'_>
[src]
Bit 0 - INRQ
impl W<u32, Reg<u32, _MSR>>
[src]
pub fn slaki(&mut self) -> SLAKI_W<'_>
[src]
Bit 4 - SLAKI
pub fn wkui(&mut self) -> WKUI_W<'_>
[src]
Bit 3 - WKUI
pub fn erri(&mut self) -> ERRI_W<'_>
[src]
Bit 2 - ERRI
impl W<u32, Reg<u32, _TSR>>
[src]
pub fn abrq2(&mut self) -> ABRQ2_W<'_>
[src]
Bit 23 - ABRQ2
pub fn terr2(&mut self) -> TERR2_W<'_>
[src]
Bit 19 - TERR2
pub fn alst2(&mut self) -> ALST2_W<'_>
[src]
Bit 18 - ALST2
pub fn txok2(&mut self) -> TXOK2_W<'_>
[src]
Bit 17 - TXOK2
pub fn rqcp2(&mut self) -> RQCP2_W<'_>
[src]
Bit 16 - RQCP2
pub fn abrq1(&mut self) -> ABRQ1_W<'_>
[src]
Bit 15 - ABRQ1
pub fn terr1(&mut self) -> TERR1_W<'_>
[src]
Bit 11 - TERR1
pub fn alst1(&mut self) -> ALST1_W<'_>
[src]
Bit 10 - ALST1
pub fn txok1(&mut self) -> TXOK1_W<'_>
[src]
Bit 9 - TXOK1
pub fn rqcp1(&mut self) -> RQCP1_W<'_>
[src]
Bit 8 - RQCP1
pub fn abrq0(&mut self) -> ABRQ0_W<'_>
[src]
Bit 7 - ABRQ0
pub fn terr0(&mut self) -> TERR0_W<'_>
[src]
Bit 3 - TERR0
pub fn alst0(&mut self) -> ALST0_W<'_>
[src]
Bit 2 - ALST0
pub fn txok0(&mut self) -> TXOK0_W<'_>
[src]
Bit 1 - TXOK0
pub fn rqcp0(&mut self) -> RQCP0_W<'_>
[src]
Bit 0 - RQCP0
impl W<u32, Reg<u32, _RFR>>
[src]
pub fn rfom(&mut self) -> RFOM_W<'_>
[src]
Bit 5 - RFOM0
pub fn fovr(&mut self) -> FOVR_W<'_>
[src]
Bit 4 - FOVR0
pub fn full(&mut self) -> FULL_W<'_>
[src]
Bit 3 - FULL0
impl W<u32, Reg<u32, _IER>>
[src]
pub fn slkie(&mut self) -> SLKIE_W<'_>
[src]
Bit 17 - SLKIE
pub fn wkuie(&mut self) -> WKUIE_W<'_>
[src]
Bit 16 - WKUIE
pub fn errie(&mut self) -> ERRIE_W<'_>
[src]
Bit 15 - ERRIE
pub fn lecie(&mut self) -> LECIE_W<'_>
[src]
Bit 11 - LECIE
pub fn bofie(&mut self) -> BOFIE_W<'_>
[src]
Bit 10 - BOFIE
pub fn epvie(&mut self) -> EPVIE_W<'_>
[src]
Bit 9 - EPVIE
pub fn ewgie(&mut self) -> EWGIE_W<'_>
[src]
Bit 8 - EWGIE
pub fn fovie1(&mut self) -> FOVIE1_W<'_>
[src]
Bit 6 - FOVIE1
pub fn ffie1(&mut self) -> FFIE1_W<'_>
[src]
Bit 5 - FFIE1
pub fn fmpie1(&mut self) -> FMPIE1_W<'_>
[src]
Bit 4 - FMPIE1
pub fn fovie0(&mut self) -> FOVIE0_W<'_>
[src]
Bit 3 - FOVIE0
pub fn ffie0(&mut self) -> FFIE0_W<'_>
[src]
Bit 2 - FFIE0
pub fn fmpie0(&mut self) -> FMPIE0_W<'_>
[src]
Bit 1 - FMPIE0
pub fn tmeie(&mut self) -> TMEIE_W<'_>
[src]
Bit 0 - TMEIE
impl W<u32, Reg<u32, _ESR>>
[src]
impl W<u32, Reg<u32, _BTR>>
[src]
pub fn silm(&mut self) -> SILM_W<'_>
[src]
Bit 31 - SILM
pub fn lbkm(&mut self) -> LBKM_W<'_>
[src]
Bit 30 - LBKM
pub fn sjw(&mut self) -> SJW_W<'_>
[src]
Bits 24:25 - SJW
pub fn ts2(&mut self) -> TS2_W<'_>
[src]
Bits 20:22 - TS2
pub fn ts1(&mut self) -> TS1_W<'_>
[src]
Bits 16:19 - TS1
pub fn brp(&mut self) -> BRP_W<'_>
[src]
Bits 0:9 - BRP
impl W<u32, Reg<u32, _FMR>>
[src]
pub fn can2sb(&mut self) -> CAN2SB_W<'_>
[src]
Bits 8:13 - CAN2SB
pub fn finit(&mut self) -> FINIT_W<'_>
[src]
Bit 0 - FINIT
impl W<u32, Reg<u32, _FM1R>>
[src]
pub fn fbm0(&mut self) -> FBM0_W<'_>
[src]
Bit 0 - Filter mode
pub fn fbm1(&mut self) -> FBM1_W<'_>
[src]
Bit 1 - Filter mode
pub fn fbm2(&mut self) -> FBM2_W<'_>
[src]
Bit 2 - Filter mode
pub fn fbm3(&mut self) -> FBM3_W<'_>
[src]
Bit 3 - Filter mode
pub fn fbm4(&mut self) -> FBM4_W<'_>
[src]
Bit 4 - Filter mode
pub fn fbm5(&mut self) -> FBM5_W<'_>
[src]
Bit 5 - Filter mode
pub fn fbm6(&mut self) -> FBM6_W<'_>
[src]
Bit 6 - Filter mode
pub fn fbm7(&mut self) -> FBM7_W<'_>
[src]
Bit 7 - Filter mode
pub fn fbm8(&mut self) -> FBM8_W<'_>
[src]
Bit 8 - Filter mode
pub fn fbm9(&mut self) -> FBM9_W<'_>
[src]
Bit 9 - Filter mode
pub fn fbm10(&mut self) -> FBM10_W<'_>
[src]
Bit 10 - Filter mode
pub fn fbm11(&mut self) -> FBM11_W<'_>
[src]
Bit 11 - Filter mode
pub fn fbm12(&mut self) -> FBM12_W<'_>
[src]
Bit 12 - Filter mode
pub fn fbm13(&mut self) -> FBM13_W<'_>
[src]
Bit 13 - Filter mode
pub fn fbm14(&mut self) -> FBM14_W<'_>
[src]
Bit 14 - Filter mode
pub fn fbm15(&mut self) -> FBM15_W<'_>
[src]
Bit 15 - Filter mode
pub fn fbm16(&mut self) -> FBM16_W<'_>
[src]
Bit 16 - Filter mode
pub fn fbm17(&mut self) -> FBM17_W<'_>
[src]
Bit 17 - Filter mode
pub fn fbm18(&mut self) -> FBM18_W<'_>
[src]
Bit 18 - Filter mode
pub fn fbm19(&mut self) -> FBM19_W<'_>
[src]
Bit 19 - Filter mode
pub fn fbm20(&mut self) -> FBM20_W<'_>
[src]
Bit 20 - Filter mode
pub fn fbm21(&mut self) -> FBM21_W<'_>
[src]
Bit 21 - Filter mode
pub fn fbm22(&mut self) -> FBM22_W<'_>
[src]
Bit 22 - Filter mode
pub fn fbm23(&mut self) -> FBM23_W<'_>
[src]
Bit 23 - Filter mode
pub fn fbm24(&mut self) -> FBM24_W<'_>
[src]
Bit 24 - Filter mode
pub fn fbm25(&mut self) -> FBM25_W<'_>
[src]
Bit 25 - Filter mode
pub fn fbm26(&mut self) -> FBM26_W<'_>
[src]
Bit 26 - Filter mode
pub fn fbm27(&mut self) -> FBM27_W<'_>
[src]
Bit 27 - Filter mode
impl W<u32, Reg<u32, _FS1R>>
[src]
pub fn fsc0(&mut self) -> FSC0_W<'_>
[src]
Bit 0 - Filter scale configuration
pub fn fsc1(&mut self) -> FSC1_W<'_>
[src]
Bit 1 - Filter scale configuration
pub fn fsc2(&mut self) -> FSC2_W<'_>
[src]
Bit 2 - Filter scale configuration
pub fn fsc3(&mut self) -> FSC3_W<'_>
[src]
Bit 3 - Filter scale configuration
pub fn fsc4(&mut self) -> FSC4_W<'_>
[src]
Bit 4 - Filter scale configuration
pub fn fsc5(&mut self) -> FSC5_W<'_>
[src]
Bit 5 - Filter scale configuration
pub fn fsc6(&mut self) -> FSC6_W<'_>
[src]
Bit 6 - Filter scale configuration
pub fn fsc7(&mut self) -> FSC7_W<'_>
[src]
Bit 7 - Filter scale configuration
pub fn fsc8(&mut self) -> FSC8_W<'_>
[src]
Bit 8 - Filter scale configuration
pub fn fsc9(&mut self) -> FSC9_W<'_>
[src]
Bit 9 - Filter scale configuration
pub fn fsc10(&mut self) -> FSC10_W<'_>
[src]
Bit 10 - Filter scale configuration
pub fn fsc11(&mut self) -> FSC11_W<'_>
[src]
Bit 11 - Filter scale configuration
pub fn fsc12(&mut self) -> FSC12_W<'_>
[src]
Bit 12 - Filter scale configuration
pub fn fsc13(&mut self) -> FSC13_W<'_>
[src]
Bit 13 - Filter scale configuration
pub fn fsc14(&mut self) -> FSC14_W<'_>
[src]
Bit 14 - Filter scale configuration
pub fn fsc15(&mut self) -> FSC15_W<'_>
[src]
Bit 15 - Filter scale configuration
pub fn fsc16(&mut self) -> FSC16_W<'_>
[src]
Bit 16 - Filter scale configuration
pub fn fsc17(&mut self) -> FSC17_W<'_>
[src]
Bit 17 - Filter scale configuration
pub fn fsc18(&mut self) -> FSC18_W<'_>
[src]
Bit 18 - Filter scale configuration
pub fn fsc19(&mut self) -> FSC19_W<'_>
[src]
Bit 19 - Filter scale configuration
pub fn fsc20(&mut self) -> FSC20_W<'_>
[src]
Bit 20 - Filter scale configuration
pub fn fsc21(&mut self) -> FSC21_W<'_>
[src]
Bit 21 - Filter scale configuration
pub fn fsc22(&mut self) -> FSC22_W<'_>
[src]
Bit 22 - Filter scale configuration
pub fn fsc23(&mut self) -> FSC23_W<'_>
[src]
Bit 23 - Filter scale configuration
pub fn fsc24(&mut self) -> FSC24_W<'_>
[src]
Bit 24 - Filter scale configuration
pub fn fsc25(&mut self) -> FSC25_W<'_>
[src]
Bit 25 - Filter scale configuration
pub fn fsc26(&mut self) -> FSC26_W<'_>
[src]
Bit 26 - Filter scale configuration
pub fn fsc27(&mut self) -> FSC27_W<'_>
[src]
Bit 27 - Filter scale configuration
impl W<u32, Reg<u32, _FFA1R>>
[src]
pub fn ffa0(&mut self) -> FFA0_W<'_>
[src]
Bit 0 - Filter FIFO assignment for filter 0
pub fn ffa1(&mut self) -> FFA1_W<'_>
[src]
Bit 1 - Filter FIFO assignment for filter 1
pub fn ffa2(&mut self) -> FFA2_W<'_>
[src]
Bit 2 - Filter FIFO assignment for filter 2
pub fn ffa3(&mut self) -> FFA3_W<'_>
[src]
Bit 3 - Filter FIFO assignment for filter 3
pub fn ffa4(&mut self) -> FFA4_W<'_>
[src]
Bit 4 - Filter FIFO assignment for filter 4
pub fn ffa5(&mut self) -> FFA5_W<'_>
[src]
Bit 5 - Filter FIFO assignment for filter 5
pub fn ffa6(&mut self) -> FFA6_W<'_>
[src]
Bit 6 - Filter FIFO assignment for filter 6
pub fn ffa7(&mut self) -> FFA7_W<'_>
[src]
Bit 7 - Filter FIFO assignment for filter 7
pub fn ffa8(&mut self) -> FFA8_W<'_>
[src]
Bit 8 - Filter FIFO assignment for filter 8
pub fn ffa9(&mut self) -> FFA9_W<'_>
[src]
Bit 9 - Filter FIFO assignment for filter 9
pub fn ffa10(&mut self) -> FFA10_W<'_>
[src]
Bit 10 - Filter FIFO assignment for filter 10
pub fn ffa11(&mut self) -> FFA11_W<'_>
[src]
Bit 11 - Filter FIFO assignment for filter 11
pub fn ffa12(&mut self) -> FFA12_W<'_>
[src]
Bit 12 - Filter FIFO assignment for filter 12
pub fn ffa13(&mut self) -> FFA13_W<'_>
[src]
Bit 13 - Filter FIFO assignment for filter 13
pub fn ffa14(&mut self) -> FFA14_W<'_>
[src]
Bit 14 - Filter FIFO assignment for filter 14
pub fn ffa15(&mut self) -> FFA15_W<'_>
[src]
Bit 15 - Filter FIFO assignment for filter 15
pub fn ffa16(&mut self) -> FFA16_W<'_>
[src]
Bit 16 - Filter FIFO assignment for filter 16
pub fn ffa17(&mut self) -> FFA17_W<'_>
[src]
Bit 17 - Filter FIFO assignment for filter 17
pub fn ffa18(&mut self) -> FFA18_W<'_>
[src]
Bit 18 - Filter FIFO assignment for filter 18
pub fn ffa19(&mut self) -> FFA19_W<'_>
[src]
Bit 19 - Filter FIFO assignment for filter 19
pub fn ffa20(&mut self) -> FFA20_W<'_>
[src]
Bit 20 - Filter FIFO assignment for filter 20
pub fn ffa21(&mut self) -> FFA21_W<'_>
[src]
Bit 21 - Filter FIFO assignment for filter 21
pub fn ffa22(&mut self) -> FFA22_W<'_>
[src]
Bit 22 - Filter FIFO assignment for filter 22
pub fn ffa23(&mut self) -> FFA23_W<'_>
[src]
Bit 23 - Filter FIFO assignment for filter 23
pub fn ffa24(&mut self) -> FFA24_W<'_>
[src]
Bit 24 - Filter FIFO assignment for filter 24
pub fn ffa25(&mut self) -> FFA25_W<'_>
[src]
Bit 25 - Filter FIFO assignment for filter 25
pub fn ffa26(&mut self) -> FFA26_W<'_>
[src]
Bit 26 - Filter FIFO assignment for filter 26
pub fn ffa27(&mut self) -> FFA27_W<'_>
[src]
Bit 27 - Filter FIFO assignment for filter 27
impl W<u32, Reg<u32, _FA1R>>
[src]
pub fn fact0(&mut self) -> FACT0_W<'_>
[src]
Bit 0 - Filter active
pub fn fact1(&mut self) -> FACT1_W<'_>
[src]
Bit 1 - Filter active
pub fn fact2(&mut self) -> FACT2_W<'_>
[src]
Bit 2 - Filter active
pub fn fact3(&mut self) -> FACT3_W<'_>
[src]
Bit 3 - Filter active
pub fn fact4(&mut self) -> FACT4_W<'_>
[src]
Bit 4 - Filter active
pub fn fact5(&mut self) -> FACT5_W<'_>
[src]
Bit 5 - Filter active
pub fn fact6(&mut self) -> FACT6_W<'_>
[src]
Bit 6 - Filter active
pub fn fact7(&mut self) -> FACT7_W<'_>
[src]
Bit 7 - Filter active
pub fn fact8(&mut self) -> FACT8_W<'_>
[src]
Bit 8 - Filter active
pub fn fact9(&mut self) -> FACT9_W<'_>
[src]
Bit 9 - Filter active
pub fn fact10(&mut self) -> FACT10_W<'_>
[src]
Bit 10 - Filter active
pub fn fact11(&mut self) -> FACT11_W<'_>
[src]
Bit 11 - Filter active
pub fn fact12(&mut self) -> FACT12_W<'_>
[src]
Bit 12 - Filter active
pub fn fact13(&mut self) -> FACT13_W<'_>
[src]
Bit 13 - Filter active
pub fn fact14(&mut self) -> FACT14_W<'_>
[src]
Bit 14 - Filter active
pub fn fact15(&mut self) -> FACT15_W<'_>
[src]
Bit 15 - Filter active
pub fn fact16(&mut self) -> FACT16_W<'_>
[src]
Bit 16 - Filter active
pub fn fact17(&mut self) -> FACT17_W<'_>
[src]
Bit 17 - Filter active
pub fn fact18(&mut self) -> FACT18_W<'_>
[src]
Bit 18 - Filter active
pub fn fact19(&mut self) -> FACT19_W<'_>
[src]
Bit 19 - Filter active
pub fn fact20(&mut self) -> FACT20_W<'_>
[src]
Bit 20 - Filter active
pub fn fact21(&mut self) -> FACT21_W<'_>
[src]
Bit 21 - Filter active
pub fn fact22(&mut self) -> FACT22_W<'_>
[src]
Bit 22 - Filter active
pub fn fact23(&mut self) -> FACT23_W<'_>
[src]
Bit 23 - Filter active
pub fn fact24(&mut self) -> FACT24_W<'_>
[src]
Bit 24 - Filter active
pub fn fact25(&mut self) -> FACT25_W<'_>
[src]
Bit 25 - Filter active
pub fn fact26(&mut self) -> FACT26_W<'_>
[src]
Bit 26 - Filter active
pub fn fact27(&mut self) -> FACT27_W<'_>
[src]
Bit 27 - Filter active
impl W<u32, Reg<u32, _CR>>
[src]
pub fn en1(&mut self) -> EN1_W<'_>
[src]
Bit 0 - DAC channel1 enable
pub fn boff1(&mut self) -> BOFF1_W<'_>
[src]
Bit 1 - DAC channel1 output buffer disable
pub fn ten1(&mut self) -> TEN1_W<'_>
[src]
Bit 2 - DAC channel1 trigger enable
pub fn tsel1(&mut self) -> TSEL1_W<'_>
[src]
Bits 3:5 - DAC channel1 trigger selection
pub fn wave1(&mut self) -> WAVE1_W<'_>
[src]
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
pub fn mamp1(&mut self) -> MAMP1_W<'_>
[src]
Bits 8:11 - DAC channel1 mask/amplitude selector
pub fn dmaen1(&mut self) -> DMAEN1_W<'_>
[src]
Bit 12 - DAC channel1 DMA enable
pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>
[src]
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
pub fn en2(&mut self) -> EN2_W<'_>
[src]
Bit 16 - DAC channel2 enable
pub fn boff2(&mut self) -> BOFF2_W<'_>
[src]
Bit 17 - DAC channel2 output buffer disable
pub fn ten2(&mut self) -> TEN2_W<'_>
[src]
Bit 18 - DAC channel2 trigger enable
pub fn tsel2(&mut self) -> TSEL2_W<'_>
[src]
Bits 19:21 - DAC channel2 trigger selection
pub fn wave2(&mut self) -> WAVE2_W<'_>
[src]
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
pub fn mamp2(&mut self) -> MAMP2_W<'_>
[src]
Bits 24:27 - DAC channel2 mask/amplitude selector
pub fn dmaen2(&mut self) -> DMAEN2_W<'_>
[src]
Bit 28 - DAC channel2 DMA enable
pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>
[src]
Bit 29 - DAC channel2 DMA underrun interrupt enable
impl W<u32, Reg<u32, _SWTRIGR>>
[src]
pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>
[src]
Bit 0 - DAC channel1 software trigger
pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>
[src]
Bit 1 - DAC channel2 software trigger
impl W<u32, Reg<u32, _DHR12R1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R1>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _SR>>
[src]
pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>
[src]
Bit 29 - DAC channel2 DMA underrun flag
pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>
[src]
Bit 13 - DAC channel1 DMA underrun flag
impl W<u32, Reg<u32, _DHR12R2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R2>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl W<u32, Reg<u32, _DHR12RD>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 16:27 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12LD>>
[src]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 20:31 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8RD>>
[src]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>
[src]
Bits 8:15 - DAC channel2 8-bit right-aligned data
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>
[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _CSR>>
[src]
pub fn enable(&mut self) -> ENABLE_W<'_>
[src]
Bit 0 - Counter enable
pub fn tickint(&mut self) -> TICKINT_W<'_>
[src]
Bit 1 - SysTick exception request enable
pub fn clksource(&mut self) -> CLKSOURCE_W<'_>
[src]
Bit 2 - Clock source selection
pub fn countflag(&mut self) -> COUNTFLAG_W<'_>
[src]
Bit 16 - COUNTFLAG
impl W<u32, Reg<u32, _RVR>>
[src]
impl W<u32, Reg<u32, _CVR>>
[src]
impl W<u32, Reg<u32, _CALIB>>
[src]
pub fn tenms(&mut self) -> TENMS_W<'_>
[src]
Bits 0:23 - Calibration value
pub fn skew(&mut self) -> SKEW_W<'_>
[src]
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
pub fn noref(&mut self) -> NOREF_W<'_>
[src]
Bit 31 - NOREF flag. Reads as zero
impl W<u32, Reg<u32, _CR1>>
[src]
pub fn ckd(&mut self) -> CKD_W<'_>
[src]
Bits 8:9 - Clock division
pub fn arpe(&mut self) -> ARPE_W<'_>
[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&mut self) -> CMS_W<'_>
[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 4 - Direction
pub fn opm(&mut self) -> OPM_W<'_>
[src]
Bit 3 - One-pulse mode
pub fn urs(&mut self) -> URS_W<'_>
[src]
Bit 2 - Update request source
pub fn udis(&mut self) -> UDIS_W<'_>
[src]
Bit 1 - Update disable
pub fn cen(&mut self) -> CEN_W<'_>
[src]
Bit 0 - Counter enable
impl W<u32, Reg<u32, _CR2>>
[src]
pub fn ti1s(&mut self) -> TI1S_W<'_>
[src]
Bit 7 - TI1 selection
pub fn mms(&mut self) -> MMS_W<'_>
[src]
Bits 4:6 - Master mode selection
pub fn ccds(&mut self) -> CCDS_W<'_>
[src]
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
[src]
pub fn etp(&mut self) -> ETP_W<'_>
[src]
Bit 15 - External trigger polarity
pub fn ece(&mut self) -> ECE_W<'_>
[src]
Bit 14 - External clock enable
pub fn etps(&mut self) -> ETPS_W<'_>
[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&mut self) -> ETF_W<'_>
[src]
Bits 8:11 - External trigger filter
pub fn msm(&mut self) -> MSM_W<'_>
[src]
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
[src]
Bits 4:6 - Trigger selection
pub fn sms(&mut self) -> SMS_W<'_>
[src]
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
[src]
pub fn tde(&mut self) -> TDE_W<'_>
[src]
Bit 14 - Trigger DMA request enable
pub fn comde(&mut self) -> COMDE_W<'_>
[src]
Bit 13 - COM DMA request enable
pub fn cc4de(&mut self) -> CC4DE_W<'_>
[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&mut self) -> CC3DE_W<'_>
[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&mut self) -> CC2DE_W<'_>
[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&mut self) -> CC1DE_W<'_>
[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&mut self) -> UDE_W<'_>
[src]
Bit 8 - Update DMA request enable
pub fn tie(&mut self) -> TIE_W<'_>
[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&mut self) -> CC4IE_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&mut self) -> CC3IE_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&mut self) -> CC2IE_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&mut self) -> CC1IE_W<'_>
[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&mut self) -> UIE_W<'_>
[src]
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
[src]
pub fn cc4of(&mut self) -> CC4OF_W<'_>
[src]
Bit 12 - Capture/Compare 4 overcapture flag
pub fn cc3of(&mut self) -> CC3OF_W<'_>
[src]
Bit 11 - Capture/Compare 3 overcapture flag
pub fn cc2of(&mut self) -> CC2OF_W<'_>
[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&mut self) -> CC1OF_W<'_>
[src]
Bit 9 - Capture/Compare 1 overcapture flag
pub fn tif(&mut self) -> TIF_W<'_>
[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&mut self) -> CC4IF_W<'_>
[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&mut self) -> CC3IF_W<'_>
[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&mut self) -> CC2IF_W<'_>
[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&mut self) -> CC1IF_W<'_>
[src]
Bit 1 - Capture/compare 1 interrupt flag
pub fn uif(&mut self) -> UIF_W<'_>
[src]
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
[src]
pub fn tg(&mut self) -> TG_W<'_>
[src]
Bit 6 - Trigger generation
pub fn cc4g(&mut self) -> CC4G_W<'_>
[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&mut self) -> CC3G_W<'_>
[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&mut self) -> CC2G_W<'_>
[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&mut self) -> CC1G_W<'_>
[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
[src]
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
[src]
pub fn oc2ce(&mut self) -> OC2CE_W<'_>
[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&mut self) -> OC2M_W<'_>
[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&mut self) -> OC2PE_W<'_>
[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&mut self) -> OC2FE_W<'_>
[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&mut self) -> CC2S_W<'_>
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Bits 8:9 - Capture/Compare 2 selection
pub fn oc1ce(&mut self) -> OC1CE_W<'_>
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Bit 7 - Output compare 1 clear enable
pub fn oc1m(&mut self) -> OC1M_W<'_>
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Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&mut self) -> OC1PE_W<'_>
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Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&mut self) -> OC1FE_W<'_>
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Bit 2 - Output compare 1 fast enable
pub fn cc1s(&mut self) -> CC1S_W<'_>
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Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
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pub fn ic2f(&mut self) -> IC2F_W<'_>
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Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&mut self) -> IC2PSC_W<'_>
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Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&mut self) -> CC2S_W<'_>
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Bits 8:9 - Capture/compare 2 selection
pub fn ic1f(&mut self) -> IC1F_W<'_>
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Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&mut self) -> IC1PSC_W<'_>
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Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&mut self) -> CC1S_W<'_>
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Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
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pub fn oc4ce(&mut self) -> OC4CE_W<'_>
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Bit 15 - Output compare 4 clear enable
pub fn oc4m(&mut self) -> OC4M_W<'_>
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Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&mut self) -> OC4PE_W<'_>
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Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&mut self) -> OC4FE_W<'_>
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Bit 10 - Output compare 4 fast enable
pub fn cc4s(&mut self) -> CC4S_W<'_>
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Bits 8:9 - Capture/Compare 4 selection
pub fn oc3ce(&mut self) -> OC3CE_W<'_>
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Bit 7 - Output compare 3 clear enable
pub fn oc3m(&mut self) -> OC3M_W<'_>
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Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&mut self) -> OC3PE_W<'_>
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Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&mut self) -> OC3FE_W<'_>
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Bit 2 - Output compare 3 fast enable
pub fn cc3s(&mut self) -> CC3S_W<'_>
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Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
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pub fn ic4f(&mut self) -> IC4F_W<'_>
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Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&mut self) -> IC4PSC_W<'_>
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Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&mut self) -> CC4S_W<'_>
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Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&mut self) -> IC3F_W<'_>
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Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&mut self) -> IC3PSC_W<'_>
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Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&mut self) -> CC3S_W<'_>
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Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
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pub fn cc4np(&mut self) -> CC4NP_W<'_>
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Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&mut self) -> CC4P_W<'_>
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Bit 13 - Capture/Compare 3 output Polarity
pub fn cc4e(&mut self) -> CC4E_W<'_>
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Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&mut self) -> CC3NP_W<'_>
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Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&mut self) -> CC3P_W<'_>
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Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&mut self) -> CC3E_W<'_>
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Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&mut self) -> CC2NP_W<'_>
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Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&mut self) -> CC2P_W<'_>
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Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&mut self) -> CC2E_W<'_>
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Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&mut self) -> CC1NP_W<'_>
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Bit 3 - Capture/Compare 1 output Polarity
pub fn cc1p(&mut self) -> CC1P_W<'_>
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Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&mut self) -> CC1E_W<'_>
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Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
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pub fn cnt_h(&mut self) -> CNT_H_W<'_>
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Bits 16:31 - High counter value (TIM2 only)
pub fn cnt(&mut self) -> CNT_W<'_>
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Bits 0:15 - Counter value
impl W<u32, Reg<u32, _PSC>>
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impl W<u32, Reg<u32, _ARR>>
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pub fn arr_h(&mut self) -> ARR_H_W<'_>
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Bits 16:31 - High Auto-reload value (TIM2 only)
pub fn arr(&mut self) -> ARR_W<'_>
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Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
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pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>
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Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
pub fn ccr(&mut self) -> CCR_W<'_>
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Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
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pub fn dbl(&mut self) -> DBL_W<'_>
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Bits 8:12 - DMA burst length
pub fn dba(&mut self) -> DBA_W<'_>
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Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
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impl W<u32, Reg<u32, _CSR>>
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pub fn comp1en(&mut self) -> COMP1EN_W<'_>
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Bit 0 - Comparator 1 enable
pub fn comp1mode(&mut self) -> COMP1MODE_W<'_>
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Bits 2:3 - Comparator 1 mode
pub fn comp1insel(&mut self) -> COMP1INSEL_W<'_>
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Bits 4:6 - Comparator 1 inverting input selection
pub fn comp1outsel(&mut self) -> COMP1OUTSEL_W<'_>
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Bits 8:10 - Comparator 1 output selection
pub fn comp1pol(&mut self) -> COMP1POL_W<'_>
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Bit 11 - Comparator 1 output polarity
pub fn comp1hyst(&mut self) -> COMP1HYST_W<'_>
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Bits 12:13 - Comparator 1 hysteresis
pub fn comp1lock(&mut self) -> COMP1LOCK_W<'_>
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Bit 15 - Comparator 1 lock
pub fn comp2en(&mut self) -> COMP2EN_W<'_>
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Bit 16 - Comparator 2 enable
pub fn comp2mode(&mut self) -> COMP2MODE_W<'_>
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Bits 18:19 - Comparator 2 mode
pub fn comp2insel(&mut self) -> COMP2INSEL_W<'_>
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Bits 20:22 - Comparator 2 inverting input selection
pub fn wndwen(&mut self) -> WNDWEN_W<'_>
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Bit 23 - Window mode enable
pub fn comp2outsel(&mut self) -> COMP2OUTSEL_W<'_>
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Bits 24:26 - Comparator 2 output selection
pub fn comp2pol(&mut self) -> COMP2POL_W<'_>
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Bit 27 - Comparator 2 output polarity
pub fn comp2hyst(&mut self) -> COMP2HYST_W<'_>
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Bits 28:29 - Comparator 2 hysteresis
pub fn comp2lock(&mut self) -> COMP2LOCK_W<'_>
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Bit 31 - Comparator 2 lock
pub fn comp1sw1(&mut self) -> COMP1SW1_W<'_>
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Bit 1 - Comparator 1 non inverting input DAC switch
Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send,
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync,
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin,
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
[src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,