pub(crate) static PERIPHERALS: &[Peripheral] = &[
Peripheral {
name: "ADC1",
address: 0x40012000,
registers: Some(PeripheralRegisters {
kind: "adc",
version: "v2",
block: "ADC",
ir: &adc::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK2",
kernel_clock: Clock("PCLK2"),
enable: Some(PeripheralRccRegister {
register: "APB2ENR",
field: "ADC1EN",
}),
reset: None,
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA0",
signal: "IN0",
af: None,
},
PeripheralPin {
pin: "PA2",
signal: "IN2",
af: None,
},
PeripheralPin {
pin: "PA3",
signal: "IN3",
af: None,
},
PeripheralPin {
pin: "PA5",
signal: "IN5",
af: None,
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "ADC1",
channel: Some("DMA2_CH0"),
dmamux: None,
remap: &[],
dma: None,
request: Some(0),
},
PeripheralDmaChannel {
signal: "ADC1",
channel: Some("DMA2_CH4"),
dmamux: None,
remap: &[],
dma: None,
request: Some(0),
},
],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "ADC",
}],
afio: None,
},
Peripheral {
name: "ADC1_COMMON",
address: 0x40012300,
registers: Some(PeripheralRegisters {
kind: "adccommon",
version: "v2",
block: "ADC_COMMON",
ir: &adccommon::REGISTERS,
}),
rcc: None,
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "CRC",
address: 0x40023000,
registers: Some(PeripheralRegisters {
kind: "crc",
version: "v1",
block: "CRC",
ir: &crc::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "CRCEN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "CRCRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "DAC1",
address: 0x40007400,
registers: Some(PeripheralRegisters {
kind: "dac",
version: "v2",
block: "DAC",
ir: &dac::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "DACEN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "DACRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[PeripheralPin {
pin: "PA5",
signal: "OUT1",
af: None,
}],
dma_channels: &[PeripheralDmaChannel {
signal: "CH1",
channel: Some("DMA1_CH5"),
dmamux: None,
remap: &[],
dma: None,
request: Some(7),
}],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "TIM6_DAC",
}],
afio: None,
},
Peripheral {
name: "DBGMCU",
address: 0xe0042000,
registers: Some(PeripheralRegisters {
kind: "dbgmcu",
version: "f4",
block: "DBGMCU",
ir: &dbgmcu::REGISTERS,
}),
rcc: None,
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "DMA1",
address: 0x40026000,
registers: Some(PeripheralRegisters {
kind: "dma",
version: "v2",
block: "DMA",
ir: &dma::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "DMA1EN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "DMA1RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[
PeripheralInterrupt {
signal: "CH0",
interrupt: "DMA1_STREAM0",
},
PeripheralInterrupt {
signal: "CH1",
interrupt: "DMA1_STREAM1",
},
PeripheralInterrupt {
signal: "CH2",
interrupt: "DMA1_STREAM2",
},
PeripheralInterrupt {
signal: "CH3",
interrupt: "DMA1_STREAM3",
},
PeripheralInterrupt {
signal: "CH4",
interrupt: "DMA1_STREAM4",
},
PeripheralInterrupt {
signal: "CH5",
interrupt: "DMA1_STREAM5",
},
PeripheralInterrupt {
signal: "CH6",
interrupt: "DMA1_STREAM6",
},
PeripheralInterrupt {
signal: "CH7",
interrupt: "DMA1_STREAM7",
},
],
afio: None,
},
Peripheral {
name: "DMA2",
address: 0x40026400,
registers: Some(PeripheralRegisters {
kind: "dma",
version: "v2",
block: "DMA",
ir: &dma::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "DMA2EN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "DMA2RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[
PeripheralInterrupt {
signal: "CH0",
interrupt: "DMA2_STREAM0",
},
PeripheralInterrupt {
signal: "CH1",
interrupt: "DMA2_STREAM1",
},
PeripheralInterrupt {
signal: "CH2",
interrupt: "DMA2_STREAM2",
},
PeripheralInterrupt {
signal: "CH3",
interrupt: "DMA2_STREAM3",
},
PeripheralInterrupt {
signal: "CH4",
interrupt: "DMA2_STREAM4",
},
PeripheralInterrupt {
signal: "CH5",
interrupt: "DMA2_STREAM5",
},
PeripheralInterrupt {
signal: "CH6",
interrupt: "DMA2_STREAM6",
},
PeripheralInterrupt {
signal: "CH7",
interrupt: "DMA2_STREAM7",
},
],
afio: None,
},
Peripheral {
name: "EXTI",
address: 0x40013c00,
registers: Some(PeripheralRegisters {
kind: "exti",
version: "v1",
block: "EXTI",
ir: &exti::REGISTERS,
}),
rcc: None,
pins: &[],
dma_channels: &[],
interrupts: &[
PeripheralInterrupt {
signal: "EXTI0",
interrupt: "EXTI0",
},
PeripheralInterrupt {
signal: "EXTI1",
interrupt: "EXTI1",
},
PeripheralInterrupt {
signal: "EXTI10",
interrupt: "EXTI15_10",
},
PeripheralInterrupt {
signal: "EXTI11",
interrupt: "EXTI15_10",
},
PeripheralInterrupt {
signal: "EXTI12",
interrupt: "EXTI15_10",
},
PeripheralInterrupt {
signal: "EXTI13",
interrupt: "EXTI15_10",
},
PeripheralInterrupt {
signal: "EXTI14",
interrupt: "EXTI15_10",
},
PeripheralInterrupt {
signal: "EXTI15",
interrupt: "EXTI15_10",
},
PeripheralInterrupt {
signal: "EXTI2",
interrupt: "EXTI2",
},
PeripheralInterrupt {
signal: "EXTI3",
interrupt: "EXTI3",
},
PeripheralInterrupt {
signal: "EXTI4",
interrupt: "EXTI4",
},
PeripheralInterrupt {
signal: "EXTI5",
interrupt: "EXTI9_5",
},
PeripheralInterrupt {
signal: "EXTI6",
interrupt: "EXTI9_5",
},
PeripheralInterrupt {
signal: "EXTI7",
interrupt: "EXTI9_5",
},
PeripheralInterrupt {
signal: "EXTI8",
interrupt: "EXTI9_5",
},
PeripheralInterrupt {
signal: "EXTI9",
interrupt: "EXTI9_5",
},
],
afio: None,
},
Peripheral {
name: "FLASH",
address: 0x40023c00,
registers: Some(PeripheralRegisters {
kind: "flash",
version: "f4",
block: "FLASH",
ir: &flash::REGISTERS,
}),
rcc: None,
pins: &[],
dma_channels: &[],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "FLASH",
}],
afio: None,
},
Peripheral {
name: "FMPI2C1",
address: 0x40006000,
registers: Some(PeripheralRegisters {
kind: "fmpi2c",
version: "v2",
block: "FMPI2C",
ir: &fmpi2c::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Mux(PeripheralRccRegister {
register: "DCKCFGR2",
field: "FMPI2C1SEL",
}),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "FMPI2C1EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "FMPI2C1RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA8",
signal: "SCL",
af: Some(4),
},
PeripheralPin {
pin: "PB10",
signal: "SCL",
af: Some(9),
},
PeripheralPin {
pin: "PB3",
signal: "SDA",
af: Some(4),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH0"),
dmamux: None,
remap: &[],
dma: None,
request: Some(7),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA1_CH1"),
dmamux: None,
remap: &[],
dma: None,
request: Some(2),
},
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH3"),
dmamux: None,
remap: &[],
dma: None,
request: Some(1),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA1_CH7"),
dmamux: None,
remap: &[],
dma: None,
request: Some(4),
},
],
interrupts: &[
PeripheralInterrupt {
signal: "ER",
interrupt: "FMPI2C1_ER",
},
PeripheralInterrupt {
signal: "EV",
interrupt: "FMPI2C1_EV",
},
],
afio: None,
},
Peripheral {
name: "GPIOA",
address: 0x40020000,
registers: Some(PeripheralRegisters {
kind: "gpio",
version: "v2",
block: "GPIO",
ir: &gpio::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "GPIOAEN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "GPIOARST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "GPIOB",
address: 0x40020400,
registers: Some(PeripheralRegisters {
kind: "gpio",
version: "v2",
block: "GPIO",
ir: &gpio::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "GPIOBEN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "GPIOBRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "GPIOC",
address: 0x40020800,
registers: Some(PeripheralRegisters {
kind: "gpio",
version: "v2",
block: "GPIO",
ir: &gpio::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "GPIOCEN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "GPIOCRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "GPIOH",
address: 0x40021c00,
registers: Some(PeripheralRegisters {
kind: "gpio",
version: "v2",
block: "GPIO",
ir: &gpio::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "GPIOHEN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "GPIOHRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "I2C1",
address: 0x40005400,
registers: Some(PeripheralRegisters {
kind: "i2c",
version: "v1",
block: "I2C",
ir: &i2c::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "I2C1EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "I2C1RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PB5",
signal: "SMBA",
af: Some(4),
},
PeripheralPin {
pin: "PB6",
signal: "SCL",
af: Some(4),
},
PeripheralPin {
pin: "PB7",
signal: "SDA",
af: Some(4),
},
PeripheralPin {
pin: "PB8",
signal: "SCL",
af: Some(4),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH0"),
dmamux: None,
remap: &[],
dma: None,
request: Some(1),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA1_CH1"),
dmamux: None,
remap: &[],
dma: None,
request: Some(0),
},
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH5"),
dmamux: None,
remap: &[],
dma: None,
request: Some(1),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA1_CH6"),
dmamux: None,
remap: &[],
dma: None,
request: Some(1),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA1_CH7"),
dmamux: None,
remap: &[],
dma: None,
request: Some(1),
},
],
interrupts: &[
PeripheralInterrupt {
signal: "ER",
interrupt: "I2C1_ER",
},
PeripheralInterrupt {
signal: "EV",
interrupt: "I2C1_EV",
},
],
afio: None,
},
Peripheral {
name: "I2C2",
address: 0x40005800,
registers: Some(PeripheralRegisters {
kind: "i2c",
version: "v1",
block: "I2C",
ir: &i2c::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "I2C2EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "I2C2RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PB10",
signal: "SCL",
af: Some(4),
},
PeripheralPin {
pin: "PB12",
signal: "SMBA",
af: Some(4),
},
PeripheralPin {
pin: "PB3",
signal: "SDA",
af: Some(9),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH2"),
dmamux: None,
remap: &[],
dma: None,
request: Some(7),
},
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH3"),
dmamux: None,
remap: &[],
dma: None,
request: Some(7),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA1_CH7"),
dmamux: None,
remap: &[],
dma: None,
request: Some(7),
},
],
interrupts: &[
PeripheralInterrupt {
signal: "ER",
interrupt: "I2C2_ER",
},
PeripheralInterrupt {
signal: "EV",
interrupt: "I2C2_EV",
},
],
afio: None,
},
Peripheral {
name: "IWDG",
address: 0x40003000,
registers: Some(PeripheralRegisters {
kind: "iwdg",
version: "v1",
block: "IWDG",
ir: &iwdg::REGISTERS,
}),
rcc: None,
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "LPTIM1",
address: 0x40002400,
registers: Some(PeripheralRegisters {
kind: "lptim",
version: "v1a",
block: "LPTIM",
ir: &lptim::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Mux(PeripheralRccRegister {
register: "DCKCFGR2",
field: "LPTIM1SEL",
}),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "LPTIM1EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "LPTIM1RST",
}),
stop_mode: StopMode::Stop2,
}),
pins: &[
PeripheralPin {
pin: "PB2",
signal: "OUT",
af: Some(1),
},
PeripheralPin {
pin: "PB5",
signal: "IN1",
af: Some(1),
},
PeripheralPin {
pin: "PB6",
signal: "ETR",
af: Some(1),
},
PeripheralPin {
pin: "PB7",
signal: "IN2",
af: Some(1),
},
PeripheralPin {
pin: "PB8",
signal: "OUT",
af: Some(1),
},
],
dma_channels: &[],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "LPTIM1",
}],
afio: None,
},
Peripheral {
name: "PWR",
address: 0x40007000,
registers: Some(PeripheralRegisters {
kind: "pwr",
version: "f4",
block: "PWR",
ir: &pwr::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "PWREN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "PWRRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "RCC",
address: 0x40023800,
registers: Some(PeripheralRegisters {
kind: "rcc",
version: "f410",
block: "RCC",
ir: &rcc::REGISTERS,
}),
rcc: None,
pins: &[
PeripheralPin {
pin: "PA8",
signal: "MCO_1",
af: Some(0),
},
PeripheralPin {
pin: "PC14",
signal: "OSC32_IN",
af: None,
},
PeripheralPin {
pin: "PC15",
signal: "OSC32_OUT",
af: None,
},
PeripheralPin {
pin: "PH0",
signal: "OSC_IN",
af: None,
},
PeripheralPin {
pin: "PH1",
signal: "OSC_OUT",
af: None,
},
],
dma_channels: &[],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "RCC",
}],
afio: None,
},
Peripheral {
name: "RNG",
address: 0x40080000,
registers: Some(PeripheralRegisters {
kind: "rng",
version: "v1",
block: "RNG",
ir: &rng::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "HCLK1",
kernel_clock: Clock("HCLK1"),
enable: Some(PeripheralRccRegister {
register: "AHB1ENR",
field: "RNGEN",
}),
reset: Some(PeripheralRccRegister {
register: "AHB1RSTR",
field: "RNGRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "RNG",
}],
afio: None,
},
Peripheral {
name: "RTC",
address: 0x40002800,
registers: Some(PeripheralRegisters {
kind: "rtc",
version: "v2f4",
block: "RTC",
ir: &rtc::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Mux(PeripheralRccRegister {
register: "BDCR",
field: "RTCSEL",
}),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "RTCAPBEN",
}),
reset: None,
stop_mode: StopMode::Standby,
}),
pins: &[PeripheralPin {
pin: "PC13",
signal: "AF1",
af: None,
}],
dma_channels: &[],
interrupts: &[
PeripheralInterrupt {
signal: "ALARM",
interrupt: "RTC_ALARM",
},
PeripheralInterrupt {
signal: "STAMP",
interrupt: "TAMP_STAMP",
},
PeripheralInterrupt {
signal: "TAMP",
interrupt: "TAMP_STAMP",
},
PeripheralInterrupt {
signal: "WKUP",
interrupt: "RTC_WKUP",
},
],
afio: None,
},
Peripheral {
name: "SPI1",
address: 0x40013000,
registers: Some(PeripheralRegisters {
kind: "spi",
version: "v1",
block: "SPI",
ir: &spi::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK2",
kernel_clock: Clock("PCLK2"),
enable: Some(PeripheralRccRegister {
register: "APB2ENR",
field: "SPI1EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB2RSTR",
field: "SPI1RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA15",
signal: "I2S_WS",
af: Some(5),
},
PeripheralPin {
pin: "PA15",
signal: "NSS",
af: Some(5),
},
PeripheralPin {
pin: "PA5",
signal: "I2S_CK",
af: Some(5),
},
PeripheralPin {
pin: "PA5",
signal: "SCK",
af: Some(5),
},
PeripheralPin {
pin: "PB10",
signal: "I2S_MCK",
af: Some(6),
},
PeripheralPin {
pin: "PB3",
signal: "I2S_CK",
af: Some(5),
},
PeripheralPin {
pin: "PB3",
signal: "SCK",
af: Some(5),
},
PeripheralPin {
pin: "PB4",
signal: "MISO",
af: Some(5),
},
PeripheralPin {
pin: "PB5",
signal: "I2S_SD",
af: Some(5),
},
PeripheralPin {
pin: "PB5",
signal: "MOSI",
af: Some(5),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA2_CH0"),
dmamux: None,
remap: &[],
dma: None,
request: Some(3),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA2_CH2"),
dmamux: None,
remap: &[],
dma: None,
request: Some(2),
},
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA2_CH2"),
dmamux: None,
remap: &[],
dma: None,
request: Some(3),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA2_CH3"),
dmamux: None,
remap: &[],
dma: None,
request: Some(3),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA2_CH5"),
dmamux: None,
remap: &[],
dma: None,
request: Some(3),
},
],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "SPI1",
}],
afio: None,
},
Peripheral {
name: "SYSCFG",
address: 0x40013800,
registers: Some(PeripheralRegisters {
kind: "syscfg",
version: "f4",
block: "SYSCFG",
ir: &syscfg::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK2",
kernel_clock: Clock("PCLK2"),
enable: Some(PeripheralRccRegister {
register: "APB2ENR",
field: "SYSCFGEN",
}),
reset: Some(PeripheralRccRegister {
register: "APB2RSTR",
field: "SYSCFGRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "TIM1",
address: 0x40010000,
registers: Some(PeripheralRegisters {
kind: "timer",
version: "v1",
block: "TIM_ADV",
ir: &timer::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK2",
kernel_clock: Clock("PCLK2_TIM"),
enable: Some(PeripheralRccRegister {
register: "APB2ENR",
field: "TIM1EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB2RSTR",
field: "TIM1RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA12",
signal: "ETR",
af: Some(1),
},
PeripheralPin {
pin: "PA8",
signal: "CH1",
af: Some(1),
},
PeripheralPin {
pin: "PB12",
signal: "BKIN",
af: Some(1),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "TRIG",
channel: Some("DMA2_CH0"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH1",
channel: Some("DMA2_CH1"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH2",
channel: Some("DMA2_CH2"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH1",
channel: Some("DMA2_CH3"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH4",
channel: Some("DMA2_CH4"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "TRIG",
channel: Some("DMA2_CH4"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "COM",
channel: Some("DMA2_CH4"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "UP",
channel: Some("DMA2_CH5"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH1",
channel: Some("DMA2_CH6"),
dmamux: None,
remap: &[],
dma: None,
request: Some(0),
},
PeripheralDmaChannel {
signal: "CH2",
channel: Some("DMA2_CH6"),
dmamux: None,
remap: &[],
dma: None,
request: Some(0),
},
PeripheralDmaChannel {
signal: "CH3",
channel: Some("DMA2_CH6"),
dmamux: None,
remap: &[],
dma: None,
request: Some(0),
},
PeripheralDmaChannel {
signal: "CH3",
channel: Some("DMA2_CH6"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
],
interrupts: &[
PeripheralInterrupt {
signal: "BRK",
interrupt: "TIM1_BRK_TIM9",
},
PeripheralInterrupt {
signal: "CC",
interrupt: "TIM1_CC",
},
PeripheralInterrupt {
signal: "COM",
interrupt: "TIM1_TRG_COM_TIM11",
},
PeripheralInterrupt {
signal: "TRG",
interrupt: "TIM1_TRG_COM_TIM11",
},
PeripheralInterrupt {
signal: "UP",
interrupt: "TIM1_UP",
},
],
afio: None,
},
Peripheral {
name: "TIM11",
address: 0x40014800,
registers: Some(PeripheralRegisters {
kind: "timer",
version: "v1",
block: "TIM_1CH",
ir: &timer::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK2",
kernel_clock: Clock("PCLK2_TIM"),
enable: Some(PeripheralRccRegister {
register: "APB2ENR",
field: "TIM11EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB2RSTR",
field: "TIM11RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[
PeripheralInterrupt {
signal: "BRK",
interrupt: "TIM1_TRG_COM_TIM11",
},
PeripheralInterrupt {
signal: "CC",
interrupt: "TIM1_TRG_COM_TIM11",
},
PeripheralInterrupt {
signal: "COM",
interrupt: "TIM1_TRG_COM_TIM11",
},
PeripheralInterrupt {
signal: "TRG",
interrupt: "TIM1_TRG_COM_TIM11",
},
PeripheralInterrupt {
signal: "UP",
interrupt: "TIM1_TRG_COM_TIM11",
},
],
afio: None,
},
Peripheral {
name: "TIM5",
address: 0x40000c00,
registers: Some(PeripheralRegisters {
kind: "timer",
version: "v1",
block: "TIM_GP32",
ir: &timer::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1_TIM"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "TIM5EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "TIM5RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA0",
signal: "CH1",
af: Some(2),
},
PeripheralPin {
pin: "PA2",
signal: "CH3",
af: Some(2),
},
PeripheralPin {
pin: "PA3",
signal: "CH4",
af: Some(2),
},
PeripheralPin {
pin: "PB12",
signal: "CH1",
af: Some(2),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "CH3",
channel: Some("DMA1_CH0"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "UP",
channel: Some("DMA1_CH0"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH4",
channel: Some("DMA1_CH1"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "TRIG",
channel: Some("DMA1_CH1"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH1",
channel: Some("DMA1_CH2"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH4",
channel: Some("DMA1_CH3"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "TRIG",
channel: Some("DMA1_CH3"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "CH2",
channel: Some("DMA1_CH4"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
PeripheralDmaChannel {
signal: "UP",
channel: Some("DMA1_CH6"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
],
interrupts: &[
PeripheralInterrupt {
signal: "BRK",
interrupt: "TIM5",
},
PeripheralInterrupt {
signal: "CC",
interrupt: "TIM5",
},
PeripheralInterrupt {
signal: "COM",
interrupt: "TIM5",
},
PeripheralInterrupt {
signal: "TRG",
interrupt: "TIM5",
},
PeripheralInterrupt {
signal: "UP",
interrupt: "TIM5",
},
],
afio: None,
},
Peripheral {
name: "TIM6",
address: 0x40001000,
registers: Some(PeripheralRegisters {
kind: "timer",
version: "v1",
block: "TIM_BASIC",
ir: &timer::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1_TIM"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "TIM6EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "TIM6RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[PeripheralDmaChannel {
signal: "UP",
channel: Some("DMA1_CH1"),
dmamux: None,
remap: &[],
dma: None,
request: Some(7),
}],
interrupts: &[
PeripheralInterrupt {
signal: "BRK",
interrupt: "TIM6_DAC",
},
PeripheralInterrupt {
signal: "CC",
interrupt: "TIM6_DAC",
},
PeripheralInterrupt {
signal: "COM",
interrupt: "TIM6_DAC",
},
PeripheralInterrupt {
signal: "TRG",
interrupt: "TIM6_DAC",
},
PeripheralInterrupt {
signal: "UP",
interrupt: "TIM6_DAC",
},
],
afio: None,
},
Peripheral {
name: "TIM9",
address: 0x40014000,
registers: Some(PeripheralRegisters {
kind: "timer",
version: "v1",
block: "TIM_2CH",
ir: &timer::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK2",
kernel_clock: Clock("PCLK2_TIM"),
enable: Some(PeripheralRccRegister {
register: "APB2ENR",
field: "TIM9EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB2RSTR",
field: "TIM9RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA2",
signal: "CH1",
af: Some(3),
},
PeripheralPin {
pin: "PA3",
signal: "CH2",
af: Some(3),
},
],
dma_channels: &[],
interrupts: &[
PeripheralInterrupt {
signal: "BRK",
interrupt: "TIM1_BRK_TIM9",
},
PeripheralInterrupt {
signal: "CC",
interrupt: "TIM1_BRK_TIM9",
},
PeripheralInterrupt {
signal: "COM",
interrupt: "TIM1_BRK_TIM9",
},
PeripheralInterrupt {
signal: "TRG",
interrupt: "TIM1_BRK_TIM9",
},
PeripheralInterrupt {
signal: "UP",
interrupt: "TIM1_BRK_TIM9",
},
],
afio: None,
},
Peripheral {
name: "UID",
address: 0x1fff7a10,
registers: Some(PeripheralRegisters {
kind: "uid",
version: "v1",
block: "UID",
ir: &uid::REGISTERS,
}),
rcc: None,
pins: &[],
dma_channels: &[],
interrupts: &[],
afio: None,
},
Peripheral {
name: "USART1",
address: 0x40011000,
registers: Some(PeripheralRegisters {
kind: "usart",
version: "v2",
block: "USART",
ir: &usart::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK2",
kernel_clock: Clock("PCLK2"),
enable: Some(PeripheralRccRegister {
register: "APB2ENR",
field: "USART1EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB2RSTR",
field: "USART1RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA12",
signal: "RTS",
af: Some(7),
},
PeripheralPin {
pin: "PA15",
signal: "TX",
af: Some(7),
},
PeripheralPin {
pin: "PA8",
signal: "CK",
af: Some(7),
},
PeripheralPin {
pin: "PB3",
signal: "RX",
af: Some(7),
},
PeripheralPin {
pin: "PB6",
signal: "TX",
af: Some(7),
},
PeripheralPin {
pin: "PB7",
signal: "RX",
af: Some(7),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA2_CH2"),
dmamux: None,
remap: &[],
dma: None,
request: Some(4),
},
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA2_CH5"),
dmamux: None,
remap: &[],
dma: None,
request: Some(4),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA2_CH7"),
dmamux: None,
remap: &[],
dma: None,
request: Some(4),
},
],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "USART1",
}],
afio: None,
},
Peripheral {
name: "USART2",
address: 0x40004400,
registers: Some(PeripheralRegisters {
kind: "usart",
version: "v2",
block: "USART",
ir: &usart::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "USART2EN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "USART2RST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[
PeripheralPin {
pin: "PA0",
signal: "CTS",
af: Some(7),
},
PeripheralPin {
pin: "PA2",
signal: "TX",
af: Some(7),
},
PeripheralPin {
pin: "PA3",
signal: "RX",
af: Some(7),
},
],
dma_channels: &[
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH5"),
dmamux: None,
remap: &[],
dma: None,
request: Some(4),
},
PeripheralDmaChannel {
signal: "TX",
channel: Some("DMA1_CH6"),
dmamux: None,
remap: &[],
dma: None,
request: Some(4),
},
PeripheralDmaChannel {
signal: "RX",
channel: Some("DMA1_CH7"),
dmamux: None,
remap: &[],
dma: None,
request: Some(6),
},
],
interrupts: &[PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "USART2",
}],
afio: None,
},
Peripheral {
name: "WWDG",
address: 0x40002c00,
registers: Some(PeripheralRegisters {
kind: "wwdg",
version: "v1",
block: "WWDG",
ir: &wwdg::REGISTERS,
}),
rcc: Some(PeripheralRcc {
bus_clock: "PCLK1",
kernel_clock: Clock("PCLK1"),
enable: Some(PeripheralRccRegister {
register: "APB1ENR",
field: "WWDGEN",
}),
reset: Some(PeripheralRccRegister {
register: "APB1RSTR",
field: "WWDGRST",
}),
stop_mode: StopMode::Stop1,
}),
pins: &[],
dma_channels: &[],
interrupts: &[
PeripheralInterrupt {
signal: "GLOBAL",
interrupt: "WWDG",
},
PeripheralInterrupt {
signal: "RST",
interrupt: "WWDG",
},
],
afio: None,
},
];
pub(crate) static INTERRUPTS: &[Interrupt] = &[
Interrupt {
name: "WWDG",
number: 0,
},
Interrupt { name: "PVD", number: 1 },
Interrupt {
name: "TAMP_STAMP",
number: 2,
},
Interrupt {
name: "RTC_WKUP",
number: 3,
},
Interrupt {
name: "FLASH",
number: 4,
},
Interrupt { name: "RCC", number: 5 },
Interrupt {
name: "EXTI0",
number: 6,
},
Interrupt {
name: "EXTI1",
number: 7,
},
Interrupt {
name: "EXTI2",
number: 8,
},
Interrupt {
name: "EXTI3",
number: 9,
},
Interrupt {
name: "EXTI4",
number: 10,
},
Interrupt {
name: "DMA1_STREAM0",
number: 11,
},
Interrupt {
name: "DMA1_STREAM1",
number: 12,
},
Interrupt {
name: "DMA1_STREAM2",
number: 13,
},
Interrupt {
name: "DMA1_STREAM3",
number: 14,
},
Interrupt {
name: "DMA1_STREAM4",
number: 15,
},
Interrupt {
name: "DMA1_STREAM5",
number: 16,
},
Interrupt {
name: "DMA1_STREAM6",
number: 17,
},
Interrupt {
name: "ADC",
number: 18,
},
Interrupt {
name: "EXTI9_5",
number: 23,
},
Interrupt {
name: "TIM1_BRK_TIM9",
number: 24,
},
Interrupt {
name: "TIM1_UP",
number: 25,
},
Interrupt {
name: "TIM1_TRG_COM_TIM11",
number: 26,
},
Interrupt {
name: "TIM1_CC",
number: 27,
},
Interrupt {
name: "I2C1_EV",
number: 31,
},
Interrupt {
name: "I2C1_ER",
number: 32,
},
Interrupt {
name: "I2C2_EV",
number: 33,
},
Interrupt {
name: "I2C2_ER",
number: 34,
},
Interrupt {
name: "SPI1",
number: 35,
},
Interrupt {
name: "USART1",
number: 37,
},
Interrupt {
name: "USART2",
number: 38,
},
Interrupt {
name: "EXTI15_10",
number: 40,
},
Interrupt {
name: "RTC_ALARM",
number: 41,
},
Interrupt {
name: "DMA1_STREAM7",
number: 47,
},
Interrupt {
name: "TIM5",
number: 50,
},
Interrupt {
name: "TIM6_DAC",
number: 54,
},
Interrupt {
name: "DMA2_STREAM0",
number: 56,
},
Interrupt {
name: "DMA2_STREAM1",
number: 57,
},
Interrupt {
name: "DMA2_STREAM2",
number: 58,
},
Interrupt {
name: "DMA2_STREAM3",
number: 59,
},
Interrupt {
name: "DMA2_STREAM4",
number: 60,
},
Interrupt {
name: "DMA2_STREAM5",
number: 68,
},
Interrupt {
name: "DMA2_STREAM6",
number: 69,
},
Interrupt {
name: "DMA2_STREAM7",
number: 70,
},
Interrupt {
name: "RNG",
number: 80,
},
Interrupt {
name: "FPU",
number: 81,
},
Interrupt {
name: "FMPI2C1_EV",
number: 95,
},
Interrupt {
name: "FMPI2C1_ER",
number: 96,
},
Interrupt {
name: "LPTIM1",
number: 97,
},
];
pub(crate) static DMA_CHANNELS: &[DmaChannel] = &[
DmaChannel {
name: "DMA1_CH0",
dma: "DMA1",
channel: 0,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA1_CH1",
dma: "DMA1",
channel: 1,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA1_CH2",
dma: "DMA1",
channel: 2,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA1_CH3",
dma: "DMA1",
channel: 3,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA1_CH4",
dma: "DMA1",
channel: 4,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA1_CH5",
dma: "DMA1",
channel: 5,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA1_CH6",
dma: "DMA1",
channel: 6,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA1_CH7",
dma: "DMA1",
channel: 7,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH0",
dma: "DMA2",
channel: 0,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH1",
dma: "DMA2",
channel: 1,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH2",
dma: "DMA2",
channel: 2,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH3",
dma: "DMA2",
channel: 3,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH4",
dma: "DMA2",
channel: 4,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH5",
dma: "DMA2",
channel: 5,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH6",
dma: "DMA2",
channel: 6,
dmamux: None,
dmamux_channel: None,
},
DmaChannel {
name: "DMA2_CH7",
dma: "DMA2",
channel: 7,
dmamux: None,
dmamux_channel: None,
},
];
pub(crate) static PINS: &[Pin] = &[
Pin { name: "PA0" },
Pin { name: "PA2" },
Pin { name: "PA3" },
Pin { name: "PA5" },
Pin { name: "PA8" },
Pin { name: "PA12" },
Pin { name: "PA13" },
Pin { name: "PA14" },
Pin { name: "PA15" },
Pin { name: "PB2" },
Pin { name: "PB3" },
Pin { name: "PB4" },
Pin { name: "PB5" },
Pin { name: "PB6" },
Pin { name: "PB7" },
Pin { name: "PB8" },
Pin { name: "PB10" },
Pin { name: "PB12" },
Pin { name: "PC13" },
Pin { name: "PC14" },
Pin { name: "PC15" },
Pin { name: "PH0" },
Pin { name: "PH1" },
];
#[path = "../registers/adc_v2.rs"]
pub mod adc;
#[path = "../registers/adccommon_v2.rs"]
pub mod adccommon;
#[path = "../registers/crc_v1.rs"]
pub mod crc;
#[path = "../registers/dac_v2.rs"]
pub mod dac;
#[path = "../registers/dbgmcu_f4.rs"]
pub mod dbgmcu;
#[path = "../registers/dma_v2.rs"]
pub mod dma;
#[path = "../registers/exti_v1.rs"]
pub mod exti;
#[path = "../registers/flash_f4.rs"]
pub mod flash;
#[path = "../registers/fmpi2c_v2.rs"]
pub mod fmpi2c;
#[path = "../registers/gpio_v2.rs"]
pub mod gpio;
#[path = "../registers/i2c_v1.rs"]
pub mod i2c;
#[path = "../registers/iwdg_v1.rs"]
pub mod iwdg;
#[path = "../registers/lptim_v1a.rs"]
pub mod lptim;
#[path = "../registers/pwr_f4.rs"]
pub mod pwr;
#[path = "../registers/rcc_f410.rs"]
pub mod rcc;
#[path = "../registers/rng_v1.rs"]
pub mod rng;
#[path = "../registers/rtc_v2f4.rs"]
pub mod rtc;
#[path = "../registers/spi_v1.rs"]
pub mod spi;
#[path = "../registers/syscfg_f4.rs"]
pub mod syscfg;
#[path = "../registers/timer_v1.rs"]
pub mod timer;
#[path = "../registers/uid_v1.rs"]
pub mod uid;
#[path = "../registers/usart_v2.rs"]
pub mod usart;
#[path = "../registers/wwdg_v1.rs"]
pub mod wwdg;