Enum stm32_hal2::timer::OutputCompare

#[repr(u8)]
pub enum OutputCompare {
    Frozen,
    Active,
    Inactive,
    Toggle,
    ForceInactive,
    ForceActive,
    Pwm1,
    Pwm2,
    RetriggerableOpmMode1,
    RetriggerableOpmMode2,
    CombinedPwm1,
    CombinedPwm2,
    AsymmetricPwm1,
    AsymmetricPwm2,
}

See F303 ref man, section 21.4.7. H745 RM, section 41.4.8. Sets TIMx_CCMR1 register, OC1M field. These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.

Variants

Frozen

Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

Active

Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

Inactive

Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

Toggle

tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1.

ForceInactive

Force inactive level - OC1REF is forced low.

ForceActive

Force active level - OC1REF is forced high.

Pwm1

PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).

Pwm2

PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.

RetriggerableOpmMode1

Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.

RetriggerableOpmMode2

Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.

CombinedPwm1

Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF.

CombinedPwm2

Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF.

AsymmetricPwm1

Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.

AsymmetricPwm2

Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. /// OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down

Trait Implementations

impl Clone for OutputCompare

fn clone(&self) -> OutputCompare

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for OutputCompare