st77916 0.1.1

// ST77916 Command Set
// Reference: ST77916 Datasheet V1.0, Sitronix Technology Corporation, 2022/08
//
// Section 13.1 — Page Set Table (CSC1–CSC4)
// Section 13.2 — Command Table 1 (standard MIPI DCS)
// Section 13.3 — Command Table 2 (manufacturer command set, requires page select)

// ---------------------------------------------------------------------------
// Page Set / Command Set Control (Section 13.1, p.141–145)
// ---------------------------------------------------------------------------

/// Command Set Ctrl 1 — selects which command pages are active.
///
/// Parameter byte enables/disables command pages:
///   0x00 — all pages disabled (default)
///   0x02 — gamma page enable
///   0x01/0x01 — command2 page enable
///   0x08 — test command page enable
///   0x80/0x40 — CDC command page enable
///   0x10 — GIP command page enable
pub const CSC1: u8 = 0xF0;

/// Command Set Ctrl 2 — command2 protocol select.
pub const CSC2: u8 = 0xF1;

/// Command Set Ctrl 3 — test/CDC protocol select.
pub const CSC3: u8 = 0xF2;

/// Command Set Ctrl 4 — GIP protocol select.
pub const CSC4: u8 = 0xF3;

/// SPI Others Read — enable/disable SPI read for command table 2.
pub const SPIOR: u8 = 0xF4;

// ---------------------------------------------------------------------------
// Command Table 1 — Standard Commands (Section 13.2, p.146–213)
// ---------------------------------------------------------------------------

/// No Operation (p.153)
pub const NOP: u8 = 0x00;

/// Software Reset (p.153)
pub const SWRESET: u8 = 0x01;

/// Read Display ID (p.155) — returns ID1, ID2, ID3
pub const RDDID: u8 = 0x04;

/// Read Display Status (p.155)
pub const RDDST: u8 = 0x09;

/// Read Display Power Mode (p.156)
pub const RDDPM: u8 = 0x0A;

/// Read Display MADCTL (p.157)
pub const RDDMADCTL: u8 = 0x0B;

/// Read Display Pixel Format (p.159)
pub const RDDCOLMOD: u8 = 0x0C;

/// Read Display Image Mode (p.160)
pub const RDDIM: u8 = 0x0D;

/// Read Display Signal Mode (p.160)
pub const RDDSM: u8 = 0x0E;

/// Read Busy Status (p.161)
pub const RDBST: u8 = 0x0F;

/// Sleep In (p.161)
pub const SLPIN: u8 = 0x10;

/// Sleep Out (p.163) — 120ms delay required after this command
pub const SLPOUT: u8 = 0x11;

/// Normal Off / Partial Mode On (p.164)
pub const NOROFF: u8 = 0x12;

/// Normal On (p.166)
pub const NORON: u8 = 0x13;

/// Display Inversion Off (p.166)
pub const INVOFF: u8 = 0x20;

/// Display Inversion On (p.168)
pub const INVON: u8 = 0x21;

/// Display Off (p.169)
pub const DISPOFF: u8 = 0x28;

/// Display On (p.171)
pub const DISPON: u8 = 0x29;

/// Column Address Set (p.172) — 4 params: `XS[15:8]`, `XS[7:0]`, `XE[15:8]`, `XE[7:0]`
pub const CASET: u8 = 0x2A;

/// Row Address Set (p.173) — 4 params: `YS[15:8]`, `YS[7:0]`, `YE[15:8]`, `YE[7:0]`
pub const RASET: u8 = 0x2B;

/// Memory Write (p.175)
pub const RAMWR: u8 = 0x2C;

/// Memory Read (p.176)
pub const RAMRD: u8 = 0x2E;

/// Vertical Scrolling Definition (p.177)
pub const VSCRDEF: u8 = 0x33;

/// Tearing Effect Line Off (p.179)
pub const TEOFF: u8 = 0x34;

/// Tearing Effect Line On (p.181) — 1 param: TE_MD
pub const TEON: u8 = 0x35;

/// Memory Data Access Control (p.182)
///
/// Parameter bits:
///   D7: MY  — Row address order
///   D6: MX  — Column address order
///   D5: MV  — Row/column exchange
///   D4: ML  — Vertical refresh order
///   D3: RGB — RGB/BGR order (0=RGB, 1=BGR)
///   D2: MH  — Horizontal refresh order
///   D1: HSD — Horizontal scan direction
pub const MADCTL: u8 = 0x36;

/// Vertical Scroll Start Address (p.185)
pub const VSCSAD: u8 = 0x37;

/// Idle Mode Off (p.186)
pub const IDMOFF: u8 = 0x38;

/// Idle Mode On (p.187)
pub const IDMON: u8 = 0x39;

/// Interface Pixel Format (p.190)
///
/// Parameter bits:
///   D6–D4: VIPF — RGB interface pixel format
///   D2–D0: IFPF — MCU/SPI interface pixel format
///     0x55 = 16-bit/pixel (RGB565)
///     0x66 = 18-bit/pixel (RGB666)
pub const COLMOD: u8 = 0x3A;

/// Memory Write Continue (p.191)
pub const RAMWRC: u8 = 0x3C;

/// Memory Read Continue (p.193)
pub const RAMRDC: u8 = 0x3E;

/// Horizontal Scrolling Definition (p.195)
pub const HSCRDEF: u8 = 0x43;

/// Write Tear Scanline (p.197) — 2 params
pub const TESLWR: u8 = 0x44;

/// Read Tear Scanline (p.199)
pub const TESLRD: u8 = 0x45;

/// Horizontal Scroll Start Address (p.200)
pub const HSCRSADD: u8 = 0x47;

/// Compress On (p.201)
pub const CPON: u8 = 0x4A;

/// Compress Off (p.201)
pub const CPOFF: u8 = 0x4B;

/// Memory Clear Act (p.201)
pub const RAMCLACT: u8 = 0x4C;

/// Memory Clear Set R (p.202)
pub const RAMCLSETR: u8 = 0x4D;

/// Memory Clear Set G (p.203)
pub const RAMCLSETG: u8 = 0x4E;

/// Memory Clear Set B (p.203)
pub const RAMCLSETB: u8 = 0x4F;

/// CDC Control (p.204)
pub const CDCCTR: u8 = 0x50;

/// Write Display Brightness (p.204)
pub const WRDISBV: u8 = 0x51;

/// Read Display Brightness (p.206)
pub const RDDISBV: u8 = 0x52;

/// Write CTRL Display (p.207)
pub const WRCTRLD: u8 = 0x53;

/// Read CTRL Display (p.208)
pub const RDCTRLD: u8 = 0x54;

/// Read ID1 (p.212)
pub const RDID1: u8 = 0xDA;

/// Read ID2 (p.212)
pub const RDID2: u8 = 0xDB;

/// Read ID3 (p.213)
pub const RDID3: u8 = 0xDC;

// ---------------------------------------------------------------------------
// Command Table 2 — Manufacturer Command Set (Section 13.3, p.214–263)
// These registers require page select via CSC1–CSC4 before access.
// ---------------------------------------------------------------------------

/// VRHP Set (p.217) — Positive gamma source driver voltage.
/// Parameter: `VRHP[6:0]` → VAP(GVDD) = 3.650V + VRHP * 0.025V + vcom_offset
pub const VRHPS: u8 = 0xB0;

/// VRHN Set (p.220) — Negative gamma source driver voltage.
/// Parameter: `VRHN[6:0]` → VAN(GVCL) = -(1.875V + VRHN * 0.025V + vcom_offset)
pub const VRHNS: u8 = 0xB1;

/// VCOM GND Set (p.222) — Feed-through voltage compensation.
/// Parameter: `VCM[6:0]` → VSF = 0.100V + VCM * 0.025V (range 0.1V–2.2V)
pub const VCOMS: u8 = 0xB2;

/// GVDD/GVEE Set (p.224) — Gamma OP power set.
/// Parameter byte: `GVEE_AD[3:0]` (high nibble) | `GVDD_AD[3:0]` (low nibble)
///   GVDD_AD: positive gamma OP voltage (5.5V–7.0V)
///   GVEE_AD: negative gamma OP voltage (-3.4V to -4.9V)
pub const GAMOPPS: u8 = 0xB4;

/// STEP SET1 (p.225) — AVCL and AVDD voltage settings.
/// Parameter byte: `AVCLS[2:0]` (high bits) | `AVDDS[2:0]` (low bits)
///   AVCLS: AVCL voltage (-3.08V to -5.00V)
///   AVDDS: AVDD voltage (5.52V to 6.99V)
pub const STEP14S: u8 = 0xB5;

/// STEP SET2 (p.227) — VGL and VGH/VGHS voltage settings.
/// Parameter byte: `VGLS[3:0]` (high nibble) | `VGHS[3:0]` (low nibble)
///   VGLS: VGL voltage (-6.80V to -12.75V)
///   VGHS: VGH/VGHS voltage (7.5V to 17.0V)
pub const STEP23S: u8 = 0xB6;

/// SVDD_SVCL_SET (p.228) — SVDD and SVCL voltage settings.
/// Parameter byte: `SELN[2:0]` (high bits) | `SELP[1:0]` (low bits)
///   SELN: SVCL voltage (-3.346V to -4.788V)
///   SELP: SVDD voltage (6.243V to 6.794V)
pub const SBSTS: u8 = 0xB7;

/// TCON_SET (p.230) — Timing controller settings.
/// Parameter byte: `GATE_TUNE[2:0]` | `NLINE[1:0]`
///   NLINE: dot inversion select (1/2/4 line)
pub const TCONS: u8 = 0xBA;

/// RGB_VBP (p.231) — RGB vertical back porch.
/// Parameter: `VBP[6:0]`
pub const RGBVBP: u8 = 0xBB;

/// RGB_HBP (p.231) — RGB horizontal back porch.
/// Parameter: `HBP[6:0]`
pub const RGBHBP: u8 = 0xBC;

/// RGB_SET (p.232) — RGB interface configuration.
/// Parameter byte: RGB_DCL, KPOL_XOR, RGB_DEP, RGB_HDP_OL_XOR, RGB_VDP_OL_XOR, WO, RCM
pub const RGBSET: u8 = 0xBD;

/// Frame Rate Control A1 in Normal Mode (p.235)
/// Parameters: NLA, `BPFPA[12:0]`
pub const FRCTRA1: u8 = 0xC0;

/// Frame Rate Control A2 in Normal Mode (p.236)
/// Parameter: `BPFPA[7:0]`
pub const FRCTRA2: u8 = 0xC1;

/// Frame Rate Control A3 in Normal Mode (p.236)
/// Parameter: `RTNA[7:0]`
pub const FRCTRA3: u8 = 0xC2;

/// Frame Rate Control B1 in Idle Mode (p.239)
pub const FRCTRB1: u8 = 0xC3;

/// Frame Rate Control B2 in Idle Mode (p.240)
pub const FRCTRB2: u8 = 0xC4;

/// Frame Rate Control B3 in Idle Mode (p.241)
pub const FRCTRB3: u8 = 0xC5;

/// Power Control A1 in Normal Mode (p.244)
/// Parameter: `DCA3[1:0]`, `DCA2S[1:0]`, `DCA2[1:0]`, `DCA1[1:0]`
pub const PWRCTRA1: u8 = 0xC6;

/// Power Control A2 in Normal Mode (p.245)
/// Parameter: `APA[2:0]`, `SAPA[1:0]`, `DCA4[1:0]`
pub const PWRCTRA2: u8 = 0xC7;

/// Power Control A3 in Normal Mode (p.246)
/// Parameter: `CLK_SNA[1:0]`, `CLK_SPA[1:0]`, `CLK_HYA[1:0]`
pub const PWRCTRA3: u8 = 0xC8;

/// Power Control B1 in Idle Mode (p.247)
pub const PWRCTRB1: u8 = 0xC9;

/// Power Control B2 in Idle Mode (p.248)
pub const PWRCTRB2: u8 = 0xCA;

/// Power Control B3 in Idle Mode (p.250)
pub const PWRCTRB3: u8 = 0xCB;

/// DSTB_DSLP (p.252) — Deep standby / deep sleep enable.
/// Parameter: DSTB_EN, DSLP_EN
pub const DSTBDSLP: u8 = 0xCF;

/// Resolution Set 1 (p.253) — Gate/source resolution, dual-gate enable.
/// Parameter: DUAL_EN, SSI, `X_RES[8]`, `Y_RES[10:8]`
pub const RESSET1: u8 = 0xD0;

/// Resolution Set 2 (p.254)
/// Parameter: `X_RES[7:0]`
pub const RESSET2: u8 = 0xD1;

/// Resolution Set 3 (p.255)
/// Parameter: `Y_RES[7:0]`
pub const RESSET3: u8 = 0xD2;

/// VCOM Offset Set (p.255) — Flicker adjustment.
/// Parameter: `VMF[6:0]`
pub const VCMOFSET: u8 = 0xDD;

/// VCOM Offset New Set (p.256) — Updated flicker adjustment.
/// Parameter: `VMF_NEW[6:0]`
pub const VCMOFNSET: u8 = 0xDE;

/// Positive Voltage Gamma Control (p.257)
///
/// 14 parameters defining the positive gamma curve:
///   VC63P, VC0P, VC1P, VC2P, VC4P, VC6P, AJ0P, VC13P,
///   VC20P, VC36P, VC27P, VC43P, AJ1P, VC50P, VC57P, VC59P, VC61P, VC62P
pub const GAMCTRP1: u8 = 0xE0;

/// Negative Voltage Gamma Control (p.259)
///
/// 14 parameters defining the negative gamma curve (same structure as GAMCTRP1).
pub const GAMCTRN1: u8 = 0xE1;

// ---------------------------------------------------------------------------
// COLMOD parameter values
// ---------------------------------------------------------------------------

/// 16-bit/pixel RGB565
pub const COLMOD_RGB565: u8 = 0x55;

/// 18-bit/pixel RGB666
pub const COLMOD_RGB666: u8 = 0x66;

// ---------------------------------------------------------------------------
// QSPI opcodes (Section 8.8.5, p.68–72)
// ---------------------------------------------------------------------------

/// Single-line command write (PP): cmd + 24-bit addr + single-line data
pub const QSPI_CMD_WRITE: u8 = 0x02;

/// 2-output write (PP2O): cmd + 24-bit addr + 2-line data
pub const QSPI_CMD_WRITE_2O: u8 = 0xA2;

/// Quad-output write (PP4O): cmd + 24-bit addr + quad-line data
pub const QSPI_CMD_WRITE_4O: u8 = 0x32;

/// Quad I/O write (PP4IO): quad addr + quad data
pub const QSPI_CMD_WRITE_4IO: u8 = 0x38;

/// Fast read: cmd + 24-bit addr + 8 dummy bits + single-line data
pub const QSPI_CMD_READ: u8 = 0x0B;