st7789v2 0.1.0

// ST7789V2 Command Set
// Reference: ST7789V2 Datasheet V1.0, Sitronix Technology Corporation, 2016/11
//
// Section 9.1 — System Function Command Table 1 (standard MIPI DCS)
// Section 9.2 — System Function Command Table 2 (manufacturer commands)

// ---------------------------------------------------------------------------
// Command Table 1 — Standard Commands (Section 9.1, p.158–254)
// ---------------------------------------------------------------------------

/// No Operation (p.164)
pub const NOP: u8 = 0x00;

/// Software Reset (p.165) — 5ms delay required after this command
pub const SWRESET: u8 = 0x01;

/// Read Display ID (p.167) — returns ID1, ID2, ID3
pub const RDDID: u8 = 0x04;

/// Read Display Status (p.169)
pub const RDDST: u8 = 0x09;

/// Read Display Power Mode (p.172)
pub const RDDPM: u8 = 0x0A;

/// Read Display MADCTL (p.174)
pub const RDDMADCTL: u8 = 0x0B;

/// Read Display Pixel Format (p.176)
pub const RDDCOLMOD: u8 = 0x0C;

/// Read Display Image Mode (p.178)
pub const RDDIM: u8 = 0x0D;

/// Read Display Signal Mode (p.180)
pub const RDDSM: u8 = 0x0E;

/// Read Display Self-Diagnostic Result (p.182)
pub const RDDSDR: u8 = 0x0F;

/// Sleep In (p.184)
pub const SLPIN: u8 = 0x10;

/// Sleep Out (p.186) — 120ms delay required after this command
pub const SLPOUT: u8 = 0x11;

/// Partial Display Mode On (p.188)
pub const PTLON: u8 = 0x12;

/// Normal Display Mode On (p.189)
pub const NORON: u8 = 0x13;

/// Display Inversion Off (p.190)
pub const INVOFF: u8 = 0x20;

/// Display Inversion On (p.192)
pub const INVON: u8 = 0x21;

/// Gamma Set (p.194) — selects gamma curve
///
/// Parameter: `GC[3:0]` — gamma curve select
///   0x01 = Gamma curve 1 (G2.2)
///   0x02 = Gamma curve 2 (G1.8)
///   0x04 = Gamma curve 3 (G2.5)
///   0x08 = Gamma curve 4 (G1.0)
pub const GAMSET: u8 = 0x26;

/// Display Off (p.196)
pub const DISPOFF: u8 = 0x28;

/// Display On (p.198)
pub const DISPON: u8 = 0x29;

/// Column Address Set (p.200) — 4 params: `XS[15:8]`, `XS[7:0]`, `XE[15:8]`, `XE[7:0]`
pub const CASET: u8 = 0x2A;

/// Row Address Set (p.202) — 4 params: `YS[15:8]`, `YS[7:0]`, `YE[15:8]`, `YE[7:0]`
pub const RASET: u8 = 0x2B;

/// Memory Write (p.204)
pub const RAMWR: u8 = 0x2C;

/// Memory Read (p.206)
pub const RAMRD: u8 = 0x2E;

/// Partial Area (p.208) — defines partial display area
pub const PTLAR: u8 = 0x30;

/// Vertical Scrolling Definition (p.210)
pub const VSCRDEF: u8 = 0x33;

/// Tearing Effect Line Off (p.213)
pub const TEOFF: u8 = 0x34;

/// Tearing Effect Line On (p.215) — 1 param: TEM
pub const TEON: u8 = 0x35;

/// Memory Data Access Control (p.217)
///
/// Parameter bits:
///   D7: MY  — Row address order
///   D6: MX  — Column address order
///   D5: MV  — Row/column exchange
///   D4: ML  — Vertical refresh order
///   D3: RGB — RGB/BGR order (0=RGB, 1=BGR)
///   D2: MH  — Horizontal refresh order
pub const MADCTL: u8 = 0x36;

/// Vertical Scroll Start Address of RAM (p.220)
pub const VSCSAD: u8 = 0x37;

/// Idle Mode Off (p.222)
pub const IDMOFF: u8 = 0x38;

/// Idle Mode On (p.224)
pub const IDMON: u8 = 0x39;

/// Interface Pixel Format (p.226)
///
/// Parameter bits:
///   D6–D4: RGB interface color format
///   D2–D0: MCU/SPI interface pixel format
///     0x55 = 16-bit/pixel (RGB565)
///     0x66 = 18-bit/pixel (RGB666)
pub const COLMOD: u8 = 0x3A;

/// Write Memory Continue (p.227)
pub const RAMWRC: u8 = 0x3C;

/// Read Memory Continue (p.229)
pub const RAMRDC: u8 = 0x3E;

/// Set Tear Scanline (p.231)
pub const STE: u8 = 0x44;

/// Get Scanline (p.233)
pub const GSCAN: u8 = 0x45;

/// Write Display Brightness (p.235) — 1 param: `DBV[7:0]`
pub const WRDISBV: u8 = 0x51;

/// Read Display Brightness (p.237)
pub const RDDISBV: u8 = 0x52;

/// Write CTRL Display (p.239)
///
/// Parameter bits:
///   D5: BCTRL — Brightness control block (0=Off, 1=On)
///   D3: DD    — Display dimming (0=Off, 1=On)
///   D2: BL    — Backlight control (0=Off, 1=On)
pub const WRCTRLD: u8 = 0x53;

/// Read CTRL Display (p.241)
pub const RDCTRLD: u8 = 0x54;

/// Write Content Adaptive Brightness Control and Color Enhancement (p.243)
pub const WRCACE: u8 = 0x55;

/// Read Content Adaptive Brightness Control (p.245)
pub const RDCABC: u8 = 0x56;

/// Write CABC Minimum Brightness (p.247)
pub const WRCABCMB: u8 = 0x5E;

/// Read CABC Minimum Brightness (p.249)
pub const RDCABCMB: u8 = 0x5F;

/// Read Automatic Brightness Control Self-Diagnostic Result (p.250)
pub const RDABCSDR: u8 = 0x68;

/// Read ID1 (p.252)
pub const RDID1: u8 = 0xDA;

/// Read ID2 (p.253)
pub const RDID2: u8 = 0xDB;

/// Read ID3 (p.254)
pub const RDID3: u8 = 0xDC;

// ---------------------------------------------------------------------------
// Command Table 2 — Manufacturer Command Set (Section 9.2, p.255–314)
// ---------------------------------------------------------------------------

/// RAM Control (p.260)
///
/// 2 parameters controlling RAM access mode, display operation,
/// endianness, and pixel data transfer method.
pub const RAMCTRL: u8 = 0xB0;

/// RGB Interface Control (p.263)
pub const RGBCTRL: u8 = 0xB1;

/// Porch Setting (p.265)
///
/// 5 parameters: `BPA[6:0]`, `FPA[6:0]`, PSEN, `FPB[3:0]`+`BPB[3:0]`, `FPC[3:0]`+`BPC[3:0]`
pub const PORCTRL: u8 = 0xB2;

/// Frame Rate Control 1 (p.266) — partial mode / idle colors
pub const FRCTRL1: u8 = 0xB3;

/// Partial Control (p.268)
pub const PARCTRL: u8 = 0xB5;

/// Gate Control (p.269)
///
/// 1 parameter: `VGHS[2:0]` | `VGLS[2:0]`
pub const GCTRL: u8 = 0xB7;

/// Gate On Timing Adjustment (p.271)
pub const GTADJ: u8 = 0xB8;

/// Digital Gamma Enable (p.273)
///
/// 1 parameter: DGMEN bit
pub const DGMEN: u8 = 0xBA;

/// VCOM Setting (p.274)
///
/// 1 parameter: `VCOMS[5:0]`
pub const VCOMS: u8 = 0xBB;

/// Power Saving Mode (p.276)
pub const POWSAVE: u8 = 0xBC;

/// Display Off Power Save (p.277)
pub const DLPOFFSAVE: u8 = 0xBD;

/// LCM Control (p.278)
pub const LCMCTRL: u8 = 0xC0;

/// ID Code Setting (p.279)
pub const IDSET: u8 = 0xC1;

/// VDV and VRH Command Enable (p.280)
///
/// 1 parameter: CMDEN bit
pub const VDVVRHEN: u8 = 0xC2;

/// VRH Set (p.281)
///
/// 1 parameter: `VRHS[5:0]`
pub const VRHS: u8 = 0xC3;

/// VDV Set (p.283)
///
/// 1 parameter: `VDVS[5:0]`
pub const VDVS: u8 = 0xC4;

/// VCOM Offset Set (p.285)
///
/// 1 parameter: `VCMOFS[5:0]`
pub const VCMOFSET: u8 = 0xC5;

/// Frame Rate Control 2 in Normal Mode (p.287)
///
/// 1 parameter: `NLA[2:0]` | `RTNA[4:0]`
pub const FRCTRL2: u8 = 0xC6;

/// CABC Control (p.289)
pub const CABCCTRL: u8 = 0xC7;

/// Register Value Selection 1 (p.290)
pub const REGSEL1: u8 = 0xC8;

/// Register Value Selection 2 (p.291)
pub const REGSEL2: u8 = 0xCA;

/// PWM Frequency Selection (p.292)
pub const PWMFRSEL: u8 = 0xCC;

/// Power Control 1 (p.293)
///
/// 2 parameters controlling AVDD, AVCL, VDS voltage levels.
pub const PWCTRL1: u8 = 0xD0;

/// Enable VAP/VAN Signal Output (p.295)
pub const VAPVANEN: u8 = 0xD2;

/// Command 2 Enable (p.296)
///
/// Unlock sequence: write 0x5A, 0x69 to enable command table 2 access.
pub const CMD2EN: u8 = 0xDF;

/// Positive Voltage Gamma Control (p.297)
///
/// 14 parameters defining the positive gamma curve.
pub const PVGAMCTRL: u8 = 0xE0;

/// Negative Voltage Gamma Control (p.299)
///
/// 14 parameters defining the negative gamma curve.
pub const NVGAMCTRL: u8 = 0xE1;

/// Digital Gamma Look-up Table for Red (p.301)
pub const DGMLUTR: u8 = 0xE2;

/// Digital Gamma Look-up Table for Blue (p.303)
pub const DGMLUTB: u8 = 0xE3;

/// Gate Control (p.305) — gate scan timing
pub const GATECTRL: u8 = 0xE4;

/// SPI2 Enable (p.307)
pub const SPI2EN: u8 = 0xE7;

/// Power Control 2 (p.308)
pub const PWCTRL2: u8 = 0xE8;

/// Equalize Time Control (p.309)
pub const EQCTRL: u8 = 0xE9;

/// Program Mode Control (p.311)
pub const PROMCTRL: u8 = 0xEC;

/// Program Mode Enable (p.312)
pub const PROMEN: u8 = 0xFA;

/// NVM Setting (p.313)
pub const NVMSET: u8 = 0xFC;

/// Program Action (p.314)
pub const PROMACT: u8 = 0xFE;

// ---------------------------------------------------------------------------
// COLMOD parameter values
// ---------------------------------------------------------------------------

/// 16-bit/pixel RGB565
pub const COLMOD_RGB565: u8 = 0x55;

/// 18-bit/pixel RGB666
pub const COLMOD_RGB666: u8 = 0x66;

/// 12-bit/pixel RGB444
pub const COLMOD_RGB444: u8 = 0x33;