st7305-lcd 0.2.0

use crate::{command::WriteCommand, instr::Instr};

/// `GATESET` (§8.2.1): number of gate lines of the panel, in steps of 4.
///
/// Must be sent before sleep out; do not change it while the display is on.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct GateLineSetting {
    gl: u8,
}

impl GateLineSetting {
    /// `lines` gate lines. The datasheet table ends at 320, the Waveshare
    /// 4.2" panel uses 400.
    ///
    /// # Panics
    ///
    /// If `lines` is 0, not a multiple of 4 or above 508 (at compile time in
    /// a `const`).
    pub const fn new(lines: u16) -> Self {
        assert!(lines != 0, "lines must be not zero");
        assert!(lines.is_multiple_of(4), "lines must be %4");
        assert!(lines / 4 < 128, "lines out of range");
        Self {
            gl: (lines / 4) as u8,
        }
    }
}

impl WriteCommand for GateLineSetting {
    const OPCODE: Instr = Instr::GATESET;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        [self.gl]
    }
}

/// `FSTCOM` (§8.2.2): first output gate number minus one, mapped to GRAM
/// page 0. Changing it step by step scrolls vertically in 4-line steps.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct FirstGateSetting {
    fst: u16,
}

impl FirstGateSetting {
    /// Register default `0x00, 0x00`: gate 1 shows GRAM page 0.
    pub const DEFAULT: Self = Self { fst: 0 };

    /// `FST[8:0]` = `fst`; e.g. 7 makes gate 8 show GRAM page 0.
    ///
    /// # Panics
    ///
    /// If `fst > 511` (at compile time in a `const`).
    pub const fn new(fst: u16) -> Self {
        assert!(fst >> 9 == 0, "FST out of range");
        Self { fst }
    }
}

impl Default for FirstGateSetting {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for FirstGateSetting {
    const OPCODE: Instr = Instr::FSTCOM;
    type Params = [u8; 2];
    fn params(&self) -> Self::Params {
        [(self.fst >> 8) as u8, self.fst as u8]
    }
}

/// `FRCTRL` (§8.2.3): frame rates of the high and the low power mode.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct FrameRateControl {
    hfra: HpmFrameRate,
    lfra: LpmFrameRate,
}

impl FrameRateControl {
    /// Register default `0x12`: full rate in HPM, 1 Hz in LPM.
    pub const DEFAULT: Self = Self {
        hfra: HpmFrameRate::Full,
        lfra: LpmFrameRate::OneHz,
    };

    /// `HFRA` (D4): frame rate in high power mode.
    #[must_use]
    pub const fn with_hpm_frame_rate(mut self, p: HpmFrameRate) -> Self {
        self.hfra = p;
        self
    }

    /// `LFRA[2:0]`: frame rate in low power mode.
    #[must_use]
    pub const fn with_lpm_frame_rate(mut self, p: LpmFrameRate) -> Self {
        self.lfra = p;
        self
    }

    const fn bytes(&self) -> [u8; 1] {
        [(self.hfra as u8) << 4 | (self.lfra as u8)]
    }
}

impl Default for FrameRateControl {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for FrameRateControl {
    const OPCODE: Instr = Instr::FRCTRL;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `HFRA`: HPM frame rate, relative to the maximum selected by
/// [`OscSwitch`](crate::cmd::power::OscSwitch).
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum HpmFrameRate {
    /// 16 Hz at OSCSW = 111; 25.5 Hz at OSCSW = 000
    Half = 0,
    /// 32 Hz at OSCSW = 111; 51 Hz at OSCSW = 000
    Full = 1,
}

/// `LFRA[2:0]`: LPM frame rate.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LpmFrameRate {
    /// 0.25 Hz
    QuarterHz = 0,
    /// 0.5 Hz
    HalfHz = 1,
    /// 1 Hz
    OneHz = 2,
    /// 2 Hz
    TwoHz = 3,
    /// 4 Hz
    FourHz = 4,
    /// 8 Hz
    EightHz = 5,
}

const _: () = assert!(matches!(FrameRateControl::DEFAULT.bytes(), [0x12]));

/// `GTUPEQH` (§8.2.4): gate EQ waveform of the update period in HPM, as the
/// voltage of each of its 16 PWM steps.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct UpdatePeriodGateEqControlInHpm {
    geqen: GateEqEnable,
    gpchpu: [GateEqVoltage; 16],
}

impl UpdatePeriodGateEqControlInHpm {
    /// Register default (gate EQ on, the datasheet waveform).
    pub const DEFAULT: Self = Self {
        geqen: GateEqEnable::Enable,
        gpchpu: [
            GateEqVoltage::Floating,
            GateEqVoltage::NaVdd,
            GateEqVoltage::Gnd,
            GateEqVoltage::AVdd,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::AVdd,
            GateEqVoltage::Gnd,
            GateEqVoltage::NaVdd,
        ],
    };

    /// `GEQEN`: gate EQ on or off, for both HPM and LPM.
    #[must_use]
    pub const fn with_gate_eq_enable(mut self, v: GateEqEnable) -> Self {
        self.geqen = v;
        self
    }

    /// `GPCHPU0..=15`: voltage of each PWM step.
    #[must_use]
    pub const fn with_gate_waveform(mut self, v: [GateEqVoltage; 16]) -> Self {
        self.gpchpu = v;
        self
    }

    const fn bytes(&self) -> [u8; 10] {
        [
            0xE5 & !(1 << 6) | (self.geqen as u8) << 6,
            0xF6,
            (self.gpchpu[0] as u8) << 4 | (self.gpchpu[1] as u8),
            (self.gpchpu[2] as u8) << 4 | (self.gpchpu[3] as u8),
            (self.gpchpu[4] as u8) << 4 | (self.gpchpu[5] as u8),
            (self.gpchpu[6] as u8) << 4 | (self.gpchpu[7] as u8),
            (self.gpchpu[8] as u8) << 4 | (self.gpchpu[9] as u8),
            (self.gpchpu[10] as u8) << 4 | (self.gpchpu[11] as u8),
            (self.gpchpu[12] as u8) << 4 | (self.gpchpu[13] as u8),
            (self.gpchpu[14] as u8) << 4 | (self.gpchpu[15] as u8),
        ]
    }
}

impl Default for UpdatePeriodGateEqControlInHpm {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for UpdatePeriodGateEqControlInHpm {
    const OPCODE: Instr = Instr::GTUPEQH;
    type Params = [u8; 10];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `GEQEN`: gate EQ on or off.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum GateEqEnable {
    /// Off
    Disable = 0,
    /// On
    Enable = 1,
}

/// Gate voltage of one PWM step of the gate EQ waveform.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum GateEqVoltage {
    /// Floating
    Floating = 0b000,
    /// VGL
    Vgl = 0b001,
    /// GND
    Gnd = 0b100,
    /// NAVDD
    NaVdd = 0b101,
    /// AVDD
    AVdd = 0b110,
    /// VGH
    Vgh = 0b111,
}

const _: () = assert!(
    matches!(
        UpdatePeriodGateEqControlInHpm::DEFAULT.bytes(),
        [0xE5, 0xF6, 0x05, 0x46, 0x77, 0x77, 0x77, 0x77, 0x76, 0x45]
    ),
    "GTUPEQH DEFAULT must match datasheet's default"
);

/// `GTUPEQL` (§8.2.5): gate EQ waveform of the update period in LPM, as the
/// voltage of each of its 16 PWM steps. Gate EQ itself is switched by
/// [`UpdatePeriodGateEqControlInHpm::with_gate_eq_enable`].
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct UpdatePeriodGateEqControlInLpm {
    gpclpu: [GateEqVoltage; 16],
}

impl UpdatePeriodGateEqControlInLpm {
    /// Register default (the datasheet waveform).
    pub const DEFAULT: Self = Self {
        gpclpu: [
            GateEqVoltage::Floating,
            GateEqVoltage::NaVdd,
            GateEqVoltage::Gnd,
            GateEqVoltage::AVdd,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::Vgh,
            GateEqVoltage::AVdd,
            GateEqVoltage::Gnd,
            GateEqVoltage::NaVdd,
        ],
    };

    /// `GPCLPU0..=15`: voltage of each PWM step.
    #[must_use]
    pub const fn with_gate_waveform(mut self, v: [GateEqVoltage; 16]) -> Self {
        self.gpclpu = v;
        self
    }

    const fn bytes(&self) -> [u8; 8] {
        [
            (self.gpclpu[0] as u8) << 4 | (self.gpclpu[1] as u8),
            (self.gpclpu[2] as u8) << 4 | (self.gpclpu[3] as u8),
            (self.gpclpu[4] as u8) << 4 | (self.gpclpu[5] as u8),
            (self.gpclpu[6] as u8) << 4 | (self.gpclpu[7] as u8),
            (self.gpclpu[8] as u8) << 4 | (self.gpclpu[9] as u8),
            (self.gpclpu[10] as u8) << 4 | (self.gpclpu[11] as u8),
            (self.gpclpu[12] as u8) << 4 | (self.gpclpu[13] as u8),
            (self.gpclpu[14] as u8) << 4 | (self.gpclpu[15] as u8),
        ]
    }
}

impl Default for UpdatePeriodGateEqControlInLpm {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for UpdatePeriodGateEqControlInLpm {
    const OPCODE: Instr = Instr::GTUPEQL;
    type Params = [u8; 8];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

const _: () = assert!(
    matches!(
        UpdatePeriodGateEqControlInLpm::DEFAULT.bytes(),
        [0x05, 0x46, 0x77, 0x77, 0x77, 0x77, 0x76, 0x45]
    ),
    "GTUPEQL DEFAULT must match datasheet's default"
);

/// `SOUEQ` (§8.2.6): source EQ on or off.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct SourceEqEnable {
    soueq: SourceEq,
}

impl SourceEqEnable {
    /// Register default `0x13`: source EQ on.
    pub const DEFAULT: Self = Self {
        soueq: SourceEq::Enable,
    };

    /// `SOUEQ` (D4).
    #[must_use]
    pub const fn with_source_eq(mut self, v: SourceEq) -> Self {
        self.soueq = v;
        self
    }

    const fn bytes(&self) -> [u8; 1] {
        [0x13 & !(1 << 4) | (self.soueq as u8) << 4]
    }
}

impl Default for SourceEqEnable {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for SourceEqEnable {
    const OPCODE: Instr = Instr::SOUEQ;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `SOUEQ`: source EQ on or off.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SourceEq {
    /// Off
    Disable = 0,
    /// On
    Enable = 1,
}

const _: () = assert!(matches!(SourceEqEnable::DEFAULT.bytes(), [0x13]));

/// `PNLSET` (§8.2.7): inversion, gate scan mode and panel layout.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct PanelSetting {
    dotinv: ColumnDotInversion,
    dpscn: GateScanMode,
    lay: PanelLayoutSelect,
}

impl PanelSetting {
    /// Register default `0x0A`: column inversion, frame interval, non
    /// interlaced.
    pub const DEFAULT: Self = Self {
        dotinv: ColumnDotInversion::ColumnInversion,
        dpscn: GateScanMode::FrameInterval,
        lay: PanelLayoutSelect::NonInterlace,
    };

    /// `DOTINV[1:0]` (D6..D5).
    #[must_use]
    pub const fn with_column_dot_inversion(mut self, v: ColumnDotInversion) -> Self {
        self.dotinv = v;
        self
    }

    /// `DPSCN[1:0]` (D3..D2).
    #[must_use]
    pub const fn with_gate_scan_mode(mut self, v: GateScanMode) -> Self {
        self.dpscn = v;
        self
    }

    /// `LAY[1:0]` (D1..D0).
    #[must_use]
    pub const fn with_panel_layout(mut self, v: PanelLayoutSelect) -> Self {
        self.lay = v;
        self
    }

    const fn bytes(&self) -> [u8; 1] {
        [(self.dotinv as u8) << 5 | (self.dpscn as u8) << 2 | self.lay as u8]
    }
}

impl Default for PanelSetting {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for PanelSetting {
    const OPCODE: Instr = Instr::PNLSET;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `DOTINV[1:0]`: polarity inversion scheme.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ColumnDotInversion {
    /// Column inversion
    ColumnInversion = 0,
    /// 1-dot inversion
    OneDotInversion = 1,
    /// 2-dot inversion
    TwoDotInversion = 2,
}

/// `DPSCN[1:0]`: display gate scan mode.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum GateScanMode {
    /// Two-line interval
    TwoLineInterval = 0,
    /// One-line interval
    OneLineInterval = 1,
    /// Frame interval
    FrameInterval = 2,
}

/// `LAY[1:0]`: panel layout.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PanelLayoutSelect {
    /// Two-line interlace
    TwoLineInterlace = 0,
    /// One-line interlace
    OneLineInterlace = 1,
    /// Non-interlaced
    NonInterlace = 2,
}

const _: () = assert!(matches!(PanelSetting::DEFAULT.bytes(), [0x0A]));

/// `GAMAMS` (§8.2.8): monochrome or 4 grey levels.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct GammaModeSetting {
    gama: GammaMode,
}

impl GammaModeSetting {
    /// Register default `0x20`: monochrome.
    pub const DEFAULT: Self = Self {
        gama: GammaMode::Mono,
    };

    /// Gamma mode `gama`.
    pub const fn new(gama: GammaMode) -> Self {
        Self { gama }
    }

    const fn bytes(&self) -> [u8; 1] {
        [(self.gama as u8) << 5]
    }
}

impl Default for GammaModeSetting {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for GammaModeSetting {
    const OPCODE: Instr = Instr::GAMAMS;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `GAMA`: gamma mode.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum GammaMode {
    /// 4 grey scales
    FourGS = 0,
    /// Monochrome
    Mono = 1,
}

const _: () = assert!(matches!(GammaModeSetting::DEFAULT.bytes(), [0x20]));

/// `CLRAM` (§8.2.9): clears GRAM to 0.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct EnableClearRam {
    clr: ClearRam,
}

impl EnableClearRam {
    /// `CLR` (D7) = `clr`. The datasheet gives no register default, so there is
    /// no `Default`: sending `ClearRam::Enable` clears the GRAM.
    pub const fn new(clr: ClearRam) -> Self {
        Self { clr }
    }

    const fn bytes(&self) -> [u8; 1] {
        [0x4F & !(1 << 7) | (self.clr as u8) << 7]
    }
}

impl WriteCommand for EnableClearRam {
    const OPCODE: Instr = Instr::CLRAM;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `CLR`: note the inverted encoding, 0 enables the clear.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ClearRam {
    /// Clear GRAM (`CLR` = 0)
    Enable = 0,
    /// Do not clear (`CLR` = 1)
    Disable = 1,
}

const _: () = assert!(matches!(
    EnableClearRam::new(ClearRam::Enable).bytes(),
    [0x4F]
));
const _: () = assert!(matches!(
    EnableClearRam::new(ClearRam::Disable).bytes(),
    [0xCF]
));

/// `GTCTRL` (`0x62`): gate timing control. Not described in datasheet v0.2;
/// the Waveshare preset sends `0x32, 0x03, 0x1F`.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct GateTimingControl {
    p1: u8,
    p2: u8,
    p3: u8,
}

impl GateTimingControl {
    /// The three raw parameter bytes.
    pub const fn new(p1: u8, p2: u8, p3: u8) -> Self {
        Self { p1, p2, p3 }
    }
}

impl WriteCommand for GateTimingControl {
    const OPCODE: Instr = Instr::GTCTRL;
    type Params = [u8; 3];
    fn params(&self) -> Self::Params {
        [self.p1, self.p2, self.p3]
    }
}