st7305-lcd 0.2.0

Platform-independent no_std driver for the Sitronix ST7305 reflective LCD controller (embedded-hal 1.0, blocking and async)
Documentation 
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/// Command opcodes of the ST7305 (mnemonics as in the datasheet).
///
/// `#[non_exhaustive]`: opcodes found later (like the undocumented `GTCTRL`)
/// can be added without a breaking change.
#[allow(non_camel_case_types, reason = "mnemonics kept as in datasheet")]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[non_exhaustive]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Instr {
    /// No operation
    NOP = 0x00,
    /// Software reset
    SWRESET = 0x01,
    /// Read display ID
    RDDID = 0x04,
    /// Read display status
    RDDST = 0x09,
    /// Read display power mode
    RDDPM = 0x0A,
    /// Sleep in
    SLPIN = 0x10,
    /// Sleep out
    SLPOUT = 0x11,
    /// Partial on
    PTLON = 0x12,
    /// Partial off
    PTLOFF = 0x13,
    /// Display inversion off
    INVOFF = 0x20,
    /// Display inversion on
    INVON = 0x21,
    /// Display off
    DISPOFF = 0x28,
    /// Display on
    DISPON = 0x29,
    /// Column address set
    CASET = 0x2A,
    /// Row address set
    RASET = 0x2B,
    /// Memory write
    RAMWR = 0x2C,
    /// Memory read
    RAMRD = 0x2E,
    /// Tearing effect line off
    TEOFF = 0x34,
    /// Tearing effect line on
    TEON = 0x35,
    /// Memory data access control
    MADCTL = 0x36,
    /// Vertical scroll start address of RAM
    VSCSAD = 0x37,
    /// High power mode on
    HPM = 0x38,
    /// Low power mode on
    LPM = 0x39,
    /// Data format select
    DTFORM = 0x3A,
    /// Write memory continue
    WRMEMC = 0x3C,
    /// Read memory continue
    RDMEMC = 0x3E,
    /// Set tear scanline
    TESCAN = 0x44,
    /// Gate timing control  WARN: undocumented in DS v0.2
    GTCTRL = 0x62,
    /// Gate line setting
    GATESET = 0xB0,
    /// First gate setting
    FSTCOM = 0xB1,
    /// Frame rate control
    FRCTRL = 0xB2,
    /// Update period gate EQ control in HPM
    GTUPEQH = 0xB3,
    /// Update period gate EQ control in LPM
    GTUPEQL = 0xB4,
    /// Source EQ enable
    SOUEQ = 0xB7,
    /// Panel setting
    PNLSET = 0xB8,
    /// Gamma mode setting
    GAMAMS = 0xB9,
    /// Enable clear RAM
    CLRAM = 0xBB,
    /// Gate voltage control
    GCTRL = 0xC0,
    /// Source high positive voltage control
    VSHPCTRL = 0xC1,
    /// Source low positive voltage control
    VSLPCTRL = 0xC2,
    /// Source high negative voltage control
    VSHNCTRL = 0xC4,
    /// Source low negative voltage control
    VSLNCTRL = 0xC5,
    /// Source gamma voltage control
    VSIKCTRL = 0xC8,
    /// Source voltage select
    VSHLSEL = 0xC9,
    /// ID1 setting
    ID1SET = 0xCA,
    /// ID2 setting
    ID2SET = 0xCB,
    /// ID3 setting
    ID3SET = 0xCC,
    /// Enable auto power down
    AUTOPWRCTRL = 0xD0,
    /// Booster enable
    BSTEN = 0xD1,
    /// NVM load control
    NVMLOADCTRL = 0xD6,
    /// OSC setting
    OSCSET = 0xD8,
    /// Read ID1
    RDID1 = 0xDA,
    /// Read ID2
    RDID2 = 0xDB,
    /// Read ID3
    RDID3 = 0xDC,
    /// NVM data read
    NVMRD = 0xE9,
    /// EXTB control
    EXTBCTRL = 0xEC,
    /// NVM WR/RD control
    NVMCTRL1 = 0xF8,
    /// NVM program setting
    NVMCTRL2 = 0xFA,
    /// NVM read enable
    NVMRDEN = 0xFB,
    /// NVM program enable
    NVMPROM = 0xFC,
}