st7305-lcd 0.2.0

use crate::{
    command::{WriteCommand, no_param_command},
    instr::Instr,
};

no_param_command!(
    /// No operation (§8.1.1).
    Nop => NOP
);
no_param_command!(
    /// Software reset (§8.1.2): registers return to their defaults, GRAM is
    /// kept. Wait 5 ms before the next command.
    SoftReset => SWRESET
);
no_param_command!(
    /// Enters sleep mode (§8.1.6). Prefer the `sleep_in` method of the
    /// drivers, which also waits the required 5 ms.
    SleepIn => SLPIN
);
no_param_command!(
    /// Leaves sleep mode (§8.1.7). Prefer the `sleep_out` method of the
    /// drivers, which also waits the required pause.
    SleepOut => SLPOUT
);
no_param_command!(
    /// Enters partial mode (§8.1.8): the display window becomes 240 duty.
    PartialOn => PTLON
);
no_param_command!(
    /// Leaves partial mode (§8.1.9): the display window becomes 320 duty.
    PartialOff => PTLOFF
);
no_param_command!(
    /// Display inversion off (§8.1.10): bit 1 in GRAM is black.
    DisplayInversionOff => INVOFF
);
no_param_command!(
    /// Display inversion on (§8.1.11): bit 1 in GRAM is white.
    DisplayInversionOn => INVON
);
no_param_command!(
    /// Turns the display output off (§8.1.12); GRAM is kept.
    DisplayOff => DISPOFF
);
no_param_command!(
    /// Turns the display output on (§8.1.13).
    DisplayOn => DISPON
);
no_param_command!(
    /// Turns the tearing effect output off (§8.1.18).
    TearingEffectLineOff => TEOFF
);
no_param_command!(
    /// High power mode (§8.1.22), the reset default. The frame rate is set by
    /// [`FrameRateControl`](crate::cmd::panel::FrameRateControl) and
    /// [`OscSetting`](crate::cmd::power::OscSetting).
    HighPowerModeOn => HPM
);
no_param_command!(
    /// Low power mode (§8.1.23), 0.25 to 8 Hz set by
    /// [`FrameRateControl`](crate::cmd::panel::FrameRateControl).
    LowPowerModeOn => LPM
);

/// `CASET` (§8.1.14): column window for the following `RAMWR`, inclusive.
///
/// One column is 3 bytes of GRAM. The field is 6 bits (0..=63). The usable
/// range depends on the panel wiring: datasheet v0.2 gives 0x13..=0x28 for a
/// 264-source layout, the Waveshare 4.2" panel uses 0x12..=0x2A.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct ColumnAddressSet {
    xs: u8,
    xe: u8,
}

impl ColumnAddressSet {
    /// Register default `0x00, 0x00`: column 0 only.
    pub const DEFAULT: Self = Self { xs: 0, xe: 0 };

    /// Columns `xs..=xe`.
    ///
    /// # Panics
    ///
    /// If `xs > xe` or `xe > 63` (at compile time in a `const`).
    pub const fn new(xs: u8, xe: u8) -> Self {
        assert!(xs <= xe, "X start must be less or equal than X end");
        assert!(xe < 64, "X end out of range");
        Self { xs, xe }
    }
}

impl Default for ColumnAddressSet {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for ColumnAddressSet {
    const OPCODE: Instr = Instr::CASET;
    type Params = [u8; 2];
    fn params(&self) -> Self::Params {
        [self.xs, self.xe]
    }
}

/// `RASET` (§8.1.15): row (page) window for the following `RAMWR`,
/// inclusive.
///
/// One row is one GRAM page line (2 gate lines). The field is 8 bits. The
/// usable range depends on the panel wiring: datasheet v0.2 gives
/// 0x00..=0x9F for a 320-gate layout, the Waveshare 4.2" panel uses
/// 0x00..=0xC7.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct RowAddressSet {
    ys: u8,
    ye: u8,
}

impl RowAddressSet {
    /// Register default `0x00, 0x00`: row 0 only.
    pub const DEFAULT: Self = Self { ys: 0, ye: 0 };

    /// Rows `ys..=ye`.
    ///
    /// # Panics
    ///
    /// If `ys > ye` (at compile time in a `const`).
    pub const fn new(ys: u8, ye: u8) -> Self {
        assert!(ys <= ye, "Y start must be less or equal than Y end");
        Self { ys, ye }
    }
}

impl Default for RowAddressSet {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for RowAddressSet {
    const OPCODE: Instr = Instr::RASET;
    type Params = [u8; 2];
    fn params(&self) -> Self::Params {
        [self.ys, self.ye]
    }
}

/// `TEON` (§8.1.19): turns the tearing effect output on. During sleep the TE
/// pin is held low.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct TearingEffectLineOn {
    /// D0
    tem: TearingEffectMode,
}

impl TearingEffectLineOn {
    /// Register default: V-blanking only.
    pub const DEFAULT: Self = Self {
        tem: TearingEffectMode::VBlanking,
    };

    /// TE output in the mode `tem`.
    pub const fn new(tem: TearingEffectMode) -> Self {
        Self { tem }
    }

    const fn bytes(&self) -> [u8; 1] {
        [self.tem as u8]
    }
}

impl Default for TearingEffectLineOn {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for TearingEffectLineOn {
    const OPCODE: Instr = Instr::TEON;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `TEM`: what the TE line reports.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TearingEffectMode {
    /// V-blanking only
    VBlanking = 0,
    /// V-blanking and H-blanking
    Both = 1,
}

const _: () = assert!(matches!(TearingEffectLineOn::DEFAULT.bytes(), [0x00]));

/// `MADCTL` (§8.1.20): scan direction of the frame memory for reads and
/// writes.
///
/// The data order bit `DO` (D3) is not a separate setting: the datasheet
/// allows it only equal to `MX`, so it follows
/// [`with_column_order`](Self::with_column_order).
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct MemoryDataAccessControl {
    /// D7
    my: PageAddressOrder,
    /// D6
    mx: ColumnAddressOrder,
    /// D5
    mv: PageOrColumnOrder,
    // NOTE: D3(DO) is derived from MX: DS allows DO=0 only with MX=0 and DO=1 only with MX=1
    /// D2
    gs: GateScanOrder,
}

impl MemoryDataAccessControl {
    /// Register default `0x00`: everything top to bottom, left to right,
    /// column direction.
    pub const DEFAULT: Self = Self {
        my: PageAddressOrder::TopToBottom,
        mx: ColumnAddressOrder::LeftToRight,
        mv: PageOrColumnOrder::ColumnDirectionMode,
        gs: GateScanOrder::TopToBottom,
    };

    /// `MY` (D7): page address order.
    #[must_use]
    pub const fn with_page_order(mut self, v: PageAddressOrder) -> Self {
        self.my = v;
        self
    }

    /// `MX` (D6): column address order; also sets the data order `DO` (D3).
    #[must_use]
    pub const fn with_column_order(mut self, v: ColumnAddressOrder) -> Self {
        self.mx = v;
        self
    }

    /// `MV` (D5): whether the address advances along columns or pages.
    #[must_use]
    pub const fn with_page_or_column_order(mut self, v: PageOrColumnOrder) -> Self {
        self.mv = v;
        self
    }

    /// `GS` (D2): gate scan (refresh) order.
    #[must_use]
    pub const fn with_gate_scan_order(mut self, v: GateScanOrder) -> Self {
        self.gs = v;
        self
    }
}

impl Default for MemoryDataAccessControl {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for MemoryDataAccessControl {
    const OPCODE: Instr = Instr::MADCTL;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        let byte = (self.my as u8) << 7
            | (self.mx as u8) << 6
            | (self.mv as u8) << 5
            | (self.mx as u8) << 3
            | (self.gs as u8) << 2;
        [byte]
    }
}

/// `MY`: page address order.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PageAddressOrder {
    /// Top to bottom
    TopToBottom = 0,
    /// Bottom to top
    BottomToTop = 1,
}

/// `MX`: column address order.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ColumnAddressOrder {
    /// Left to right
    LeftToRight = 0,
    /// Right to left
    RightToLeft = 1,
}

/// `MV`: direction in which the address advances.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PageOrColumnOrder {
    /// Along the columns, then to the next page
    ColumnDirectionMode = 0,
    /// Along the pages, then to the next column
    PageDirectionMode = 1,
}

/// `GS`: order in which the gates refresh the panel.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum GateScanOrder {
    /// Top to bottom
    TopToBottom = 0,
    /// Bottom to top
    BottomToTop = 1,
}

/// `VSCSAD` (§8.1.21): the frame memory line shown as the first display
/// line (vertical scrolling).
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct VerticalScrollStartAddressOfRam {
    vsp: u16, // 9-bit vertical scroll shift value (first line)
}

impl VerticalScrollStartAddressOfRam {
    /// Register default `0x00, 0x00`: line 0.
    pub const DEFAULT: Self = Self { vsp: 0 };

    /// Start line `vsp` (9 bits).
    ///
    /// # Panics
    ///
    /// If `vsp > 511` (at compile time in a `const`).
    pub const fn new(vsp: u16) -> Self {
        assert!(vsp >> 9 == 0, "VSP out of range");
        Self { vsp }
    }
}

impl Default for VerticalScrollStartAddressOfRam {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for VerticalScrollStartAddressOfRam {
    const OPCODE: Instr = Instr::VSCSAD;
    type Params = [u8; 2];
    fn params(&self) -> Self::Params {
        [(self.vsp >> 8) as u8, self.vsp as u8]
    }
}

/// `DTFORM` (§8.1.24): format of the pixel data written to GRAM.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct DataFormatSelect {
    xde: DataUpDownSwitch,
    bps: BytesPerPixelSelect,
}

impl DataFormatSelect {
    /// Register default `0x00`.
    pub const DEFAULT: Self = Self {
        xde: DataUpDownSwitch::On,
        bps: BytesPerPixelSelect::FourWriteOps,
    };

    /// `XDE` (D4): data up/down switch.
    #[must_use]
    pub const fn with_data_up_down_switch(mut self, p: DataUpDownSwitch) -> Self {
        self.xde = p;
        self
    }

    /// `BPS` (D0): number of write operations per 24 bits of data.
    #[must_use]
    pub const fn with_bytes_per_pixel(mut self, p: BytesPerPixelSelect) -> Self {
        self.bps = p;
        self
    }

    const fn bytes(&self) -> [u8; 1] {
        [(self.xde as u8) << 4 | self.bps as u8]
    }
}

impl Default for DataFormatSelect {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for DataFormatSelect {
    const OPCODE: Instr = Instr::DTFORM;
    type Params = [u8; 1];
    fn params(&self) -> Self::Params {
        self.bytes()
    }
}

/// `XDE`: data up/down switch.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DataUpDownSwitch {
    /// Switch on (to be used with `MY` = 1)
    On = 0,
    /// Switch off
    Off = 1,
}

/// `BPS`: how 24 bits of pixel data are written.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BytesPerPixelSelect {
    /// 4 write operations per 24 bits
    FourWriteOps = 0,
    /// 3 write operations per 24 bits (used by the Waveshare preset)
    ThreeWriteOps = 1,
}

const _: () = assert!(matches!(DataFormatSelect::DEFAULT.bytes(), [0x00]));

/// `TESCAN` (§8.1.27): turns the TE output on when the panel reaches line
/// `N` (V-blanking only). `N` = 0 is the same as `TEON` with
/// [`TearingEffectMode::VBlanking`].
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub struct SetTearScanline {
    n: u16, // 9-bit turn on TE pin on this line
}

impl SetTearScanline {
    /// Register default `0x00, 0x00`: line 0.
    pub const DEFAULT: Self = Self { n: 0 };

    /// TE on line `n` (9 bits).
    ///
    /// # Panics
    ///
    /// If `n > 511` (at compile time in a `const`).
    pub const fn new(n: u16) -> Self {
        assert!(n >> 9 == 0, "N out of range");
        Self { n }
    }
}

impl Default for SetTearScanline {
    fn default() -> Self {
        Self::DEFAULT
    }
}

impl WriteCommand for SetTearScanline {
    const OPCODE: Instr = Instr::TESCAN;
    type Params = [u8; 2];
    fn params(&self) -> Self::Params {
        [(self.n >> 8) as u8, self.n as u8]
    }
}