*SPEF "IEEE 1481-1998"
*DESIGN "simple"
*DATE "Tue Sep 25 11:51:50 2012"
*VENDOR "TAU 2015 Contest"
*PROGRAM "Benchmark Parasitic Generator"
*VERSION "0.0"
*DESIGN_FLOW "NETLIST_TYPE_VERILOG"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER [ ]
*T_UNIT 1 PS
*C_UNIT 1 FF
*R_UNIT 1 KOHM
*L_UNIT 1 UH
*NAME_MAP
*1 inp1
*2 inp2
*3 out
*4 n1
*5 n2
*6 n3
*7 u1
*8 u3
*9 u4
*10 f1
*11 u2
*D_NET *1 5.4
*CONN
*P *1 I
*I *7:a I
*CAP
1 *1 1.2
2 *1:1 1.3
3 *1:2 1.4
4 *7:a 1.5
*RES
1 *1 *1:1 3.4
2 *1:1 *1:2 3.5
3 *1:2 *7:a 3.6
*END
*D_NET *2 2
*CONN
*P *2 I
*I *7:b I
*CAP
1 *2 0.2
2 *2:1 0.5
3 *2:2 0.4
4 *7:b 0.9
*RES
1 *2 *2:1 1.4
2 *2:1 *2:2 1.5
3 *2:2 *7:b 1.6
*END
*D_NET *3 0.7
*CONN
*I *8:o O
*P *3 O
*CAP
1 *8:o 0.2
2 *3 0.5
*RES
1 *8:o *3 1.4
*END
*D_NET *4 1
*CONN
*I *7:o O
*I *9:a I
*CAP
1 *7:o 0.2
2 *4:1 0.3
3 *9:a 0.5
*RES
1 *7:o *4:1 1.1
2 *4:1 *9:a 1
*END
*D_NET *5 1.2
*CONN
*I *9:o O
*I *10:d I
*CAP
1 *9:o 0.7
2 *10:d 0.5
*RES
1 *9:o *10:d 2.1
*END
*D_NET *6 23.4
*CONN
*I *10:q O
*I *11:a I
*I *9:b I
*CAP
1 *6:1 6.7
2 *6:2 7.8
3 *6:3 8.9
*RES
1 *10:q *6:3 1.2
2 *6:3 *6:1 2.3
3 *6:1 *11:a 3.4
4 *6:3 *6:2 4.5
5 *6:2 *9:b 5.6
*END