sp1-core-executor 6.1.0

RISC-V executor for SP1
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

use crate::{
    events::{Poseidon2PrecompileEvent, PrecompileEvent},
    vm::syscall::SyscallRuntime,
    SyscallCode,
};

pub(crate) fn poseidon2<'a, RT: SyscallRuntime<'a>>(
    rt: &mut RT,
    syscall_code: SyscallCode,
    arg1: u64,
    arg2: u64,
) -> Option<u64> {
    assert!(arg2 == 0, "arg2 must be 0");
    assert!(arg1.is_multiple_of(8));

    let clk = rt.core().clk();
    let ptr = arg1;

    // Read the input values using unsafe read (since we'll overwrite them)
    let _ = rt.mr_slice_unsafe(8);

    // Write the computed results from memory records
    let output_memory_records = rt.mw_slice(ptr, 8);

    if RT::TRACING {
        // Create and add the event
        let event = PrecompileEvent::POSEIDON2(Poseidon2PrecompileEvent {
            clk,
            ptr,
            memory_records: output_memory_records,
            local_mem_access: rt.postprocess_precompile(),
            ..Default::default()
        });

        let syscall_event = rt.syscall_event(
            clk,
            syscall_code,
            arg1,
            arg2,
            false,
            rt.core().next_pc(),
            rt.core().exit_code(),
        );

        rt.add_precompile_event(syscall_code, syscall_event, event);
    }

    None
}