//! System-timer surface for architectures whose timer arming is driven by
//! someboot's `SystimerArch` capability (Arm generic timer, RISC-V SBI timer,
//! LoongArch TCG). On x86_64 the system timer lives inside the local APIC and
//! [`crate::arch::x86_64::timer`] replaces this module.
// The counter domain stays in someboot, which owns the hardware counter.
pub use ;
use ;
/// Brings the system timer into its enabled state.
/// Unmasks the timer interrupt.
/// Arms a one-shot deadline `ticks` from now.
/// Acknowledge and clear the timer interrupt.