1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
//! SIMD-accelerated byte pattern pre-filtering.
//!
//! `simdsieve` scans a byte haystack for multiple fixed-string patterns at
//! once and yields verified match offsets through a streaming iterator.
//!
//! # SIMD Prefiltering
//!
//! The engine uses a multi-stage prefiltering approach. First, it extracts
//! candidate offsets by searching for the first 1-4 bytes (the "prefix") of
//! each pattern using SIMD vector instructions. This allows scanning dozens of
//! gigabytes per second because the hardware can compare 32 or 64 bytes
//! simultaneously.
//!
//! Once a prefix hit is found in a SIMD register, the engine performs a
//! lightweight verification of the full pattern at that offset.
//!
//! # Supported Architectures
//!
//! The crate includes specialized backends for different CPU architectures:
//!
//! - **AVX-512 (`x86_64`):** Uses 512-bit ZMM registers for maximum throughput
//! on modern Intel and AMD processors.
//! - **AVX2 (`x86_64`):** Uses 256-bit YMM registers for broad compatibility
//! across most `x86_64` hardware.
//! - **NEON (AArch64):** Uses 128-bit vector registers on ARM processors,
//! optimized for Apple Silicon and Graviton.
//! - **Scalar (Any):** A portable fallback implementation for architectures
//! without specialized SIMD support.
//!
//! The backend is selected automatically at runtime based on the host CPU's
//! capabilities.
//!
//! # Example
//!
//! ```rust
//! use simdsieve::SimdSieve;
//!
//! let haystack = b"GET /admin HTTP/1.1\r\nHost: example\r\n";
//! let patterns: &[&[u8]] = &[b"GET", b"/admin"];
//!
//! let matches: Vec<usize> = SimdSieve::new(haystack, patterns)
//! .unwrap()
//! .collect();
//!
//! assert_eq!(matches, vec![0, 4]);
//! ```
pub use ;
pub use MultiSieve;
pub use SimdSieve;