//! aarch64 SIMD backends.
/// Bit-position mask shared between the NEON and SVE2 movemask reductions.
///
/// Each byte holds `1 << (position & 7)`, repeated across the two halves so
/// the same 16-byte vector can be applied to either half via NEON's halved
/// `vaddv_u8` reduction (NEON path) or via SVE2's NEON-aliased low 128 bits
/// after the predicate-to-byte expansion (SVE2 path).
pub const MOVEMASK_BIT_MASK: =
;
pub
pub