sifive-core 0.0.2

Low level access to SiFive RISC-V processor cores
Documentation 
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[dependencies.bit_field]
version = "0.10"

[dependencies.bitflags]
version = "1.3"

[package]
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to SiFive RISC-V processor cores"
documentation = "https://docs.rs/sifive-core"
edition = "2021"
keywords = ["riscv", "register"]
license = "MulanPSL-2.0"
name = "sifive-core"
readme = "README.md"
repository = "https://github.com/luojia65/sifive-core"
resolver = "2"
version = "0.0.2"
[package.metadata.docs.rs]
default-target = "riscv64imac-unknown-none-elf"
targets = ["riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf", "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf"]