#[cfg(target_arch = "x86")]
use core::arch::x86::*;
#[cfg(target_arch = "x86_64")]
use core::arch::x86_64::*;
use crate::Schedule;
use crate::mem::store_u32x4;
mod sha_ni;
#[cfg(target_feature = "sse2")]
pub(super) mod sse2;
pub(super) use sha_ni::ShaNi;
const REVERSE: i32 = 0b00_01_10_11;
#[inline]
#[target_feature(enable = "sse2")]
fn spill<const I: usize>(w: &mut Schedule, msg: __m128i) {
store_u32x4(w.window_mut::<I, 4>(), msg);
}
#[inline]
#[target_feature(enable = "sse2")]
fn alignr8(hi: __m128i, lo: __m128i) -> __m128i {
_mm_castpd_si128(_mm_shuffle_pd(
_mm_castsi128_pd(lo),
_mm_castsi128_pd(hi),
1,
))
}
#[inline]
#[target_feature(enable = "sse2")]
fn rol<const L: i32, const R: i32>(x: __m128i) -> __m128i {
_mm_or_si128(_mm_slli_epi32(x, L), _mm_srli_epi32(x, R))
}
#[inline]
#[target_feature(enable = "sse2")]
fn expand_rol2(v8: __m128i, v7: __m128i, v4: __m128i, v2: __m128i, v1: __m128i) -> __m128i {
let far = _mm_xor_si128(_mm_xor_si128(v8, v7), v4);
rol::<2, 30>(_mm_xor_si128(far, alignr8(v2, v1)))
}