1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License..
use crate::*;
//
// The processor is a generic IA32 CPU
//
pub const CPU_FEATURE_GENERIC_IA32 :uint64_t = 0x00000001;
//
// Floating point unit is on-chip.
//
pub const CPU_FEATURE_FPU :uint64_t = 0x00000002;
//
// Conditional mov instructions are supported.
//
pub const CPU_FEATURE_CMOV :uint64_t = 0x00000004;
//
// The processor supports the MMX technology instruction set extensions
// to Intel Architecture.
//
pub const CPU_FEATURE_MMX :uint64_t = 0x00000008;
//
// The FXSAVE and FXRSTOR instructions are supported for fast
// save and restore of the floating point context.
//
pub const CPU_FEATURE_FXSAVE :uint64_t = 0x00000010;
//
// Indicates the processor supports the Streaming SIMD Extensions Instructions.
//
pub const CPU_FEATURE_SSE :uint64_t = 0x00000020;
//
// Indicates the processor supports the Streaming SIMD
// Extensions 2 Instructions.
//
pub const CPU_FEATURE_SSE2 :uint64_t = 0x00000040;
//
// Indicates the processor supports the Streaming SIMD
// Extensions 3 Instructions. (PNI)
//
pub const CPU_FEATURE_SSE3 :uint64_t = 0x00000080;
//
// The processor supports the Supplemental Streaming SIMD Extensions 3
// instructions. (MNI)
//
pub const CPU_FEATURE_SSSE3 :uint64_t = 0x00000100;
//
// The processor supports the Streaming SIMD Extensions 4.1 instructions.(SNI)
//
pub const CPU_FEATURE_SSE4_1 :uint64_t = 0x00000200;
//
// The processor supports the Streaming SIMD Extensions 4.1 instructions.
// (NNI + STTNI)
//
pub const CPU_FEATURE_SSE4_2 :uint64_t = 0x00000400;
//
// The processor supports MOVBE instruction.
//
pub const CPU_FEATURE_MOVBE :uint64_t = 0x00000800;
//
// The processor supports POPCNT instruction.
//
pub const CPU_FEATURE_POPCNT :uint64_t = 0x00001000;
//
// The processor supports PCLMULQDQ instruction.
//
pub const CPU_FEATURE_PCLMULQDQ :uint64_t = 0x00002000;
//
// The processor supports instruction extension for encryption.
//
pub const CPU_FEATURE_AES :uint64_t = 0x00004000;
//
// The processor supports 16-bit floating-point conversions instructions.
//
pub const CPU_FEATURE_F16C :uint64_t = 0x00008000;
//
// The processor supports AVX instruction extension.
//
pub const CPU_FEATURE_AVX :uint64_t = 0x00010000;
//
// The processor supports RDRND (read random value) instruction.
//
pub const CPU_FEATURE_RDRND :uint64_t = 0x00020000;
//
// The processor supports FMA instructions.
//
pub const CPU_FEATURE_FMA :uint64_t = 0x00040000;
//
// The processor supports two groups of advanced bit manipulation extensions. - Haswell introduced, AVX2 related
//
pub const CPU_FEATURE_BMI :uint64_t = 0x00080000;
//
// The processor supports LZCNT instruction (counts the number of leading zero
// bits). - Haswell introduced
//
pub const CPU_FEATURE_LZCNT :uint64_t = 0x00100000;
//
// The processor supports HLE extension (hardware lock elision). - Haswell introduced
//
pub const CPU_FEATURE_HLE :uint64_t = 0x00200000;
//
// The processor supports RTM extension (restricted transactional memory) - Haswell AVX2 related.
//
pub const CPU_FEATURE_RTM :uint64_t = 0x00400000;
//
// The processor supports AVX2 instruction extension.
//
pub const CPU_FEATURE_AVX2 :uint64_t = 0x00800000;
//
// The processor supports AVX512 dword/qword instruction extension.
//
pub const CPU_FEATURE_AVX512DQ :uint64_t = 0x01000000;
//
// The processor supports the PTWRITE instruction.
//
pub const CPU_FEATURE_PTWRITE :uint64_t = 0x02000000;
//
// KNC instruction set
//
pub const CPU_FEATURE_KNCNI :uint64_t = 0x04000000;
//
// AVX512 foundation instructions
//
pub const CPU_FEATURE_AVX512F :uint64_t = 0x08000000;
//
// The processor supports uint add with OF or CF flags (ADOX, ADCX)
//
pub const CPU_FEATURE_ADX :uint64_t = 0x10000000;
//
// The processor supports RDSEED instruction.
//
pub const CPU_FEATURE_RDSEED :uint64_t = 0x20000000;
// AVX512IFMA52: vpmadd52huq and vpmadd52luq
pub const CPU_FEATURE_AVX512IFMA52 :uint64_t = 0x40000000;
//
// The processor is a full inorder (Silverthorne) processor
//
pub const CPU_FEATURE_F_INORDER :uint64_t = 0x80000000;
// AVX512 exponential and reciprocal instructions
pub const CPU_FEATURE_AVX512ER :uint64_t = 0x100000000;
// AVX512 prefetch instructions
pub const CPU_FEATURE_AVX512PF :uint64_t = 0x200000000;
// AVX-512 conflict detection instructions
pub const CPU_FEATURE_AVX512CD :uint64_t = 0x400000000;
// Secure Hash Algorithm instructions (SHA)
pub const CPU_FEATURE_SHA :uint64_t = 0x800000000;
// Memory Protection Extensions (MPX)
pub const CPU_FEATURE_MPX :uint64_t = 0x1000000000;
// AVX512BW - AVX512 byte/word vector instruction set
pub const CPU_FEATURE_AVX512BW :uint64_t = 0x2000000000;
// AVX512VL - 128/256-bit vector support of AVX512 instructions
pub const CPU_FEATURE_AVX512VL :uint64_t = 0x4000000000;
// AVX512VBMI: vpermb, vpermi2b, vpermt2b and vpmultishiftqb
pub const CPU_FEATURE_AVX512VBMI :uint64_t = 0x8000000000;
// AVX512_4FMAPS: Single Precision FMA for multivector(4 vector) operand.
pub const CPU_FEATURE_AVX512_4FMAPS :uint64_t = 0x10000000000;
// AVX512_4VNNIW: Vector Neural Network Instructions for multivector(4 vector) operand with word elements.
pub const CPU_FEATURE_AVX512_4VNNIW :uint64_t = 0x20000000000;
// AVX512_VPOPCNTDQ: 512-bit vector POPCNT instruction.
pub const CPU_FEATURE_AVX512_VPOPCNTDQ :uint64_t = 0x40000000000;
// AVX512_BITALG: vector bit algebra in AVX512
pub const CPU_FEATURE_AVX512_BITALG :uint64_t = 0x80000000000;
// AVX512_VBMI2: additional byte, word, dword and qword capabilities
pub const CPU_FEATURE_AVX512_VBMI2 :uint64_t = 0x100000000000;
// GFNI: Galois Field New Instructions.
pub const CPU_FEATURE_GFNI :uint64_t = 0x200000000000;
// VAES: vector AES instructions
pub const CPU_FEATURE_VAES :uint64_t = 0x400000000000;
// VPCLMULQDQ: Vector CLMUL instruction set.
pub const CPU_FEATURE_VPCLMULQDQ :uint64_t = 0x800000000000;
// AVX512_VNNI: vector Neural Network Instructions.
pub const CPU_FEATURE_AVX512_VNNI :uint64_t = 0x1000000000000;
// CLWB: Cache Line Write Back
pub const CPU_FEATURE_CLWB :uint64_t = 0x2000000000000;
// RDPID: Read Processor ID.
pub const CPU_FEATURE_RDPID :uint64_t = 0x4000000000000;
// IBT - Indirect branch tracking
pub const CPU_FEATURE_IBT :uint64_t = 0x8000000000000;
// Shadow stack
pub const CPU_FEATURE_SHSTK :uint64_t = 0x10000000000000;
// Intel Software Guard Extensions
pub const CPU_FEATURE_SGX :uint64_t = 0x20000000000000;
// Write back and do not invalidate cache
pub const CPU_FEATURE_WBNOINVD :uint64_t = 0x40000000000000;
// Platform configuration - 1 << 55
pub const CPU_FEATURE_PCONFIG :uint64_t = 0x80000000000000;
// Reserved feature bits
pub const RESERVED_CPU_FEATURE_BIT :uint64_t = !;
// Incompatible bits which we should unset in trts
pub const INCOMPAT_FEATURE_BIT :uint64_t = | | | | | ;