#![allow(dead_code)]
use tock_registers::{register_bitfields, register_structs, registers::ReadWrite};
pub use crate::soc::{SD_DRIVER_BASE, TOP_BASE};
pub const BLOCK_SIZE: usize = 0x200;
register_bitfields! [
u32,
pub SDMA_SYS_ADDR [
ADDR OFFSET(0) NUMBITS(32) []
],
pub BLK_SIZE_AND_CNT [
BLK_CNT OFFSET(16) NUMBITS(16) [],
SDMA_BUF_BDARY OFFSET(12) NUMBITS(3) [],
XFER_BLK_SIZE OFFSET(0) NUMBITS(12) []
],
pub ARGUMENT1 [
ARG OFFSET(0) NUMBITS(32) []
],
pub XFER_MODE_AND_CMD [
CMD_IDX OFFSET(24) NUMBITS(6) [],
CMD_TYPE OFFSET(22) NUMBITS(2) [
Normal = 0,
Suspend = 1,
Resume = 2,
Abort = 3
],
DATA_PRESENT OFFSET(21) NUMBITS(1) [],
CMD_IDX_CHK_EN OFFSET(20) NUMBITS(1) [],
CMD_CRC_CHK_EN OFFSET(19) NUMBITS(1) [],
SUB_CMD_FLAG OFFSET(18) NUMBITS(1) [],
RESP_TYPE OFFSET(16) NUMBITS(2) [
NoResponse = 0,
Response136 = 1,
Response48 = 2,
Response48Busy = 3
],
RESP_INT_EN OFFSET(8) NUMBITS(1) [],
RESP_ERR_CHK_EN OFFSET(7) NUMBITS(1) [],
RESP_TYPE_R1R5 OFFSET(6) NUMBITS(1) [],
MULTI_BLK_SEL OFFSET(5) NUMBITS(1) [],
DAT_XFER_DIR OFFSET(4) NUMBITS(1) [
Write = 0,
Read = 1
],
AUTO_CMD_EN OFFSET(2) NUMBITS(2) [
Disabled = 0,
AutoCmd12 = 1,
AutoCmd23 = 2
],
BLK_CNT_EN OFFSET(1) NUMBITS(1) [],
DMA_EN OFFSET(0) NUMBITS(1) []
],
pub RESPONSE0 [
RESP OFFSET(0) NUMBITS(32) []
],
pub RESPONSE1 [
RESP OFFSET(0) NUMBITS(32) []
],
pub RESPONSE2 [
RESP OFFSET(0) NUMBITS(32) []
],
pub RESPONSE3 [
RESP OFFSET(0) NUMBITS(32) []
],
pub BUF_DATA_PORT [
DATA OFFSET(0) NUMBITS(32) []
],
pub PRESENT_STATE [
CMD_LINE_STATE OFFSET(24) NUMBITS(1) [],
DAT_3_0_STATE OFFSET(20) NUMBITS(4) [],
CARD_WP_STATE OFFSET(19) NUMBITS(1) [],
CARD_CD_STATE OFFSET(18) NUMBITS(1) [],
CARD_STABLE OFFSET(17) NUMBITS(1) [],
CARD_INSERTED OFFSET(16) NUMBITS(1) [],
BUF_RD_EN OFFSET(11) NUMBITS(1) [],
BUF_WR_EN OFFSET(10) NUMBITS(1) [],
RD_XFER_ACTIVE OFFSET(9) NUMBITS(1) [],
WR_XFER_ACTIVE OFFSET(8) NUMBITS(1) [],
RE_TUNE_REQ OFFSET(3) NUMBITS(1) [],
DAT_LINE_ACTIVE OFFSET(2) NUMBITS(1) [],
CMD_INHIBIT_DAT OFFSET(1) NUMBITS(1) [],
CMD_INHIBIT OFFSET(0) NUMBITS(1) []
],
pub HOST_CTL1_PWR_BG_WUP [
WAKEUP_ON_CARD_REMV OFFSET(26) NUMBITS(1) [],
WAKEUP_ON_CARD_INSERT OFFSET(25) NUMBITS(1) [],
WAKEUP_ON_CARD_INT OFFSET(24) NUMBITS(1) [],
INT_BG OFFSET(19) NUMBITS(1) [],
READ_WAIT OFFSET(18) NUMBITS(1) [],
CONTINUE_REQ OFFSET(17) NUMBITS(1) [],
STOP_BG_REQ OFFSET(16) NUMBITS(1) [],
SD_BUS_VOL_SEL OFFSET(9) NUMBITS(3) [
V33 = 0b111,
V30 = 0b110,
V18 = 0b101
],
SD_BUS_PWR OFFSET(8) NUMBITS(1) [],
CARD_DET_SEL OFFSET(7) NUMBITS(1) [],
CARD_DET_TEST OFFSET(6) NUMBITS(1) [],
EXT_DAT_WIDTH OFFSET(5) NUMBITS(1) [],
DMA_SEL OFFSET(3) NUMBITS(2) [
SDMA = 0,
Reserved = 1,
ADMA2 = 2,
ADMA2_3 = 3
],
HS_EN OFFSET(2) NUMBITS(1) [
NormalSpeed = 0,
HighSpeed = 1
],
DAT_XFER_WIDTH OFFSET(1) NUMBITS(1) [
Width1Bit = 0,
Width4Bit = 1
],
LED_CTL OFFSET(0) NUMBITS(1) []
],
pub CLK_CTL [
SW_RST_DAT OFFSET(26) NUMBITS(1) [],
SW_RST_CMD OFFSET(25) NUMBITS(1) [],
SW_RST_ALL OFFSET(24) NUMBITS(1) [],
TOUT_CNT OFFSET(16) NUMBITS(4) [
TMCLK2p13 = 0,
TMCLK2p14 = 1,
TMCLK2p15 = 2,
TMCLK2p16 = 3,
TMCLK2p17 = 4,
TMCLK2p18 = 5,
TMCLK2p19 = 6,
TMCLK2p20 = 7,
TMCLK2p21 = 8,
TMCLK2p22 = 9,
TMCLK2p23 = 10,
TMCLK2p24 = 11,
TMCLK2p25 = 12,
TMCLK2p26 = 13,
TMCLK2p27 = 14,
Reserved = 15
],
FREQ_SEL OFFSET(8) NUMBITS(8) [],
UP_FREQ_SEL OFFSET(6) NUMBITS(2) [],
PLL_EN OFFSET(3) NUMBITS(1) [],
SD_CLK_EN OFFSET(2) NUMBITS(1) [],
INT_CLK_STABLE OFFSET(1) NUMBITS(1) [],
INT_CLK_EN OFFSET(0) NUMBITS(1) []
],
pub NORM_AND_ERR_INT_STS [
BOOT_ACK_ERR OFFSET(28) NUMBITS(1) [],
TUNE_ERR OFFSET(26) NUMBITS(1) [],
ADMA_ERR OFFSET(25) NUMBITS(1) [],
AUTO_CMD_ERR OFFSET(24) NUMBITS(1) [],
CURR_LIMIT_ERR OFFSET(23) NUMBITS(1) [],
DAT_ENDBIT_ERR OFFSET(22) NUMBITS(1) [],
DAT_CRC_ERR OFFSET(21) NUMBITS(1) [],
DAT_TOUT_ERR OFFSET(20) NUMBITS(1) [],
CMD_IDX_ERR OFFSET(19) NUMBITS(1) [],
CMD_ENDBIT_ERR OFFSET(18) NUMBITS(1) [],
CMD_CRC_ERR OFFSET(17) NUMBITS(1) [],
CMD_TOUT_ERR OFFSET(16) NUMBITS(1) [],
ERR_INT OFFSET(15) NUMBITS(1) [],
CQE_EVENT OFFSET(14) NUMBITS(1) [],
RE_TUNE_EVENT OFFSET(12) NUMBITS(1) [],
INT_C OFFSET(11) NUMBITS(1) [],
INT_B OFFSET(10) NUMBITS(1) [],
INT_A OFFSET(9) NUMBITS(1) [],
CARD_INT OFFSET(8) NUMBITS(1) [],
CARD_REMOVE_INT OFFSET(7) NUMBITS(1) [],
CARD_INSERT_INT OFFSET(6) NUMBITS(1) [],
BUF_RRDY OFFSET(5) NUMBITS(1) [],
BUF_WRDY OFFSET(4) NUMBITS(1) [],
DMA_INT OFFSET(3) NUMBITS(1) [],
BG_EVENT OFFSET(2) NUMBITS(1) [],
XFER_CMPL OFFSET(1) NUMBITS(1) [],
CMD_CMPL OFFSET(0) NUMBITS(1) []
],
pub NORM_AND_ERR_INT_STS_EN [
BOOT_ACK_ERR_EN OFFSET(28) NUMBITS(1) [],
TUNE_ERR_EN OFFSET(26) NUMBITS(1) [],
ADMA_ERR_EN OFFSET(25) NUMBITS(1) [],
AUTO_CMD_ERR_EN OFFSET(24) NUMBITS(1) [],
CURR_LIMIT_ERR_EN OFFSET(23) NUMBITS(1) [],
DAT_ENDBIT_ERR_EN OFFSET(22) NUMBITS(1) [],
DAT_CRC_ERR_EN OFFSET(21) NUMBITS(1) [],
DAT_TOUT_ERR_EN OFFSET(20) NUMBITS(1) [],
CMD_IDX_ERR_EN OFFSET(19) NUMBITS(1) [],
CMD_ENDBIT_ERR_EN OFFSET(18) NUMBITS(1) [],
CMD_CRC_ERR_EN OFFSET(17) NUMBITS(1) [],
CMD_TOUT_ERR_EN OFFSET(16) NUMBITS(1) [],
CQE_EVENT_EN OFFSET(14) NUMBITS(1) [],
RE_TUNE_EVENT_EN OFFSET(12) NUMBITS(1) [],
INT_C_EN OFFSET(11) NUMBITS(1) [],
INT_B_EN OFFSET(10) NUMBITS(1) [],
INT_A_EN OFFSET(9) NUMBITS(1) [],
CARD_INT_EN OFFSET(8) NUMBITS(1) [],
CARD_REMOVE_INT_EN OFFSET(7) NUMBITS(1) [],
CARD_INSERT_INT_EN OFFSET(6) NUMBITS(1) [],
BUF_RRDY_EN OFFSET(5) NUMBITS(1) [],
BUF_WRDY_EN OFFSET(4) NUMBITS(1) [],
DMA_INT_EN OFFSET(3) NUMBITS(1) [],
BG_EVENT_EN OFFSET(2) NUMBITS(1) [],
XFER_CMPL_EN OFFSET(1) NUMBITS(1) [],
CMD_CMPL_EN OFFSET(0) NUMBITS(1) []
],
pub NORM_AND_ERR_INT_SIG_EN [
BOOT_ACK_ERR_SIG_EN OFFSET(28) NUMBITS(1) [],
TUNE_ERR_SIG_EN OFFSET(26) NUMBITS(1) [],
ADMA_ERR_SIG_EN OFFSET(25) NUMBITS(1) [],
AUTO_CMD_ERR_SIG_EN OFFSET(24) NUMBITS(1) [],
CURR_LIMIT_ERR_SIG_EN OFFSET(23) NUMBITS(1) [],
DAT_ENDBIT_ERR_SIG_EN OFFSET(22) NUMBITS(1) [],
DAT_CRC_ERR_SIG_EN OFFSET(21) NUMBITS(1) [],
DAT_TOUT_ERR_SIG_EN OFFSET(20) NUMBITS(1) [],
CMD_IDX_ERR_SIG_EN OFFSET(19) NUMBITS(1) [],
CMD_ENDBIT_ERR_SIG_EN OFFSET(18) NUMBITS(1) [],
CMD_CRC_ERR_SIG_EN OFFSET(17) NUMBITS(1) [],
CMD_TOUT_ERR_SIG_EN OFFSET(16) NUMBITS(1) [],
CQE_EVENT_SIG_EN OFFSET(14) NUMBITS(1) [],
RE_TUNE_EVENT_SIG_EN OFFSET(12) NUMBITS(1) [],
INT_C_SIG_EN OFFSET(11) NUMBITS(1) [],
INT_B_SIG_EN OFFSET(10) NUMBITS(1) [],
INT_A_SIG_EN OFFSET(9) NUMBITS(1) [],
CARD_INT_SIG_EN OFFSET(8) NUMBITS(1) [],
CARD_REMOVE_INT_SIG_EN OFFSET(7) NUMBITS(1) [],
CARD_INSERT_INT_SIG_EN OFFSET(6) NUMBITS(1) [],
BUF_RRDY_SIG_EN OFFSET(5) NUMBITS(1) [],
BUF_WRDY_SIG_EN OFFSET(4) NUMBITS(1) [],
DMA_INT_SIG_EN OFFSET(3) NUMBITS(1) [],
BG_EVENT_SIG_EN OFFSET(2) NUMBITS(1) [],
XFER_CMPL_SIG_EN OFFSET(1) NUMBITS(1) [],
CMD_CMPL_SIG_EN OFFSET(0) NUMBITS(1) []
],
pub AUTO_CMD_ERR_AND_HOST_CTL2 [
PRESENT_VAL_EN OFFSET(31) NUMBITS(1) [],
ASYNC_INT_EN OFFSET(30) NUMBITS(1) [],
SAMPLE_CLK_SEL OFFSET(23) NUMBITS(1) [],
EXECUTE_TUNE OFFSET(22) NUMBITS(1) [],
DRV_SEL OFFSET(20) NUMBITS(2) [],
EN_18_SIG OFFSET(19) NUMBITS(1) [],
UHS_MODE_SEL OFFSET(16) NUMBITS(3) [
SDR12 = 0,
SDR25 = 1,
SDR50 = 2,
SDR104 = 3,
DDR50 = 4
],
CMD_NOT_ISSUE_BY_CMD12 OFFSET(7) NUMBITS(1) [],
AUTO_CMD_IDX_ERR OFFSET(4) NUMBITS(1) [],
AUTO_CMD_ENDBIT_ERR OFFSET(3) NUMBITS(1) [],
AUTO_CMD_CRC_ERR OFFSET(2) NUMBITS(1) [],
AUTO_CMD_TOUT_ERR OFFSET(1) NUMBITS(1) [],
AUTO_CMD12_NO_EXE OFFSET(0) NUMBITS(1) []
],
pub CAPABILITIES1 [
SLOT_TYPE OFFSET(30) NUMBITS(2) [
Removable = 0,
Embedded = 1,
SharedBus = 2
],
ASYNC_INT_SUPPORT OFFSET(29) NUMBITS(1) [],
BUS64_SUPPORT OFFSET(28) NUMBITS(1) [],
V18_SUPPORT OFFSET(26) NUMBITS(1) [],
V30_SUPPORT OFFSET(25) NUMBITS(1) [],
V33_SUPPORT OFFSET(24) NUMBITS(1) [],
SUSP_RES_SUPPORT OFFSET(23) NUMBITS(1) [],
SDMA_SUPPORT OFFSET(22) NUMBITS(1) [],
HS_SUPPORT OFFSET(21) NUMBITS(1) [],
ADMA2_SUPPORT OFFSET(19) NUMBITS(1) [],
EMBEDDED_8BIT OFFSET(18) NUMBITS(1) [],
MAX_BLK_LEN OFFSET(16) NUMBITS(2) [],
BASE_CLK_FREQ OFFSET(8) NUMBITS(8) [],
TOUT_CLK_UNIT OFFSET(7) NUMBITS(1) [],
TOUT_CLK_FREQ OFFSET(0) NUMBITS(6) []
],
pub CAPABILITIES2 [
CLK_MULTIPLIER OFFSET(16) NUMBITS(8) [],
RETUNE_MODE OFFSET(14) NUMBITS(2) [],
TUNE_SDR50 OFFSET(13) NUMBITS(1) [],
RETUNE_TIMER OFFSET(8) NUMBITS(4) [],
DRV_D_SUPPORT OFFSET(6) NUMBITS(1) [],
DRV_C_SUPPORT OFFSET(5) NUMBITS(1) [],
DRV_A_SUPPORT OFFSET(4) NUMBITS(1) [],
DDR50_SUPPORT OFFSET(2) NUMBITS(1) [],
SDR104_SUPPORT OFFSET(1) NUMBITS(1) [],
SDR50_SUPPORT OFFSET(0) NUMBITS(1) []
],
pub EMMC_CTL [
TIMER_CLK_SEL OFFSET(13) NUMBITS(1) [],
CQE_PREFETCH_DISABLE OFFSET(10) NUMBITS(1) [],
CQE_ALGO_SEL OFFSET(9) NUMBITS(1) [],
EMMC_RSTN_OEN OFFSET(6) NUMBITS(1) [],
EMMC_RSTN OFFSET(5) NUMBITS(1) [],
DISABLE_DATA_CRC_CHECK OFFSET(3) NUMBITS(1) [],
CLK_FREE_EN OFFSET(2) NUMBITS(1) [],
LATANCY_1T OFFSET(1) NUMBITS(1) [],
EMMC_FUNC_EN OFFSET(0) NUMBITS(1) []
],
pub TOP_SD_PWRSW_CTRL [
PWRSW_CTRL OFFSET(0) NUMBITS(8) []
]
];
register_structs! {
pub SdmmcRegisters {
(0x000 => pub sdma_sys_addr: ReadWrite<u32, SDMA_SYS_ADDR::Register>),
(0x004 => pub blk_size_and_cnt: ReadWrite<u32, BLK_SIZE_AND_CNT::Register>),
(0x008 => pub argument1: ReadWrite<u32, ARGUMENT1::Register>),
(0x00C => pub xfer_mode_and_cmd: ReadWrite<u32, XFER_MODE_AND_CMD::Register>),
(0x010 => pub response0: ReadWrite<u32, RESPONSE0::Register>),
(0x014 => pub response1: ReadWrite<u32, RESPONSE1::Register>),
(0x018 => pub response2: ReadWrite<u32, RESPONSE2::Register>),
(0x01C => pub response3: ReadWrite<u32, RESPONSE3::Register>),
(0x020 => pub buf_data_port: ReadWrite<u32, BUF_DATA_PORT::Register>),
(0x024 => pub present_state: ReadWrite<u32, PRESENT_STATE::Register>),
(0x028 => pub host_ctl1_pwr_bg_wup: ReadWrite<u32, HOST_CTL1_PWR_BG_WUP::Register>),
(0x02C => pub clk_ctl: ReadWrite<u32, CLK_CTL::Register>),
(0x030 => pub norm_and_err_int_sts: ReadWrite<u32, NORM_AND_ERR_INT_STS::Register>),
(0x034 => pub norm_and_err_int_sts_en: ReadWrite<u32, NORM_AND_ERR_INT_STS_EN::Register>),
(0x038 => pub norm_and_err_int_sig_en: ReadWrite<u32, NORM_AND_ERR_INT_SIG_EN::Register>),
(0x03C => pub auto_cmd_err_and_host_ctl2: ReadWrite<u32, AUTO_CMD_ERR_AND_HOST_CTL2::Register>),
(0x040 => pub capabilities1: ReadWrite<u32, CAPABILITIES1::Register>),
(0x044 => pub capabilities2: ReadWrite<u32, CAPABILITIES2::Register>),
(0x048 => _reserved0),
(0x200 => pub emmc_ctl: ReadWrite<u32, EMMC_CTL::Register>),
(0x204 => @END),
}
}
register_structs! {
pub TopRegisters {
(0x000 => _reserved0),
(0x1F4 => pub sd_pwrsw_ctrl: ReadWrite<u32, TOP_SD_PWRSW_CTRL::Register>),
(0x1F8 => @END),
}
}
#[derive(Debug)]
pub enum CmdError {
IntError,
CmdTimeout,
DataTimeout,
CrcError,
}
#[derive(Debug, Clone, Copy)]
pub enum CommandType {
CMD(u8),
ACMD(u8),
}
impl CommandType {
pub fn num(&self) -> u8 {
match self {
CommandType::CMD(t) => *t,
CommandType::ACMD(t) => *t,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum PowerLevel {
V33,
V30,
V18,
Close,
}
#[derive(Debug, Clone, Copy)]
pub enum ResponseType {
None,
R1,
R1b,
R2,
R3,
R6,
R7,
}