#![allow(dead_code)]
use tock_registers::{register_bitfields, register_structs, registers::ReadWrite};
register_bitfields! [
u32,
pub IC_CON [
IC_SLAVE_DISABLE OFFSET(6) NUMBITS(1) [],
IC_RESTART_EN OFFSET(5) NUMBITS(1) [],
IC_10BITADDR_MASTER OFFSET(4) NUMBITS(1) [],
IC_10BITADDR_SLAVE OFFSET(3) NUMBITS(1) [],
SPEED OFFSET(1) NUMBITS(2) [
Standard = 1,
Fast = 2
],
MASTER_MODE OFFSET(0) NUMBITS(1) []
],
pub IC_TAR [
SPECIAL OFFSET(11) NUMBITS(1) [],
GC_OR_START OFFSET(10) NUMBITS(1) [
GeneralCall = 0,
StartByte = 1
],
IC_TAR OFFSET(0) NUMBITS(10) []
],
pub IC_SAR [
IC_SAR OFFSET(0) NUMBITS(10) []
],
pub IC_DATA_CMD [
RESTART OFFSET(10) NUMBITS(1) [],
STOP OFFSET(9) NUMBITS(1) [],
CMD OFFSET(8) NUMBITS(1) [
Write = 0,
Read = 1
],
DAT OFFSET(0) NUMBITS(8) []
],
pub IC_SS_SCL_HCNT [
IC_SS_SCL_HCNT OFFSET(0) NUMBITS(16) []
],
pub IC_SS_SCL_LCNT [
IC_SS_SCL_LCNT OFFSET(0) NUMBITS(16) []
],
pub IC_FS_SCL_HCNT [
IC_FS_SCL_HCNT OFFSET(0) NUMBITS(16) []
],
pub IC_FS_SCL_LCNT [
IC_FS_SCL_LCNT OFFSET(0) NUMBITS(16) []
],
pub IC_INTR_STAT [
R_GEN_CALL OFFSET(11) NUMBITS(1) [],
R_START_DET OFFSET(10) NUMBITS(1) [],
R_STOP_DET OFFSET(9) NUMBITS(1) [],
R_ACTIVITY OFFSET(8) NUMBITS(1) [],
R_RX_DONE OFFSET(7) NUMBITS(1) [],
R_TX_ABRT OFFSET(6) NUMBITS(1) [],
R_RD_REQ OFFSET(5) NUMBITS(1) [],
R_TX_EMPTY OFFSET(4) NUMBITS(1) [],
R_TX_OVER OFFSET(3) NUMBITS(1) [],
R_RX_FULL OFFSET(2) NUMBITS(1) [],
R_RX_OVER OFFSET(1) NUMBITS(1) [],
R_RX_UNDER OFFSET(0) NUMBITS(1) []
],
pub IC_INTR_MASK [
M_GEN_CALL OFFSET(11) NUMBITS(1) [],
M_START_DET OFFSET(10) NUMBITS(1) [],
M_STOP_DET OFFSET(9) NUMBITS(1) [],
M_ACTIVITY OFFSET(8) NUMBITS(1) [],
M_RX_DONE OFFSET(7) NUMBITS(1) [],
M_TX_ABRT OFFSET(6) NUMBITS(1) [],
M_RD_REQ OFFSET(5) NUMBITS(1) [],
M_TX_EMPTY OFFSET(4) NUMBITS(1) [],
M_TX_OVER OFFSET(3) NUMBITS(1) [],
M_RX_FULL OFFSET(2) NUMBITS(1) [],
M_RX_OVER OFFSET(1) NUMBITS(1) [],
M_RX_UNDER OFFSET(0) NUMBITS(1) []
],
pub IC_RAW_INTR_STAT [
IST_GEN_CALL OFFSET(11) NUMBITS(1) [],
IST_START_DET OFFSET(10) NUMBITS(1) [],
IST_STOP_DET OFFSET(9) NUMBITS(1) [],
IST_ACTIVITY OFFSET(8) NUMBITS(1) [],
IST_RX_DONE OFFSET(7) NUMBITS(1) [],
IST_TX_ABRT OFFSET(6) NUMBITS(1) [],
IST_RD_REQ OFFSET(5) NUMBITS(1) [],
IST_TX_EMPTY OFFSET(4) NUMBITS(1) [],
IST_TX_OVER OFFSET(3) NUMBITS(1) [],
IST_RX_FULL OFFSET(2) NUMBITS(1) [],
IST_RX_OVER OFFSET(1) NUMBITS(1) [],
IST_RX_UNDER OFFSET(0) NUMBITS(1) []
],
pub IC_RX_TL [
RX_TL OFFSET(0) NUMBITS(8) []
],
pub IC_TX_TL [
TX_TL OFFSET(0) NUMBITS(8) []
],
pub IC_CLR_INTR [
CLR_INTR OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_RX_UNDER [
CLR_RX_UNDER OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_RX_OVER [
CLR_RX_OVER OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_TX_OVER [
CLR_TX_OVER OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_RD_REQ [
CLR_RD_REQ OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_TX_ABRT [
CLR_TX_ABRT OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_RX_DONE [
CLR_RX_DONE OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_ACTIVITY [
CLR_ACTIVITY OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_STOP_DET [
CLR_STOP_DET OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_START_DET [
CLR_START_DET OFFSET(0) NUMBITS(1) []
],
pub IC_CLR_GEN_CALL [
CLR_GEN_CALL OFFSET(0) NUMBITS(1) []
],
pub IC_ENABLE [
ENABLE OFFSET(0) NUMBITS(1) []
],
pub IC_STATUS [
ST_SLV_ACTIVITY OFFSET(6) NUMBITS(1) [],
ST_MST_ACTIVITY OFFSET(5) NUMBITS(1) [],
ST_RFF OFFSET(4) NUMBITS(1) [],
ST_RFNE OFFSET(3) NUMBITS(1) [],
ST_TFE OFFSET(2) NUMBITS(1) [],
ST_TFNF OFFSET(1) NUMBITS(1) [],
ST_ACTIVITY OFFSET(0) NUMBITS(1) []
],
pub IC_TXFLR [
TXFLR OFFSET(0) NUMBITS(7) []
],
pub IC_RXFLR [
RXFLR OFFSET(0) NUMBITS(7) []
],
pub IC_SDA_HOLD [
IC_SDA_HOLD OFFSET(0) NUMBITS(16) []
],
pub IC_TX_ABRT_SOURCE [
TX_ABRT_SOURCE OFFSET(0) NUMBITS(16) []
],
pub IC_SLV_DATA_NACK_ONLY [
NACK OFFSET(0) NUMBITS(1) []
],
pub IC_DMA_CR [
TDMAE OFFSET(1) NUMBITS(1) [],
RDMAE OFFSET(0) NUMBITS(1) []
],
pub IC_DMA_TDLR [
DMATDL OFFSET(0) NUMBITS(6) []
],
pub IC_DMA_RDLR [
DMARDL OFFSET(0) NUMBITS(6) []
],
pub IC_SDA_SETUP [
SDA_SETUP OFFSET(0) NUMBITS(1) []
],
pub IC_ACK_GENERAL_CALL [
ACK_GEN_CALL OFFSET(0) NUMBITS(1) []
],
pub IC_ENABLE_STATUS [
SLV_RX_DATA_LOST OFFSET(2) NUMBITS(1) [],
SLV_DISABLED_WHILE_BUSY OFFSET(1) NUMBITS(1) [],
IC_EN OFFSET(0) NUMBITS(1) []
],
pub IC_FS_SPKLEN [
IC_FS_SPKLEN OFFSET(0) NUMBITS(8) []
],
pub IC_HS_SPKLEN [
IC_HS_SPKLEN OFFSET(0) NUMBITS(8) []
]
];
register_structs! {
pub I2cRegisters {
(0x000 => pub ic_con: ReadWrite<u32, IC_CON::Register>),
(0x004 => pub ic_tar: ReadWrite<u32, IC_TAR::Register>),
(0x008 => pub ic_sar: ReadWrite<u32, IC_SAR::Register>),
(0x00c => _reserved0),
(0x010 => pub ic_data_cmd: ReadWrite<u32, IC_DATA_CMD::Register>),
(0x014 => pub ic_ss_scl_hcnt: ReadWrite<u32, IC_SS_SCL_HCNT::Register>),
(0x018 => pub ic_ss_scl_lcnt: ReadWrite<u32, IC_SS_SCL_LCNT::Register>),
(0x01c => pub ic_fs_scl_hcnt: ReadWrite<u32, IC_FS_SCL_HCNT::Register>),
(0x020 => pub ic_fs_scl_lcnt: ReadWrite<u32, IC_FS_SCL_LCNT::Register>),
(0x024 => _reserved1),
(0x02c => pub ic_intr_stat: ReadWrite<u32, IC_INTR_STAT::Register>),
(0x030 => pub ic_intr_mask: ReadWrite<u32, IC_INTR_MASK::Register>),
(0x034 => pub ic_raw_intr_stat: ReadWrite<u32, IC_RAW_INTR_STAT::Register>),
(0x038 => pub ic_rx_tl: ReadWrite<u32, IC_RX_TL::Register>),
(0x03c => pub ic_tx_tl: ReadWrite<u32, IC_TX_TL::Register>),
(0x040 => pub ic_clr_intr: ReadWrite<u32, IC_CLR_INTR::Register>),
(0x044 => pub ic_clr_rx_under: ReadWrite<u32, IC_CLR_RX_UNDER::Register>),
(0x048 => pub ic_clr_rx_over: ReadWrite<u32, IC_CLR_RX_OVER::Register>),
(0x04c => pub ic_clr_tx_over: ReadWrite<u32, IC_CLR_TX_OVER::Register>),
(0x050 => pub ic_clr_rd_req: ReadWrite<u32, IC_CLR_RD_REQ::Register>),
(0x054 => pub ic_clr_tx_abrt: ReadWrite<u32, IC_CLR_TX_ABRT::Register>),
(0x058 => pub ic_clr_rx_done: ReadWrite<u32, IC_CLR_RX_DONE::Register>),
(0x05c => pub ic_clr_activity: ReadWrite<u32, IC_CLR_ACTIVITY::Register>),
(0x060 => pub ic_clr_stop_det: ReadWrite<u32, IC_CLR_STOP_DET::Register>),
(0x064 => pub ic_clr_start_det: ReadWrite<u32, IC_CLR_START_DET::Register>),
(0x068 => pub ic_clr_gen_call: ReadWrite<u32, IC_CLR_GEN_CALL::Register>),
(0x06c => pub ic_enable: ReadWrite<u32, IC_ENABLE::Register>),
(0x070 => pub ic_status: ReadWrite<u32, IC_STATUS::Register>),
(0x074 => pub ic_txflr: ReadWrite<u32, IC_TXFLR::Register>),
(0x078 => pub ic_rxflr: ReadWrite<u32, IC_RXFLR::Register>),
(0x07c => pub ic_sda_hold: ReadWrite<u32, IC_SDA_HOLD::Register>),
(0x080 => pub ic_tx_abrt_source: ReadWrite<u32, IC_TX_ABRT_SOURCE::Register>),
(0x084 => pub ic_slv_data_nack_only: ReadWrite<u32, IC_SLV_DATA_NACK_ONLY::Register>),
(0x088 => pub ic_dma_cr: ReadWrite<u32, IC_DMA_CR::Register>),
(0x08c => pub ic_dma_tdlr: ReadWrite<u32, IC_DMA_TDLR::Register>),
(0x090 => pub ic_dma_rdlr: ReadWrite<u32, IC_DMA_RDLR::Register>),
(0x094 => pub ic_sda_setup: ReadWrite<u32, IC_SDA_SETUP::Register>),
(0x098 => pub ic_ack_general_call: ReadWrite<u32, IC_ACK_GENERAL_CALL::Register>),
(0x09c => pub ic_enable_status: ReadWrite<u32, IC_ENABLE_STATUS::Register>),
(0x0a0 => pub ic_fs_spklen: ReadWrite<u32, IC_FS_SPKLEN::Register>),
(0x0a4 => pub ic_hs_spklen: ReadWrite<u32, IC_HS_SPKLEN::Register>),
(0x0a8 => @END),
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum I2cError {
TxAbort,
RxOverflow,
TxOverflow,
Timeout,
BusBusy,
Nack,
ArbitrationLost,
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[repr(u32)]
pub enum I2cSpeed {
Standard = 1,
Fast = 2,
}
impl I2cSpeed {
pub fn from_u32(value: u32) -> Option<Self> {
match value {
1 => Some(Self::Standard),
2 => Some(Self::Fast),
_ => None,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum I2cAddressMode {
SevenBit,
TenBit,
}
pub const I2C_TX_FIFO_DEPTH: usize = 64;
pub const I2C_RX_FIFO_DEPTH: usize = 64;
pub const I2C_DEFAULT_TIMEOUT: u32 = 100_000;