use tock_registers::interfaces::{Readable, Writeable};
use super::regs::{Dwc3GmacRegs, MII_CLK_CSR_60_100M_DIV42, MiiAddr};
const MDIO_POLL_LIMIT: u32 = 100_000;
#[inline]
fn mdio_wait(gmac: &Dwc3GmacRegs) {
let mut t = MDIO_POLL_LIMIT;
while gmac.mii_addr.is_set(MiiAddr::MII_BUSY) {
t = t.wrapping_sub(1);
if t == 0 {
break;
}
}
}
pub fn mdio_read(gmac: &Dwc3GmacRegs, phy: u32, reg: u32) -> u16 {
mdio_wait(gmac);
gmac.mii_addr.write(
MiiAddr::MII_PHY.val(phy)
+ MiiAddr::MII_REG.val(reg)
+ MiiAddr::MII_CLK_CSR.val(MII_CLK_CSR_60_100M_DIV42)
+ MiiAddr::MII_BUSY::SET,
);
mdio_wait(gmac);
gmac.mii_data.get() as u16
}
pub fn mdio_write(gmac: &Dwc3GmacRegs, phy: u32, reg: u32, data: u16) {
mdio_wait(gmac);
gmac.mii_data.set(data as u32);
gmac.mii_addr.write(
MiiAddr::MII_PHY.val(phy)
+ MiiAddr::MII_REG.val(reg)
+ MiiAddr::MII_CLK_CSR.val(MII_CLK_CSR_60_100M_DIV42)
+ MiiAddr::MII_WRITE::SET
+ MiiAddr::MII_BUSY::SET,
);
mdio_wait(gmac);
}