#![allow(dead_code)]
use tock_registers::{register_bitfields, register_structs, registers::ReadWrite};
register_bitfields! [
u32,
pub HLPERIOD [
HLPERIOD OFFSET(0) NUMBITS(30) []
],
pub PERIOD [
PERIOD OFFSET(0) NUMBITS(30) []
],
pub POLARITY [
POLARITY OFFSET(0) NUMBITS(4) [],
PWMMODE OFFSET(8) NUMBITS(4) [],
SHIFTMODE OFFSET(16) NUMBITS(1) [],
PCLK_FORCE_EN OFFSET(20) NUMBITS(1) []
],
pub PWMSTART [
PWMSTART OFFSET(0) NUMBITS(4) []
],
pub PWMDONE [
PWMDONE OFFSET(0) NUMBITS(4) []
],
pub PWMUPDATE [
PWMUPDATE OFFSET(0) NUMBITS(4) []
],
pub PCOUNT [
PCOUNT OFFSET(0) NUMBITS(24) []
],
pub PULSECOUNT [
PULSECOUNT OFFSET(0) NUMBITS(24) []
],
pub SHIFTCOUNT [
SHIFTCOUNT OFFSET(0) NUMBITS(24) []
],
pub SHIFTSTART [
SHIFTSTART OFFSET(0) NUMBITS(1) []
],
pub PWM_OE [
PWM_OE OFFSET(0) NUMBITS(4) []
]
];
register_structs! {
pub PwmRegisters {
(0x000 => pub hlperiod0: ReadWrite<u32, HLPERIOD::Register>),
(0x004 => pub period0: ReadWrite<u32, PERIOD::Register>),
(0x008 => pub hlperiod1: ReadWrite<u32, HLPERIOD::Register>),
(0x00c => pub period1: ReadWrite<u32, PERIOD::Register>),
(0x010 => pub hlperiod2: ReadWrite<u32, HLPERIOD::Register>),
(0x014 => pub period2: ReadWrite<u32, PERIOD::Register>),
(0x018 => pub hlperiod3: ReadWrite<u32, HLPERIOD::Register>),
(0x01c => pub period3: ReadWrite<u32, PERIOD::Register>),
(0x020 => _reserved0),
(0x040 => pub polarity: ReadWrite<u32, POLARITY::Register>),
(0x044 => pub pwmstart: ReadWrite<u32, PWMSTART::Register>),
(0x048 => pub pwmdone: ReadWrite<u32, PWMDONE::Register>),
(0x04c => pub pwmupdate: ReadWrite<u32, PWMUPDATE::Register>),
(0x050 => pub pcount0: ReadWrite<u32, PCOUNT::Register>),
(0x054 => pub pcount1: ReadWrite<u32, PCOUNT::Register>),
(0x058 => pub pcount2: ReadWrite<u32, PCOUNT::Register>),
(0x05c => pub pcount3: ReadWrite<u32, PCOUNT::Register>),
(0x060 => pub pulsecount0: ReadWrite<u32, PULSECOUNT::Register>),
(0x064 => pub pulsecount1: ReadWrite<u32, PULSECOUNT::Register>),
(0x068 => pub pulsecount2: ReadWrite<u32, PULSECOUNT::Register>),
(0x06c => pub pulsecount3: ReadWrite<u32, PULSECOUNT::Register>),
(0x070 => _reserved1),
(0x080 => pub shiftcount0: ReadWrite<u32, SHIFTCOUNT::Register>),
(0x084 => pub shiftcount1: ReadWrite<u32, SHIFTCOUNT::Register>),
(0x088 => pub shiftcount2: ReadWrite<u32, SHIFTCOUNT::Register>),
(0x08c => pub shiftcount3: ReadWrite<u32, SHIFTCOUNT::Register>),
(0x090 => pub shiftstart: ReadWrite<u32, SHIFTSTART::Register>),
(0x094 => _reserved2),
(0x0d0 => pub pwm_oe: ReadWrite<u32, PWM_OE::Register>),
(0x0d4 => @END),
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum PwmError {
InvalidChannel,
InvalidPeriod,
InvalidDutyCycle,
InvalidPulseCount,
Busy,
ConfigError,
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[repr(u8)]
pub enum PwmMode {
Continuous = 0,
PulseCount = 1,
}
impl PwmMode {
pub fn from_u8(value: u8) -> Option<Self> {
match value {
0 => Some(Self::Continuous),
1 => Some(Self::PulseCount),
_ => None,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[repr(u8)]
pub enum PwmPolarity {
ActiveHigh = 0,
ActiveLow = 1,
}
impl PwmPolarity {
pub fn from_u8(value: u8) -> Option<Self> {
match value {
0 => Some(Self::ActiveHigh),
1 => Some(Self::ActiveLow),
_ => None,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum PwmClockSource {
Clk100MHz,
Clk148_5MHz,
}
impl PwmClockSource {
pub const fn frequency(&self) -> u32 {
match self {
Self::Clk100MHz => 100_000_000,
Self::Clk148_5MHz => 148_500_000,
}
}
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[repr(u8)]
pub enum PwmChannel {
Channel0 = 0,
Channel1 = 1,
Channel2 = 2,
Channel3 = 3,
}
impl PwmChannel {
pub fn from_u8(value: u8) -> Option<Self> {
match value {
0 => Some(Self::Channel0),
1 => Some(Self::Channel1),
2 => Some(Self::Channel2),
3 => Some(Self::Channel3),
_ => None,
}
}
pub const fn index(&self) -> u8 {
*self as u8
}
pub const fn mask(&self) -> u32 {
1 << (*self as u32)
}
}
pub const PWM_MAX_PERIOD: u32 = (1 << 30) - 1;
pub const PWM_MAX_PULSE_COUNT: u32 = (1 << 24) - 1;
pub const PWM_MAX_SHIFT_COUNT: u32 = (1 << 24) - 1;
pub const PWM_DEFAULT_CLK_FREQ: u32 = 100_000_000;