sf32lb52_pac/epic/
debug.rs

1///Register `DEBUG` reader
2pub type R = crate::R<DEBUGrs>;
3///Register `DEBUG` writer
4pub type W = crate::W<DEBUGrs>;
5///Field `DEBUG_OUT_SEL` reader -
6pub type DebugOutSelR = crate::FieldReader;
7///Field `DEBUG_OUT_SEL` writer -
8pub type DebugOutSelW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `DEBUG_INT_SEL` reader -
10pub type DebugIntSelR = crate::FieldReader;
11///Field `DEBUG_INT_SEL` writer -
12pub type DebugIntSelW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13///Field `DEBUG_INT_DATA` reader - 4'h0: RSVD 4'h1: OL0 debug info 4'h2: OL1 debug info 4'h3: OL2 debug info 4'h4: VL debug info1 4'h5: VL debug info2 4'h6: ROI debug out 4'h7: mem intfa debug out 4'h8: mem intfb debug out 4'h9: ahb ctrl debug out 4'ha: ROI XX 4'hb: ROI YY 4'hc: EPIC_EZIP debug out others: RSVD
14pub type DebugIntDataR = crate::FieldReader<u16>;
15///Field `DEBUG_INT_DATA` writer - 4'h0: RSVD 4'h1: OL0 debug info 4'h2: OL1 debug info 4'h3: OL2 debug info 4'h4: VL debug info1 4'h5: VL debug info2 4'h6: ROI debug out 4'h7: mem intfa debug out 4'h8: mem intfb debug out 4'h9: ahb ctrl debug out 4'ha: ROI XX 4'hb: ROI YY 4'hc: EPIC_EZIP debug out others: RSVD
16pub type DebugIntDataW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
17impl R {
18    ///Bits 0:3
19    #[inline(always)]
20    pub fn debug_out_sel(&self) -> DebugOutSelR {
21        DebugOutSelR::new((self.bits & 0x0f) as u8)
22    }
23    ///Bits 4:7
24    #[inline(always)]
25    pub fn debug_int_sel(&self) -> DebugIntSelR {
26        DebugIntSelR::new(((self.bits >> 4) & 0x0f) as u8)
27    }
28    ///Bits 16:31 - 4'h0: RSVD 4'h1: OL0 debug info 4'h2: OL1 debug info 4'h3: OL2 debug info 4'h4: VL debug info1 4'h5: VL debug info2 4'h6: ROI debug out 4'h7: mem intfa debug out 4'h8: mem intfb debug out 4'h9: ahb ctrl debug out 4'ha: ROI XX 4'hb: ROI YY 4'hc: EPIC_EZIP debug out others: RSVD
29    #[inline(always)]
30    pub fn debug_int_data(&self) -> DebugIntDataR {
31        DebugIntDataR::new(((self.bits >> 16) & 0xffff) as u16)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("DEBUG")
37            .field("debug_int_data", &self.debug_int_data())
38            .field("debug_int_sel", &self.debug_int_sel())
39            .field("debug_out_sel", &self.debug_out_sel())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:3
45    #[inline(always)]
46    pub fn debug_out_sel(&mut self) -> DebugOutSelW<DEBUGrs> {
47        DebugOutSelW::new(self, 0)
48    }
49    ///Bits 4:7
50    #[inline(always)]
51    pub fn debug_int_sel(&mut self) -> DebugIntSelW<DEBUGrs> {
52        DebugIntSelW::new(self, 4)
53    }
54    ///Bits 16:31 - 4'h0: RSVD 4'h1: OL0 debug info 4'h2: OL1 debug info 4'h3: OL2 debug info 4'h4: VL debug info1 4'h5: VL debug info2 4'h6: ROI debug out 4'h7: mem intfa debug out 4'h8: mem intfb debug out 4'h9: ahb ctrl debug out 4'ha: ROI XX 4'hb: ROI YY 4'hc: EPIC_EZIP debug out others: RSVD
55    #[inline(always)]
56    pub fn debug_int_data(&mut self) -> DebugIntDataW<DEBUGrs> {
57        DebugIntDataW::new(self, 16)
58    }
59}
60///
61///
62///You can [`read`](crate::Reg::read) this register and get [`debug::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63pub struct DEBUGrs;
64impl crate::RegisterSpec for DEBUGrs {
65    type Ux = u32;
66}
67///`read()` method returns [`debug::R`](R) reader structure
68impl crate::Readable for DEBUGrs {}
69///`write(|w| ..)` method takes [`debug::W`](W) writer structure
70impl crate::Writable for DEBUGrs {
71    type Safety = crate::Unsafe;
72    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
74}
75///`reset()` method sets DEBUG to value 0
76impl crate::Resettable for DEBUGrs {
77    const RESET_VALUE: u32 = 0;
78}
sf32lb52_pac/epic/debug.rs

sf32lb52_pac/epic/
debug.rs
