#![doc = "Peripheral access API for SF32LB52X microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
use core::marker::PhantomData;
use core::ops::Deref;
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 3;
#[allow(unused_imports)]
use generic::*;
#[doc = "Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 0] = [];
#[doc = r"Enumeration of all the interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
pub enum Interrupt {}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
match self {}
}
}
#[doc = "HPSYS_RCC"]
pub struct HpsysRcc {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for HpsysRcc {}
impl HpsysRcc {
#[doc = r"Pointer to the register block"]
pub const PTR: *const hpsys_rcc::RegisterBlock = 0x5000_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const hpsys_rcc::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for HpsysRcc {
type Target = hpsys_rcc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for HpsysRcc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HpsysRcc").finish()
}
}
#[doc = "HPSYS_RCC"]
pub mod hpsys_rcc {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
rstr1: Rstr1,
rstr2: Rstr2,
enr1: Enr1,
enr2: Enr2,
esr1: Esr1,
esr2: Esr2,
ecr1: Ecr1,
ecr2: Ecr2,
csr: Csr,
cfgr: Cfgr,
usbcr: Usbcr,
dll1cr: Dll1cr,
dll2cr: Dll2cr,
hrccal1: Hrccal1,
hrccal2: Hrccal2,
rsvd1: Rsvd1,
_reserved16: [u8; 0x04],
dwcfgr: Dwcfgr,
}
impl RegisterBlock {
#[doc = "0x00 - Reset Register 1"]
#[inline(always)]
pub const fn rstr1(&self) -> &Rstr1 {
&self.rstr1
}
#[doc = "0x04 - Reset Register 2"]
#[inline(always)]
pub const fn rstr2(&self) -> &Rstr2 {
&self.rstr2
}
#[doc = "0x08 - Enable Register 1"]
#[inline(always)]
pub const fn enr1(&self) -> &Enr1 {
&self.enr1
}
#[doc = "0x0c - Enable Register 2"]
#[inline(always)]
pub const fn enr2(&self) -> &Enr2 {
&self.enr2
}
#[doc = "0x10 - Enable Set Register 1"]
#[inline(always)]
pub const fn esr1(&self) -> &Esr1 {
&self.esr1
}
#[doc = "0x14 - Enable Set Register 2"]
#[inline(always)]
pub const fn esr2(&self) -> &Esr2 {
&self.esr2
}
#[doc = "0x18 - Enable Clear Register 1"]
#[inline(always)]
pub const fn ecr1(&self) -> &Ecr1 {
&self.ecr1
}
#[doc = "0x1c - Enable Clear Register 2"]
#[inline(always)]
pub const fn ecr2(&self) -> &Ecr2 {
&self.ecr2
}
#[doc = "0x20 - Clock Select Register"]
#[inline(always)]
pub const fn csr(&self) -> &Csr {
&self.csr
}
#[doc = "0x24 - Clock Configuration Register"]
#[inline(always)]
pub const fn cfgr(&self) -> &Cfgr {
&self.cfgr
}
#[doc = "0x28 - USBC Control Register"]
#[inline(always)]
pub const fn usbcr(&self) -> &Usbcr {
&self.usbcr
}
#[doc = "0x2c - DLL1 Control Register"]
#[inline(always)]
pub const fn dll1cr(&self) -> &Dll1cr {
&self.dll1cr
}
#[doc = "0x30 - DLL2 Control Register"]
#[inline(always)]
pub const fn dll2cr(&self) -> &Dll2cr {
&self.dll2cr
}
#[doc = "0x34 - HRC Calibration Register 1"]
#[inline(always)]
pub const fn hrccal1(&self) -> &Hrccal1 {
&self.hrccal1
}
#[doc = "0x38 - HRC Calibration Register 2"]
#[inline(always)]
pub const fn hrccal2(&self) -> &Hrccal2 {
&self.hrccal2
}
#[doc = "0x3c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x44 - Deep WFI mode Clock Configuration Register"]
#[inline(always)]
pub const fn dwcfgr(&self) -> &Dwcfgr {
&self.dwcfgr
}
}
#[doc = "RSTR1 (rw) register accessor: Reset Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstr1`]
module"]
#[doc(alias = "RSTR1")]
pub type Rstr1 = crate::Reg<rstr1::Rstr1Spec>;
#[doc = "Reset Register 1"]
pub mod rstr1 {
#[doc = "Register `RSTR1` reader"]
pub type R = crate::R<Rstr1Spec>;
#[doc = "Register `RSTR1` writer"]
pub type W = crate::W<Rstr1Spec>;
#[doc = "Field `DMAC1` reader - 0 - no reset; 1 - reset"]
pub type Dmac1R = crate::BitReader;
#[doc = "Field `DMAC1` writer - 0 - no reset; 1 - reset"]
pub type Dmac1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MAILBOX1` reader - "]
pub type Mailbox1R = crate::BitReader;
#[doc = "Field `MAILBOX1` writer - "]
pub type Mailbox1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINMUX1` reader - "]
pub type Pinmux1R = crate::BitReader;
#[doc = "Field `PINMUX1` writer - "]
pub type Pinmux1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART1` reader - "]
pub type Usart1R = crate::BitReader;
#[doc = "Field `USART1` writer - "]
pub type Usart1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART2` reader - "]
pub type Usart2R = crate::BitReader;
#[doc = "Field `USART2` writer - "]
pub type Usart2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EZIP1` reader - "]
pub type Ezip1R = crate::BitReader;
#[doc = "Field `EZIP1` writer - "]
pub type Ezip1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPIC` reader - "]
pub type EpicR = crate::BitReader;
#[doc = "Field `EPIC` writer - "]
pub type EpicW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCDC1` reader - "]
pub type Lcdc1R = crate::BitReader;
#[doc = "Field `LCDC1` writer - "]
pub type Lcdc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2S1` reader - "]
pub type I2s1R = crate::BitReader;
#[doc = "Field `I2S1` writer - "]
pub type I2s1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSCFG1` reader - "]
pub type Syscfg1R = crate::BitReader;
#[doc = "Field `SYSCFG1` writer - "]
pub type Syscfg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EFUSEC` reader - "]
pub type EfusecR = crate::BitReader;
#[doc = "Field `EFUSEC` writer - "]
pub type EfusecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AES` reader - "]
pub type AesR = crate::BitReader;
#[doc = "Field `AES` writer - "]
pub type AesW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CRC1` reader - "]
pub type Crc1R = crate::BitReader;
#[doc = "Field `CRC1` writer - "]
pub type Crc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRNG` reader - "]
pub type TrngR = crate::BitReader;
#[doc = "Field `TRNG` writer - "]
pub type TrngW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM1` reader - "]
pub type Gptim1R = crate::BitReader;
#[doc = "Field `GPTIM1` writer - "]
pub type Gptim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM2` reader - "]
pub type Gptim2R = crate::BitReader;
#[doc = "Field `GPTIM2` writer - "]
pub type Gptim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM1` reader - "]
pub type Btim1R = crate::BitReader;
#[doc = "Field `BTIM1` writer - "]
pub type Btim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM2` reader - "]
pub type Btim2R = crate::BitReader;
#[doc = "Field `BTIM2` writer - "]
pub type Btim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI1` reader - "]
pub type Spi1R = crate::BitReader;
#[doc = "Field `SPI1` writer - "]
pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI2` reader - "]
pub type Spi2R = crate::BitReader;
#[doc = "Field `SPI2` writer - "]
pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXTDMA` reader - "]
pub type ExtdmaR = crate::BitReader;
#[doc = "Field `EXTDMA` writer - "]
pub type ExtdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PDM1` reader - "]
pub type Pdm1R = crate::BitReader;
#[doc = "Field `PDM1` writer - "]
pub type Pdm1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C1` reader - "]
pub type I2c1R = crate::BitReader;
#[doc = "Field `I2C1` writer - "]
pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C2` reader - "]
pub type I2c2R = crate::BitReader;
#[doc = "Field `I2C2` writer - "]
pub type I2c2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PTC1` reader - "]
pub type Ptc1R = crate::BitReader;
#[doc = "Field `PTC1` writer - "]
pub type Ptc1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0 - no reset; 1 - reset"]
#[inline(always)]
pub fn dmac1(&self) -> Dmac1R {
Dmac1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mailbox1(&self) -> Mailbox1R {
Mailbox1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn pinmux1(&self) -> Pinmux1R {
Pinmux1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn usart1(&self) -> Usart1R {
Usart1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn usart2(&self) -> Usart2R {
Usart2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn ezip1(&self) -> Ezip1R {
Ezip1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn epic(&self) -> EpicR {
EpicR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn lcdc1(&self) -> Lcdc1R {
Lcdc1R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2s1(&self) -> I2s1R {
I2s1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn syscfg1(&self) -> Syscfg1R {
Syscfg1R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn efusec(&self) -> EfusecR {
EfusecR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn aes(&self) -> AesR {
AesR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn crc1(&self) -> Crc1R {
Crc1R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn trng(&self) -> TrngR {
TrngR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn gptim1(&self) -> Gptim1R {
Gptim1R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn gptim2(&self) -> Gptim2R {
Gptim2R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn btim1(&self) -> Btim1R {
Btim1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn btim2(&self) -> Btim2R {
Btim2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn spi1(&self) -> Spi1R {
Spi1R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn spi2(&self) -> Spi2R {
Spi2R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn extdma(&self) -> ExtdmaR {
ExtdmaR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn pdm1(&self) -> Pdm1R {
Pdm1R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn i2c1(&self) -> I2c1R {
I2c1R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn i2c2(&self) -> I2c2R {
I2c2R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn ptc1(&self) -> Ptc1R {
Ptc1R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0 - no reset; 1 - reset"]
#[inline(always)]
#[must_use]
pub fn dmac1(&mut self) -> Dmac1W<Rstr1Spec> {
Dmac1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mailbox1(&mut self) -> Mailbox1W<Rstr1Spec> {
Mailbox1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn pinmux1(&mut self) -> Pinmux1W<Rstr1Spec> {
Pinmux1W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn usart1(&mut self) -> Usart1W<Rstr1Spec> {
Usart1W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn usart2(&mut self) -> Usart2W<Rstr1Spec> {
Usart2W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn ezip1(&mut self) -> Ezip1W<Rstr1Spec> {
Ezip1W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn epic(&mut self) -> EpicW<Rstr1Spec> {
EpicW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn lcdc1(&mut self) -> Lcdc1W<Rstr1Spec> {
Lcdc1W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2s1(&mut self) -> I2s1W<Rstr1Spec> {
I2s1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Rstr1Spec> {
Rsvd7W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn syscfg1(&mut self) -> Syscfg1W<Rstr1Spec> {
Syscfg1W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn efusec(&mut self) -> EfusecW<Rstr1Spec> {
EfusecW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn aes(&mut self) -> AesW<Rstr1Spec> {
AesW::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn crc1(&mut self) -> Crc1W<Rstr1Spec> {
Crc1W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn trng(&mut self) -> TrngW<Rstr1Spec> {
TrngW::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn gptim1(&mut self) -> Gptim1W<Rstr1Spec> {
Gptim1W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn gptim2(&mut self) -> Gptim2W<Rstr1Spec> {
Gptim2W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn btim1(&mut self) -> Btim1W<Rstr1Spec> {
Btim1W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn btim2(&mut self) -> Btim2W<Rstr1Spec> {
Btim2W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Rstr1Spec> {
Rsvd6W::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn spi1(&mut self) -> Spi1W<Rstr1Spec> {
Spi1W::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn spi2(&mut self) -> Spi2W<Rstr1Spec> {
Spi2W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn extdma(&mut self) -> ExtdmaW<Rstr1Spec> {
ExtdmaW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Rstr1Spec> {
Rsvd5W::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Rstr1Spec> {
Rsvd4W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn pdm1(&mut self) -> Pdm1W<Rstr1Spec> {
Pdm1W::new(self, 25)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Rstr1Spec> {
Rsvd3W::new(self, 26)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn i2c1(&mut self) -> I2c1W<Rstr1Spec> {
I2c1W::new(self, 27)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn i2c2(&mut self) -> I2c2W<Rstr1Spec> {
I2c2W::new(self, 28)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Rstr1Spec> {
Rsvd2W::new(self, 29)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Rstr1Spec> {
RsvdW::new(self, 30)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn ptc1(&mut self) -> Ptc1W<Rstr1Spec> {
Ptc1W::new(self, 31)
}
}
#[doc = "Reset Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rstr1Spec;
impl crate::RegisterSpec for Rstr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rstr1::R`](R) reader structure"]
impl crate::Readable for Rstr1Spec {}
#[doc = "`write(|w| ..)` method takes [`rstr1::W`](W) writer structure"]
impl crate::Writable for Rstr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSTR1 to value 0"]
impl crate::Resettable for Rstr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSTR2 (rw) register accessor: Reset Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstr2`]
module"]
#[doc(alias = "RSTR2")]
pub type Rstr2 = crate::Reg<rstr2::Rstr2Spec>;
#[doc = "Reset Register 2"]
pub mod rstr2 {
#[doc = "Register `RSTR2` reader"]
pub type R = crate::R<Rstr2Spec>;
#[doc = "Register `RSTR2` writer"]
pub type W = crate::W<Rstr2Spec>;
#[doc = "Field `GPIO1` reader - 0 - no reset; 1 - reset"]
pub type Gpio1R = crate::BitReader;
#[doc = "Field `GPIO1` writer - 0 - no reset; 1 - reset"]
pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI1` reader - "]
pub type Mpi1R = crate::BitReader;
#[doc = "Field `MPI1` writer - "]
pub type Mpi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI2` reader - "]
pub type Mpi2R = crate::BitReader;
#[doc = "Field `MPI2` writer - "]
pub type Mpi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD14` reader - "]
pub type Rsvd14R = crate::BitReader;
#[doc = "Field `RSVD14` writer - "]
pub type Rsvd14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SDMMC1` reader - "]
pub type Sdmmc1R = crate::BitReader;
#[doc = "Field `SDMMC1` writer - "]
pub type Sdmmc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD13` reader - "]
pub type Rsvd13R = crate::BitReader;
#[doc = "Field `RSVD13` writer - "]
pub type Rsvd13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USBC` reader - "]
pub type UsbcR = crate::BitReader;
#[doc = "Field `USBC` writer - "]
pub type UsbcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD12` reader - "]
pub type Rsvd12R = crate::BitReader;
#[doc = "Field `RSVD12` writer - "]
pub type Rsvd12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C3` reader - "]
pub type I2c3R = crate::BitReader;
#[doc = "Field `I2C3` writer - "]
pub type I2c3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ATIM1` reader - "]
pub type Atim1R = crate::BitReader;
#[doc = "Field `ATIM1` writer - "]
pub type Atim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD11` reader - "]
pub type Rsvd11R = crate::BitReader;
#[doc = "Field `RSVD11` writer - "]
pub type Rsvd11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD10` reader - "]
pub type Rsvd10R = crate::BitReader;
#[doc = "Field `RSVD10` writer - "]
pub type Rsvd10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART3` reader - "]
pub type Usart3R = crate::BitReader;
#[doc = "Field `USART3` writer - "]
pub type Usart3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD9` reader - "]
pub type Rsvd9R = crate::BitReader;
#[doc = "Field `RSVD9` writer - "]
pub type Rsvd9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD8` reader - "]
pub type Rsvd8R = crate::BitReader;
#[doc = "Field `RSVD8` writer - "]
pub type Rsvd8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDCODEC` reader - "]
pub type AudcodecR = crate::BitReader;
#[doc = "Field `AUDCODEC` writer - "]
pub type AudcodecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDPRC` reader - "]
pub type AudprcR = crate::BitReader;
#[doc = "Field `AUDPRC` writer - "]
pub type AudprcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPADC` reader - "]
pub type GpadcR = crate::BitReader;
#[doc = "Field `GPADC` writer - "]
pub type GpadcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSEN` reader - "]
pub type TsenR = crate::BitReader;
#[doc = "Field `TSEN` writer - "]
pub type TsenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C4` reader - "]
pub type I2c4R = crate::BitReader;
#[doc = "Field `I2C4` writer - "]
pub type I2c4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bit 0 - 0 - no reset; 1 - reset"]
#[inline(always)]
pub fn gpio1(&self) -> Gpio1R {
Gpio1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mpi1(&self) -> Mpi1R {
Mpi1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn mpi2(&self) -> Mpi2R {
Mpi2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd14(&self) -> Rsvd14R {
Rsvd14R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn sdmmc1(&self) -> Sdmmc1R {
Sdmmc1R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd13(&self) -> Rsvd13R {
Rsvd13R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn usbc(&self) -> UsbcR {
UsbcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd12(&self) -> Rsvd12R {
Rsvd12R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2c3(&self) -> I2c3R {
I2c3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn atim1(&self) -> Atim1R {
Atim1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd11(&self) -> Rsvd11R {
Rsvd11R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd10(&self) -> Rsvd10R {
Rsvd10R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn usart3(&self) -> Usart3R {
Usart3R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn rsvd9(&self) -> Rsvd9R {
Rsvd9R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn rsvd8(&self) -> Rsvd8R {
Rsvd8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn audcodec(&self) -> AudcodecR {
AudcodecR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn audprc(&self) -> AudprcR {
AudprcR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn gpadc(&self) -> GpadcR {
GpadcR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn tsen(&self) -> TsenR {
TsenR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn i2c4(&self) -> I2c4R {
I2c4R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bits 26:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 26) & 0x3f) as u8)
}
}
impl W {
#[doc = "Bit 0 - 0 - no reset; 1 - reset"]
#[inline(always)]
#[must_use]
pub fn gpio1(&mut self) -> Gpio1W<Rstr2Spec> {
Gpio1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mpi1(&mut self) -> Mpi1W<Rstr2Spec> {
Mpi1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn mpi2(&mut self) -> Mpi2W<Rstr2Spec> {
Mpi2W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd14(&mut self) -> Rsvd14W<Rstr2Spec> {
Rsvd14W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn sdmmc1(&mut self) -> Sdmmc1W<Rstr2Spec> {
Sdmmc1W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd13(&mut self) -> Rsvd13W<Rstr2Spec> {
Rsvd13W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn usbc(&mut self) -> UsbcW<Rstr2Spec> {
UsbcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd12(&mut self) -> Rsvd12W<Rstr2Spec> {
Rsvd12W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2c3(&mut self) -> I2c3W<Rstr2Spec> {
I2c3W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn atim1(&mut self) -> Atim1W<Rstr2Spec> {
Atim1W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd11(&mut self) -> Rsvd11W<Rstr2Spec> {
Rsvd11W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd10(&mut self) -> Rsvd10W<Rstr2Spec> {
Rsvd10W::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn usart3(&mut self) -> Usart3W<Rstr2Spec> {
Usart3W::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn rsvd9(&mut self) -> Rsvd9W<Rstr2Spec> {
Rsvd9W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn rsvd8(&mut self) -> Rsvd8W<Rstr2Spec> {
Rsvd8W::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Rstr2Spec> {
Rsvd7W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Rstr2Spec> {
Rsvd6W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Rstr2Spec> {
Rsvd5W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Rstr2Spec> {
Rsvd4W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn audcodec(&mut self) -> AudcodecW<Rstr2Spec> {
AudcodecW::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn audprc(&mut self) -> AudprcW<Rstr2Spec> {
AudprcW::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Rstr2Spec> {
Rsvd3W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn gpadc(&mut self) -> GpadcW<Rstr2Spec> {
GpadcW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn tsen(&mut self) -> TsenW<Rstr2Spec> {
TsenW::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Rstr2Spec> {
Rsvd2W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn i2c4(&mut self) -> I2c4W<Rstr2Spec> {
I2c4W::new(self, 25)
}
#[doc = "Bits 26:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Rstr2Spec> {
RsvdW::new(self, 26)
}
}
#[doc = "Reset Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rstr2Spec;
impl crate::RegisterSpec for Rstr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rstr2::R`](R) reader structure"]
impl crate::Readable for Rstr2Spec {}
#[doc = "`write(|w| ..)` method takes [`rstr2::W`](W) writer structure"]
impl crate::Writable for Rstr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSTR2 to value 0"]
impl crate::Resettable for Rstr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ENR1 (rw) register accessor: Enable Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enr1`]
module"]
#[doc(alias = "ENR1")]
pub type Enr1 = crate::Reg<enr1::Enr1Spec>;
#[doc = "Enable Register 1"]
pub mod enr1 {
#[doc = "Register `ENR1` reader"]
pub type R = crate::R<Enr1Spec>;
#[doc = "Register `ENR1` writer"]
pub type W = crate::W<Enr1Spec>;
#[doc = "Field `DMAC1` reader - write 1 to set module enable, write 0 to disable module"]
pub type Dmac1R = crate::BitReader;
#[doc = "Field `DMAC1` writer - write 1 to set module enable, write 0 to disable module"]
pub type Dmac1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MAILBOX1` reader - "]
pub type Mailbox1R = crate::BitReader;
#[doc = "Field `MAILBOX1` writer - "]
pub type Mailbox1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINMUX1` reader - "]
pub type Pinmux1R = crate::BitReader;
#[doc = "Field `PINMUX1` writer - "]
pub type Pinmux1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART2` reader - "]
pub type Usart2R = crate::BitReader;
#[doc = "Field `USART2` writer - "]
pub type Usart2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EZIP1` reader - "]
pub type Ezip1R = crate::BitReader;
#[doc = "Field `EZIP1` writer - "]
pub type Ezip1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPIC` reader - "]
pub type EpicR = crate::BitReader;
#[doc = "Field `EPIC` writer - "]
pub type EpicW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCDC1` reader - "]
pub type Lcdc1R = crate::BitReader;
#[doc = "Field `LCDC1` writer - "]
pub type Lcdc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2S1` reader - "]
pub type I2s1R = crate::BitReader;
#[doc = "Field `I2S1` writer - "]
pub type I2s1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSCFG1` reader - "]
pub type Syscfg1R = crate::BitReader;
#[doc = "Field `SYSCFG1` writer - "]
pub type Syscfg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EFUSEC` reader - "]
pub type EfusecR = crate::BitReader;
#[doc = "Field `EFUSEC` writer - "]
pub type EfusecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AES` reader - "]
pub type AesR = crate::BitReader;
#[doc = "Field `AES` writer - "]
pub type AesW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CRC1` reader - "]
pub type Crc1R = crate::BitReader;
#[doc = "Field `CRC1` writer - "]
pub type Crc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRNG` reader - "]
pub type TrngR = crate::BitReader;
#[doc = "Field `TRNG` writer - "]
pub type TrngW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM1` reader - "]
pub type Gptim1R = crate::BitReader;
#[doc = "Field `GPTIM1` writer - "]
pub type Gptim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM2` reader - "]
pub type Gptim2R = crate::BitReader;
#[doc = "Field `GPTIM2` writer - "]
pub type Gptim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM1` reader - "]
pub type Btim1R = crate::BitReader;
#[doc = "Field `BTIM1` writer - "]
pub type Btim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM2` reader - "]
pub type Btim2R = crate::BitReader;
#[doc = "Field `BTIM2` writer - "]
pub type Btim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI1` reader - "]
pub type Spi1R = crate::BitReader;
#[doc = "Field `SPI1` writer - "]
pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI2` reader - "]
pub type Spi2R = crate::BitReader;
#[doc = "Field `SPI2` writer - "]
pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXTDMA` reader - "]
pub type ExtdmaR = crate::BitReader;
#[doc = "Field `EXTDMA` writer - "]
pub type ExtdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECU1` reader - "]
pub type Secu1R = crate::BitReader;
#[doc = "Field `SECU1` writer - "]
pub type Secu1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PDM1` reader - "]
pub type Pdm1R = crate::BitReader;
#[doc = "Field `PDM1` writer - "]
pub type Pdm1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C1` reader - "]
pub type I2c1R = crate::BitReader;
#[doc = "Field `I2C1` writer - "]
pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C2` reader - "]
pub type I2c2R = crate::BitReader;
#[doc = "Field `I2C2` writer - "]
pub type I2c2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PTC1` reader - "]
pub type Ptc1R = crate::BitReader;
#[doc = "Field `PTC1` writer - "]
pub type Ptc1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - write 1 to set module enable, write 0 to disable module"]
#[inline(always)]
pub fn dmac1(&self) -> Dmac1R {
Dmac1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mailbox1(&self) -> Mailbox1R {
Mailbox1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn pinmux1(&self) -> Pinmux1R {
Pinmux1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn usart2(&self) -> Usart2R {
Usart2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn ezip1(&self) -> Ezip1R {
Ezip1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn epic(&self) -> EpicR {
EpicR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn lcdc1(&self) -> Lcdc1R {
Lcdc1R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2s1(&self) -> I2s1R {
I2s1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn syscfg1(&self) -> Syscfg1R {
Syscfg1R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn efusec(&self) -> EfusecR {
EfusecR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn aes(&self) -> AesR {
AesR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn crc1(&self) -> Crc1R {
Crc1R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn trng(&self) -> TrngR {
TrngR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn gptim1(&self) -> Gptim1R {
Gptim1R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn gptim2(&self) -> Gptim2R {
Gptim2R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn btim1(&self) -> Btim1R {
Btim1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn btim2(&self) -> Btim2R {
Btim2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn spi1(&self) -> Spi1R {
Spi1R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn spi2(&self) -> Spi2R {
Spi2R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn extdma(&self) -> ExtdmaR {
ExtdmaR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn secu1(&self) -> Secu1R {
Secu1R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn pdm1(&self) -> Pdm1R {
Pdm1R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn i2c1(&self) -> I2c1R {
I2c1R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn i2c2(&self) -> I2c2R {
I2c2R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn ptc1(&self) -> Ptc1R {
Ptc1R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - write 1 to set module enable, write 0 to disable module"]
#[inline(always)]
#[must_use]
pub fn dmac1(&mut self) -> Dmac1W<Enr1Spec> {
Dmac1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mailbox1(&mut self) -> Mailbox1W<Enr1Spec> {
Mailbox1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn pinmux1(&mut self) -> Pinmux1W<Enr1Spec> {
Pinmux1W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Enr1Spec> {
Rsvd7W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn usart2(&mut self) -> Usart2W<Enr1Spec> {
Usart2W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn ezip1(&mut self) -> Ezip1W<Enr1Spec> {
Ezip1W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn epic(&mut self) -> EpicW<Enr1Spec> {
EpicW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn lcdc1(&mut self) -> Lcdc1W<Enr1Spec> {
Lcdc1W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2s1(&mut self) -> I2s1W<Enr1Spec> {
I2s1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Enr1Spec> {
Rsvd6W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn syscfg1(&mut self) -> Syscfg1W<Enr1Spec> {
Syscfg1W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn efusec(&mut self) -> EfusecW<Enr1Spec> {
EfusecW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn aes(&mut self) -> AesW<Enr1Spec> {
AesW::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn crc1(&mut self) -> Crc1W<Enr1Spec> {
Crc1W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn trng(&mut self) -> TrngW<Enr1Spec> {
TrngW::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn gptim1(&mut self) -> Gptim1W<Enr1Spec> {
Gptim1W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn gptim2(&mut self) -> Gptim2W<Enr1Spec> {
Gptim2W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn btim1(&mut self) -> Btim1W<Enr1Spec> {
Btim1W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn btim2(&mut self) -> Btim2W<Enr1Spec> {
Btim2W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Enr1Spec> {
Rsvd5W::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn spi1(&mut self) -> Spi1W<Enr1Spec> {
Spi1W::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn spi2(&mut self) -> Spi2W<Enr1Spec> {
Spi2W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn extdma(&mut self) -> ExtdmaW<Enr1Spec> {
ExtdmaW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn secu1(&mut self) -> Secu1W<Enr1Spec> {
Secu1W::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Enr1Spec> {
Rsvd4W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn pdm1(&mut self) -> Pdm1W<Enr1Spec> {
Pdm1W::new(self, 25)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Enr1Spec> {
Rsvd3W::new(self, 26)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn i2c1(&mut self) -> I2c1W<Enr1Spec> {
I2c1W::new(self, 27)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn i2c2(&mut self) -> I2c2W<Enr1Spec> {
I2c2W::new(self, 28)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Enr1Spec> {
Rsvd2W::new(self, 29)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Enr1Spec> {
RsvdW::new(self, 30)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn ptc1(&mut self) -> Ptc1W<Enr1Spec> {
Ptc1W::new(self, 31)
}
}
#[doc = "Enable Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Enr1Spec;
impl crate::RegisterSpec for Enr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`enr1::R`](R) reader structure"]
impl crate::Readable for Enr1Spec {}
#[doc = "`write(|w| ..)` method takes [`enr1::W`](W) writer structure"]
impl crate::Writable for Enr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ENR1 to value 0"]
impl crate::Resettable for Enr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ENR2 (rw) register accessor: Enable Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enr2`]
module"]
#[doc(alias = "ENR2")]
pub type Enr2 = crate::Reg<enr2::Enr2Spec>;
#[doc = "Enable Register 2"]
pub mod enr2 {
#[doc = "Register `ENR2` reader"]
pub type R = crate::R<Enr2Spec>;
#[doc = "Register `ENR2` writer"]
pub type W = crate::W<Enr2Spec>;
#[doc = "Field `GPIO1` reader - write 1 to set module enable, write 0 to disable module"]
pub type Gpio1R = crate::BitReader;
#[doc = "Field `GPIO1` writer - write 1 to set module enable, write 0 to disable module"]
pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI1` reader - "]
pub type Mpi1R = crate::BitReader;
#[doc = "Field `MPI1` writer - "]
pub type Mpi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI2` reader - "]
pub type Mpi2R = crate::BitReader;
#[doc = "Field `MPI2` writer - "]
pub type Mpi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD14` reader - "]
pub type Rsvd14R = crate::BitReader;
#[doc = "Field `RSVD14` writer - "]
pub type Rsvd14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SDMMC1` reader - "]
pub type Sdmmc1R = crate::BitReader;
#[doc = "Field `SDMMC1` writer - "]
pub type Sdmmc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD13` reader - "]
pub type Rsvd13R = crate::BitReader;
#[doc = "Field `RSVD13` writer - "]
pub type Rsvd13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USBC` reader - "]
pub type UsbcR = crate::BitReader;
#[doc = "Field `USBC` writer - "]
pub type UsbcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD12` reader - "]
pub type Rsvd12R = crate::BitReader;
#[doc = "Field `RSVD12` writer - "]
pub type Rsvd12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C3` reader - "]
pub type I2c3R = crate::BitReader;
#[doc = "Field `I2C3` writer - "]
pub type I2c3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ATIM1` reader - "]
pub type Atim1R = crate::BitReader;
#[doc = "Field `ATIM1` writer - "]
pub type Atim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD11` reader - "]
pub type Rsvd11R = crate::BitReader;
#[doc = "Field `RSVD11` writer - "]
pub type Rsvd11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD10` reader - "]
pub type Rsvd10R = crate::BitReader;
#[doc = "Field `RSVD10` writer - "]
pub type Rsvd10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART3` reader - "]
pub type Usart3R = crate::BitReader;
#[doc = "Field `USART3` writer - "]
pub type Usart3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD9` reader - "]
pub type Rsvd9R = crate::BitReader;
#[doc = "Field `RSVD9` writer - "]
pub type Rsvd9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD8` reader - "]
pub type Rsvd8R = crate::BitReader;
#[doc = "Field `RSVD8` writer - "]
pub type Rsvd8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDCODEC` reader - "]
pub type AudcodecR = crate::BitReader;
#[doc = "Field `AUDCODEC` writer - "]
pub type AudcodecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDPRC` reader - "]
pub type AudprcR = crate::BitReader;
#[doc = "Field `AUDPRC` writer - "]
pub type AudprcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPADC` reader - "]
pub type GpadcR = crate::BitReader;
#[doc = "Field `GPADC` writer - "]
pub type GpadcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSEN` reader - "]
pub type TsenR = crate::BitReader;
#[doc = "Field `TSEN` writer - "]
pub type TsenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C4` reader - "]
pub type I2c4R = crate::BitReader;
#[doc = "Field `I2C4` writer - "]
pub type I2c4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bit 0 - write 1 to set module enable, write 0 to disable module"]
#[inline(always)]
pub fn gpio1(&self) -> Gpio1R {
Gpio1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mpi1(&self) -> Mpi1R {
Mpi1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn mpi2(&self) -> Mpi2R {
Mpi2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd14(&self) -> Rsvd14R {
Rsvd14R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn sdmmc1(&self) -> Sdmmc1R {
Sdmmc1R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd13(&self) -> Rsvd13R {
Rsvd13R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn usbc(&self) -> UsbcR {
UsbcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd12(&self) -> Rsvd12R {
Rsvd12R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2c3(&self) -> I2c3R {
I2c3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn atim1(&self) -> Atim1R {
Atim1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd11(&self) -> Rsvd11R {
Rsvd11R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd10(&self) -> Rsvd10R {
Rsvd10R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn usart3(&self) -> Usart3R {
Usart3R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn rsvd9(&self) -> Rsvd9R {
Rsvd9R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn rsvd8(&self) -> Rsvd8R {
Rsvd8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn audcodec(&self) -> AudcodecR {
AudcodecR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn audprc(&self) -> AudprcR {
AudprcR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn gpadc(&self) -> GpadcR {
GpadcR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn tsen(&self) -> TsenR {
TsenR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn i2c4(&self) -> I2c4R {
I2c4R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bits 26:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 26) & 0x3f) as u8)
}
}
impl W {
#[doc = "Bit 0 - write 1 to set module enable, write 0 to disable module"]
#[inline(always)]
#[must_use]
pub fn gpio1(&mut self) -> Gpio1W<Enr2Spec> {
Gpio1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mpi1(&mut self) -> Mpi1W<Enr2Spec> {
Mpi1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn mpi2(&mut self) -> Mpi2W<Enr2Spec> {
Mpi2W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd14(&mut self) -> Rsvd14W<Enr2Spec> {
Rsvd14W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn sdmmc1(&mut self) -> Sdmmc1W<Enr2Spec> {
Sdmmc1W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd13(&mut self) -> Rsvd13W<Enr2Spec> {
Rsvd13W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn usbc(&mut self) -> UsbcW<Enr2Spec> {
UsbcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd12(&mut self) -> Rsvd12W<Enr2Spec> {
Rsvd12W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2c3(&mut self) -> I2c3W<Enr2Spec> {
I2c3W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn atim1(&mut self) -> Atim1W<Enr2Spec> {
Atim1W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd11(&mut self) -> Rsvd11W<Enr2Spec> {
Rsvd11W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd10(&mut self) -> Rsvd10W<Enr2Spec> {
Rsvd10W::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn usart3(&mut self) -> Usart3W<Enr2Spec> {
Usart3W::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn rsvd9(&mut self) -> Rsvd9W<Enr2Spec> {
Rsvd9W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn rsvd8(&mut self) -> Rsvd8W<Enr2Spec> {
Rsvd8W::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Enr2Spec> {
Rsvd7W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Enr2Spec> {
Rsvd6W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Enr2Spec> {
Rsvd5W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Enr2Spec> {
Rsvd4W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn audcodec(&mut self) -> AudcodecW<Enr2Spec> {
AudcodecW::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn audprc(&mut self) -> AudprcW<Enr2Spec> {
AudprcW::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Enr2Spec> {
Rsvd3W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn gpadc(&mut self) -> GpadcW<Enr2Spec> {
GpadcW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn tsen(&mut self) -> TsenW<Enr2Spec> {
TsenW::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Enr2Spec> {
Rsvd2W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn i2c4(&mut self) -> I2c4W<Enr2Spec> {
I2c4W::new(self, 25)
}
#[doc = "Bits 26:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Enr2Spec> {
RsvdW::new(self, 26)
}
}
#[doc = "Enable Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Enr2Spec;
impl crate::RegisterSpec for Enr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`enr2::R`](R) reader structure"]
impl crate::Readable for Enr2Spec {}
#[doc = "`write(|w| ..)` method takes [`enr2::W`](W) writer structure"]
impl crate::Writable for Enr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ENR2 to value 0"]
impl crate::Resettable for Enr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ESR1 (rw) register accessor: Enable Set Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr1`]
module"]
#[doc(alias = "ESR1")]
pub type Esr1 = crate::Reg<esr1::Esr1Spec>;
#[doc = "Enable Set Register 1"]
pub mod esr1 {
#[doc = "Register `ESR1` reader"]
pub type R = crate::R<Esr1Spec>;
#[doc = "Register `ESR1` writer"]
pub type W = crate::W<Esr1Spec>;
#[doc = "Field `DMAC1` reader - write 1 to set module enable, write 0 has no effect"]
pub type Dmac1R = crate::BitReader;
#[doc = "Field `DMAC1` writer - write 1 to set module enable, write 0 has no effect"]
pub type Dmac1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MAILBOX1` reader - "]
pub type Mailbox1R = crate::BitReader;
#[doc = "Field `MAILBOX1` writer - "]
pub type Mailbox1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINMUX1` reader - "]
pub type Pinmux1R = crate::BitReader;
#[doc = "Field `PINMUX1` writer - "]
pub type Pinmux1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART2` reader - "]
pub type Usart2R = crate::BitReader;
#[doc = "Field `USART2` writer - "]
pub type Usart2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EZIP1` reader - "]
pub type Ezip1R = crate::BitReader;
#[doc = "Field `EZIP1` writer - "]
pub type Ezip1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPIC` reader - "]
pub type EpicR = crate::BitReader;
#[doc = "Field `EPIC` writer - "]
pub type EpicW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCDC1` reader - "]
pub type Lcdc1R = crate::BitReader;
#[doc = "Field `LCDC1` writer - "]
pub type Lcdc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2S1` reader - "]
pub type I2s1R = crate::BitReader;
#[doc = "Field `I2S1` writer - "]
pub type I2s1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSCFG1` reader - "]
pub type Syscfg1R = crate::BitReader;
#[doc = "Field `SYSCFG1` writer - "]
pub type Syscfg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EFUSEC` reader - "]
pub type EfusecR = crate::BitReader;
#[doc = "Field `EFUSEC` writer - "]
pub type EfusecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AES` reader - "]
pub type AesR = crate::BitReader;
#[doc = "Field `AES` writer - "]
pub type AesW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CRC1` reader - "]
pub type Crc1R = crate::BitReader;
#[doc = "Field `CRC1` writer - "]
pub type Crc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRNG` reader - "]
pub type TrngR = crate::BitReader;
#[doc = "Field `TRNG` writer - "]
pub type TrngW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM1` reader - "]
pub type Gptim1R = crate::BitReader;
#[doc = "Field `GPTIM1` writer - "]
pub type Gptim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM2` reader - "]
pub type Gptim2R = crate::BitReader;
#[doc = "Field `GPTIM2` writer - "]
pub type Gptim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM1` reader - "]
pub type Btim1R = crate::BitReader;
#[doc = "Field `BTIM1` writer - "]
pub type Btim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM2` reader - "]
pub type Btim2R = crate::BitReader;
#[doc = "Field `BTIM2` writer - "]
pub type Btim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI1` reader - "]
pub type Spi1R = crate::BitReader;
#[doc = "Field `SPI1` writer - "]
pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI2` reader - "]
pub type Spi2R = crate::BitReader;
#[doc = "Field `SPI2` writer - "]
pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXTDMA` reader - "]
pub type ExtdmaR = crate::BitReader;
#[doc = "Field `EXTDMA` writer - "]
pub type ExtdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECU1` reader - "]
pub type Secu1R = crate::BitReader;
#[doc = "Field `SECU1` writer - "]
pub type Secu1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PDM1` reader - "]
pub type Pdm1R = crate::BitReader;
#[doc = "Field `PDM1` writer - "]
pub type Pdm1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C1` reader - "]
pub type I2c1R = crate::BitReader;
#[doc = "Field `I2C1` writer - "]
pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C2` reader - "]
pub type I2c2R = crate::BitReader;
#[doc = "Field `I2C2` writer - "]
pub type I2c2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PTC1` reader - "]
pub type Ptc1R = crate::BitReader;
#[doc = "Field `PTC1` writer - "]
pub type Ptc1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - write 1 to set module enable, write 0 has no effect"]
#[inline(always)]
pub fn dmac1(&self) -> Dmac1R {
Dmac1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mailbox1(&self) -> Mailbox1R {
Mailbox1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn pinmux1(&self) -> Pinmux1R {
Pinmux1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn usart2(&self) -> Usart2R {
Usart2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn ezip1(&self) -> Ezip1R {
Ezip1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn epic(&self) -> EpicR {
EpicR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn lcdc1(&self) -> Lcdc1R {
Lcdc1R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2s1(&self) -> I2s1R {
I2s1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn syscfg1(&self) -> Syscfg1R {
Syscfg1R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn efusec(&self) -> EfusecR {
EfusecR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn aes(&self) -> AesR {
AesR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn crc1(&self) -> Crc1R {
Crc1R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn trng(&self) -> TrngR {
TrngR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn gptim1(&self) -> Gptim1R {
Gptim1R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn gptim2(&self) -> Gptim2R {
Gptim2R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn btim1(&self) -> Btim1R {
Btim1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn btim2(&self) -> Btim2R {
Btim2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn spi1(&self) -> Spi1R {
Spi1R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn spi2(&self) -> Spi2R {
Spi2R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn extdma(&self) -> ExtdmaR {
ExtdmaR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn secu1(&self) -> Secu1R {
Secu1R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn pdm1(&self) -> Pdm1R {
Pdm1R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn i2c1(&self) -> I2c1R {
I2c1R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn i2c2(&self) -> I2c2R {
I2c2R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn ptc1(&self) -> Ptc1R {
Ptc1R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - write 1 to set module enable, write 0 has no effect"]
#[inline(always)]
#[must_use]
pub fn dmac1(&mut self) -> Dmac1W<Esr1Spec> {
Dmac1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mailbox1(&mut self) -> Mailbox1W<Esr1Spec> {
Mailbox1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn pinmux1(&mut self) -> Pinmux1W<Esr1Spec> {
Pinmux1W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Esr1Spec> {
Rsvd7W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn usart2(&mut self) -> Usart2W<Esr1Spec> {
Usart2W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn ezip1(&mut self) -> Ezip1W<Esr1Spec> {
Ezip1W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn epic(&mut self) -> EpicW<Esr1Spec> {
EpicW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn lcdc1(&mut self) -> Lcdc1W<Esr1Spec> {
Lcdc1W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2s1(&mut self) -> I2s1W<Esr1Spec> {
I2s1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Esr1Spec> {
Rsvd6W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn syscfg1(&mut self) -> Syscfg1W<Esr1Spec> {
Syscfg1W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn efusec(&mut self) -> EfusecW<Esr1Spec> {
EfusecW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn aes(&mut self) -> AesW<Esr1Spec> {
AesW::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn crc1(&mut self) -> Crc1W<Esr1Spec> {
Crc1W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn trng(&mut self) -> TrngW<Esr1Spec> {
TrngW::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn gptim1(&mut self) -> Gptim1W<Esr1Spec> {
Gptim1W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn gptim2(&mut self) -> Gptim2W<Esr1Spec> {
Gptim2W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn btim1(&mut self) -> Btim1W<Esr1Spec> {
Btim1W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn btim2(&mut self) -> Btim2W<Esr1Spec> {
Btim2W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Esr1Spec> {
Rsvd5W::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn spi1(&mut self) -> Spi1W<Esr1Spec> {
Spi1W::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn spi2(&mut self) -> Spi2W<Esr1Spec> {
Spi2W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn extdma(&mut self) -> ExtdmaW<Esr1Spec> {
ExtdmaW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn secu1(&mut self) -> Secu1W<Esr1Spec> {
Secu1W::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Esr1Spec> {
Rsvd4W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn pdm1(&mut self) -> Pdm1W<Esr1Spec> {
Pdm1W::new(self, 25)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Esr1Spec> {
Rsvd3W::new(self, 26)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn i2c1(&mut self) -> I2c1W<Esr1Spec> {
I2c1W::new(self, 27)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn i2c2(&mut self) -> I2c2W<Esr1Spec> {
I2c2W::new(self, 28)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Esr1Spec> {
Rsvd2W::new(self, 29)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Esr1Spec> {
RsvdW::new(self, 30)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn ptc1(&mut self) -> Ptc1W<Esr1Spec> {
Ptc1W::new(self, 31)
}
}
#[doc = "Enable Set Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esr1Spec;
impl crate::RegisterSpec for Esr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`esr1::R`](R) reader structure"]
impl crate::Readable for Esr1Spec {}
#[doc = "`write(|w| ..)` method takes [`esr1::W`](W) writer structure"]
impl crate::Writable for Esr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ESR1 to value 0"]
impl crate::Resettable for Esr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ESR2 (rw) register accessor: Enable Set Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esr2`]
module"]
#[doc(alias = "ESR2")]
pub type Esr2 = crate::Reg<esr2::Esr2Spec>;
#[doc = "Enable Set Register 2"]
pub mod esr2 {
#[doc = "Register `ESR2` reader"]
pub type R = crate::R<Esr2Spec>;
#[doc = "Register `ESR2` writer"]
pub type W = crate::W<Esr2Spec>;
#[doc = "Field `GPIO1` reader - write 1 to set module enable, write 0 has no effect"]
pub type Gpio1R = crate::BitReader;
#[doc = "Field `GPIO1` writer - write 1 to set module enable, write 0 has no effect"]
pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI1` reader - "]
pub type Mpi1R = crate::BitReader;
#[doc = "Field `MPI1` writer - "]
pub type Mpi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI2` reader - "]
pub type Mpi2R = crate::BitReader;
#[doc = "Field `MPI2` writer - "]
pub type Mpi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD14` reader - "]
pub type Rsvd14R = crate::BitReader;
#[doc = "Field `RSVD14` writer - "]
pub type Rsvd14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SDMMC1` reader - "]
pub type Sdmmc1R = crate::BitReader;
#[doc = "Field `SDMMC1` writer - "]
pub type Sdmmc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD13` reader - "]
pub type Rsvd13R = crate::BitReader;
#[doc = "Field `RSVD13` writer - "]
pub type Rsvd13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USBC` reader - "]
pub type UsbcR = crate::BitReader;
#[doc = "Field `USBC` writer - "]
pub type UsbcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD12` reader - "]
pub type Rsvd12R = crate::BitReader;
#[doc = "Field `RSVD12` writer - "]
pub type Rsvd12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C3` reader - "]
pub type I2c3R = crate::BitReader;
#[doc = "Field `I2C3` writer - "]
pub type I2c3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ATIM1` reader - "]
pub type Atim1R = crate::BitReader;
#[doc = "Field `ATIM1` writer - "]
pub type Atim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD11` reader - "]
pub type Rsvd11R = crate::BitReader;
#[doc = "Field `RSVD11` writer - "]
pub type Rsvd11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD10` reader - "]
pub type Rsvd10R = crate::BitReader;
#[doc = "Field `RSVD10` writer - "]
pub type Rsvd10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART3` reader - "]
pub type Usart3R = crate::BitReader;
#[doc = "Field `USART3` writer - "]
pub type Usart3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD9` reader - "]
pub type Rsvd9R = crate::BitReader;
#[doc = "Field `RSVD9` writer - "]
pub type Rsvd9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD8` reader - "]
pub type Rsvd8R = crate::BitReader;
#[doc = "Field `RSVD8` writer - "]
pub type Rsvd8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDCODEC` reader - "]
pub type AudcodecR = crate::BitReader;
#[doc = "Field `AUDCODEC` writer - "]
pub type AudcodecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDPRC` reader - "]
pub type AudprcR = crate::BitReader;
#[doc = "Field `AUDPRC` writer - "]
pub type AudprcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPADC` reader - "]
pub type GpadcR = crate::BitReader;
#[doc = "Field `GPADC` writer - "]
pub type GpadcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSEN` reader - "]
pub type TsenR = crate::BitReader;
#[doc = "Field `TSEN` writer - "]
pub type TsenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C4` reader - "]
pub type I2c4R = crate::BitReader;
#[doc = "Field `I2C4` writer - "]
pub type I2c4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bit 0 - write 1 to set module enable, write 0 has no effect"]
#[inline(always)]
pub fn gpio1(&self) -> Gpio1R {
Gpio1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mpi1(&self) -> Mpi1R {
Mpi1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn mpi2(&self) -> Mpi2R {
Mpi2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd14(&self) -> Rsvd14R {
Rsvd14R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn sdmmc1(&self) -> Sdmmc1R {
Sdmmc1R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd13(&self) -> Rsvd13R {
Rsvd13R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn usbc(&self) -> UsbcR {
UsbcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd12(&self) -> Rsvd12R {
Rsvd12R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2c3(&self) -> I2c3R {
I2c3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn atim1(&self) -> Atim1R {
Atim1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd11(&self) -> Rsvd11R {
Rsvd11R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd10(&self) -> Rsvd10R {
Rsvd10R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn usart3(&self) -> Usart3R {
Usart3R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn rsvd9(&self) -> Rsvd9R {
Rsvd9R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn rsvd8(&self) -> Rsvd8R {
Rsvd8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn audcodec(&self) -> AudcodecR {
AudcodecR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn audprc(&self) -> AudprcR {
AudprcR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn gpadc(&self) -> GpadcR {
GpadcR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn tsen(&self) -> TsenR {
TsenR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn i2c4(&self) -> I2c4R {
I2c4R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bits 26:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 26) & 0x3f) as u8)
}
}
impl W {
#[doc = "Bit 0 - write 1 to set module enable, write 0 has no effect"]
#[inline(always)]
#[must_use]
pub fn gpio1(&mut self) -> Gpio1W<Esr2Spec> {
Gpio1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mpi1(&mut self) -> Mpi1W<Esr2Spec> {
Mpi1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn mpi2(&mut self) -> Mpi2W<Esr2Spec> {
Mpi2W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd14(&mut self) -> Rsvd14W<Esr2Spec> {
Rsvd14W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn sdmmc1(&mut self) -> Sdmmc1W<Esr2Spec> {
Sdmmc1W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd13(&mut self) -> Rsvd13W<Esr2Spec> {
Rsvd13W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn usbc(&mut self) -> UsbcW<Esr2Spec> {
UsbcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd12(&mut self) -> Rsvd12W<Esr2Spec> {
Rsvd12W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2c3(&mut self) -> I2c3W<Esr2Spec> {
I2c3W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn atim1(&mut self) -> Atim1W<Esr2Spec> {
Atim1W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd11(&mut self) -> Rsvd11W<Esr2Spec> {
Rsvd11W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd10(&mut self) -> Rsvd10W<Esr2Spec> {
Rsvd10W::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn usart3(&mut self) -> Usart3W<Esr2Spec> {
Usart3W::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn rsvd9(&mut self) -> Rsvd9W<Esr2Spec> {
Rsvd9W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn rsvd8(&mut self) -> Rsvd8W<Esr2Spec> {
Rsvd8W::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Esr2Spec> {
Rsvd7W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Esr2Spec> {
Rsvd6W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Esr2Spec> {
Rsvd5W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Esr2Spec> {
Rsvd4W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn audcodec(&mut self) -> AudcodecW<Esr2Spec> {
AudcodecW::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn audprc(&mut self) -> AudprcW<Esr2Spec> {
AudprcW::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Esr2Spec> {
Rsvd3W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn gpadc(&mut self) -> GpadcW<Esr2Spec> {
GpadcW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn tsen(&mut self) -> TsenW<Esr2Spec> {
TsenW::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Esr2Spec> {
Rsvd2W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn i2c4(&mut self) -> I2c4W<Esr2Spec> {
I2c4W::new(self, 25)
}
#[doc = "Bits 26:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Esr2Spec> {
RsvdW::new(self, 26)
}
}
#[doc = "Enable Set Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Esr2Spec;
impl crate::RegisterSpec for Esr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`esr2::R`](R) reader structure"]
impl crate::Readable for Esr2Spec {}
#[doc = "`write(|w| ..)` method takes [`esr2::W`](W) writer structure"]
impl crate::Writable for Esr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ESR2 to value 0"]
impl crate::Resettable for Esr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ECR1 (rw) register accessor: Enable Clear Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr1`]
module"]
#[doc(alias = "ECR1")]
pub type Ecr1 = crate::Reg<ecr1::Ecr1Spec>;
#[doc = "Enable Clear Register 1"]
pub mod ecr1 {
#[doc = "Register `ECR1` reader"]
pub type R = crate::R<Ecr1Spec>;
#[doc = "Register `ECR1` writer"]
pub type W = crate::W<Ecr1Spec>;
#[doc = "Field `DMAC1` reader - write 1 to clear module enable, write 0 has no effect"]
pub type Dmac1R = crate::BitReader;
#[doc = "Field `DMAC1` writer - write 1 to clear module enable, write 0 has no effect"]
pub type Dmac1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MAILBOX1` reader - "]
pub type Mailbox1R = crate::BitReader;
#[doc = "Field `MAILBOX1` writer - "]
pub type Mailbox1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINMUX1` reader - "]
pub type Pinmux1R = crate::BitReader;
#[doc = "Field `PINMUX1` writer - "]
pub type Pinmux1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART2` reader - "]
pub type Usart2R = crate::BitReader;
#[doc = "Field `USART2` writer - "]
pub type Usart2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EZIP1` reader - "]
pub type Ezip1R = crate::BitReader;
#[doc = "Field `EZIP1` writer - "]
pub type Ezip1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPIC` reader - "]
pub type EpicR = crate::BitReader;
#[doc = "Field `EPIC` writer - "]
pub type EpicW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCDC1` reader - "]
pub type Lcdc1R = crate::BitReader;
#[doc = "Field `LCDC1` writer - "]
pub type Lcdc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2S1` reader - "]
pub type I2s1R = crate::BitReader;
#[doc = "Field `I2S1` writer - "]
pub type I2s1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSCFG1` reader - "]
pub type Syscfg1R = crate::BitReader;
#[doc = "Field `SYSCFG1` writer - "]
pub type Syscfg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EFUSEC` reader - "]
pub type EfusecR = crate::BitReader;
#[doc = "Field `EFUSEC` writer - "]
pub type EfusecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AES` reader - "]
pub type AesR = crate::BitReader;
#[doc = "Field `AES` writer - "]
pub type AesW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CRC1` reader - "]
pub type Crc1R = crate::BitReader;
#[doc = "Field `CRC1` writer - "]
pub type Crc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRNG` reader - "]
pub type TrngR = crate::BitReader;
#[doc = "Field `TRNG` writer - "]
pub type TrngW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM1` reader - "]
pub type Gptim1R = crate::BitReader;
#[doc = "Field `GPTIM1` writer - "]
pub type Gptim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIM2` reader - "]
pub type Gptim2R = crate::BitReader;
#[doc = "Field `GPTIM2` writer - "]
pub type Gptim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM1` reader - "]
pub type Btim1R = crate::BitReader;
#[doc = "Field `BTIM1` writer - "]
pub type Btim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BTIM2` reader - "]
pub type Btim2R = crate::BitReader;
#[doc = "Field `BTIM2` writer - "]
pub type Btim2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI1` reader - "]
pub type Spi1R = crate::BitReader;
#[doc = "Field `SPI1` writer - "]
pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI2` reader - "]
pub type Spi2R = crate::BitReader;
#[doc = "Field `SPI2` writer - "]
pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXTDMA` reader - "]
pub type ExtdmaR = crate::BitReader;
#[doc = "Field `EXTDMA` writer - "]
pub type ExtdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECU1` reader - "]
pub type Secu1R = crate::BitReader;
#[doc = "Field `SECU1` writer - "]
pub type Secu1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PDM1` reader - "]
pub type Pdm1R = crate::BitReader;
#[doc = "Field `PDM1` writer - "]
pub type Pdm1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C1` reader - "]
pub type I2c1R = crate::BitReader;
#[doc = "Field `I2C1` writer - "]
pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C2` reader - "]
pub type I2c2R = crate::BitReader;
#[doc = "Field `I2C2` writer - "]
pub type I2c2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PTC1` reader - "]
pub type Ptc1R = crate::BitReader;
#[doc = "Field `PTC1` writer - "]
pub type Ptc1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - write 1 to clear module enable, write 0 has no effect"]
#[inline(always)]
pub fn dmac1(&self) -> Dmac1R {
Dmac1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mailbox1(&self) -> Mailbox1R {
Mailbox1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn pinmux1(&self) -> Pinmux1R {
Pinmux1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn usart2(&self) -> Usart2R {
Usart2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn ezip1(&self) -> Ezip1R {
Ezip1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn epic(&self) -> EpicR {
EpicR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn lcdc1(&self) -> Lcdc1R {
Lcdc1R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2s1(&self) -> I2s1R {
I2s1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn syscfg1(&self) -> Syscfg1R {
Syscfg1R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn efusec(&self) -> EfusecR {
EfusecR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn aes(&self) -> AesR {
AesR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn crc1(&self) -> Crc1R {
Crc1R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn trng(&self) -> TrngR {
TrngR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn gptim1(&self) -> Gptim1R {
Gptim1R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn gptim2(&self) -> Gptim2R {
Gptim2R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn btim1(&self) -> Btim1R {
Btim1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn btim2(&self) -> Btim2R {
Btim2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn spi1(&self) -> Spi1R {
Spi1R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn spi2(&self) -> Spi2R {
Spi2R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn extdma(&self) -> ExtdmaR {
ExtdmaR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn secu1(&self) -> Secu1R {
Secu1R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn pdm1(&self) -> Pdm1R {
Pdm1R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn i2c1(&self) -> I2c1R {
I2c1R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn i2c2(&self) -> I2c2R {
I2c2R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn ptc1(&self) -> Ptc1R {
Ptc1R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - write 1 to clear module enable, write 0 has no effect"]
#[inline(always)]
#[must_use]
pub fn dmac1(&mut self) -> Dmac1W<Ecr1Spec> {
Dmac1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mailbox1(&mut self) -> Mailbox1W<Ecr1Spec> {
Mailbox1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn pinmux1(&mut self) -> Pinmux1W<Ecr1Spec> {
Pinmux1W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Ecr1Spec> {
Rsvd7W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn usart2(&mut self) -> Usart2W<Ecr1Spec> {
Usart2W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn ezip1(&mut self) -> Ezip1W<Ecr1Spec> {
Ezip1W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn epic(&mut self) -> EpicW<Ecr1Spec> {
EpicW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn lcdc1(&mut self) -> Lcdc1W<Ecr1Spec> {
Lcdc1W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2s1(&mut self) -> I2s1W<Ecr1Spec> {
I2s1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Ecr1Spec> {
Rsvd6W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn syscfg1(&mut self) -> Syscfg1W<Ecr1Spec> {
Syscfg1W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn efusec(&mut self) -> EfusecW<Ecr1Spec> {
EfusecW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn aes(&mut self) -> AesW<Ecr1Spec> {
AesW::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn crc1(&mut self) -> Crc1W<Ecr1Spec> {
Crc1W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn trng(&mut self) -> TrngW<Ecr1Spec> {
TrngW::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn gptim1(&mut self) -> Gptim1W<Ecr1Spec> {
Gptim1W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn gptim2(&mut self) -> Gptim2W<Ecr1Spec> {
Gptim2W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn btim1(&mut self) -> Btim1W<Ecr1Spec> {
Btim1W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn btim2(&mut self) -> Btim2W<Ecr1Spec> {
Btim2W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Ecr1Spec> {
Rsvd5W::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn spi1(&mut self) -> Spi1W<Ecr1Spec> {
Spi1W::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn spi2(&mut self) -> Spi2W<Ecr1Spec> {
Spi2W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn extdma(&mut self) -> ExtdmaW<Ecr1Spec> {
ExtdmaW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn secu1(&mut self) -> Secu1W<Ecr1Spec> {
Secu1W::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Ecr1Spec> {
Rsvd4W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn pdm1(&mut self) -> Pdm1W<Ecr1Spec> {
Pdm1W::new(self, 25)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Ecr1Spec> {
Rsvd3W::new(self, 26)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn i2c1(&mut self) -> I2c1W<Ecr1Spec> {
I2c1W::new(self, 27)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn i2c2(&mut self) -> I2c2W<Ecr1Spec> {
I2c2W::new(self, 28)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Ecr1Spec> {
Rsvd2W::new(self, 29)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ecr1Spec> {
RsvdW::new(self, 30)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn ptc1(&mut self) -> Ptc1W<Ecr1Spec> {
Ptc1W::new(self, 31)
}
}
#[doc = "Enable Clear Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ecr1Spec;
impl crate::RegisterSpec for Ecr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ecr1::R`](R) reader structure"]
impl crate::Readable for Ecr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ecr1::W`](W) writer structure"]
impl crate::Writable for Ecr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ECR1 to value 0"]
impl crate::Resettable for Ecr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ECR2 (rw) register accessor: Enable Clear Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr2`]
module"]
#[doc(alias = "ECR2")]
pub type Ecr2 = crate::Reg<ecr2::Ecr2Spec>;
#[doc = "Enable Clear Register 2"]
pub mod ecr2 {
#[doc = "Register `ECR2` reader"]
pub type R = crate::R<Ecr2Spec>;
#[doc = "Register `ECR2` writer"]
pub type W = crate::W<Ecr2Spec>;
#[doc = "Field `GPIO1` reader - write 1 to clear module enable, write 0 has no effect"]
pub type Gpio1R = crate::BitReader;
#[doc = "Field `GPIO1` writer - write 1 to clear module enable, write 0 has no effect"]
pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI1` reader - "]
pub type Mpi1R = crate::BitReader;
#[doc = "Field `MPI1` writer - "]
pub type Mpi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPI2` reader - "]
pub type Mpi2R = crate::BitReader;
#[doc = "Field `MPI2` writer - "]
pub type Mpi2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD14` reader - "]
pub type Rsvd14R = crate::BitReader;
#[doc = "Field `RSVD14` writer - "]
pub type Rsvd14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SDMMC1` reader - "]
pub type Sdmmc1R = crate::BitReader;
#[doc = "Field `SDMMC1` writer - "]
pub type Sdmmc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD13` reader - "]
pub type Rsvd13R = crate::BitReader;
#[doc = "Field `RSVD13` writer - "]
pub type Rsvd13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USBC` reader - "]
pub type UsbcR = crate::BitReader;
#[doc = "Field `USBC` writer - "]
pub type UsbcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD12` reader - "]
pub type Rsvd12R = crate::BitReader;
#[doc = "Field `RSVD12` writer - "]
pub type Rsvd12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C3` reader - "]
pub type I2c3R = crate::BitReader;
#[doc = "Field `I2C3` writer - "]
pub type I2c3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ATIM1` reader - "]
pub type Atim1R = crate::BitReader;
#[doc = "Field `ATIM1` writer - "]
pub type Atim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD11` reader - "]
pub type Rsvd11R = crate::BitReader;
#[doc = "Field `RSVD11` writer - "]
pub type Rsvd11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD10` reader - "]
pub type Rsvd10R = crate::BitReader;
#[doc = "Field `RSVD10` writer - "]
pub type Rsvd10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USART3` reader - "]
pub type Usart3R = crate::BitReader;
#[doc = "Field `USART3` writer - "]
pub type Usart3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD9` reader - "]
pub type Rsvd9R = crate::BitReader;
#[doc = "Field `RSVD9` writer - "]
pub type Rsvd9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD8` reader - "]
pub type Rsvd8R = crate::BitReader;
#[doc = "Field `RSVD8` writer - "]
pub type Rsvd8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD7` reader - "]
pub type Rsvd7R = crate::BitReader;
#[doc = "Field `RSVD7` writer - "]
pub type Rsvd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD6` reader - "]
pub type Rsvd6R = crate::BitReader;
#[doc = "Field `RSVD6` writer - "]
pub type Rsvd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::BitReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDCODEC` reader - "]
pub type AudcodecR = crate::BitReader;
#[doc = "Field `AUDCODEC` writer - "]
pub type AudcodecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUDPRC` reader - "]
pub type AudprcR = crate::BitReader;
#[doc = "Field `AUDPRC` writer - "]
pub type AudprcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPADC` reader - "]
pub type GpadcR = crate::BitReader;
#[doc = "Field `GPADC` writer - "]
pub type GpadcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSEN` reader - "]
pub type TsenR = crate::BitReader;
#[doc = "Field `TSEN` writer - "]
pub type TsenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C4` reader - "]
pub type I2c4R = crate::BitReader;
#[doc = "Field `I2C4` writer - "]
pub type I2c4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bit 0 - write 1 to clear module enable, write 0 has no effect"]
#[inline(always)]
pub fn gpio1(&self) -> Gpio1R {
Gpio1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mpi1(&self) -> Mpi1R {
Mpi1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn mpi2(&self) -> Mpi2R {
Mpi2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd14(&self) -> Rsvd14R {
Rsvd14R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn sdmmc1(&self) -> Sdmmc1R {
Sdmmc1R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd13(&self) -> Rsvd13R {
Rsvd13R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn usbc(&self) -> UsbcR {
UsbcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd12(&self) -> Rsvd12R {
Rsvd12R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn i2c3(&self) -> I2c3R {
I2c3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn atim1(&self) -> Atim1R {
Atim1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd11(&self) -> Rsvd11R {
Rsvd11R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd10(&self) -> Rsvd10R {
Rsvd10R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn usart3(&self) -> Usart3R {
Usart3R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn rsvd9(&self) -> Rsvd9R {
Rsvd9R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn rsvd8(&self) -> Rsvd8R {
Rsvd8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd7(&self) -> Rsvd7R {
Rsvd7R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rsvd6(&self) -> Rsvd6R {
Rsvd6R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn audcodec(&self) -> AudcodecR {
AudcodecR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn audprc(&self) -> AudprcR {
AudprcR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn gpadc(&self) -> GpadcR {
GpadcR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn tsen(&self) -> TsenR {
TsenR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn i2c4(&self) -> I2c4R {
I2c4R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bits 26:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 26) & 0x3f) as u8)
}
}
impl W {
#[doc = "Bit 0 - write 1 to clear module enable, write 0 has no effect"]
#[inline(always)]
#[must_use]
pub fn gpio1(&mut self) -> Gpio1W<Ecr2Spec> {
Gpio1W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mpi1(&mut self) -> Mpi1W<Ecr2Spec> {
Mpi1W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn mpi2(&mut self) -> Mpi2W<Ecr2Spec> {
Mpi2W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd14(&mut self) -> Rsvd14W<Ecr2Spec> {
Rsvd14W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn sdmmc1(&mut self) -> Sdmmc1W<Ecr2Spec> {
Sdmmc1W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd13(&mut self) -> Rsvd13W<Ecr2Spec> {
Rsvd13W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn usbc(&mut self) -> UsbcW<Ecr2Spec> {
UsbcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd12(&mut self) -> Rsvd12W<Ecr2Spec> {
Rsvd12W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn i2c3(&mut self) -> I2c3W<Ecr2Spec> {
I2c3W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn atim1(&mut self) -> Atim1W<Ecr2Spec> {
Atim1W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd11(&mut self) -> Rsvd11W<Ecr2Spec> {
Rsvd11W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd10(&mut self) -> Rsvd10W<Ecr2Spec> {
Rsvd10W::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn usart3(&mut self) -> Usart3W<Ecr2Spec> {
Usart3W::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn rsvd9(&mut self) -> Rsvd9W<Ecr2Spec> {
Rsvd9W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn rsvd8(&mut self) -> Rsvd8W<Ecr2Spec> {
Rsvd8W::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd7(&mut self) -> Rsvd7W<Ecr2Spec> {
Rsvd7W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rsvd6(&mut self) -> Rsvd6W<Ecr2Spec> {
Rsvd6W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<Ecr2Spec> {
Rsvd5W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Ecr2Spec> {
Rsvd4W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn audcodec(&mut self) -> AudcodecW<Ecr2Spec> {
AudcodecW::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn audprc(&mut self) -> AudprcW<Ecr2Spec> {
AudprcW::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Ecr2Spec> {
Rsvd3W::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn gpadc(&mut self) -> GpadcW<Ecr2Spec> {
GpadcW::new(self, 22)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn tsen(&mut self) -> TsenW<Ecr2Spec> {
TsenW::new(self, 23)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Ecr2Spec> {
Rsvd2W::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn i2c4(&mut self) -> I2c4W<Ecr2Spec> {
I2c4W::new(self, 25)
}
#[doc = "Bits 26:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ecr2Spec> {
RsvdW::new(self, 26)
}
}
#[doc = "Enable Clear Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ecr2Spec;
impl crate::RegisterSpec for Ecr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ecr2::R`](R) reader structure"]
impl crate::Readable for Ecr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ecr2::W`](W) writer structure"]
impl crate::Writable for Ecr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ECR2 to value 0"]
impl crate::Resettable for Ecr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CSR (rw) register accessor: Clock Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csr`]
module"]
#[doc(alias = "CSR")]
pub type Csr = crate::Reg<csr::CsrSpec>;
#[doc = "Clock Select Register"]
pub mod csr {
#[doc = "Register `CSR` reader"]
pub type R = crate::R<CsrSpec>;
#[doc = "Register `CSR` writer"]
pub type W = crate::W<CsrSpec>;
#[doc = "Field `SEL_SYS` reader - select clock source for clk_sys. 0 - hrc48; 1 - hxt48; 2 - dbl96; 3 - dll1"]
pub type SelSysR = crate::FieldReader;
#[doc = "Field `SEL_SYS` writer - select clock source for clk_sys. 0 - hrc48; 1 - hxt48; 2 - dbl96; 3 - dll1"]
pub type SelSysW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL_SYS_LP` reader - if set to 1, clk_sys will switch to clk_wdt"]
pub type SelSysLpR = crate::BitReader;
#[doc = "Field `SEL_SYS_LP` writer - if set to 1, clk_sys will switch to clk_wdt"]
pub type SelSysLpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEL_MPI1` reader - select clock source for MPI1. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
pub type SelMpi1R = crate::FieldReader;
#[doc = "Field `SEL_MPI1` writer - select clock source for MPI1. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
pub type SelMpi1W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL_MPI2` reader - select clock source for MPI2. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
pub type SelMpi2R = crate::FieldReader;
#[doc = "Field `SEL_MPI2` writer - select clock source for MPI2. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
pub type SelMpi2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL_PERI` reader - select clock source for clk_peri. 0 - hrc48; 1 - hxt48. clk_peri is the clock source of USART/SPI/I2C/GPTIM2/BTIM2"]
pub type SelPeriR = crate::BitReader;
#[doc = "Field `SEL_PERI` writer - select clock source for clk_peri. 0 - hrc48; 1 - hxt48. clk_peri is the clock source of USART/SPI/I2C/GPTIM2/BTIM2"]
pub type SelPeriW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEL_TICK` reader - select clock source for systick reference. 0 - clk_rtc; 1 - RSVD; 2 - hrc48; 3 - hxt48"]
pub type SelTickR = crate::FieldReader;
#[doc = "Field `SEL_TICK` writer - select clock source for systick reference. 0 - clk_rtc; 1 - RSVD; 2 - hrc48; 3 - hxt48"]
pub type SelTickW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL_USBC` reader - select clock source for USBC. 0 - clk_sys; 1 - dll2"]
pub type SelUsbcR = crate::BitReader;
#[doc = "Field `SEL_USBC` writer - select clock source for USBC. 0 - clk_sys; 1 - dll2"]
pub type SelUsbcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:1 - select clock source for clk_sys. 0 - hrc48; 1 - hxt48; 2 - dbl96; 3 - dll1"]
#[inline(always)]
pub fn sel_sys(&self) -> SelSysR {
SelSysR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - if set to 1, clk_sys will switch to clk_wdt"]
#[inline(always)]
pub fn sel_sys_lp(&self) -> SelSysLpR {
SelSysLpR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - select clock source for MPI1. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
#[inline(always)]
pub fn sel_mpi1(&self) -> SelMpi1R {
SelMpi1R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - select clock source for MPI2. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
#[inline(always)]
pub fn sel_mpi2(&self) -> SelMpi2R {
SelMpi2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 12 - select clock source for clk_peri. 0 - hrc48; 1 - hxt48. clk_peri is the clock source of USART/SPI/I2C/GPTIM2/BTIM2"]
#[inline(always)]
pub fn sel_peri(&self) -> SelPeriR {
SelPeriR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:14 - select clock source for systick reference. 0 - clk_rtc; 1 - RSVD; 2 - hrc48; 3 - hxt48"]
#[inline(always)]
pub fn sel_tick(&self) -> SelTickR {
SelTickR::new(((self.bits >> 13) & 3) as u8)
}
#[doc = "Bit 15 - select clock source for USBC. 0 - clk_sys; 1 - dll2"]
#[inline(always)]
pub fn sel_usbc(&self) -> SelUsbcR {
SelUsbcR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:1 - select clock source for clk_sys. 0 - hrc48; 1 - hxt48; 2 - dbl96; 3 - dll1"]
#[inline(always)]
#[must_use]
pub fn sel_sys(&mut self) -> SelSysW<CsrSpec> {
SelSysW::new(self, 0)
}
#[doc = "Bit 2 - if set to 1, clk_sys will switch to clk_wdt"]
#[inline(always)]
#[must_use]
pub fn sel_sys_lp(&mut self) -> SelSysLpW<CsrSpec> {
SelSysLpW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CsrSpec> {
Rsvd4W::new(self, 3)
}
#[doc = "Bits 4:5 - select clock source for MPI1. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
#[inline(always)]
#[must_use]
pub fn sel_mpi1(&mut self) -> SelMpi1W<CsrSpec> {
SelMpi1W::new(self, 4)
}
#[doc = "Bits 6:7 - select clock source for MPI2. 0 - clk_peri; 1 - dll1; 2 - dll2; 3 - dbl96"]
#[inline(always)]
#[must_use]
pub fn sel_mpi2(&mut self) -> SelMpi2W<CsrSpec> {
SelMpi2W::new(self, 6)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CsrSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CsrSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bit 12 - select clock source for clk_peri. 0 - hrc48; 1 - hxt48. clk_peri is the clock source of USART/SPI/I2C/GPTIM2/BTIM2"]
#[inline(always)]
#[must_use]
pub fn sel_peri(&mut self) -> SelPeriW<CsrSpec> {
SelPeriW::new(self, 12)
}
#[doc = "Bits 13:14 - select clock source for systick reference. 0 - clk_rtc; 1 - RSVD; 2 - hrc48; 3 - hxt48"]
#[inline(always)]
#[must_use]
pub fn sel_tick(&mut self) -> SelTickW<CsrSpec> {
SelTickW::new(self, 13)
}
#[doc = "Bit 15 - select clock source for USBC. 0 - clk_sys; 1 - dll2"]
#[inline(always)]
#[must_use]
pub fn sel_usbc(&mut self) -> SelUsbcW<CsrSpec> {
SelUsbcW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CsrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Clock Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CsrSpec;
impl crate::RegisterSpec for CsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`csr::R`](R) reader structure"]
impl crate::Readable for CsrSpec {}
#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"]
impl crate::Writable for CsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CSR to value 0"]
impl crate::Resettable for CsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CFGR (rw) register accessor: Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr`]
module"]
#[doc(alias = "CFGR")]
pub type Cfgr = crate::Reg<cfgr::CfgrSpec>;
#[doc = "Clock Configuration Register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub type R = crate::R<CfgrSpec>;
#[doc = "Register `CFGR` writer"]
pub type W = crate::W<CfgrSpec>;
#[doc = "Field `HDIV` reader - HCLK = CLK_SYS / HDIV"]
pub type HdivR = crate::FieldReader;
#[doc = "Field `HDIV` writer - HCLK = CLK_SYS / HDIV"]
pub type HdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `PDIV1` reader - PCLK1 = HCLK2 / (2^PDIV1), by default divided by 2"]
pub type Pdiv1R = crate::FieldReader;
#[doc = "Field `PDIV1` writer - PCLK1 = HCLK2 / (2^PDIV1), by default divided by 2"]
pub type Pdiv1W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PDIV2` reader - PCLK2 = HCLK2 / (2^PDIV2), by default divided by 16"]
pub type Pdiv2R = crate::FieldReader;
#[doc = "Field `PDIV2` writer - PCLK2 = HCLK2 / (2^PDIV2), by default divided by 16"]
pub type Pdiv2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TICKDIV` reader - systick reference is divided by TICKDIV"]
pub type TickdivR = crate::FieldReader;
#[doc = "Field `TICKDIV` writer - systick reference is divided by TICKDIV"]
pub type TickdivW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:7 - HCLK = CLK_SYS / HDIV"]
#[inline(always)]
pub fn hdiv(&self) -> HdivR {
HdivR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:10 - PCLK1 = HCLK2 / (2^PDIV1), by default divided by 2"]
#[inline(always)]
pub fn pdiv1(&self) -> Pdiv1R {
Pdiv1R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - PCLK2 = HCLK2 / (2^PDIV2), by default divided by 16"]
#[inline(always)]
pub fn pdiv2(&self) -> Pdiv2R {
Pdiv2R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:21 - systick reference is divided by TICKDIV"]
#[inline(always)]
pub fn tickdiv(&self) -> TickdivR {
TickdivR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:7 - HCLK = CLK_SYS / HDIV"]
#[inline(always)]
#[must_use]
pub fn hdiv(&mut self) -> HdivW<CfgrSpec> {
HdivW::new(self, 0)
}
#[doc = "Bits 8:10 - PCLK1 = HCLK2 / (2^PDIV1), by default divided by 2"]
#[inline(always)]
#[must_use]
pub fn pdiv1(&mut self) -> Pdiv1W<CfgrSpec> {
Pdiv1W::new(self, 8)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CfgrSpec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bits 12:14 - PCLK2 = HCLK2 / (2^PDIV2), by default divided by 16"]
#[inline(always)]
#[must_use]
pub fn pdiv2(&mut self) -> Pdiv2W<CfgrSpec> {
Pdiv2W::new(self, 12)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CfgrSpec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bits 16:21 - systick reference is divided by TICKDIV"]
#[inline(always)]
#[must_use]
pub fn tickdiv(&mut self) -> TickdivW<CfgrSpec> {
TickdivW::new(self, 16)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CfgrSpec> {
RsvdW::new(self, 22)
}
}
#[doc = "Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgrSpec;
impl crate::RegisterSpec for CfgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cfgr::R`](R) reader structure"]
impl crate::Readable for CfgrSpec {}
#[doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"]
impl crate::Writable for CfgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CFGR to value 0"]
impl crate::Resettable for CfgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "USBCR (rw) register accessor: USBC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbcr`]
module"]
#[doc(alias = "USBCR")]
pub type Usbcr = crate::Reg<usbcr::UsbcrSpec>;
#[doc = "USBC Control Register"]
pub mod usbcr {
#[doc = "Register `USBCR` reader"]
pub type R = crate::R<UsbcrSpec>;
#[doc = "Register `USBCR` writer"]
pub type W = crate::W<UsbcrSpec>;
#[doc = "Field `DIV` reader - USBC function clock is divided by DIV. USBC function clock should keep at 60MHz. For example, if USBC clock source is 240MHz dll2, DIV should be 4."]
pub type DivR = crate::FieldReader;
#[doc = "Field `DIV` writer - USBC function clock is divided by DIV. USBC function clock should keep at 60MHz. For example, if USBC clock source is 240MHz dll2, DIV should be 4."]
pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bits 0:2 - USBC function clock is divided by DIV. USBC function clock should keep at 60MHz. For example, if USBC clock source is 240MHz dll2, DIV should be 4."]
#[inline(always)]
pub fn div(&self) -> DivR {
DivR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bits 0:2 - USBC function clock is divided by DIV. USBC function clock should keep at 60MHz. For example, if USBC clock source is 240MHz dll2, DIV should be 4."]
#[inline(always)]
#[must_use]
pub fn div(&mut self) -> DivW<UsbcrSpec> {
DivW::new(self, 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<UsbcrSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "USBC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UsbcrSpec;
impl crate::RegisterSpec for UsbcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usbcr::R`](R) reader structure"]
impl crate::Readable for UsbcrSpec {}
#[doc = "`write(|w| ..)` method takes [`usbcr::W`](W) writer structure"]
impl crate::Writable for UsbcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets USBCR to value 0"]
impl crate::Resettable for UsbcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DLL1CR (rw) register accessor: DLL1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll1cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll1cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll1cr`]
module"]
#[doc(alias = "DLL1CR")]
pub type Dll1cr = crate::Reg<dll1cr::Dll1crSpec>;
#[doc = "DLL1 Control Register"]
pub mod dll1cr {
#[doc = "Register `DLL1CR` reader"]
pub type R = crate::R<Dll1crSpec>;
#[doc = "Register `DLL1CR` writer"]
pub type W = crate::W<Dll1crSpec>;
#[doc = "Field `EN` reader - 0: dll disabled 1: dll enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - 0: dll disabled 1: dll enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STG` reader - dll lock frequency is (STG+1)*24MHz"]
pub type StgR = crate::FieldReader;
#[doc = "Field `STG` writer - dll lock frequency is (STG+1)*24MHz"]
pub type StgW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `OUT_DIV2_EN` reader - 0: dll output not divided 1: dll output divided by 2"]
pub type OutDiv2EnR = crate::BitReader;
#[doc = "Field `OUT_DIV2_EN` writer - 0: dll output not divided 1: dll output divided by 2"]
pub type OutDiv2EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
#[doc = "Field `READY` reader - 0: dll not ready 1: dll ready"]
pub type ReadyR = crate::BitReader;
#[doc = "Field `READY` writer - 0: dll not ready 1: dll ready"]
pub type ReadyW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0: dll disabled 1: dll enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:5 - dll lock frequency is (STG+1)*24MHz"]
#[inline(always)]
pub fn stg(&self) -> StgR {
StgR::new(((self.bits >> 2) & 0x0f) as u8)
}
#[doc = "Bits 6:12"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 0x7f) as u8)
}
#[doc = "Bit 13 - 0: dll output not divided 1: dll output divided by 2"]
#[inline(always)]
pub fn out_div2_en(&self) -> OutDiv2EnR {
OutDiv2EnR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0001_ffff)
}
#[doc = "Bit 31 - 0: dll not ready 1: dll ready"]
#[inline(always)]
pub fn ready(&self) -> ReadyR {
ReadyR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0: dll disabled 1: dll enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Dll1crSpec> {
EnW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Dll1crSpec> {
Rsvd3W::new(self, 1)
}
#[doc = "Bits 2:5 - dll lock frequency is (STG+1)*24MHz"]
#[inline(always)]
#[must_use]
pub fn stg(&mut self) -> StgW<Dll1crSpec> {
StgW::new(self, 2)
}
#[doc = "Bits 6:12"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Dll1crSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bit 13 - 0: dll output not divided 1: dll output divided by 2"]
#[inline(always)]
#[must_use]
pub fn out_div2_en(&mut self) -> OutDiv2EnW<Dll1crSpec> {
OutDiv2EnW::new(self, 13)
}
#[doc = "Bits 14:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dll1crSpec> {
RsvdW::new(self, 14)
}
#[doc = "Bit 31 - 0: dll not ready 1: dll ready"]
#[inline(always)]
#[must_use]
pub fn ready(&mut self) -> ReadyW<Dll1crSpec> {
ReadyW::new(self, 31)
}
}
#[doc = "DLL1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll1cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll1cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dll1crSpec;
impl crate::RegisterSpec for Dll1crSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dll1cr::R`](R) reader structure"]
impl crate::Readable for Dll1crSpec {}
#[doc = "`write(|w| ..)` method takes [`dll1cr::W`](W) writer structure"]
impl crate::Writable for Dll1crSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DLL1CR to value 0"]
impl crate::Resettable for Dll1crSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DLL2CR (rw) register accessor: DLL2 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll2cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll2cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll2cr`]
module"]
#[doc(alias = "DLL2CR")]
pub type Dll2cr = crate::Reg<dll2cr::Dll2crSpec>;
#[doc = "DLL2 Control Register"]
pub mod dll2cr {
#[doc = "Register `DLL2CR` reader"]
pub type R = crate::R<Dll2crSpec>;
#[doc = "Register `DLL2CR` writer"]
pub type W = crate::W<Dll2crSpec>;
#[doc = "Field `EN` reader - 0: dll disabled 1: dll enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - 0: dll disabled 1: dll enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STG` reader - dll lock frequency is (STG+1)*24MHz"]
pub type StgR = crate::FieldReader;
#[doc = "Field `STG` writer - dll lock frequency is (STG+1)*24MHz"]
pub type StgW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `OUT_DIV2_EN` reader - 0: dll output not divided 1: dll output divided by 2"]
pub type OutDiv2EnR = crate::BitReader;
#[doc = "Field `OUT_DIV2_EN` writer - 0: dll output not divided 1: dll output divided by 2"]
pub type OutDiv2EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
#[doc = "Field `READY` reader - 0: dll not ready 1: dll ready"]
pub type ReadyR = crate::BitReader;
#[doc = "Field `READY` writer - 0: dll not ready 1: dll ready"]
pub type ReadyW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0: dll disabled 1: dll enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:5 - dll lock frequency is (STG+1)*24MHz"]
#[inline(always)]
pub fn stg(&self) -> StgR {
StgR::new(((self.bits >> 2) & 0x0f) as u8)
}
#[doc = "Bits 6:12"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 0x7f) as u8)
}
#[doc = "Bit 13 - 0: dll output not divided 1: dll output divided by 2"]
#[inline(always)]
pub fn out_div2_en(&self) -> OutDiv2EnR {
OutDiv2EnR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0001_ffff)
}
#[doc = "Bit 31 - 0: dll not ready 1: dll ready"]
#[inline(always)]
pub fn ready(&self) -> ReadyR {
ReadyR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0: dll disabled 1: dll enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Dll2crSpec> {
EnW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Dll2crSpec> {
Rsvd3W::new(self, 1)
}
#[doc = "Bits 2:5 - dll lock frequency is (STG+1)*24MHz"]
#[inline(always)]
#[must_use]
pub fn stg(&mut self) -> StgW<Dll2crSpec> {
StgW::new(self, 2)
}
#[doc = "Bits 6:12"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Dll2crSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bit 13 - 0: dll output not divided 1: dll output divided by 2"]
#[inline(always)]
#[must_use]
pub fn out_div2_en(&mut self) -> OutDiv2EnW<Dll2crSpec> {
OutDiv2EnW::new(self, 13)
}
#[doc = "Bits 14:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dll2crSpec> {
RsvdW::new(self, 14)
}
#[doc = "Bit 31 - 0: dll not ready 1: dll ready"]
#[inline(always)]
#[must_use]
pub fn ready(&mut self) -> ReadyW<Dll2crSpec> {
ReadyW::new(self, 31)
}
}
#[doc = "DLL2 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll2cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll2cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dll2crSpec;
impl crate::RegisterSpec for Dll2crSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dll2cr::R`](R) reader structure"]
impl crate::Readable for Dll2crSpec {}
#[doc = "`write(|w| ..)` method takes [`dll2cr::W`](W) writer structure"]
impl crate::Writable for Dll2crSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DLL2CR to value 0"]
impl crate::Resettable for Dll2crSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HRCCAL1 (rw) register accessor: HRC Calibration Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccal1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccal1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hrccal1`]
module"]
#[doc(alias = "HRCCAL1")]
pub type Hrccal1 = crate::Reg<hrccal1::Hrccal1Spec>;
#[doc = "HRC Calibration Register 1"]
pub mod hrccal1 {
#[doc = "Register `HRCCAL1` reader"]
pub type R = crate::R<Hrccal1Spec>;
#[doc = "Register `HRCCAL1` writer"]
pub type W = crate::W<Hrccal1Spec>;
#[doc = "Field `CAL_LENGTH` reader - "]
pub type CalLengthR = crate::FieldReader<u16>;
#[doc = "Field `CAL_LENGTH` writer - "]
pub type CalLengthW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `CAL_EN` reader - "]
pub type CalEnR = crate::BitReader;
#[doc = "Field `CAL_EN` writer - "]
pub type CalEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAL_DONE` reader - "]
pub type CalDoneR = crate::BitReader;
#[doc = "Field `CAL_DONE` writer - "]
pub type CalDoneW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cal_length(&self) -> CalLengthR {
CalLengthR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:29"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0x3fff) as u16)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn cal_en(&self) -> CalEnR {
CalEnR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn cal_done(&self) -> CalDoneR {
CalDoneR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cal_length(&mut self) -> CalLengthW<Hrccal1Spec> {
CalLengthW::new(self, 0)
}
#[doc = "Bits 16:29"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Hrccal1Spec> {
RsvdW::new(self, 16)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn cal_en(&mut self) -> CalEnW<Hrccal1Spec> {
CalEnW::new(self, 30)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn cal_done(&mut self) -> CalDoneW<Hrccal1Spec> {
CalDoneW::new(self, 31)
}
}
#[doc = "HRC Calibration Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccal1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccal1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hrccal1Spec;
impl crate::RegisterSpec for Hrccal1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hrccal1::R`](R) reader structure"]
impl crate::Readable for Hrccal1Spec {}
#[doc = "`write(|w| ..)` method takes [`hrccal1::W`](W) writer structure"]
impl crate::Writable for Hrccal1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HRCCAL1 to value 0"]
impl crate::Resettable for Hrccal1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HRCCAL2 (rw) register accessor: HRC Calibration Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccal2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccal2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hrccal2`]
module"]
#[doc(alias = "HRCCAL2")]
pub type Hrccal2 = crate::Reg<hrccal2::Hrccal2Spec>;
#[doc = "HRC Calibration Register 2"]
pub mod hrccal2 {
#[doc = "Register `HRCCAL2` reader"]
pub type R = crate::R<Hrccal2Spec>;
#[doc = "Register `HRCCAL2` writer"]
pub type W = crate::W<Hrccal2Spec>;
#[doc = "Field `HRC_CNT` reader - "]
pub type HrcCntR = crate::FieldReader<u16>;
#[doc = "Field `HRC_CNT` writer - "]
pub type HrcCntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `HXT_CNT` reader - "]
pub type HxtCntR = crate::FieldReader<u16>;
#[doc = "Field `HXT_CNT` writer - "]
pub type HxtCntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn hrc_cnt(&self) -> HrcCntR {
HrcCntR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn hxt_cnt(&self) -> HxtCntR {
HxtCntR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn hrc_cnt(&mut self) -> HrcCntW<Hrccal2Spec> {
HrcCntW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn hxt_cnt(&mut self) -> HxtCntW<Hrccal2Spec> {
HxtCntW::new(self, 16)
}
}
#[doc = "HRC Calibration Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccal2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccal2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Hrccal2Spec;
impl crate::RegisterSpec for Hrccal2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hrccal2::R`](R) reader structure"]
impl crate::Readable for Hrccal2Spec {}
#[doc = "`write(|w| ..)` method takes [`hrccal2::W`](W) writer structure"]
impl crate::Writable for Hrccal2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HRCCAL2 to value 0"]
impl crate::Resettable for Hrccal2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DWCFGR (rw) register accessor: Deep WFI mode Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dwcfgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dwcfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dwcfgr`]
module"]
#[doc(alias = "DWCFGR")]
pub type Dwcfgr = crate::Reg<dwcfgr::DwcfgrSpec>;
#[doc = "Deep WFI mode Clock Configuration Register"]
pub mod dwcfgr {
#[doc = "Register `DWCFGR` reader"]
pub type R = crate::R<DwcfgrSpec>;
#[doc = "Register `DWCFGR` writer"]
pub type W = crate::W<DwcfgrSpec>;
#[doc = "Field `HDIV` reader - HCLK = CLK_SYS / HDIV during deep wfi"]
pub type HdivR = crate::FieldReader;
#[doc = "Field `HDIV` writer - HCLK = CLK_SYS / HDIV during deep wfi"]
pub type HdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `PDIV1` reader - PCLK = HCLK / (2^PDIV1) during deep wfi"]
pub type Pdiv1R = crate::FieldReader;
#[doc = "Field `PDIV1` writer - PCLK = HCLK / (2^PDIV1) during deep wfi"]
pub type Pdiv1W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PDIV2` reader - PCLK2 = HCLK / (2^PDIV2) during deep wfi"]
pub type Pdiv2R = crate::FieldReader;
#[doc = "Field `PDIV2` writer - PCLK2 = HCLK / (2^PDIV2) during deep wfi"]
pub type Pdiv2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `DIV_EN` reader - enable PDIV1, PDIV2 and HDIV reconfiguration during deep wfi"]
pub type DivEnR = crate::BitReader;
#[doc = "Field `DIV_EN` writer - enable PDIV1, PDIV2 and HDIV reconfiguration during deep wfi"]
pub type DivEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEL_SYS` reader - 0 - HRC48; 1 - HXT48; 2 - RSVD; 3 - DLL1"]
pub type SelSysR = crate::FieldReader;
#[doc = "Field `SEL_SYS` writer - 0 - HRC48; 1 - HXT48; 2 - RSVD; 3 - DLL1"]
pub type SelSysW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL_SYS_LP` reader - 0 - SYSCLK; 1 - CLK_LP"]
pub type SelSysLpR = crate::BitReader;
#[doc = "Field `SEL_SYS_LP` writer - 0 - SYSCLK; 1 - CLK_LP"]
pub type SelSysLpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
impl R {
#[doc = "Bits 0:7 - HCLK = CLK_SYS / HDIV during deep wfi"]
#[inline(always)]
pub fn hdiv(&self) -> HdivR {
HdivR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:10 - PCLK = HCLK / (2^PDIV1) during deep wfi"]
#[inline(always)]
pub fn pdiv1(&self) -> Pdiv1R {
Pdiv1R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - PCLK2 = HCLK / (2^PDIV2) during deep wfi"]
#[inline(always)]
pub fn pdiv2(&self) -> Pdiv2R {
Pdiv2R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15 - enable PDIV1, PDIV2 and HDIV reconfiguration during deep wfi"]
#[inline(always)]
pub fn div_en(&self) -> DivEnR {
DivEnR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:17 - 0 - HRC48; 1 - HXT48; 2 - RSVD; 3 - DLL1"]
#[inline(always)]
pub fn sel_sys(&self) -> SelSysR {
SelSysR::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bit 18 - 0 - SYSCLK; 1 - CLK_LP"]
#[inline(always)]
pub fn sel_sys_lp(&self) -> SelSysLpR {
SelSysLpR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bits 19:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 19) & 0x1fff) as u16)
}
}
impl W {
#[doc = "Bits 0:7 - HCLK = CLK_SYS / HDIV during deep wfi"]
#[inline(always)]
#[must_use]
pub fn hdiv(&mut self) -> HdivW<DwcfgrSpec> {
HdivW::new(self, 0)
}
#[doc = "Bits 8:10 - PCLK = HCLK / (2^PDIV1) during deep wfi"]
#[inline(always)]
#[must_use]
pub fn pdiv1(&mut self) -> Pdiv1W<DwcfgrSpec> {
Pdiv1W::new(self, 8)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DwcfgrSpec> {
Rsvd2W::new(self, 11)
}
#[doc = "Bits 12:14 - PCLK2 = HCLK / (2^PDIV2) during deep wfi"]
#[inline(always)]
#[must_use]
pub fn pdiv2(&mut self) -> Pdiv2W<DwcfgrSpec> {
Pdiv2W::new(self, 12)
}
#[doc = "Bit 15 - enable PDIV1, PDIV2 and HDIV reconfiguration during deep wfi"]
#[inline(always)]
#[must_use]
pub fn div_en(&mut self) -> DivEnW<DwcfgrSpec> {
DivEnW::new(self, 15)
}
#[doc = "Bits 16:17 - 0 - HRC48; 1 - HXT48; 2 - RSVD; 3 - DLL1"]
#[inline(always)]
#[must_use]
pub fn sel_sys(&mut self) -> SelSysW<DwcfgrSpec> {
SelSysW::new(self, 16)
}
#[doc = "Bit 18 - 0 - SYSCLK; 1 - CLK_LP"]
#[inline(always)]
#[must_use]
pub fn sel_sys_lp(&mut self) -> SelSysLpW<DwcfgrSpec> {
SelSysLpW::new(self, 18)
}
#[doc = "Bits 19:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DwcfgrSpec> {
RsvdW::new(self, 19)
}
}
#[doc = "Deep WFI mode Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dwcfgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dwcfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DwcfgrSpec;
impl crate::RegisterSpec for DwcfgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dwcfgr::R`](R) reader structure"]
impl crate::Readable for DwcfgrSpec {}
#[doc = "`write(|w| ..)` method takes [`dwcfgr::W`](W) writer structure"]
impl crate::Writable for DwcfgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DWCFGR to value 0"]
impl crate::Resettable for DwcfgrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "ATIM1"]
pub struct Atim1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Atim1 {}
impl Atim1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const atim1::RegisterBlock = 0x5000_4000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const atim1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Atim1 {
type Target = atim1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Atim1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Atim1").finish()
}
}
#[doc = "ATIM1"]
pub mod atim1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
smcr: Smcr,
dier: Dier,
sr: Sr,
egr: Egr,
ccmr1: Ccmr1,
ccmr2: Ccmr2,
ccer: Ccer,
cnt: Cnt,
psc: Psc,
arr: Arr,
rcr: Rcr,
ccr1: Ccr1,
ccr2: Ccr2,
ccr3: Ccr3,
ccr4: Ccr4,
bdtr: Bdtr,
rsvd1: Rsvd1,
_reserved19: [u8; 0x08],
ccmr3: Ccmr3,
ccr5: Ccr5,
ccr6: Ccr6,
af1: Af1,
af2: Af2,
}
impl RegisterBlock {
#[doc = "0x00 - TIM control register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - TIM control register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - TIM slave mode control register"]
#[inline(always)]
pub const fn smcr(&self) -> &Smcr {
&self.smcr
}
#[doc = "0x0c - TIM DMA/Interrupt enable register"]
#[inline(always)]
pub const fn dier(&self) -> &Dier {
&self.dier
}
#[doc = "0x10 - TIM status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Event generation register"]
#[inline(always)]
pub const fn egr(&self) -> &Egr {
&self.egr
}
#[doc = "0x18 - TIM capture/compare mode register 1"]
#[inline(always)]
pub const fn ccmr1(&self) -> &Ccmr1 {
&self.ccmr1
}
#[doc = "0x1c - TIM capture/compare mode register 2"]
#[inline(always)]
pub const fn ccmr2(&self) -> &Ccmr2 {
&self.ccmr2
}
#[doc = "0x20 - Capture/Compare enable register"]
#[inline(always)]
pub const fn ccer(&self) -> &Ccer {
&self.ccer
}
#[doc = "0x24 - Counter"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x28 - Prescaler"]
#[inline(always)]
pub const fn psc(&self) -> &Psc {
&self.psc
}
#[doc = "0x2c - Auto-reload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
#[doc = "0x30 - Repetition counter register"]
#[inline(always)]
pub const fn rcr(&self) -> &Rcr {
&self.rcr
}
#[doc = "0x34 - Capture/Compare register 1"]
#[inline(always)]
pub const fn ccr1(&self) -> &Ccr1 {
&self.ccr1
}
#[doc = "0x38 - Capture/Compare register 2"]
#[inline(always)]
pub const fn ccr2(&self) -> &Ccr2 {
&self.ccr2
}
#[doc = "0x3c - Capture/Compare register 3"]
#[inline(always)]
pub const fn ccr3(&self) -> &Ccr3 {
&self.ccr3
}
#[doc = "0x40 - Capture/Compare register 4"]
#[inline(always)]
pub const fn ccr4(&self) -> &Ccr4 {
&self.ccr4
}
#[doc = "0x44 - TIM break and dead-time register"]
#[inline(always)]
pub const fn bdtr(&self) -> &Bdtr {
&self.bdtr
}
#[doc = "0x48 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x54 - TIM capture/compare mode register 3"]
#[inline(always)]
pub const fn ccmr3(&self) -> &Ccmr3 {
&self.ccmr3
}
#[doc = "0x58 - Capture/Compare register 5"]
#[inline(always)]
pub const fn ccr5(&self) -> &Ccr5 {
&self.ccr5
}
#[doc = "0x5c - Capture/Compare register 6"]
#[inline(always)]
pub const fn ccr6(&self) -> &Ccr6 {
&self.ccr6
}
#[doc = "0x60 - Alternate function option register"]
#[inline(always)]
pub const fn af1(&self) -> &Af1 {
&self.af1
}
#[doc = "0x64 - Alternate function option register 2"]
#[inline(always)]
pub const fn af2(&self) -> &Af2 {
&self.af2
}
}
#[doc = "CR1 (rw) register accessor: TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "TIM control register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `CEN` reader - Counter enable 0: Counter disabled 1: Counter enabled External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - Counter enable 0: Counter disabled 1: Counter enabled External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UDIS` reader - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisR = crate::BitReader;
#[doc = "Field `UDIS` writer - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `URS` reader - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled."]
pub type UrsR = crate::BitReader;
#[doc = "Field `URS` writer - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled."]
pub type UrsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OPM` reader - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmR = crate::BitReader;
#[doc = "Field `OPM` writer - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - Direction 0: Counter used as upcounter 1: Counter used as downcounter"]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - Direction 0: Counter used as upcounter 1: Counter used as downcounter"]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CMS` reader - Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set both when the counter is counting up or down."]
pub type CmsR = crate::FieldReader;
#[doc = "Field `CMS` writer - Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set both when the counter is counting up or down."]
pub type CmsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ARPE` reader - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeR = crate::BitReader;
#[doc = "Field `ARPE` writer - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `UIFREMAP` reader - UIF status bit remapping 0: No remapping. UIF status bit is not copied to CNT register bit 31 1: Remapping enabled. UIF status bit is copied to CNT register bit 31."]
pub type UifremapR = crate::BitReader;
#[doc = "Field `UIFREMAP` writer - UIF status bit remapping 0: No remapping. UIF status bit is not copied to CNT register bit 31 1: Remapping enabled. UIF status bit is copied to CNT register bit 31."]
pub type UifremapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
impl R {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
pub fn udis(&self) -> UdisR {
UdisR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
pub fn urs(&self) -> UrsR {
UrsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
pub fn opm(&self) -> OpmR {
OpmR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Direction 0: Counter used as upcounter 1: Counter used as downcounter"]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6 - Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set both when the counter is counting up or down."]
#[inline(always)]
pub fn cms(&self) -> CmsR {
CmsR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
pub fn arpe(&self) -> ArpeR {
ArpeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bit 11 - UIF status bit remapping 0: No remapping. UIF status bit is not copied to CNT register bit 31 1: Remapping enabled. UIF status bit is copied to CNT register bit 31."]
#[inline(always)]
pub fn uifremap(&self) -> UifremapR {
UifremapR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 12) & 0x000f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CenW<Cr1Spec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UdisW<Cr1Spec> {
UdisW::new(self, 1)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> UrsW<Cr1Spec> {
UrsW::new(self, 2)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OpmW<Cr1Spec> {
OpmW::new(self, 3)
}
#[doc = "Bit 4 - Direction 0: Counter used as upcounter 1: Counter used as downcounter"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Cr1Spec> {
DirW::new(self, 4)
}
#[doc = "Bits 5:6 - Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set both when the counter is counting up or down."]
#[inline(always)]
#[must_use]
pub fn cms(&mut self) -> CmsW<Cr1Spec> {
CmsW::new(self, 5)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ArpeW<Cr1Spec> {
ArpeW::new(self, 7)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 11 - UIF status bit remapping 0: No remapping. UIF status bit is not copied to CNT register bit 31 1: Remapping enabled. UIF status bit is copied to CNT register bit 31."]
#[inline(always)]
#[must_use]
pub fn uifremap(&mut self) -> UifremapW<Cr1Spec> {
UifremapW::new(self, 11)
}
#[doc = "Bits 12:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 12)
}
}
#[doc = "TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "TIM control register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `CCPC` reader - Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or edge detected on TRGI after Trigger selection, depending on the CCUS bit). This bit acts only on channels that have a complementary output."]
pub type CcpcR = crate::BitReader;
#[doc = "Field `CCPC` writer - Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or edge detected on TRGI after Trigger selection, depending on the CCUS bit). This bit acts only on channels that have a complementary output."]
pub type CcpcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCUS` reader - Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an edge occurs on TRGI after Trigger selection This bit acts only on channels that have a complementary output."]
pub type CcusR = crate::BitReader;
#[doc = "Field `CCUS` writer - Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an edge occurs on TRGI after Trigger selection This bit acts only on channels that have a complementary output."]
pub type CcusW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCDS` reader - Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs"]
pub type CcdsR = crate::BitReader;
#[doc = "Field `CCDS` writer - Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs"]
pub type CcdsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MMS` reader - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected. 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REFC signal is used as trigger output (TRGO) 101: Compare - OC2REFC signal is used as trigger output (TRGO) 110: Compare - OC3REFC signal is used as trigger output (TRGO) 111: Compare - OC4REFC signal is used as trigger output (TRGO)"]
pub type MmsR = crate::FieldReader;
#[doc = "Field `MMS` writer - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected. 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REFC signal is used as trigger output (TRGO) 101: Compare - OC2REFC signal is used as trigger output (TRGO) 110: Compare - OC3REFC signal is used as trigger output (TRGO) 111: Compare - OC4REFC signal is used as trigger output (TRGO)"]
pub type MmsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `TI1S` reader - TI1 selection 0: The CH1 pin is connected to TI1 input 1: The CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)"]
pub type Ti1sR = crate::BitReader;
#[doc = "Field `TI1S` writer - TI1 selection 0: The CH1 pin is connected to TI1 input 1: The CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)"]
pub type Ti1sW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS1` reader - Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 This bit, as well as other OISx, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
pub type Ois1R = crate::BitReader;
#[doc = "Field `OIS1` writer - Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 This bit, as well as other OISx, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
pub type Ois1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS1N` reader - Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 This bit, as well as other OISxN, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
pub type Ois1nR = crate::BitReader;
#[doc = "Field `OIS1N` writer - Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 This bit, as well as other OISxN, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
pub type Ois1nW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS2` reader - Output Idle state 2 (OC2 output)"]
pub type Ois2R = crate::BitReader;
#[doc = "Field `OIS2` writer - Output Idle state 2 (OC2 output)"]
pub type Ois2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS2N` reader - Output Idle state 2 (OC2N output)"]
pub type Ois2nR = crate::BitReader;
#[doc = "Field `OIS2N` writer - Output Idle state 2 (OC2N output)"]
pub type Ois2nW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS3` reader - Output Idle state 3 (OC3 output)"]
pub type Ois3R = crate::BitReader;
#[doc = "Field `OIS3` writer - Output Idle state 3 (OC3 output)"]
pub type Ois3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS3N` reader - Output Idle state 3 (OC3N output)"]
pub type Ois3nR = crate::BitReader;
#[doc = "Field `OIS3N` writer - Output Idle state 3 (OC3N output)"]
pub type Ois3nW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS4` reader - Output Idle state 4 (OC4 output)"]
pub type Ois4R = crate::BitReader;
#[doc = "Field `OIS4` writer - Output Idle state 4 (OC4 output)"]
pub type Ois4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS5` reader - Output Idle state 5 (OC5 output)"]
pub type Ois5R = crate::BitReader;
#[doc = "Field `OIS5` writer - Output Idle state 5 (OC5 output)"]
pub type Ois5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS6` reader - Output Idle state 6 (OC6 output)"]
pub type Ois6R = crate::BitReader;
#[doc = "Field `OIS6` writer - Output Idle state 6 (OC6 output)"]
pub type Ois6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
impl R {
#[doc = "Bit 0 - Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or edge detected on TRGI after Trigger selection, depending on the CCUS bit). This bit acts only on channels that have a complementary output."]
#[inline(always)]
pub fn ccpc(&self) -> CcpcR {
CcpcR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an edge occurs on TRGI after Trigger selection This bit acts only on channels that have a complementary output."]
#[inline(always)]
pub fn ccus(&self) -> CcusR {
CcusR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs"]
#[inline(always)]
pub fn ccds(&self) -> CcdsR {
CcdsR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected. 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REFC signal is used as trigger output (TRGO) 101: Compare - OC2REFC signal is used as trigger output (TRGO) 110: Compare - OC3REFC signal is used as trigger output (TRGO) 111: Compare - OC4REFC signal is used as trigger output (TRGO)"]
#[inline(always)]
pub fn mms(&self) -> MmsR {
MmsR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - TI1 selection 0: The CH1 pin is connected to TI1 input 1: The CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)"]
#[inline(always)]
pub fn ti1s(&self) -> Ti1sR {
Ti1sR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 This bit, as well as other OISx, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
#[inline(always)]
pub fn ois1(&self) -> Ois1R {
Ois1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 This bit, as well as other OISxN, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
#[inline(always)]
pub fn ois1n(&self) -> Ois1nR {
Ois1nR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Output Idle state 2 (OC2 output)"]
#[inline(always)]
pub fn ois2(&self) -> Ois2R {
Ois2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Output Idle state 2 (OC2N output)"]
#[inline(always)]
pub fn ois2n(&self) -> Ois2nR {
Ois2nR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Output Idle state 3 (OC3 output)"]
#[inline(always)]
pub fn ois3(&self) -> Ois3R {
Ois3R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Output Idle state 3 (OC3N output)"]
#[inline(always)]
pub fn ois3n(&self) -> Ois3nR {
Ois3nR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Output Idle state 4 (OC4 output)"]
#[inline(always)]
pub fn ois4(&self) -> Ois4R {
Ois4R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Output Idle state 5 (OC5 output)"]
#[inline(always)]
pub fn ois5(&self) -> Ois5R {
Ois5R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Output Idle state 6 (OC6 output)"]
#[inline(always)]
pub fn ois6(&self) -> Ois6R {
Ois6R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bits 19:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 19) & 0x1fff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or edge detected on TRGI after Trigger selection, depending on the CCUS bit). This bit acts only on channels that have a complementary output."]
#[inline(always)]
#[must_use]
pub fn ccpc(&mut self) -> CcpcW<Cr2Spec> {
CcpcW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cr2Spec> {
Rsvd4W::new(self, 1)
}
#[doc = "Bit 2 - Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an edge occurs on TRGI after Trigger selection This bit acts only on channels that have a complementary output."]
#[inline(always)]
#[must_use]
pub fn ccus(&mut self) -> CcusW<Cr2Spec> {
CcusW::new(self, 2)
}
#[doc = "Bit 3 - Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs"]
#[inline(always)]
#[must_use]
pub fn ccds(&mut self) -> CcdsW<Cr2Spec> {
CcdsW::new(self, 3)
}
#[doc = "Bits 4:6 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected. 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REFC signal is used as trigger output (TRGO) 101: Compare - OC2REFC signal is used as trigger output (TRGO) 110: Compare - OC3REFC signal is used as trigger output (TRGO) 111: Compare - OC4REFC signal is used as trigger output (TRGO)"]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MmsW<Cr2Spec> {
MmsW::new(self, 4)
}
#[doc = "Bit 7 - TI1 selection 0: The CH1 pin is connected to TI1 input 1: The CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)"]
#[inline(always)]
#[must_use]
pub fn ti1s(&mut self) -> Ti1sW<Cr2Spec> {
Ti1sW::new(self, 7)
}
#[doc = "Bit 8 - Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 This bit, as well as other OISx, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
#[inline(always)]
#[must_use]
pub fn ois1(&mut self) -> Ois1W<Cr2Spec> {
Ois1W::new(self, 8)
}
#[doc = "Bit 9 - Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 This bit, as well as other OISxN, can not be modified as long as LOCK level 1, 2 or 3 has been programmed"]
#[inline(always)]
#[must_use]
pub fn ois1n(&mut self) -> Ois1nW<Cr2Spec> {
Ois1nW::new(self, 9)
}
#[doc = "Bit 10 - Output Idle state 2 (OC2 output)"]
#[inline(always)]
#[must_use]
pub fn ois2(&mut self) -> Ois2W<Cr2Spec> {
Ois2W::new(self, 10)
}
#[doc = "Bit 11 - Output Idle state 2 (OC2N output)"]
#[inline(always)]
#[must_use]
pub fn ois2n(&mut self) -> Ois2nW<Cr2Spec> {
Ois2nW::new(self, 11)
}
#[doc = "Bit 12 - Output Idle state 3 (OC3 output)"]
#[inline(always)]
#[must_use]
pub fn ois3(&mut self) -> Ois3W<Cr2Spec> {
Ois3W::new(self, 12)
}
#[doc = "Bit 13 - Output Idle state 3 (OC3N output)"]
#[inline(always)]
#[must_use]
pub fn ois3n(&mut self) -> Ois3nW<Cr2Spec> {
Ois3nW::new(self, 13)
}
#[doc = "Bit 14 - Output Idle state 4 (OC4 output)"]
#[inline(always)]
#[must_use]
pub fn ois4(&mut self) -> Ois4W<Cr2Spec> {
Ois4W::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cr2Spec> {
Rsvd3W::new(self, 15)
}
#[doc = "Bit 16 - Output Idle state 5 (OC5 output)"]
#[inline(always)]
#[must_use]
pub fn ois5(&mut self) -> Ois5W<Cr2Spec> {
Ois5W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 17)
}
#[doc = "Bit 18 - Output Idle state 6 (OC6 output)"]
#[inline(always)]
#[must_use]
pub fn ois6(&mut self) -> Ois6W<Cr2Spec> {
Ois6W::new(self, 18)
}
#[doc = "Bits 19:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 19)
}
}
#[doc = "TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMCR (rw) register accessor: TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcr`]
module"]
#[doc(alias = "SMCR")]
pub type Smcr = crate::Reg<smcr::SmcrSpec>;
#[doc = "TIM slave mode control register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub type R = crate::R<SmcrSpec>;
#[doc = "Register `SMCR` writer"]
pub type W = crate::W<SmcrSpec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TS` reader - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF)"]
pub type TsR = crate::FieldReader;
#[doc = "Field `TS` writer - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF)"]
pub type TsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `MSM` reader - Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmR = crate::BitReader;
#[doc = "Field `MSM` writer - Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETF` reader - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
pub type EtfR = crate::FieldReader;
#[doc = "Field `ETF` writer - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
pub type EtfW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `ETPS` reader - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8"]
pub type EtpsR = crate::FieldReader;
#[doc = "Field `ETPS` writer - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8"]
pub type EtpsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ECE` reader - External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
pub type EceR = crate::BitReader;
#[doc = "Field `ECE` writer - External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
pub type EceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETP` reader - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge"]
pub type EtpR = crate::BitReader;
#[doc = "Field `ETP` writer - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge"]
pub type EtpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SMS` reader - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 0000: Slave mode disabled. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter."]
pub type SmsR = crate::FieldReader;
#[doc = "Field `SMS` writer - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 0000: Slave mode disabled. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter."]
pub type SmsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:6 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF)"]
#[inline(always)]
pub fn ts(&self) -> TsR {
TsR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
pub fn msm(&self) -> MsmR {
MsmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
#[inline(always)]
pub fn etf(&self) -> EtfR {
EtfR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:13 - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8"]
#[inline(always)]
pub fn etps(&self) -> EtpsR {
EtpsR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
#[inline(always)]
pub fn ece(&self) -> EceR {
EceR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge"]
#[inline(always)]
pub fn etp(&self) -> EtpR {
EtpR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:19 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 0000: Slave mode disabled. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter."]
#[inline(always)]
pub fn sms(&self) -> SmsR {
SmsR::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SmcrSpec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 4:6 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF)"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TsW<SmcrSpec> {
TsW::new(self, 4)
}
#[doc = "Bit 7 - Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MsmW<SmcrSpec> {
MsmW::new(self, 7)
}
#[doc = "Bits 8:11 - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
#[inline(always)]
#[must_use]
pub fn etf(&mut self) -> EtfW<SmcrSpec> {
EtfW::new(self, 8)
}
#[doc = "Bits 12:13 - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8"]
#[inline(always)]
#[must_use]
pub fn etps(&mut self) -> EtpsW<SmcrSpec> {
EtpsW::new(self, 12)
}
#[doc = "Bit 14 - External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
#[inline(always)]
#[must_use]
pub fn ece(&mut self) -> EceW<SmcrSpec> {
EceW::new(self, 14)
}
#[doc = "Bit 15 - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge"]
#[inline(always)]
#[must_use]
pub fn etp(&mut self) -> EtpW<SmcrSpec> {
EtpW::new(self, 15)
}
#[doc = "Bits 16:19 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 0000: Slave mode disabled. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter."]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SmsW<SmcrSpec> {
SmsW::new(self, 16)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SmcrSpec> {
RsvdW::new(self, 20)
}
}
#[doc = "TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmcrSpec;
impl crate::RegisterSpec for SmcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smcr::R`](R) reader structure"]
impl crate::Readable for SmcrSpec {}
#[doc = "`write(|w| ..)` method takes [`smcr::W`](W) writer structure"]
impl crate::Writable for SmcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SmcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DIER (rw) register accessor: TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dier`]
module"]
#[doc(alias = "DIER")]
pub type Dier = crate::Reg<dier::DierSpec>;
#[doc = "TIM DMA/Interrupt enable register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub type R = crate::R<DierSpec>;
#[doc = "Register `DIER` writer"]
pub type W = crate::W<DierSpec>;
#[doc = "Field `UIE` reader - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieR = crate::BitReader;
#[doc = "Field `UIE` writer - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1IE` reader - Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled"]
pub type Cc1ieR = crate::BitReader;
#[doc = "Field `CC1IE` writer - Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled"]
pub type Cc1ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2IE` reader - Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled."]
pub type Cc2ieR = crate::BitReader;
#[doc = "Field `CC2IE` writer - Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled."]
pub type Cc2ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3IE` reader - Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled"]
pub type Cc3ieR = crate::BitReader;
#[doc = "Field `CC3IE` writer - Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled"]
pub type Cc3ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4IE` reader - Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled"]
pub type Cc4ieR = crate::BitReader;
#[doc = "Field `CC4IE` writer - Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled"]
pub type Cc4ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMIE` reader - COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled"]
pub type ComieR = crate::BitReader;
#[doc = "Field `COMIE` writer - COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled"]
pub type ComieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIE` reader - Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled"]
pub type TieR = crate::BitReader;
#[doc = "Field `TIE` writer - Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled"]
pub type TieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BIE` reader - Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled"]
pub type BieR = crate::BitReader;
#[doc = "Field `BIE` writer - Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled"]
pub type BieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UDE` reader - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeR = crate::BitReader;
#[doc = "Field `UDE` writer - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1DE` reader - Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled."]
pub type Cc1deR = crate::BitReader;
#[doc = "Field `CC1DE` writer - Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled."]
pub type Cc1deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2DE` reader - Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled."]
pub type Cc2deR = crate::BitReader;
#[doc = "Field `CC2DE` writer - Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled."]
pub type Cc2deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3DE` reader - Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled."]
pub type Cc3deR = crate::BitReader;
#[doc = "Field `CC3DE` writer - Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled."]
pub type Cc3deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4DE` reader - Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled"]
pub type Cc4deR = crate::BitReader;
#[doc = "Field `CC4DE` writer - Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled"]
pub type Cc4deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMDE` reader - COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled"]
pub type ComdeR = crate::BitReader;
#[doc = "Field `COMDE` writer - COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled"]
pub type ComdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TDE` reader - Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled."]
pub type TdeR = crate::BitReader;
#[doc = "Field `TDE` writer - Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled."]
pub type TdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC5IE` reader - Capture/Compare 5 interrupt enable 0: CC5 interrupt disabled. 1: CC5 interrupt enabled"]
pub type Cc5ieR = crate::BitReader;
#[doc = "Field `CC5IE` writer - Capture/Compare 5 interrupt enable 0: CC5 interrupt disabled. 1: CC5 interrupt enabled"]
pub type Cc5ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC6IE` reader - Capture/Compare 6 interrupt enable 0: CC6 interrupt disabled. 1: CC6 interrupt enabled"]
pub type Cc6ieR = crate::BitReader;
#[doc = "Field `CC6IE` writer - Capture/Compare 6 interrupt enable 0: CC6 interrupt disabled. 1: CC6 interrupt enabled"]
pub type Cc6ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
pub fn uie(&self) -> UieR {
UieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled"]
#[inline(always)]
pub fn cc1ie(&self) -> Cc1ieR {
Cc1ieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled."]
#[inline(always)]
pub fn cc2ie(&self) -> Cc2ieR {
Cc2ieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled"]
#[inline(always)]
pub fn cc3ie(&self) -> Cc3ieR {
Cc3ieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled"]
#[inline(always)]
pub fn cc4ie(&self) -> Cc4ieR {
Cc4ieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled"]
#[inline(always)]
pub fn comie(&self) -> ComieR {
ComieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled"]
#[inline(always)]
pub fn tie(&self) -> TieR {
TieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled"]
#[inline(always)]
pub fn bie(&self) -> BieR {
BieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
pub fn ude(&self) -> UdeR {
UdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled."]
#[inline(always)]
pub fn cc1de(&self) -> Cc1deR {
Cc1deR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled."]
#[inline(always)]
pub fn cc2de(&self) -> Cc2deR {
Cc2deR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled."]
#[inline(always)]
pub fn cc3de(&self) -> Cc3deR {
Cc3deR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled"]
#[inline(always)]
pub fn cc4de(&self) -> Cc4deR {
Cc4deR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled"]
#[inline(always)]
pub fn comde(&self) -> ComdeR {
ComdeR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled."]
#[inline(always)]
pub fn tde(&self) -> TdeR {
TdeR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Capture/Compare 5 interrupt enable 0: CC5 interrupt disabled. 1: CC5 interrupt enabled"]
#[inline(always)]
pub fn cc5ie(&self) -> Cc5ieR {
Cc5ieR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Capture/Compare 6 interrupt enable 0: CC6 interrupt disabled. 1: CC6 interrupt enabled"]
#[inline(always)]
pub fn cc6ie(&self) -> Cc6ieR {
Cc6ieR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bits 18:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 18) & 0x3fff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UieW<DierSpec> {
UieW::new(self, 0)
}
#[doc = "Bit 1 - Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn cc1ie(&mut self) -> Cc1ieW<DierSpec> {
Cc1ieW::new(self, 1)
}
#[doc = "Bit 2 - Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled."]
#[inline(always)]
#[must_use]
pub fn cc2ie(&mut self) -> Cc2ieW<DierSpec> {
Cc2ieW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn cc3ie(&mut self) -> Cc3ieW<DierSpec> {
Cc3ieW::new(self, 3)
}
#[doc = "Bit 4 - Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn cc4ie(&mut self) -> Cc4ieW<DierSpec> {
Cc4ieW::new(self, 4)
}
#[doc = "Bit 5 - COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn comie(&mut self) -> ComieW<DierSpec> {
ComieW::new(self, 5)
}
#[doc = "Bit 6 - Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn tie(&mut self) -> TieW<DierSpec> {
TieW::new(self, 6)
}
#[doc = "Bit 7 - Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn bie(&mut self) -> BieW<DierSpec> {
BieW::new(self, 7)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UdeW<DierSpec> {
UdeW::new(self, 8)
}
#[doc = "Bit 9 - Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled."]
#[inline(always)]
#[must_use]
pub fn cc1de(&mut self) -> Cc1deW<DierSpec> {
Cc1deW::new(self, 9)
}
#[doc = "Bit 10 - Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled."]
#[inline(always)]
#[must_use]
pub fn cc2de(&mut self) -> Cc2deW<DierSpec> {
Cc2deW::new(self, 10)
}
#[doc = "Bit 11 - Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled."]
#[inline(always)]
#[must_use]
pub fn cc3de(&mut self) -> Cc3deW<DierSpec> {
Cc3deW::new(self, 11)
}
#[doc = "Bit 12 - Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled"]
#[inline(always)]
#[must_use]
pub fn cc4de(&mut self) -> Cc4deW<DierSpec> {
Cc4deW::new(self, 12)
}
#[doc = "Bit 13 - COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled"]
#[inline(always)]
#[must_use]
pub fn comde(&mut self) -> ComdeW<DierSpec> {
ComdeW::new(self, 13)
}
#[doc = "Bit 14 - Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled."]
#[inline(always)]
#[must_use]
pub fn tde(&mut self) -> TdeW<DierSpec> {
TdeW::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DierSpec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bit 16 - Capture/Compare 5 interrupt enable 0: CC5 interrupt disabled. 1: CC5 interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn cc5ie(&mut self) -> Cc5ieW<DierSpec> {
Cc5ieW::new(self, 16)
}
#[doc = "Bit 17 - Capture/Compare 6 interrupt enable 0: CC6 interrupt disabled. 1: CC6 interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn cc6ie(&mut self) -> Cc6ieW<DierSpec> {
Cc6ieW::new(self, 17)
}
#[doc = "Bits 18:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DierSpec> {
RsvdW::new(self, 18)
}
}
#[doc = "TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DierSpec;
impl crate::RegisterSpec for DierSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dier::R`](R) reader structure"]
impl crate::Readable for DierSpec {}
#[doc = "`write(|w| ..)` method takes [`dier::W`](W) writer structure"]
impl crate::Writable for DierSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DierSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "TIM status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `UIF` reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: - At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if UDIS=0 in the CR1 register. - When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. - When CNT is reinitialized by a trigger event, if URS=0 and UDIS=0 in the CR1 register."]
pub type UifR = crate::BitReader;
#[doc = "Field `UIF` writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: - At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if UDIS=0 in the CR1 register. - When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. - When CNT is reinitialized by a trigger event, if URS=0 and UDIS=0 in the CR1 register."]
pub type UifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1IF` reader - Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value and in retriggerable one pulse mode. It is cleared by software. 0: No match. 1: The content of the counter CNT has matched the content of the CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in CCR1 register."]
pub type Cc1ifR = crate::BitReader;
#[doc = "Field `CC1IF` writer - Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value and in retriggerable one pulse mode. It is cleared by software. 0: No match. 1: The content of the counter CNT has matched the content of the CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in CCR1 register."]
pub type Cc1ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2IF` reader - Capture/Compare 2 interrupt flag"]
pub type Cc2ifR = crate::BitReader;
#[doc = "Field `CC2IF` writer - Capture/Compare 2 interrupt flag"]
pub type Cc2ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3IF` reader - Capture/Compare 3 interrupt flag"]
pub type Cc3ifR = crate::BitReader;
#[doc = "Field `CC3IF` writer - Capture/Compare 3 interrupt flag"]
pub type Cc3ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4IF` reader - Capture/Compare 4 interrupt flag"]
pub type Cc4ifR = crate::BitReader;
#[doc = "Field `CC4IF` writer - Capture/Compare 4 interrupt flag"]
pub type Cc4ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMIF` reader - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending."]
pub type ComifR = crate::BitReader;
#[doc = "Field `COMIF` writer - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending."]
pub type ComifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIF` reader - Trigger interrupt flag This flag is set by hardware on trigger event. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending."]
pub type TifR = crate::BitReader;
#[doc = "Field `TIF` writer - Trigger interrupt flag This flag is set by hardware on trigger event. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending."]
pub type TifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BIF` reader - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the DIER register."]
pub type BifR = crate::BitReader;
#[doc = "Field `BIF` writer - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the DIER register."]
pub type BifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `B2IF` reader - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred. 1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the DIER register."]
pub type B2ifR = crate::BitReader;
#[doc = "Field `B2IF` writer - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred. 1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the DIER register."]
pub type B2ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1OF` reader - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in CCR1 register while CC1IF flag was already set"]
pub type Cc1ofR = crate::BitReader;
#[doc = "Field `CC1OF` writer - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in CCR1 register while CC1IF flag was already set"]
pub type Cc1ofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2OF` reader - Capture/Compare 2 overcapture flag"]
pub type Cc2ofR = crate::BitReader;
#[doc = "Field `CC2OF` writer - Capture/Compare 2 overcapture flag"]
pub type Cc2ofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3OF` reader - Capture/Compare 3 overcapture flag"]
pub type Cc3ofR = crate::BitReader;
#[doc = "Field `CC3OF` writer - Capture/Compare 3 overcapture flag"]
pub type Cc3ofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4OF` reader - Capture/Compare 4 overcapture flag"]
pub type Cc4ofR = crate::BitReader;
#[doc = "Field `CC4OF` writer - Capture/Compare 4 overcapture flag"]
pub type Cc4ofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SBIF` reader - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0: No break event occurred. 1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the DIER register."]
pub type SbifR = crate::BitReader;
#[doc = "Field `SBIF` writer - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0: No break event occurred. 1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the DIER register."]
pub type SbifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC5IF` reader - Compare 5 interrupt flag"]
pub type Cc5ifR = crate::BitReader;
#[doc = "Field `CC5IF` writer - Compare 5 interrupt flag"]
pub type Cc5ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC6IF` reader - Compare 6 interrupt flag"]
pub type Cc6ifR = crate::BitReader;
#[doc = "Field `CC6IF` writer - Compare 6 interrupt flag"]
pub type Cc6ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: - At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if UDIS=0 in the CR1 register. - When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. - When CNT is reinitialized by a trigger event, if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
pub fn uif(&self) -> UifR {
UifR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value and in retriggerable one pulse mode. It is cleared by software. 0: No match. 1: The content of the counter CNT has matched the content of the CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in CCR1 register."]
#[inline(always)]
pub fn cc1if(&self) -> Cc1ifR {
Cc1ifR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/Compare 2 interrupt flag"]
#[inline(always)]
pub fn cc2if(&self) -> Cc2ifR {
Cc2ifR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/Compare 3 interrupt flag"]
#[inline(always)]
pub fn cc3if(&self) -> Cc3ifR {
Cc3ifR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/Compare 4 interrupt flag"]
#[inline(always)]
pub fn cc4if(&self) -> Cc4ifR {
Cc4ifR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending."]
#[inline(always)]
pub fn comif(&self) -> ComifR {
ComifR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Trigger interrupt flag This flag is set by hardware on trigger event. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending."]
#[inline(always)]
pub fn tif(&self) -> TifR {
TifR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the DIER register."]
#[inline(always)]
pub fn bif(&self) -> BifR {
BifR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred. 1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the DIER register."]
#[inline(always)]
pub fn b2if(&self) -> B2ifR {
B2ifR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in CCR1 register while CC1IF flag was already set"]
#[inline(always)]
pub fn cc1of(&self) -> Cc1ofR {
Cc1ofR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Capture/Compare 2 overcapture flag"]
#[inline(always)]
pub fn cc2of(&self) -> Cc2ofR {
Cc2ofR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture/Compare 3 overcapture flag"]
#[inline(always)]
pub fn cc3of(&self) -> Cc3ofR {
Cc3ofR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Capture/Compare 4 overcapture flag"]
#[inline(always)]
pub fn cc4of(&self) -> Cc4ofR {
Cc4ofR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0: No break event occurred. 1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the DIER register."]
#[inline(always)]
pub fn sbif(&self) -> SbifR {
SbifR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Compare 5 interrupt flag"]
#[inline(always)]
pub fn cc5if(&self) -> Cc5ifR {
Cc5ifR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Compare 6 interrupt flag"]
#[inline(always)]
pub fn cc6if(&self) -> Cc6ifR {
Cc6ifR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bits 18:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 18) & 0x3fff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: - At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if UDIS=0 in the CR1 register. - When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. - When CNT is reinitialized by a trigger event, if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UifW<SrSpec> {
UifW::new(self, 0)
}
#[doc = "Bit 1 - Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value and in retriggerable one pulse mode. It is cleared by software. 0: No match. 1: The content of the counter CNT has matched the content of the CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in CCR1 register."]
#[inline(always)]
#[must_use]
pub fn cc1if(&mut self) -> Cc1ifW<SrSpec> {
Cc1ifW::new(self, 1)
}
#[doc = "Bit 2 - Capture/Compare 2 interrupt flag"]
#[inline(always)]
#[must_use]
pub fn cc2if(&mut self) -> Cc2ifW<SrSpec> {
Cc2ifW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare 3 interrupt flag"]
#[inline(always)]
#[must_use]
pub fn cc3if(&mut self) -> Cc3ifW<SrSpec> {
Cc3ifW::new(self, 3)
}
#[doc = "Bit 4 - Capture/Compare 4 interrupt flag"]
#[inline(always)]
#[must_use]
pub fn cc4if(&mut self) -> Cc4ifW<SrSpec> {
Cc4ifW::new(self, 4)
}
#[doc = "Bit 5 - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending."]
#[inline(always)]
#[must_use]
pub fn comif(&mut self) -> ComifW<SrSpec> {
ComifW::new(self, 5)
}
#[doc = "Bit 6 - Trigger interrupt flag This flag is set by hardware on trigger event. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending."]
#[inline(always)]
#[must_use]
pub fn tif(&mut self) -> TifW<SrSpec> {
TifW::new(self, 6)
}
#[doc = "Bit 7 - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the DIER register."]
#[inline(always)]
#[must_use]
pub fn bif(&mut self) -> BifW<SrSpec> {
BifW::new(self, 7)
}
#[doc = "Bit 8 - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred. 1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the DIER register."]
#[inline(always)]
#[must_use]
pub fn b2if(&mut self) -> B2ifW<SrSpec> {
B2ifW::new(self, 8)
}
#[doc = "Bit 9 - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in CCR1 register while CC1IF flag was already set"]
#[inline(always)]
#[must_use]
pub fn cc1of(&mut self) -> Cc1ofW<SrSpec> {
Cc1ofW::new(self, 9)
}
#[doc = "Bit 10 - Capture/Compare 2 overcapture flag"]
#[inline(always)]
#[must_use]
pub fn cc2of(&mut self) -> Cc2ofW<SrSpec> {
Cc2ofW::new(self, 10)
}
#[doc = "Bit 11 - Capture/Compare 3 overcapture flag"]
#[inline(always)]
#[must_use]
pub fn cc3of(&mut self) -> Cc3ofW<SrSpec> {
Cc3ofW::new(self, 11)
}
#[doc = "Bit 12 - Capture/Compare 4 overcapture flag"]
#[inline(always)]
#[must_use]
pub fn cc4of(&mut self) -> Cc4ofW<SrSpec> {
Cc4ofW::new(self, 12)
}
#[doc = "Bit 13 - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0: No break event occurred. 1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the DIER register."]
#[inline(always)]
#[must_use]
pub fn sbif(&mut self) -> SbifW<SrSpec> {
SbifW::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<SrSpec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SrSpec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bit 16 - Compare 5 interrupt flag"]
#[inline(always)]
#[must_use]
pub fn cc5if(&mut self) -> Cc5ifW<SrSpec> {
Cc5ifW::new(self, 16)
}
#[doc = "Bit 17 - Compare 6 interrupt flag"]
#[inline(always)]
#[must_use]
pub fn cc6if(&mut self) -> Cc6ifW<SrSpec> {
Cc6ifW::new(self, 17)
}
#[doc = "Bits 18:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 18)
}
}
#[doc = "TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EGR (rw) register accessor: Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@egr`]
module"]
#[doc(alias = "EGR")]
pub type Egr = crate::Reg<egr::EgrSpec>;
#[doc = "Event generation register"]
pub mod egr {
#[doc = "Register `EGR` reader"]
pub type R = crate::R<EgrSpec>;
#[doc = "Register `EGR` writer"]
pub type W = crate::W<EgrSpec>;
#[doc = "Field `UG` reader - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. The prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgR = crate::BitReader;
#[doc = "Field `UG` writer - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. The prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1G` reader - Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high."]
pub type Cc1gR = crate::BitReader;
#[doc = "Field `CC1G` writer - Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high."]
pub type Cc1gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2G` reader - Capture/compare 2 generation"]
pub type Cc2gR = crate::BitReader;
#[doc = "Field `CC2G` writer - Capture/compare 2 generation"]
pub type Cc2gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3G` reader - Capture/compare 3 generation"]
pub type Cc3gR = crate::BitReader;
#[doc = "Field `CC3G` writer - Capture/compare 3 generation"]
pub type Cc3gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4G` reader - Capture/compare 4 generation"]
pub type Cc4gR = crate::BitReader;
#[doc = "Field `CC4G` writer - Capture/compare 4 generation"]
pub type Cc4gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMG` reader - Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits This bit acts only on channels having a complementary output."]
pub type ComgR = crate::BitReader;
#[doc = "Field `COMG` writer - Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits This bit acts only on channels having a complementary output."]
pub type ComgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TG` reader - Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in SR register. Related interrupt or DMA transfer can occur if enabled."]
pub type TgR = crate::BitReader;
#[doc = "Field `TG` writer - Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in SR register. Related interrupt or DMA transfer can occur if enabled."]
pub type TgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BG` reader - Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled."]
pub type BgR = crate::BitReader;
#[doc = "Field `BG` writer - Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled."]
pub type BgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `B2G` reader - Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled."]
pub type B2gR = crate::BitReader;
#[doc = "Field `B2G` writer - Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled."]
pub type B2gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. The prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
pub fn ug(&self) -> UgR {
UgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high."]
#[inline(always)]
pub fn cc1g(&self) -> Cc1gR {
Cc1gR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/compare 2 generation"]
#[inline(always)]
pub fn cc2g(&self) -> Cc2gR {
Cc2gR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/compare 3 generation"]
#[inline(always)]
pub fn cc3g(&self) -> Cc3gR {
Cc3gR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare 4 generation"]
#[inline(always)]
pub fn cc4g(&self) -> Cc4gR {
Cc4gR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits This bit acts only on channels having a complementary output."]
#[inline(always)]
pub fn comg(&self) -> ComgR {
ComgR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in SR register. Related interrupt or DMA transfer can occur if enabled."]
#[inline(always)]
pub fn tg(&self) -> TgR {
TgR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled."]
#[inline(always)]
pub fn bg(&self) -> BgR {
BgR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled."]
#[inline(always)]
pub fn b2g(&self) -> B2gR {
B2gR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. The prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UgW<EgrSpec> {
UgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high."]
#[inline(always)]
#[must_use]
pub fn cc1g(&mut self) -> Cc1gW<EgrSpec> {
Cc1gW::new(self, 1)
}
#[doc = "Bit 2 - Capture/compare 2 generation"]
#[inline(always)]
#[must_use]
pub fn cc2g(&mut self) -> Cc2gW<EgrSpec> {
Cc2gW::new(self, 2)
}
#[doc = "Bit 3 - Capture/compare 3 generation"]
#[inline(always)]
#[must_use]
pub fn cc3g(&mut self) -> Cc3gW<EgrSpec> {
Cc3gW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare 4 generation"]
#[inline(always)]
#[must_use]
pub fn cc4g(&mut self) -> Cc4gW<EgrSpec> {
Cc4gW::new(self, 4)
}
#[doc = "Bit 5 - Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits This bit acts only on channels having a complementary output."]
#[inline(always)]
#[must_use]
pub fn comg(&mut self) -> ComgW<EgrSpec> {
ComgW::new(self, 5)
}
#[doc = "Bit 6 - Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in SR register. Related interrupt or DMA transfer can occur if enabled."]
#[inline(always)]
#[must_use]
pub fn tg(&mut self) -> TgW<EgrSpec> {
TgW::new(self, 6)
}
#[doc = "Bit 7 - Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled."]
#[inline(always)]
#[must_use]
pub fn bg(&mut self) -> BgW<EgrSpec> {
BgW::new(self, 7)
}
#[doc = "Bit 8 - Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled."]
#[inline(always)]
#[must_use]
pub fn b2g(&mut self) -> B2gW<EgrSpec> {
B2gW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<EgrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EgrSpec;
impl crate::RegisterSpec for EgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`egr::R`](R) reader structure"]
impl crate::Readable for EgrSpec {}
#[doc = "`write(|w| ..)` method takes [`egr::W`](W) writer structure"]
impl crate::Writable for EgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCMR1 (rw) register accessor: TIM capture/compare mode register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccmr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccmr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccmr1`]
module"]
#[doc(alias = "CCMR1")]
pub type Ccmr1 = crate::Reg<ccmr1::Ccmr1Spec>;
#[doc = "TIM capture/compare mode register 1"]
pub mod ccmr1 {
#[doc = "Register `CCMR1` reader"]
pub type R = crate::R<Ccmr1Spec>;
#[doc = "Register `CCMR1` writer"]
pub type W = crate::W<Ccmr1Spec>;
#[doc = "Field `CC1S` reader - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
pub type Cc1sR = crate::FieldReader;
#[doc = "Field `CC1S` writer - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
pub type Cc1sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC1PSC` reader - Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events"]
pub type Ic1pscR = crate::FieldReader;
#[doc = "Field `IC1PSC` writer - Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events"]
pub type Ic1pscW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC1F` reader - Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
pub type Ic1fR = crate::FieldReader;
#[doc = "Field `IC1F` writer - Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
pub type Ic1fW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CC2S` reader - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (SMCR register)"]
pub type Cc2sR = crate::FieldReader;
#[doc = "Field `CC2S` writer - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (SMCR register)"]
pub type Cc2sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC2PSC` reader - Input capture 2 prescaler"]
pub type Ic2pscR = crate::FieldReader;
#[doc = "Field `IC2PSC` writer - Input capture 2 prescaler"]
pub type Ic2pscW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC2F` reader - Input capture 2 filter"]
pub type Ic2fR = crate::FieldReader;
#[doc = "Field `IC2F` writer - Input capture 2 filter"]
pub type Ic2fW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `OC1CE` reader - Output compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input"]
pub type Oc1ceR = crate::BitReader;
#[doc = "Field `OC1CE` writer - Output compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input"]
pub type Oc1ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OC1PE` reader - Output compare 1 preload enable 0: Preload register on CCR1 disabled. CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on CCR1 enabled. Read/Write operations access the preload register. CCR1 preload value is loaded in the active register at each update event. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=’00’ (the channel is configured in output)."]
pub type Oc1peR = crate::BitReader;
#[doc = "Field `OC1PE` writer - Output compare 1 preload enable 0: Preload register on CCR1 disabled. CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on CCR1 enabled. Read/Write operations access the preload register. CCR1 preload value is loaded in the active register at each update event. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=’00’ (the channel is configured in output)."]
pub type Oc1peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC1M` reader - Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register CCR1 and the counter CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter CNT matches the capture/compare register 1 (CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter CNT matches the capture/compare register 1 (CCR1). 0011: Toggle - OC1REF toggles when CNT=CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as CNT<CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as CNT>CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as CNT<CCR1 else active. In downcounting, channel 1 is active as long as CNT>CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=00 (the channel is configured in output). On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated."]
pub type Oc1mR = crate::FieldReader;
#[doc = "Field `OC1M` writer - Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register CCR1 and the counter CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter CNT matches the capture/compare register 1 (CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter CNT matches the capture/compare register 1 (CCR1). 0011: Toggle - OC1REF toggles when CNT=CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as CNT<CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as CNT>CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as CNT<CCR1 else active. In downcounting, channel 1 is active as long as CNT>CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=00 (the channel is configured in output). On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated."]
pub type Oc1mW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `OC2CE` reader - Output compare 2 clear enable"]
pub type Oc2ceR = crate::BitReader;
#[doc = "Field `OC2CE` writer - Output compare 2 clear enable"]
pub type Oc2ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OC2PE` reader - Output compare 2 preload enable"]
pub type Oc2peR = crate::BitReader;
#[doc = "Field `OC2PE` writer - Output compare 2 preload enable"]
pub type Oc2peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC2M` reader - Output compare 2 mode"]
pub type Oc2mR = crate::FieldReader;
#[doc = "Field `OC2M` writer - Output compare 2 mode"]
pub type Oc2mW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:1 - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
#[inline(always)]
pub fn cc1s(&self) -> Cc1sR {
Cc1sR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events"]
#[inline(always)]
pub fn ic1psc(&self) -> Ic1pscR {
Ic1pscR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7 - Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
#[inline(always)]
pub fn ic1f(&self) -> Ic1fR {
Ic1fR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9 - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (SMCR register)"]
#[inline(always)]
pub fn cc2s(&self) -> Cc2sR {
Cc2sR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Input capture 2 prescaler"]
#[inline(always)]
pub fn ic2psc(&self) -> Ic2pscR {
Ic2pscR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15 - Input capture 2 filter"]
#[inline(always)]
pub fn ic2f(&self) -> Ic2fR {
Ic2fR::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bit 16 - Output compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input"]
#[inline(always)]
pub fn oc1ce(&self) -> Oc1ceR {
Oc1ceR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bit 19 - Output compare 1 preload enable 0: Preload register on CCR1 disabled. CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on CCR1 enabled. Read/Write operations access the preload register. CCR1 preload value is loaded in the active register at each update event. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=’00’ (the channel is configured in output)."]
#[inline(always)]
pub fn oc1pe(&self) -> Oc1peR {
Oc1peR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:23 - Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register CCR1 and the counter CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter CNT matches the capture/compare register 1 (CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter CNT matches the capture/compare register 1 (CCR1). 0011: Toggle - OC1REF toggles when CNT=CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as CNT<CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as CNT>CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as CNT<CCR1 else active. In downcounting, channel 1 is active as long as CNT>CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=00 (the channel is configured in output). On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated."]
#[inline(always)]
pub fn oc1m(&self) -> Oc1mR {
Oc1mR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24 - Output compare 2 clear enable"]
#[inline(always)]
pub fn oc2ce(&self) -> Oc2ceR {
Oc2ceR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:26"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 25) & 3) as u8)
}
#[doc = "Bit 27 - Output compare 2 preload enable"]
#[inline(always)]
pub fn oc2pe(&self) -> Oc2peR {
Oc2peR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bits 28:31 - Output compare 2 mode"]
#[inline(always)]
pub fn oc2m(&self) -> Oc2mR {
Oc2mR::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
#[inline(always)]
#[must_use]
pub fn cc1s(&mut self) -> Cc1sW<Ccmr1Spec> {
Cc1sW::new(self, 0)
}
#[doc = "Bits 2:3 - Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events"]
#[inline(always)]
#[must_use]
pub fn ic1psc(&mut self) -> Ic1pscW<Ccmr1Spec> {
Ic1pscW::new(self, 2)
}
#[doc = "Bits 4:7 - Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8"]
#[inline(always)]
#[must_use]
pub fn ic1f(&mut self) -> Ic1fW<Ccmr1Spec> {
Ic1fW::new(self, 4)
}
#[doc = "Bits 8:9 - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (SMCR register)"]
#[inline(always)]
#[must_use]
pub fn cc2s(&mut self) -> Cc2sW<Ccmr1Spec> {
Cc2sW::new(self, 8)
}
#[doc = "Bits 10:11 - Input capture 2 prescaler"]
#[inline(always)]
#[must_use]
pub fn ic2psc(&mut self) -> Ic2pscW<Ccmr1Spec> {
Ic2pscW::new(self, 10)
}
#[doc = "Bits 12:15 - Input capture 2 filter"]
#[inline(always)]
#[must_use]
pub fn ic2f(&mut self) -> Ic2fW<Ccmr1Spec> {
Ic2fW::new(self, 12)
}
#[doc = "Bit 16 - Output compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input"]
#[inline(always)]
#[must_use]
pub fn oc1ce(&mut self) -> Oc1ceW<Ccmr1Spec> {
Oc1ceW::new(self, 16)
}
#[doc = "Bits 17:18"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Ccmr1Spec> {
Rsvd2W::new(self, 17)
}
#[doc = "Bit 19 - Output compare 1 preload enable 0: Preload register on CCR1 disabled. CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on CCR1 enabled. Read/Write operations access the preload register. CCR1 preload value is loaded in the active register at each update event. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=’00’ (the channel is configured in output)."]
#[inline(always)]
#[must_use]
pub fn oc1pe(&mut self) -> Oc1peW<Ccmr1Spec> {
Oc1peW::new(self, 19)
}
#[doc = "Bits 20:23 - Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register CCR1 and the counter CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter CNT matches the capture/compare register 1 (CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter CNT matches the capture/compare register 1 (CCR1). 0011: Toggle - OC1REF toggles when CNT=CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as CNT<CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as CNT>CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as CNT<CCR1 else active. In downcounting, channel 1 is active as long as CNT>CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=00 (the channel is configured in output). On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated."]
#[inline(always)]
#[must_use]
pub fn oc1m(&mut self) -> Oc1mW<Ccmr1Spec> {
Oc1mW::new(self, 20)
}
#[doc = "Bit 24 - Output compare 2 clear enable"]
#[inline(always)]
#[must_use]
pub fn oc2ce(&mut self) -> Oc2ceW<Ccmr1Spec> {
Oc2ceW::new(self, 24)
}
#[doc = "Bits 25:26"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccmr1Spec> {
RsvdW::new(self, 25)
}
#[doc = "Bit 27 - Output compare 2 preload enable"]
#[inline(always)]
#[must_use]
pub fn oc2pe(&mut self) -> Oc2peW<Ccmr1Spec> {
Oc2peW::new(self, 27)
}
#[doc = "Bits 28:31 - Output compare 2 mode"]
#[inline(always)]
#[must_use]
pub fn oc2m(&mut self) -> Oc2mW<Ccmr1Spec> {
Oc2mW::new(self, 28)
}
}
#[doc = "TIM capture/compare mode register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccmr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccmr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccmr1Spec;
impl crate::RegisterSpec for Ccmr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccmr1::R`](R) reader structure"]
impl crate::Readable for Ccmr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ccmr1::W`](W) writer structure"]
impl crate::Writable for Ccmr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCMR1 to value 0"]
impl crate::Resettable for Ccmr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCMR2 (rw) register accessor: TIM capture/compare mode register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccmr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccmr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccmr2`]
module"]
#[doc(alias = "CCMR2")]
pub type Ccmr2 = crate::Reg<ccmr2::Ccmr2Spec>;
#[doc = "TIM capture/compare mode register 2"]
pub mod ccmr2 {
#[doc = "Register `CCMR2` reader"]
pub type R = crate::R<Ccmr2Spec>;
#[doc = "Register `CCMR2` writer"]
pub type W = crate::W<Ccmr2Spec>;
#[doc = "Field `CC3S` reader - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
pub type Cc3sR = crate::FieldReader;
#[doc = "Field `CC3S` writer - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
pub type Cc3sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC3PSC` reader - Input capture 3 prescaler"]
pub type Ic3pscR = crate::FieldReader;
#[doc = "Field `IC3PSC` writer - Input capture 3 prescaler"]
pub type Ic3pscW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC3F` reader - Input capture 3 filter"]
pub type Ic3fR = crate::FieldReader;
#[doc = "Field `IC3F` writer - Input capture 3 filter"]
pub type Ic3fW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CC4S` reader - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
pub type Cc4sR = crate::FieldReader;
#[doc = "Field `CC4S` writer - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
pub type Cc4sW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC4PSC` reader - Input capture 4 prescaler"]
pub type Ic4pscR = crate::FieldReader;
#[doc = "Field `IC4PSC` writer - Input capture 4 prescaler"]
pub type Ic4pscW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IC4F` reader - Input capture 4 filter"]
pub type Ic4fR = crate::FieldReader;
#[doc = "Field `IC4F` writer - Input capture 4 filter"]
pub type Ic4fW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `OC3CE` reader - Output compare 3 clear enable"]
pub type Oc3ceR = crate::BitReader;
#[doc = "Field `OC3CE` writer - Output compare 3 clear enable"]
pub type Oc3ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OC3PE` reader - Output compare 3 preload enable"]
pub type Oc3peR = crate::BitReader;
#[doc = "Field `OC3PE` writer - Output compare 3 preload enable"]
pub type Oc3peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC3M` reader - Output compare 3 mode"]
pub type Oc3mR = crate::FieldReader;
#[doc = "Field `OC3M` writer - Output compare 3 mode"]
pub type Oc3mW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `OC4CE` reader - Output compare 4 clear enable"]
pub type Oc4ceR = crate::BitReader;
#[doc = "Field `OC4CE` writer - Output compare 4 clear enable"]
pub type Oc4ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OC4PE` reader - Output compare 4 preload enable"]
pub type Oc4peR = crate::BitReader;
#[doc = "Field `OC4PE` writer - Output compare 4 preload enable"]
pub type Oc4peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC4M` reader - Output compare 4 mode"]
pub type Oc4mR = crate::FieldReader;
#[doc = "Field `OC4M` writer - Output compare 4 mode"]
pub type Oc4mW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:1 - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
#[inline(always)]
pub fn cc3s(&self) -> Cc3sR {
Cc3sR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Input capture 3 prescaler"]
#[inline(always)]
pub fn ic3psc(&self) -> Ic3pscR {
Ic3pscR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7 - Input capture 3 filter"]
#[inline(always)]
pub fn ic3f(&self) -> Ic3fR {
Ic3fR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9 - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
#[inline(always)]
pub fn cc4s(&self) -> Cc4sR {
Cc4sR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Input capture 4 prescaler"]
#[inline(always)]
pub fn ic4psc(&self) -> Ic4pscR {
Ic4pscR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15 - Input capture 4 filter"]
#[inline(always)]
pub fn ic4f(&self) -> Ic4fR {
Ic4fR::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bit 16 - Output compare 3 clear enable"]
#[inline(always)]
pub fn oc3ce(&self) -> Oc3ceR {
Oc3ceR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bit 19 - Output compare 3 preload enable"]
#[inline(always)]
pub fn oc3pe(&self) -> Oc3peR {
Oc3peR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:23 - Output compare 3 mode"]
#[inline(always)]
pub fn oc3m(&self) -> Oc3mR {
Oc3mR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24 - Output compare 4 clear enable"]
#[inline(always)]
pub fn oc4ce(&self) -> Oc4ceR {
Oc4ceR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:26"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 25) & 3) as u8)
}
#[doc = "Bit 27 - Output compare 4 preload enable"]
#[inline(always)]
pub fn oc4pe(&self) -> Oc4peR {
Oc4peR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bits 28:31 - Output compare 4 mode"]
#[inline(always)]
pub fn oc4m(&self) -> Oc4mR {
Oc4mR::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
#[inline(always)]
#[must_use]
pub fn cc3s(&mut self) -> Cc3sW<Ccmr2Spec> {
Cc3sW::new(self, 0)
}
#[doc = "Bits 2:3 - Input capture 3 prescaler"]
#[inline(always)]
#[must_use]
pub fn ic3psc(&mut self) -> Ic3pscW<Ccmr2Spec> {
Ic3pscW::new(self, 2)
}
#[doc = "Bits 4:7 - Input capture 3 filter"]
#[inline(always)]
#[must_use]
pub fn ic3f(&mut self) -> Ic3fW<Ccmr2Spec> {
Ic3fW::new(self, 4)
}
#[doc = "Bits 8:9 - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register)"]
#[inline(always)]
#[must_use]
pub fn cc4s(&mut self) -> Cc4sW<Ccmr2Spec> {
Cc4sW::new(self, 8)
}
#[doc = "Bits 10:11 - Input capture 4 prescaler"]
#[inline(always)]
#[must_use]
pub fn ic4psc(&mut self) -> Ic4pscW<Ccmr2Spec> {
Ic4pscW::new(self, 10)
}
#[doc = "Bits 12:15 - Input capture 4 filter"]
#[inline(always)]
#[must_use]
pub fn ic4f(&mut self) -> Ic4fW<Ccmr2Spec> {
Ic4fW::new(self, 12)
}
#[doc = "Bit 16 - Output compare 3 clear enable"]
#[inline(always)]
#[must_use]
pub fn oc3ce(&mut self) -> Oc3ceW<Ccmr2Spec> {
Oc3ceW::new(self, 16)
}
#[doc = "Bits 17:18"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Ccmr2Spec> {
Rsvd2W::new(self, 17)
}
#[doc = "Bit 19 - Output compare 3 preload enable"]
#[inline(always)]
#[must_use]
pub fn oc3pe(&mut self) -> Oc3peW<Ccmr2Spec> {
Oc3peW::new(self, 19)
}
#[doc = "Bits 20:23 - Output compare 3 mode"]
#[inline(always)]
#[must_use]
pub fn oc3m(&mut self) -> Oc3mW<Ccmr2Spec> {
Oc3mW::new(self, 20)
}
#[doc = "Bit 24 - Output compare 4 clear enable"]
#[inline(always)]
#[must_use]
pub fn oc4ce(&mut self) -> Oc4ceW<Ccmr2Spec> {
Oc4ceW::new(self, 24)
}
#[doc = "Bits 25:26"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccmr2Spec> {
RsvdW::new(self, 25)
}
#[doc = "Bit 27 - Output compare 4 preload enable"]
#[inline(always)]
#[must_use]
pub fn oc4pe(&mut self) -> Oc4peW<Ccmr2Spec> {
Oc4peW::new(self, 27)
}
#[doc = "Bits 28:31 - Output compare 4 mode"]
#[inline(always)]
#[must_use]
pub fn oc4m(&mut self) -> Oc4mW<Ccmr2Spec> {
Oc4mW::new(self, 28)
}
}
#[doc = "TIM capture/compare mode register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccmr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccmr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccmr2Spec;
impl crate::RegisterSpec for Ccmr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccmr2::R`](R) reader structure"]
impl crate::Readable for Ccmr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ccmr2::W`](W) writer structure"]
impl crate::Writable for Ccmr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCMR2 to value 0"]
impl crate::Resettable for Ccmr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCER (rw) register accessor: Capture/Compare enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccer`]
module"]
#[doc(alias = "CCER")]
pub type Ccer = crate::Reg<ccer::CcerSpec>;
#[doc = "Capture/Compare enable register"]
pub mod ccer {
#[doc = "Register `CCER` reader"]
pub type R = crate::R<CcerSpec>;
#[doc = "Register `CCER` writer"]
pub type W = crate::W<CcerSpec>;
#[doc = "Field `CC1E` reader - Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (CCR1) or not. 0: Capture disabled. 1: Capture enabled. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
pub type Cc1eR = crate::BitReader;
#[doc = "Field `CC1E` writer - Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (CCR1) or not. 0: Capture disabled. 1: Capture enabled. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
pub type Cc1eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1P` reader - Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge. Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge. Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges. Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxP is not writable as soon as LOCK level 2 or 3 has been programmed."]
pub type Cc1pR = crate::BitReader;
#[doc = "Field `CC1P` writer - Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge. Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge. Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges. Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxP is not writable as soon as LOCK level 2 or 3 has been programmed."]
pub type Cc1pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1NE` reader - Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
pub type Cc1neR = crate::BitReader;
#[doc = "Field `CC1NE` writer - Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
pub type Cc1neW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1NP` reader - Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxNP is not writable as soon as LOCK level 2 or 3 has been programmed and CC1S=00 (channel configured as output)."]
pub type Cc1npR = crate::BitReader;
#[doc = "Field `CC1NP` writer - Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxNP is not writable as soon as LOCK level 2 or 3 has been programmed and CC1S=00 (channel configured as output)."]
pub type Cc1npW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2E` reader - Capture/Compare 2 output enable."]
pub type Cc2eR = crate::BitReader;
#[doc = "Field `CC2E` writer - Capture/Compare 2 output enable."]
pub type Cc2eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2P` reader - Capture/Compare 2 output Polarity."]
pub type Cc2pR = crate::BitReader;
#[doc = "Field `CC2P` writer - Capture/Compare 2 output Polarity."]
pub type Cc2pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2NE` reader - Capture/Compare 2 complementary output enable"]
pub type Cc2neR = crate::BitReader;
#[doc = "Field `CC2NE` writer - Capture/Compare 2 complementary output enable"]
pub type Cc2neW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2NP` reader - Capture/Compare 2 complementary output polarity"]
pub type Cc2npR = crate::BitReader;
#[doc = "Field `CC2NP` writer - Capture/Compare 2 complementary output polarity"]
pub type Cc2npW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3E` reader - Capture/Compare 3 output enable."]
pub type Cc3eR = crate::BitReader;
#[doc = "Field `CC3E` writer - Capture/Compare 3 output enable."]
pub type Cc3eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3P` reader - Capture/Compare 3 output Polarity."]
pub type Cc3pR = crate::BitReader;
#[doc = "Field `CC3P` writer - Capture/Compare 3 output Polarity."]
pub type Cc3pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3NE` reader - Capture/Compare 3 complementary output enable"]
pub type Cc3neR = crate::BitReader;
#[doc = "Field `CC3NE` writer - Capture/Compare 3 complementary output enable"]
pub type Cc3neW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3NP` reader - Capture/Compare 3 complementary output polarity"]
pub type Cc3npR = crate::BitReader;
#[doc = "Field `CC3NP` writer - Capture/Compare 3 complementary output polarity"]
pub type Cc3npW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4E` reader - Capture/Compare 4 output enable."]
pub type Cc4eR = crate::BitReader;
#[doc = "Field `CC4E` writer - Capture/Compare 4 output enable."]
pub type Cc4eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4P` reader - Capture/Compare 4 output Polarity."]
pub type Cc4pR = crate::BitReader;
#[doc = "Field `CC4P` writer - Capture/Compare 4 output Polarity."]
pub type Cc4pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC4NP` reader - Capture/Compare 4 complementary output polarity"]
pub type Cc4npR = crate::BitReader;
#[doc = "Field `CC4NP` writer - Capture/Compare 4 complementary output polarity"]
pub type Cc4npW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC5E` reader - Capture/Compare 5 output enable."]
pub type Cc5eR = crate::BitReader;
#[doc = "Field `CC5E` writer - Capture/Compare 5 output enable."]
pub type Cc5eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC5P` reader - Capture/Compare 5 output Polarity."]
pub type Cc5pR = crate::BitReader;
#[doc = "Field `CC5P` writer - Capture/Compare 5 output Polarity."]
pub type Cc5pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC6E` reader - Capture/Compare 6 output enable."]
pub type Cc6eR = crate::BitReader;
#[doc = "Field `CC6E` writer - Capture/Compare 6 output enable."]
pub type Cc6eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC6P` reader - Capture/Compare 6 output Polarity."]
pub type Cc6pR = crate::BitReader;
#[doc = "Field `CC6P` writer - Capture/Compare 6 output Polarity."]
pub type Cc6pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bit 0 - Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (CCR1) or not. 0: Capture disabled. 1: Capture enabled. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
#[inline(always)]
pub fn cc1e(&self) -> Cc1eR {
Cc1eR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge. Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge. Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges. Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxP is not writable as soon as LOCK level 2 or 3 has been programmed."]
#[inline(always)]
pub fn cc1p(&self) -> Cc1pR {
Cc1pR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
#[inline(always)]
pub fn cc1ne(&self) -> Cc1neR {
Cc1neR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxNP is not writable as soon as LOCK level 2 or 3 has been programmed and CC1S=00 (channel configured as output)."]
#[inline(always)]
pub fn cc1np(&self) -> Cc1npR {
Cc1npR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/Compare 2 output enable."]
#[inline(always)]
pub fn cc2e(&self) -> Cc2eR {
Cc2eR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Capture/Compare 2 output Polarity."]
#[inline(always)]
pub fn cc2p(&self) -> Cc2pR {
Cc2pR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Capture/Compare 2 complementary output enable"]
#[inline(always)]
pub fn cc2ne(&self) -> Cc2neR {
Cc2neR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Capture/Compare 2 complementary output polarity"]
#[inline(always)]
pub fn cc2np(&self) -> Cc2npR {
Cc2npR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Capture/Compare 3 output enable."]
#[inline(always)]
pub fn cc3e(&self) -> Cc3eR {
Cc3eR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Capture/Compare 3 output Polarity."]
#[inline(always)]
pub fn cc3p(&self) -> Cc3pR {
Cc3pR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Capture/Compare 3 complementary output enable"]
#[inline(always)]
pub fn cc3ne(&self) -> Cc3neR {
Cc3neR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture/Compare 3 complementary output polarity"]
#[inline(always)]
pub fn cc3np(&self) -> Cc3npR {
Cc3npR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Capture/Compare 4 output enable."]
#[inline(always)]
pub fn cc4e(&self) -> Cc4eR {
Cc4eR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Capture/Compare 4 output Polarity."]
#[inline(always)]
pub fn cc4p(&self) -> Cc4pR {
Cc4pR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Capture/Compare 4 complementary output polarity"]
#[inline(always)]
pub fn cc4np(&self) -> Cc4npR {
Cc4npR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Capture/Compare 5 output enable."]
#[inline(always)]
pub fn cc5e(&self) -> Cc5eR {
Cc5eR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Capture/Compare 5 output Polarity."]
#[inline(always)]
pub fn cc5p(&self) -> Cc5pR {
Cc5pR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Capture/Compare 6 output enable."]
#[inline(always)]
pub fn cc6e(&self) -> Cc6eR {
Cc6eR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Capture/Compare 6 output Polarity."]
#[inline(always)]
pub fn cc6p(&self) -> Cc6pR {
Cc6pR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (CCR1) or not. 0: Capture disabled. 1: Capture enabled. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
#[inline(always)]
#[must_use]
pub fn cc1e(&mut self) -> Cc1eW<CcerSpec> {
Cc1eW::new(self, 0)
}
#[doc = "Bit 1 - Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge. Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge. Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges. Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxP is not writable as soon as LOCK level 2 or 3 has been programmed."]
#[inline(always)]
#[must_use]
pub fn cc1p(&mut self) -> Cc1pW<CcerSpec> {
Cc1pW::new(self, 1)
}
#[doc = "Bit 2 - Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated."]
#[inline(always)]
#[must_use]
pub fn cc1ne(&mut self) -> Cc1neW<CcerSpec> {
Cc1neW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxNP is not writable as soon as LOCK level 2 or 3 has been programmed and CC1S=00 (channel configured as output)."]
#[inline(always)]
#[must_use]
pub fn cc1np(&mut self) -> Cc1npW<CcerSpec> {
Cc1npW::new(self, 3)
}
#[doc = "Bit 4 - Capture/Compare 2 output enable."]
#[inline(always)]
#[must_use]
pub fn cc2e(&mut self) -> Cc2eW<CcerSpec> {
Cc2eW::new(self, 4)
}
#[doc = "Bit 5 - Capture/Compare 2 output Polarity."]
#[inline(always)]
#[must_use]
pub fn cc2p(&mut self) -> Cc2pW<CcerSpec> {
Cc2pW::new(self, 5)
}
#[doc = "Bit 6 - Capture/Compare 2 complementary output enable"]
#[inline(always)]
#[must_use]
pub fn cc2ne(&mut self) -> Cc2neW<CcerSpec> {
Cc2neW::new(self, 6)
}
#[doc = "Bit 7 - Capture/Compare 2 complementary output polarity"]
#[inline(always)]
#[must_use]
pub fn cc2np(&mut self) -> Cc2npW<CcerSpec> {
Cc2npW::new(self, 7)
}
#[doc = "Bit 8 - Capture/Compare 3 output enable."]
#[inline(always)]
#[must_use]
pub fn cc3e(&mut self) -> Cc3eW<CcerSpec> {
Cc3eW::new(self, 8)
}
#[doc = "Bit 9 - Capture/Compare 3 output Polarity."]
#[inline(always)]
#[must_use]
pub fn cc3p(&mut self) -> Cc3pW<CcerSpec> {
Cc3pW::new(self, 9)
}
#[doc = "Bit 10 - Capture/Compare 3 complementary output enable"]
#[inline(always)]
#[must_use]
pub fn cc3ne(&mut self) -> Cc3neW<CcerSpec> {
Cc3neW::new(self, 10)
}
#[doc = "Bit 11 - Capture/Compare 3 complementary output polarity"]
#[inline(always)]
#[must_use]
pub fn cc3np(&mut self) -> Cc3npW<CcerSpec> {
Cc3npW::new(self, 11)
}
#[doc = "Bit 12 - Capture/Compare 4 output enable."]
#[inline(always)]
#[must_use]
pub fn cc4e(&mut self) -> Cc4eW<CcerSpec> {
Cc4eW::new(self, 12)
}
#[doc = "Bit 13 - Capture/Compare 4 output Polarity."]
#[inline(always)]
#[must_use]
pub fn cc4p(&mut self) -> Cc4pW<CcerSpec> {
Cc4pW::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CcerSpec> {
Rsvd4W::new(self, 14)
}
#[doc = "Bit 15 - Capture/Compare 4 complementary output polarity"]
#[inline(always)]
#[must_use]
pub fn cc4np(&mut self) -> Cc4npW<CcerSpec> {
Cc4npW::new(self, 15)
}
#[doc = "Bit 16 - Capture/Compare 5 output enable."]
#[inline(always)]
#[must_use]
pub fn cc5e(&mut self) -> Cc5eW<CcerSpec> {
Cc5eW::new(self, 16)
}
#[doc = "Bit 17 - Capture/Compare 5 output Polarity."]
#[inline(always)]
#[must_use]
pub fn cc5p(&mut self) -> Cc5pW<CcerSpec> {
Cc5pW::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CcerSpec> {
Rsvd3W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CcerSpec> {
Rsvd2W::new(self, 19)
}
#[doc = "Bit 20 - Capture/Compare 6 output enable."]
#[inline(always)]
#[must_use]
pub fn cc6e(&mut self) -> Cc6eW<CcerSpec> {
Cc6eW::new(self, 20)
}
#[doc = "Bit 21 - Capture/Compare 6 output Polarity."]
#[inline(always)]
#[must_use]
pub fn cc6p(&mut self) -> Cc6pW<CcerSpec> {
Cc6pW::new(self, 21)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CcerSpec> {
RsvdW::new(self, 22)
}
}
#[doc = "Capture/Compare enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcerSpec;
impl crate::RegisterSpec for CcerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccer::R`](R) reader structure"]
impl crate::Readable for CcerSpec {}
#[doc = "`write(|w| ..)` method takes [`ccer::W`](W) writer structure"]
impl crate::Writable for CcerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCER to value 0"]
impl crate::Resettable for CcerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "Counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - bit 30 to 0 is the lower bits of counter value bit 31 depends on IUFREMAP in CR1. If UIFREMAP = 1 this bit is a read-only copy of the UIF bit of the ISR register If UIFREMAP = 0 this bit is counter value bit 31"]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - bit 30 to 0 is the lower bits of counter value bit 31 depends on IUFREMAP in CR1. If UIFREMAP = 1 this bit is a read-only copy of the UIF bit of the ISR register If UIFREMAP = 0 this bit is counter value bit 31"]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - bit 30 to 0 is the lower bits of counter value bit 31 depends on IUFREMAP in CR1. If UIFREMAP = 1 this bit is a read-only copy of the UIF bit of the ISR register If UIFREMAP = 0 this bit is counter value bit 31"]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - bit 30 to 0 is the lower bits of counter value bit 31 depends on IUFREMAP in CR1. If UIFREMAP = 1 this bit is a read-only copy of the UIF bit of the ISR register If UIFREMAP = 0 this bit is counter value bit 31"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
}
#[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSC (rw) register accessor: Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`]
module"]
#[doc(alias = "PSC")]
pub type Psc = crate::Reg<psc::PscSpec>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub type R = crate::R<PscSpec>;
#[doc = "Register `PSC` writer"]
pub type W = crate::W<PscSpec>;
#[doc = "Field `PSC` reader - Prescaler value The counter clock frequency is fCLK/(PSC+1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscR = crate::FieldReader<u16>;
#[doc = "Field `PSC` writer - Prescaler value The counter clock frequency is fCLK/(PSC+1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is fCLK/(PSC+1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
pub fn psc(&self) -> PscR {
PscR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is fCLK/(PSC+1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PscW<PscSpec> {
PscW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PscSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PscSpec;
impl crate::RegisterSpec for PscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate::Readable for PscSpec {}
#[doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate::Writable for PscSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PscSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "Auto-reload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto-reload value ARR is the value to be loaded in the actual auto-reload register."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto-reload value ARR is the value to be loaded in the actual auto-reload register."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
}
#[doc = "Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RCR (rw) register accessor: Repetition counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcr`]
module"]
#[doc(alias = "RCR")]
pub type Rcr = crate::Reg<rcr::RcrSpec>;
#[doc = "Repetition counter register"]
pub mod rcr {
#[doc = "Register `RCR` reader"]
pub type R = crate::R<RcrSpec>;
#[doc = "Register `RCR` writer"]
pub type W = crate::W<RcrSpec>;
#[doc = "Field `REP` reader - Repetition counter value These bits allow the user to set-up the update rate of the compare registers when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event, any write to the RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode or the number of half PWM period in center-aligned mode.."]
pub type RepR = crate::FieldReader<u16>;
#[doc = "Field `REP` writer - Repetition counter value These bits allow the user to set-up the update rate of the compare registers when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event, any write to the RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode or the number of half PWM period in center-aligned mode.."]
pub type RepW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Repetition counter value These bits allow the user to set-up the update rate of the compare registers when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event, any write to the RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode or the number of half PWM period in center-aligned mode.."]
#[inline(always)]
pub fn rep(&self) -> RepR {
RepR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Repetition counter value These bits allow the user to set-up the update rate of the compare registers when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event, any write to the RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode or the number of half PWM period in center-aligned mode.."]
#[inline(always)]
#[must_use]
pub fn rep(&mut self) -> RepW<RcrSpec> {
RepW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RcrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Repetition counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RcrSpec;
impl crate::RegisterSpec for RcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rcr::R`](R) reader structure"]
impl crate::Readable for RcrSpec {}
#[doc = "`write(|w| ..)` method takes [`rcr::W`](W) writer structure"]
impl crate::Writable for RcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCR to value 0"]
impl crate::Resettable for RcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR1 (rw) register accessor: Capture/Compare register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`]
module"]
#[doc(alias = "CCR1")]
pub type Ccr1 = crate::Reg<ccr1::Ccr1Spec>;
#[doc = "Capture/Compare register 1"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub type R = crate::R<Ccr1Spec>;
#[doc = "Register `CCR1` writer"]
pub type W = crate::W<Ccr1Spec>;
#[doc = "Field `CCR1` reader - Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)."]
pub type Ccr1R = crate::FieldReader<u32>;
#[doc = "Field `CCR1` writer - Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)."]
pub type Ccr1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)."]
#[inline(always)]
pub fn ccr1(&self) -> Ccr1R {
Ccr1R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1)."]
#[inline(always)]
#[must_use]
pub fn ccr1(&mut self) -> Ccr1W<Ccr1Spec> {
Ccr1W::new(self, 0)
}
}
#[doc = "Capture/Compare register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr1Spec;
impl crate::RegisterSpec for Ccr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"]
impl crate::Readable for Ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"]
impl crate::Writable for Ccr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for Ccr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR2 (rw) register accessor: Capture/Compare register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`]
module"]
#[doc(alias = "CCR2")]
pub type Ccr2 = crate::Reg<ccr2::Ccr2Spec>;
#[doc = "Capture/Compare register 2"]
pub mod ccr2 {
#[doc = "Register `CCR2` reader"]
pub type R = crate::R<Ccr2Spec>;
#[doc = "Register `CCR2` writer"]
pub type W = crate::W<Ccr2Spec>;
#[doc = "Field `CCR2` reader - Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2)."]
pub type Ccr2R = crate::FieldReader<u32>;
#[doc = "Field `CCR2` writer - Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2)."]
pub type Ccr2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2)."]
#[inline(always)]
pub fn ccr2(&self) -> Ccr2R {
Ccr2R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2)."]
#[inline(always)]
#[must_use]
pub fn ccr2(&mut self) -> Ccr2W<Ccr2Spec> {
Ccr2W::new(self, 0)
}
}
#[doc = "Capture/Compare register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr2Spec;
impl crate::RegisterSpec for Ccr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"]
impl crate::Readable for Ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"]
impl crate::Writable for Ccr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR2 to value 0"]
impl crate::Resettable for Ccr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR3 (rw) register accessor: Capture/Compare register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr3`]
module"]
#[doc(alias = "CCR3")]
pub type Ccr3 = crate::Reg<ccr3::Ccr3Spec>;
#[doc = "Capture/Compare register 3"]
pub mod ccr3 {
#[doc = "Register `CCR3` reader"]
pub type R = crate::R<Ccr3Spec>;
#[doc = "Register `CCR3` writer"]
pub type W = crate::W<Ccr3Spec>;
#[doc = "Field `CCR3` reader - Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3)."]
pub type Ccr3R = crate::FieldReader<u32>;
#[doc = "Field `CCR3` writer - Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3)."]
pub type Ccr3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3)."]
#[inline(always)]
pub fn ccr3(&self) -> Ccr3R {
Ccr3R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3)."]
#[inline(always)]
#[must_use]
pub fn ccr3(&mut self) -> Ccr3W<Ccr3Spec> {
Ccr3W::new(self, 0)
}
}
#[doc = "Capture/Compare register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr3Spec;
impl crate::RegisterSpec for Ccr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr3::R`](R) reader structure"]
impl crate::Readable for Ccr3Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr3::W`](W) writer structure"]
impl crate::Writable for Ccr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR3 to value 0"]
impl crate::Resettable for Ccr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR4 (rw) register accessor: Capture/Compare register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr4`]
module"]
#[doc(alias = "CCR4")]
pub type Ccr4 = crate::Reg<ccr4::Ccr4Spec>;
#[doc = "Capture/Compare register 4"]
pub mod ccr4 {
#[doc = "Register `CCR4` reader"]
pub type R = crate::R<Ccr4Spec>;
#[doc = "Register `CCR4` writer"]
pub type W = crate::W<Ccr4Spec>;
#[doc = "Field `CCR4` reader - Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4)."]
pub type Ccr4R = crate::FieldReader<u32>;
#[doc = "Field `CCR4` writer - Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4)."]
pub type Ccr4W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4)."]
#[inline(always)]
pub fn ccr4(&self) -> Ccr4R {
Ccr4R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4)."]
#[inline(always)]
#[must_use]
pub fn ccr4(&mut self) -> Ccr4W<Ccr4Spec> {
Ccr4W::new(self, 0)
}
}
#[doc = "Capture/Compare register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr4Spec;
impl crate::RegisterSpec for Ccr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr4::R`](R) reader structure"]
impl crate::Readable for Ccr4Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr4::W`](W) writer structure"]
impl crate::Writable for Ccr4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR4 to value 0"]
impl crate::Resettable for Ccr4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BDTR (rw) register accessor: TIM break and dead-time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtr`]
module"]
#[doc(alias = "BDTR")]
pub type Bdtr = crate::Reg<bdtr::BdtrSpec>;
#[doc = "TIM break and dead-time register"]
pub mod bdtr {
#[doc = "Register `BDTR` reader"]
pub type R = crate::R<BdtrSpec>;
#[doc = "Register `BDTR` writer"]
pub type W = crate::W<BdtrSpec>;
#[doc = "Field `DTG` reader - Dead-time generator setup This bit-field, together with DTPSC, defines the duration of the dead-time inserted between the complementary outputs. If DTG=0, dead-time is disabled. Example if tCLK=8.33ns (120MHz), dead-time possible values are: 16.67ns to 8533.33 ns by 8.33 ns steps if DTPSC=0, 266.67ns to 136.53 us by 133.33 ns steps if DTPSC=1 This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type DtgR = crate::FieldReader<u16>;
#[doc = "Field `DTG` writer - Dead-time generator setup This bit-field, together with DTPSC, defines the duration of the dead-time inserted between the complementary outputs. If DTG=0, dead-time is disabled. Example if tCLK=8.33ns (120MHz), dead-time possible values are: 16.67ns to 8533.33 ns by 8.33 ns steps if DTPSC=0, 266.67ns to 136.53 us by 133.33 ns steps if DTPSC=1 This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type DtgW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DTPSC` reader - Dead-time prescaler This bit-field enables dead-time prescaler. 0: dead-time is tCLK*(DTG+1) if DTG is not zero 1: dead-time is tCLK*(DTG+1)*16 if DTG is not zero This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type DtpscR = crate::BitReader;
#[doc = "Field `DTPSC` writer - Dead-time prescaler This bit-field enables dead-time prescaler. 0: dead-time is tCLK*(DTG+1) if DTG is not zero 1: dead-time is tCLK*(DTG+1)*16 if DTG is not zero This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type DtpscW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKE` reader - Break enable This bit enables the complete break protection. 0: Break function disabled 1: Break function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkeR = crate::BitReader;
#[doc = "Field `BKE` writer - Break enable This bit enables the complete break protection. 0: Break function disabled 1: Break function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKP` reader - Break polarity 0: Break input BRK is active low 1: Break input BRK is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkpR = crate::BitReader;
#[doc = "Field `BKP` writer - Break polarity 0: Break input BRK is active low 1: Break input BRK is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AOE` reader - Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type AoeR = crate::BitReader;
#[doc = "Field `AOE` writer - Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type AoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MOE` reader - Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in CCER register)."]
pub type MoeR = crate::BitReader;
#[doc = "Field `MOE` writer - Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in CCER register)."]
pub type MoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKF` reader - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkfR = crate::FieldReader;
#[doc = "Field `BKF` writer - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkfW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `BK2F` reader - Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2fR = crate::FieldReader;
#[doc = "Field `BK2F` writer - Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2fW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `BK2E` reader - Break 2 enable This bit enables the complete break 2 protection. 0: Break2 function disabled 1: Break2 function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2eR = crate::BitReader;
#[doc = "Field `BK2E` writer - Break 2 enable This bit enables the complete break 2 protection. 0: Break2 function disabled 1: Break2 function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BK2P` reader - BK2P: Break 2 polarity 0: Break input BRK2 is active low 1: Break input BRK2 is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2pR = crate::BitReader;
#[doc = "Field `BK2P` writer - BK2P: Break 2 polarity 0: Break input BRK2 is active low 1: Break input BRK2 is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKDSRM` reader - Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared."]
pub type BkdsrmR = crate::BitReader;
#[doc = "Field `BKDSRM` writer - Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared."]
pub type BkdsrmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BK2DSRM` reader - Break2 Disarm"]
pub type Bk2dsrmR = crate::BitReader;
#[doc = "Field `BK2DSRM` writer - Break2 Disarm"]
pub type Bk2dsrmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKBID` reader - Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in BDTR register)."]
pub type BkbidR = crate::BitReader;
#[doc = "Field `BKBID` writer - Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in BDTR register)."]
pub type BkbidW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BK2BID` reader - Break2 bidirectional"]
pub type Bk2bidR = crate::BitReader;
#[doc = "Field `BK2BID` writer - Break2 bidirectional"]
pub type Bk2bidW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OSSI` reader - Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, imposes a Hi-Z state). 1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. This bit can not be modified as soon as the LOCK level 2 has been programmed."]
pub type OssiR = crate::BitReader;
#[doc = "Field `OSSI` writer - Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, imposes a Hi-Z state). 1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. This bit can not be modified as soon as the LOCK level 2 has been programmed."]
pub type OssiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OSSR` reader - Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, forces a Hi-Z state). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). This bit can not be modified as soon as the LOCK level 2 has been programmed."]
pub type OssrR = crate::BitReader;
#[doc = "Field `OSSR` writer - Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, forces a Hi-Z state). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). This bit can not be modified as soon as the LOCK level 2 has been programmed."]
pub type OssrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9 - Dead-time generator setup This bit-field, together with DTPSC, defines the duration of the dead-time inserted between the complementary outputs. If DTG=0, dead-time is disabled. Example if tCLK=8.33ns (120MHz), dead-time possible values are: 16.67ns to 8533.33 ns by 8.33 ns steps if DTPSC=0, 266.67ns to 136.53 us by 133.33 ns steps if DTPSC=1 This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn dtg(&self) -> DtgR {
DtgR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Dead-time prescaler This bit-field enables dead-time prescaler. 0: dead-time is tCLK*(DTG+1) if DTG is not zero 1: dead-time is tCLK*(DTG+1)*16 if DTG is not zero This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn dtpsc(&self) -> DtpscR {
DtpscR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Break enable This bit enables the complete break protection. 0: Break function disabled 1: Break function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bke(&self) -> BkeR {
BkeR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Break polarity 0: Break input BRK is active low 1: Break input BRK is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn aoe(&self) -> AoeR {
AoeR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in CCER register)."]
#[inline(always)]
pub fn moe(&self) -> MoeR {
MoeR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:19 - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkf(&self) -> BkfR {
BkfR::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23 - Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2f(&self) -> Bk2fR {
Bk2fR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24 - Break 2 enable This bit enables the complete break 2 protection. 0: Break2 function disabled 1: Break2 function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2e(&self) -> Bk2eR {
Bk2eR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - BK2P: Break 2 polarity 0: Break input BRK2 is active low 1: Break input BRK2 is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2p(&self) -> Bk2pR {
Bk2pR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared."]
#[inline(always)]
pub fn bkdsrm(&self) -> BkdsrmR {
BkdsrmR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Break2 Disarm"]
#[inline(always)]
pub fn bk2dsrm(&self) -> Bk2dsrmR {
Bk2dsrmR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in BDTR register)."]
#[inline(always)]
pub fn bkbid(&self) -> BkbidR {
BkbidR::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - Break2 bidirectional"]
#[inline(always)]
pub fn bk2bid(&self) -> Bk2bidR {
Bk2bidR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, imposes a Hi-Z state). 1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. This bit can not be modified as soon as the LOCK level 2 has been programmed."]
#[inline(always)]
pub fn ossi(&self) -> OssiR {
OssiR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, forces a Hi-Z state). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). This bit can not be modified as soon as the LOCK level 2 has been programmed."]
#[inline(always)]
pub fn ossr(&self) -> OssrR {
OssrR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:9 - Dead-time generator setup This bit-field, together with DTPSC, defines the duration of the dead-time inserted between the complementary outputs. If DTG=0, dead-time is disabled. Example if tCLK=8.33ns (120MHz), dead-time possible values are: 16.67ns to 8533.33 ns by 8.33 ns steps if DTPSC=0, 266.67ns to 136.53 us by 133.33 ns steps if DTPSC=1 This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn dtg(&mut self) -> DtgW<BdtrSpec> {
DtgW::new(self, 0)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BdtrSpec> {
RsvdW::new(self, 10)
}
#[doc = "Bit 11 - Dead-time prescaler This bit-field enables dead-time prescaler. 0: dead-time is tCLK*(DTG+1) if DTG is not zero 1: dead-time is tCLK*(DTG+1)*16 if DTG is not zero This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn dtpsc(&mut self) -> DtpscW<BdtrSpec> {
DtpscW::new(self, 11)
}
#[doc = "Bit 12 - Break enable This bit enables the complete break protection. 0: Break function disabled 1: Break function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bke(&mut self) -> BkeW<BdtrSpec> {
BkeW::new(self, 12)
}
#[doc = "Bit 13 - Break polarity 0: Break input BRK is active low 1: Break input BRK is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<BdtrSpec> {
BkpW::new(self, 13)
}
#[doc = "Bit 14 - Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn aoe(&mut self) -> AoeW<BdtrSpec> {
AoeW::new(self, 14)
}
#[doc = "Bit 15 - Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in CCER register)."]
#[inline(always)]
#[must_use]
pub fn moe(&mut self) -> MoeW<BdtrSpec> {
MoeW::new(self, 15)
}
#[doc = "Bits 16:19 - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkf(&mut self) -> BkfW<BdtrSpec> {
BkfW::new(self, 16)
}
#[doc = "Bits 20:23 - Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2f(&mut self) -> Bk2fW<BdtrSpec> {
Bk2fW::new(self, 20)
}
#[doc = "Bit 24 - Break 2 enable This bit enables the complete break 2 protection. 0: Break2 function disabled 1: Break2 function enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2e(&mut self) -> Bk2eW<BdtrSpec> {
Bk2eW::new(self, 24)
}
#[doc = "Bit 25 - BK2P: Break 2 polarity 0: Break input BRK2 is active low 1: Break input BRK2 is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2p(&mut self) -> Bk2pW<BdtrSpec> {
Bk2pW::new(self, 25)
}
#[doc = "Bit 26 - Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared."]
#[inline(always)]
#[must_use]
pub fn bkdsrm(&mut self) -> BkdsrmW<BdtrSpec> {
BkdsrmW::new(self, 26)
}
#[doc = "Bit 27 - Break2 Disarm"]
#[inline(always)]
#[must_use]
pub fn bk2dsrm(&mut self) -> Bk2dsrmW<BdtrSpec> {
Bk2dsrmW::new(self, 27)
}
#[doc = "Bit 28 - Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in BDTR register)."]
#[inline(always)]
#[must_use]
pub fn bkbid(&mut self) -> BkbidW<BdtrSpec> {
BkbidW::new(self, 28)
}
#[doc = "Bit 29 - Break2 bidirectional"]
#[inline(always)]
#[must_use]
pub fn bk2bid(&mut self) -> Bk2bidW<BdtrSpec> {
Bk2bidW::new(self, 29)
}
#[doc = "Bit 30 - Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, imposes a Hi-Z state). 1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. This bit can not be modified as soon as the LOCK level 2 has been programmed."]
#[inline(always)]
#[must_use]
pub fn ossi(&mut self) -> OssiW<BdtrSpec> {
OssiW::new(self, 30)
}
#[doc = "Bit 31 - Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, forces a Hi-Z state). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). This bit can not be modified as soon as the LOCK level 2 has been programmed."]
#[inline(always)]
#[must_use]
pub fn ossr(&mut self) -> OssrW<BdtrSpec> {
OssrW::new(self, 31)
}
}
#[doc = "TIM break and dead-time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bdtr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bdtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BdtrSpec;
impl crate::RegisterSpec for BdtrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bdtr::R`](R) reader structure"]
impl crate::Readable for BdtrSpec {}
#[doc = "`write(|w| ..)` method takes [`bdtr::W`](W) writer structure"]
impl crate::Writable for BdtrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BDTR to value 0"]
impl crate::Resettable for BdtrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCMR3 (rw) register accessor: TIM capture/compare mode register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccmr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccmr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccmr3`]
module"]
#[doc(alias = "CCMR3")]
pub type Ccmr3 = crate::Reg<ccmr3::Ccmr3Spec>;
#[doc = "TIM capture/compare mode register 3"]
pub mod ccmr3 {
#[doc = "Register `CCMR3` reader"]
pub type R = crate::R<Ccmr3Spec>;
#[doc = "Register `CCMR3` writer"]
pub type W = crate::W<Ccmr3Spec>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader<u16>;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `GC5C1` reader - Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
pub type Gc5c1R = crate::BitReader;
#[doc = "Field `GC5C1` writer - Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
pub type Gc5c1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GC5C2` reader - Group Channel 5 and Channel 2 Distortion on Channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
pub type Gc5c2R = crate::BitReader;
#[doc = "Field `GC5C2` writer - Group Channel 5 and Channel 2 Distortion on Channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
pub type Gc5c2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GC5C3` reader - Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2)."]
pub type Gc5c3R = crate::BitReader;
#[doc = "Field `GC5C3` writer - Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2)."]
pub type Gc5c3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC5CE` reader - Output compare 5 clear enable"]
pub type Oc5ceR = crate::BitReader;
#[doc = "Field `OC5CE` writer - Output compare 5 clear enable"]
pub type Oc5ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OC5PE` reader - Output compare 5 preload enable"]
pub type Oc5peR = crate::BitReader;
#[doc = "Field `OC5PE` writer - Output compare 5 preload enable"]
pub type Oc5peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC5M` reader - Output compare 5 mode"]
pub type Oc5mR = crate::FieldReader;
#[doc = "Field `OC5M` writer - Output compare 5 mode"]
pub type Oc5mW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `OC6CE` reader - Output compare 6 clear enable"]
pub type Oc6ceR = crate::BitReader;
#[doc = "Field `OC6CE` writer - Output compare 6 clear enable"]
pub type Oc6ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OC6PE` reader - Output compare 6 preload enable"]
pub type Oc6peR = crate::BitReader;
#[doc = "Field `OC6PE` writer - Output compare 6 preload enable"]
pub type Oc6peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC6M` reader - Output compare 6 mode"]
pub type Oc6mR = crate::FieldReader;
#[doc = "Field `OC6M` writer - Output compare 6 mode"]
pub type Oc6mW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:12"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bit 13 - Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
#[inline(always)]
pub fn gc5c1(&self) -> Gc5c1R {
Gc5c1R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Group Channel 5 and Channel 2 Distortion on Channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
#[inline(always)]
pub fn gc5c2(&self) -> Gc5c2R {
Gc5c2R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2)."]
#[inline(always)]
pub fn gc5c3(&self) -> Gc5c3R {
Gc5c3R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Output compare 5 clear enable"]
#[inline(always)]
pub fn oc5ce(&self) -> Oc5ceR {
Oc5ceR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bit 19 - Output compare 5 preload enable"]
#[inline(always)]
pub fn oc5pe(&self) -> Oc5peR {
Oc5peR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:23 - Output compare 5 mode"]
#[inline(always)]
pub fn oc5m(&self) -> Oc5mR {
Oc5mR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24 - Output compare 6 clear enable"]
#[inline(always)]
pub fn oc6ce(&self) -> Oc6ceR {
Oc6ceR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:26"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 25) & 3) as u8)
}
#[doc = "Bit 27 - Output compare 6 preload enable"]
#[inline(always)]
pub fn oc6pe(&self) -> Oc6peR {
Oc6peR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bits 28:31 - Output compare 6 mode"]
#[inline(always)]
pub fn oc6m(&self) -> Oc6mR {
Oc6mR::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:12"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Ccmr3Spec> {
Rsvd3W::new(self, 0)
}
#[doc = "Bit 13 - Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
#[inline(always)]
#[must_use]
pub fn gc5c1(&mut self) -> Gc5c1W<Ccmr3Spec> {
Gc5c1W::new(self, 13)
}
#[doc = "Bit 14 - Group Channel 5 and Channel 2 Distortion on Channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1)."]
#[inline(always)]
#[must_use]
pub fn gc5c2(&mut self) -> Gc5c2W<Ccmr3Spec> {
Gc5c2W::new(self, 14)
}
#[doc = "Bit 15 - Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2)."]
#[inline(always)]
#[must_use]
pub fn gc5c3(&mut self) -> Gc5c3W<Ccmr3Spec> {
Gc5c3W::new(self, 15)
}
#[doc = "Bit 16 - Output compare 5 clear enable"]
#[inline(always)]
#[must_use]
pub fn oc5ce(&mut self) -> Oc5ceW<Ccmr3Spec> {
Oc5ceW::new(self, 16)
}
#[doc = "Bits 17:18"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Ccmr3Spec> {
Rsvd2W::new(self, 17)
}
#[doc = "Bit 19 - Output compare 5 preload enable"]
#[inline(always)]
#[must_use]
pub fn oc5pe(&mut self) -> Oc5peW<Ccmr3Spec> {
Oc5peW::new(self, 19)
}
#[doc = "Bits 20:23 - Output compare 5 mode"]
#[inline(always)]
#[must_use]
pub fn oc5m(&mut self) -> Oc5mW<Ccmr3Spec> {
Oc5mW::new(self, 20)
}
#[doc = "Bit 24 - Output compare 6 clear enable"]
#[inline(always)]
#[must_use]
pub fn oc6ce(&mut self) -> Oc6ceW<Ccmr3Spec> {
Oc6ceW::new(self, 24)
}
#[doc = "Bits 25:26"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccmr3Spec> {
RsvdW::new(self, 25)
}
#[doc = "Bit 27 - Output compare 6 preload enable"]
#[inline(always)]
#[must_use]
pub fn oc6pe(&mut self) -> Oc6peW<Ccmr3Spec> {
Oc6peW::new(self, 27)
}
#[doc = "Bits 28:31 - Output compare 6 mode"]
#[inline(always)]
#[must_use]
pub fn oc6m(&mut self) -> Oc6mW<Ccmr3Spec> {
Oc6mW::new(self, 28)
}
}
#[doc = "TIM capture/compare mode register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccmr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccmr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccmr3Spec;
impl crate::RegisterSpec for Ccmr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccmr3::R`](R) reader structure"]
impl crate::Readable for Ccmr3Spec {}
#[doc = "`write(|w| ..)` method takes [`ccmr3::W`](W) writer structure"]
impl crate::Writable for Ccmr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCMR3 to value 0"]
impl crate::Resettable for Ccmr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR5 (rw) register accessor: Capture/Compare register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr5`]
module"]
#[doc(alias = "CCR5")]
pub type Ccr5 = crate::Reg<ccr5::Ccr5Spec>;
#[doc = "Capture/Compare register 5"]
pub mod ccr5 {
#[doc = "Register `CCR5` reader"]
pub type R = crate::R<Ccr5Spec>;
#[doc = "Register `CCR5` writer"]
pub type W = crate::W<Ccr5Spec>;
#[doc = "Field `CCR5` reader - Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC5 output."]
pub type Ccr5R = crate::FieldReader<u32>;
#[doc = "Field `CCR5` writer - Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC5 output."]
pub type Ccr5W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC5 output."]
#[inline(always)]
pub fn ccr5(&self) -> Ccr5R {
Ccr5R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC5 output."]
#[inline(always)]
#[must_use]
pub fn ccr5(&mut self) -> Ccr5W<Ccr5Spec> {
Ccr5W::new(self, 0)
}
}
#[doc = "Capture/Compare register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr5Spec;
impl crate::RegisterSpec for Ccr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr5::R`](R) reader structure"]
impl crate::Readable for Ccr5Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr5::W`](W) writer structure"]
impl crate::Writable for Ccr5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR5 to value 0"]
impl crate::Resettable for Ccr5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR6 (rw) register accessor: Capture/Compare register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr6`]
module"]
#[doc(alias = "CCR6")]
pub type Ccr6 = crate::Reg<ccr6::Ccr6Spec>;
#[doc = "Capture/Compare register 6"]
pub mod ccr6 {
#[doc = "Register `CCR6` reader"]
pub type R = crate::R<Ccr6Spec>;
#[doc = "Register `CCR6` writer"]
pub type W = crate::W<Ccr6Spec>;
#[doc = "Field `CCR6` reader - Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC6 output."]
pub type Ccr6R = crate::FieldReader<u32>;
#[doc = "Field `CCR6` writer - Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC6 output."]
pub type Ccr6W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC6 output."]
#[inline(always)]
pub fn ccr6(&self) -> Ccr6R {
Ccr6R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC6 output."]
#[inline(always)]
#[must_use]
pub fn ccr6(&mut self) -> Ccr6W<Ccr6Spec> {
Ccr6W::new(self, 0)
}
}
#[doc = "Capture/Compare register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr6Spec;
impl crate::RegisterSpec for Ccr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr6::R`](R) reader structure"]
impl crate::Readable for Ccr6Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr6::W`](W) writer structure"]
impl crate::Writable for Ccr6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR6 to value 0"]
impl crate::Resettable for Ccr6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AF1 (rw) register accessor: Alternate function option register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af1`]
module"]
#[doc(alias = "AF1")]
pub type Af1 = crate::Reg<af1::Af1Spec>;
#[doc = "Alternate function option register"]
pub mod af1 {
#[doc = "Register `AF1` reader"]
pub type R = crate::R<Af1Spec>;
#[doc = "Register `AF1` writer"]
pub type W = crate::W<Af1Spec>;
#[doc = "Field `BKINE` reader - BRK BKIN input enable This bit enables the BKIN input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkineR = crate::BitReader;
#[doc = "Field `BKINE` writer - BRK BKIN input enable This bit enables the BKIN input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkineW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKCMP1E` reader - BRK LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output1 is ‘ORed’ with the other BRK sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp1eR = crate::BitReader;
#[doc = "Field `BKCMP1E` writer - BRK LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output1 is ‘ORed’ with the other BRK sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp1eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKCMP2E` reader - BRK LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output2 is ‘ORed’ with the other BRK sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp2eR = crate::BitReader;
#[doc = "Field `BKCMP2E` writer - BRK LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output2 is ‘ORed’ with the other BRK sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp2eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `BKINP` reader - BRK BKIN input polarity This bit selects the BKIN input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkinpR = crate::BitReader;
#[doc = "Field `BKINP` writer - BRK BKIN input polarity This bit selects the BKIN input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type BkinpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKCMP1P` reader - BRK LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp1pR = crate::BitReader;
#[doc = "Field `BKCMP1P` writer - BRK LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp1pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKCMP2P` reader - BRK LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp2pR = crate::BitReader;
#[doc = "Field `BKCMP2P` writer - BRK LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bkcmp2pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ETRSEL` reader - ETR source selection 00: ETR input is connected to I/O 01: LPCOMP output1 (if LPCOMP integrated) 10: LPCOMP output2 (if LPCOMP integrated) 11: ETR input is connected to I/O This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type EtrselR = crate::FieldReader;
#[doc = "Field `ETRSEL` writer - ETR source selection 00: ETR input is connected to I/O 01: LPCOMP output1 (if LPCOMP integrated) 10: LPCOMP output2 (if LPCOMP integrated) 11: ETR input is connected to I/O This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type EtrselW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `LOCK` reader - Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = OISx and OISxN bits in CR2 register, BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F\\[3:0\\], BKF\\[3:0\\], AOE, BKP, BKE, OSSI, OSSR, DTPSC and DTG bits in BDTR register, AF1 register and AF2 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. The LOCK bits can be written to non-zero only once after reset."]
pub type LockR = crate::FieldReader;
#[doc = "Field `LOCK` writer - Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = OISx and OISxN bits in CR2 register, BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F\\[3:0\\], BKF\\[3:0\\], AOE, BKP, BKE, OSSI, OSSR, DTPSC and DTG bits in BDTR register, AF1 register and AF2 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. The LOCK bits can be written to non-zero only once after reset."]
pub type LockW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bit 0 - BRK BKIN input enable This bit enables the BKIN input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkine(&self) -> BkineR {
BkineR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - BRK LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output1 is ‘ORed’ with the other BRK sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkcmp1e(&self) -> Bkcmp1eR {
Bkcmp1eR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - BRK LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output2 is ‘ORed’ with the other BRK sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkcmp2e(&self) -> Bkcmp2eR {
Bkcmp2eR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:8"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 3) & 0x3f) as u8)
}
#[doc = "Bit 9 - BRK BKIN input polarity This bit selects the BKIN input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkinp(&self) -> BkinpR {
BkinpR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - BRK LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkcmp1p(&self) -> Bkcmp1pR {
Bkcmp1pR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - BRK LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bkcmp2p(&self) -> Bkcmp2pR {
Bkcmp2pR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - ETR source selection 00: ETR input is connected to I/O 01: LPCOMP output1 (if LPCOMP integrated) 10: LPCOMP output2 (if LPCOMP integrated) 11: ETR input is connected to I/O This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn etrsel(&self) -> EtrselR {
EtrselR::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:29"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0x3fff) as u16)
}
#[doc = "Bits 30:31 - Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = OISx and OISxN bits in CR2 register, BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F\\[3:0\\], BKF\\[3:0\\], AOE, BKP, BKE, OSSI, OSSR, DTPSC and DTG bits in BDTR register, AF1 register and AF2 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. The LOCK bits can be written to non-zero only once after reset."]
#[inline(always)]
pub fn lock(&self) -> LockR {
LockR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - BRK BKIN input enable This bit enables the BKIN input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkine(&mut self) -> BkineW<Af1Spec> {
BkineW::new(self, 0)
}
#[doc = "Bit 1 - BRK LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output1 is ‘ORed’ with the other BRK sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkcmp1e(&mut self) -> Bkcmp1eW<Af1Spec> {
Bkcmp1eW::new(self, 1)
}
#[doc = "Bit 2 - BRK LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK input. LPCOMP output2 is ‘ORed’ with the other BRK sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkcmp2e(&mut self) -> Bkcmp2eW<Af1Spec> {
Bkcmp2eW::new(self, 2)
}
#[doc = "Bits 3:8"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Af1Spec> {
Rsvd3W::new(self, 3)
}
#[doc = "Bit 9 - BRK BKIN input polarity This bit selects the BKIN input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkinp(&mut self) -> BkinpW<Af1Spec> {
BkinpW::new(self, 9)
}
#[doc = "Bit 10 - BRK LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkcmp1p(&mut self) -> Bkcmp1pW<Af1Spec> {
Bkcmp1pW::new(self, 10)
}
#[doc = "Bit 11 - BRK LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bkcmp2p(&mut self) -> Bkcmp2pW<Af1Spec> {
Bkcmp2pW::new(self, 11)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Af1Spec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bits 14:15 - ETR source selection 00: ETR input is connected to I/O 01: LPCOMP output1 (if LPCOMP integrated) 10: LPCOMP output2 (if LPCOMP integrated) 11: ETR input is connected to I/O This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn etrsel(&mut self) -> EtrselW<Af1Spec> {
EtrselW::new(self, 14)
}
#[doc = "Bits 16:29"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Af1Spec> {
RsvdW::new(self, 16)
}
#[doc = "Bits 30:31 - Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = OISx and OISxN bits in CR2 register, BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F\\[3:0\\], BKF\\[3:0\\], AOE, BKP, BKE, OSSI, OSSR, DTPSC and DTG bits in BDTR register, AF1 register and AF2 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. The LOCK bits can be written to non-zero only once after reset."]
#[inline(always)]
#[must_use]
pub fn lock(&mut self) -> LockW<Af1Spec> {
LockW::new(self, 30)
}
}
#[doc = "Alternate function option register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Af1Spec;
impl crate::RegisterSpec for Af1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`af1::R`](R) reader structure"]
impl crate::Readable for Af1Spec {}
#[doc = "`write(|w| ..)` method takes [`af1::W`](W) writer structure"]
impl crate::Writable for Af1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AF1 to value 0x01"]
impl crate::Resettable for Af1Spec {
const RESET_VALUE: u32 = 0x01;
}
}
#[doc = "AF2 (rw) register accessor: Alternate function option register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af2`]
module"]
#[doc(alias = "AF2")]
pub type Af2 = crate::Reg<af2::Af2Spec>;
#[doc = "Alternate function option register 2"]
pub mod af2 {
#[doc = "Register `AF2` reader"]
pub type R = crate::R<Af2Spec>;
#[doc = "Register `AF2` writer"]
pub type W = crate::W<Af2Spec>;
#[doc = "Field `BK2INE` reader - BRK2 BKIN input enable This bit enables the BKIN2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2ineR = crate::BitReader;
#[doc = "Field `BK2INE` writer - BRK2 BKIN input enable This bit enables the BKIN2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2ineW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BK2CMP1E` reader - BRK2 LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output1 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp1eR = crate::BitReader;
#[doc = "Field `BK2CMP1E` writer - BRK2 LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output1 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp1eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BK2CMP2E` reader - BRK2 LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output2 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp2eR = crate::BitReader;
#[doc = "Field `BK2CMP2E` writer - BRK2 LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output2 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp2eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `BK2INP` reader - BRK2 BKIN2 input polarity This bit selects the BKIN2 input sensitivity. It must be programmed together with the BK2P polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2inpR = crate::BitReader;
#[doc = "Field `BK2INP` writer - BRK2 BKIN2 input polarity This bit selects the BKIN2 input sensitivity. It must be programmed together with the BK2P polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2inpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BK2CMP1P` reader - BRK2 LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp1pR = crate::BitReader;
#[doc = "Field `BK2CMP1P` writer - BRK2 LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp1pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BK2CMP2P` reader - BRK2 LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp2pR = crate::BitReader;
#[doc = "Field `BK2CMP2P` writer - BRK2 LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
pub type Bk2cmp2pW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
impl R {
#[doc = "Bit 0 - BRK2 BKIN input enable This bit enables the BKIN2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2ine(&self) -> Bk2ineR {
Bk2ineR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - BRK2 LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output1 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2cmp1e(&self) -> Bk2cmp1eR {
Bk2cmp1eR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - BRK2 LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output2 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2cmp2e(&self) -> Bk2cmp2eR {
Bk2cmp2eR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 3) & 0x3f) as u8)
}
#[doc = "Bit 9 - BRK2 BKIN2 input polarity This bit selects the BKIN2 input sensitivity. It must be programmed together with the BK2P polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2inp(&self) -> Bk2inpR {
Bk2inpR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - BRK2 LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2cmp1p(&self) -> Bk2cmp1pR {
Bk2cmp1pR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - BRK2 LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
pub fn bk2cmp2p(&self) -> Bk2cmp2pR {
Bk2cmp2pR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 12) & 0x000f_ffff)
}
}
impl W {
#[doc = "Bit 0 - BRK2 BKIN input enable This bit enables the BKIN2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2ine(&mut self) -> Bk2ineW<Af2Spec> {
Bk2ineW::new(self, 0)
}
#[doc = "Bit 1 - BRK2 LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output1 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2cmp1e(&mut self) -> Bk2cmp1eW<Af2Spec> {
Bk2cmp1eW::new(self, 1)
}
#[doc = "Bit 2 - BRK2 LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer’s BRK2 input. LPCOMP output2 is ‘ORed’ with the other BRK2 sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2cmp2e(&mut self) -> Bk2cmp2eW<Af2Spec> {
Bk2cmp2eW::new(self, 2)
}
#[doc = "Bits 3:8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Af2Spec> {
Rsvd2W::new(self, 3)
}
#[doc = "Bit 9 - BRK2 BKIN2 input polarity This bit selects the BKIN2 input sensitivity. It must be programmed together with the BK2P polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2inp(&mut self) -> Bk2inpW<Af2Spec> {
Bk2inpW::new(self, 9)
}
#[doc = "Bit 10 - BRK2 LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2cmp1p(&mut self) -> Bk2cmp1pW<Af2Spec> {
Bk2cmp1pW::new(self, 10)
}
#[doc = "Bit 11 - BRK2 LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed."]
#[inline(always)]
#[must_use]
pub fn bk2cmp2p(&mut self) -> Bk2cmp2pW<Af2Spec> {
Bk2cmp2pW::new(self, 11)
}
#[doc = "Bits 12:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Af2Spec> {
RsvdW::new(self, 12)
}
}
#[doc = "Alternate function option register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Af2Spec;
impl crate::RegisterSpec for Af2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`af2::R`](R) reader structure"]
impl crate::Readable for Af2Spec {}
#[doc = "`write(|w| ..)` method takes [`af2::W`](W) writer structure"]
impl crate::Writable for Af2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AF2 to value 0x01"]
impl crate::Resettable for Af2Spec {
const RESET_VALUE: u32 = 0x01;
}
}
}
#[doc = "I2S1"]
pub struct I2s1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2s1 {}
impl I2s1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2s1::RegisterBlock = 0x5000_9000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2s1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2s1 {
type Target = i2s1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2s1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2s1").finish()
}
}
#[doc = "I2S1"]
pub mod i2s1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
rsvd41: Rsvd41,
_reserved1: [u8; 0x0c],
tx_pcm_format: TxPcmFormat,
rsvd40: Rsvd40,
_reserved3: [u8; 0x08],
tx_pcm_sample_clk: TxPcmSampleClk,
rsvd39: Rsvd39,
_reserved5: [u8; 0x08],
tx_rs_smooth: TxRsSmooth,
rsvd38: Rsvd38,
_reserved7: [u8; 0x08],
tx_pcm_ch_sel: TxPcmChSel,
rsvd37: Rsvd37,
_reserved9: [u8; 0x08],
tx_vol_ctrl: TxVolCtrl,
rsvd36: Rsvd36,
_reserved11: [u8; 0x08],
tx_lr_bal_ctrl: TxLrBalCtrl,
rsvd35: Rsvd35,
_reserved13: [u8; 0x08],
audio_tx_lrck_div: AudioTxLrckDiv,
rsvd34: Rsvd34,
_reserved15: [u8; 0x08],
audio_tx_bclk_div: AudioTxBclkDiv,
rsvd33: Rsvd33,
_reserved17: [u8; 0x08],
audio_tx_format: AudioTxFormat,
rsvd32: Rsvd32,
_reserved19: [u8; 0x08],
audio_serial_timing: AudioSerialTiming,
rsvd31: Rsvd31,
_reserved21: [u8; 0x08],
audio_tx_func_en: AudioTxFuncEn,
rsvd30: Rsvd30,
_reserved23: [u8; 0x08],
audio_tx_pause: AudioTxPause,
rsvd29: Rsvd29,
audio_i2s_sl_merge: AudioI2sSlMerge,
rsvd28: Rsvd28,
_reserved27: [u8; 0x30],
audio_rx_func_en: AudioRxFuncEn,
rsvd27: Rsvd27,
_reserved29: [u8; 0x08],
audio_rx_pause: AudioRxPause,
rsvd26: Rsvd26,
_reserved31: [u8; 0x08],
audio_rx_serial_timing: AudioRxSerialTiming,
rsvd25: Rsvd25,
_reserved33: [u8; 0x08],
audio_rx_pcm_dw: AudioRxPcmDw,
rsvd24: Rsvd24,
_reserved35: [u8; 0x08],
audio_rx_lrck_div: AudioRxLrckDiv,
rsvd23: Rsvd23,
_reserved37: [u8; 0x08],
audio_rx_bclk_div: AudioRxBclkDiv,
rsvd22: Rsvd22,
_reserved39: [u8; 0x08],
record_data_sel: RecordDataSel,
rsvd21: Rsvd21,
_reserved41: [u8; 0x08],
rx_re_sample_clk_div: RxReSampleClkDiv,
rsvd20: Rsvd20,
_reserved43: [u8; 0x08],
rx_re_sample: RxReSample,
rsvd19: Rsvd19,
_reserved45: [u8; 0x08],
record_format: RecordFormat,
rsvd18: Rsvd18,
_reserved47: [u8; 0x08],
rx_ch_sel: RxChSel,
rsvd17: Rsvd17,
_reserved49: [u8; 0x58],
bt_phone_ctrl: BtPhoneCtrl,
rsvd16: Rsvd16,
_reserved51: [u8; 0x08],
bb_pcm_format: BbPcmFormat,
rsvd15: Rsvd15,
_reserved53: [u8; 0x08],
bt_pcm_dw: BtPcmDw,
rsvd14: Rsvd14,
_reserved55: [u8; 0x08],
bt_pcm_timing: BtPcmTiming,
rsvd13: Rsvd13,
_reserved57: [u8; 0x08],
bt_pcm_clk_duty: BtPcmClkDuty,
rsvd12: Rsvd12,
_reserved59: [u8; 0x08],
bt_pcm_sync_duty: BtPcmSyncDuty,
rsvd11: Rsvd11,
_reserved61: [u8; 0x08],
bt_vol_ctrl: BtVolCtrl,
rsvd10: Rsvd10,
_reserved63: [u8; 0x98],
int_mask: IntMask,
rsvd9: Rsvd9,
_reserved65: [u8; 0x08],
int_status: IntStatus,
rsvd8: Rsvd8,
_reserved67: [u8; 0xe8],
tx_dma_entry: TxDmaEntry,
rsvd7: Rsvd7,
_reserved69: [u8; 0x38],
rx_dma_entry: RxDmaEntry,
rsvd6: Rsvd6,
_reserved71: [u8; 0x38],
dma_mask: DmaMask,
rsvd5: Rsvd5,
_reserved73: [u8; 0x78],
debug_loop: DebugLoop,
rsvd4: Rsvd4,
_reserved75: [u8; 0xf8],
fifo_status: FifoStatus,
rsvd3: Rsvd3,
_reserved77: [u8; 0xf8],
tx_equalizer_en: TxEqualizerEn,
rsvd2: Rsvd2,
_reserved79: [u8; 0x08],
tx_equalizer_gain1: TxEqualizerGain1,
rsvd1: Rsvd1,
_reserved81: [u8; 0x08],
tx_equalizer_gain2: TxEqualizerGain2,
}
impl RegisterBlock {
#[doc = "0x00 - "]
#[inline(always)]
pub const fn rsvd41(&self) -> &Rsvd41 {
&self.rsvd41
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn tx_pcm_format(&self) -> &TxPcmFormat {
&self.tx_pcm_format
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn rsvd40(&self) -> &Rsvd40 {
&self.rsvd40
}
#[doc = "0x20 - "]
#[inline(always)]
pub const fn tx_pcm_sample_clk(&self) -> &TxPcmSampleClk {
&self.tx_pcm_sample_clk
}
#[doc = "0x24 - "]
#[inline(always)]
pub const fn rsvd39(&self) -> &Rsvd39 {
&self.rsvd39
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn tx_rs_smooth(&self) -> &TxRsSmooth {
&self.tx_rs_smooth
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn rsvd38(&self) -> &Rsvd38 {
&self.rsvd38
}
#[doc = "0x40 - "]
#[inline(always)]
pub const fn tx_pcm_ch_sel(&self) -> &TxPcmChSel {
&self.tx_pcm_ch_sel
}
#[doc = "0x44 - "]
#[inline(always)]
pub const fn rsvd37(&self) -> &Rsvd37 {
&self.rsvd37
}
#[doc = "0x50 - "]
#[inline(always)]
pub const fn tx_vol_ctrl(&self) -> &TxVolCtrl {
&self.tx_vol_ctrl
}
#[doc = "0x54 - "]
#[inline(always)]
pub const fn rsvd36(&self) -> &Rsvd36 {
&self.rsvd36
}
#[doc = "0x60 - "]
#[inline(always)]
pub const fn tx_lr_bal_ctrl(&self) -> &TxLrBalCtrl {
&self.tx_lr_bal_ctrl
}
#[doc = "0x64 - "]
#[inline(always)]
pub const fn rsvd35(&self) -> &Rsvd35 {
&self.rsvd35
}
#[doc = "0x70 - "]
#[inline(always)]
pub const fn audio_tx_lrck_div(&self) -> &AudioTxLrckDiv {
&self.audio_tx_lrck_div
}
#[doc = "0x74 - "]
#[inline(always)]
pub const fn rsvd34(&self) -> &Rsvd34 {
&self.rsvd34
}
#[doc = "0x80 - "]
#[inline(always)]
pub const fn audio_tx_bclk_div(&self) -> &AudioTxBclkDiv {
&self.audio_tx_bclk_div
}
#[doc = "0x84 - "]
#[inline(always)]
pub const fn rsvd33(&self) -> &Rsvd33 {
&self.rsvd33
}
#[doc = "0x90 - "]
#[inline(always)]
pub const fn audio_tx_format(&self) -> &AudioTxFormat {
&self.audio_tx_format
}
#[doc = "0x94 - "]
#[inline(always)]
pub const fn rsvd32(&self) -> &Rsvd32 {
&self.rsvd32
}
#[doc = "0xa0 - "]
#[inline(always)]
pub const fn audio_serial_timing(&self) -> &AudioSerialTiming {
&self.audio_serial_timing
}
#[doc = "0xa4 - "]
#[inline(always)]
pub const fn rsvd31(&self) -> &Rsvd31 {
&self.rsvd31
}
#[doc = "0xb0 - "]
#[inline(always)]
pub const fn audio_tx_func_en(&self) -> &AudioTxFuncEn {
&self.audio_tx_func_en
}
#[doc = "0xb4 - "]
#[inline(always)]
pub const fn rsvd30(&self) -> &Rsvd30 {
&self.rsvd30
}
#[doc = "0xc0 - "]
#[inline(always)]
pub const fn audio_tx_pause(&self) -> &AudioTxPause {
&self.audio_tx_pause
}
#[doc = "0xc4 - "]
#[inline(always)]
pub const fn rsvd29(&self) -> &Rsvd29 {
&self.rsvd29
}
#[doc = "0xc8 - "]
#[inline(always)]
pub const fn audio_i2s_sl_merge(&self) -> &AudioI2sSlMerge {
&self.audio_i2s_sl_merge
}
#[doc = "0xcc - "]
#[inline(always)]
pub const fn rsvd28(&self) -> &Rsvd28 {
&self.rsvd28
}
#[doc = "0x100 - "]
#[inline(always)]
pub const fn audio_rx_func_en(&self) -> &AudioRxFuncEn {
&self.audio_rx_func_en
}
#[doc = "0x104 - "]
#[inline(always)]
pub const fn rsvd27(&self) -> &Rsvd27 {
&self.rsvd27
}
#[doc = "0x110 - "]
#[inline(always)]
pub const fn audio_rx_pause(&self) -> &AudioRxPause {
&self.audio_rx_pause
}
#[doc = "0x114 - "]
#[inline(always)]
pub const fn rsvd26(&self) -> &Rsvd26 {
&self.rsvd26
}
#[doc = "0x120 - "]
#[inline(always)]
pub const fn audio_rx_serial_timing(&self) -> &AudioRxSerialTiming {
&self.audio_rx_serial_timing
}
#[doc = "0x124 - "]
#[inline(always)]
pub const fn rsvd25(&self) -> &Rsvd25 {
&self.rsvd25
}
#[doc = "0x130 - "]
#[inline(always)]
pub const fn audio_rx_pcm_dw(&self) -> &AudioRxPcmDw {
&self.audio_rx_pcm_dw
}
#[doc = "0x134 - "]
#[inline(always)]
pub const fn rsvd24(&self) -> &Rsvd24 {
&self.rsvd24
}
#[doc = "0x140 - "]
#[inline(always)]
pub const fn audio_rx_lrck_div(&self) -> &AudioRxLrckDiv {
&self.audio_rx_lrck_div
}
#[doc = "0x144 - "]
#[inline(always)]
pub const fn rsvd23(&self) -> &Rsvd23 {
&self.rsvd23
}
#[doc = "0x150 - "]
#[inline(always)]
pub const fn audio_rx_bclk_div(&self) -> &AudioRxBclkDiv {
&self.audio_rx_bclk_div
}
#[doc = "0x154 - "]
#[inline(always)]
pub const fn rsvd22(&self) -> &Rsvd22 {
&self.rsvd22
}
#[doc = "0x160 - "]
#[inline(always)]
pub const fn record_data_sel(&self) -> &RecordDataSel {
&self.record_data_sel
}
#[doc = "0x164 - "]
#[inline(always)]
pub const fn rsvd21(&self) -> &Rsvd21 {
&self.rsvd21
}
#[doc = "0x170 - "]
#[inline(always)]
pub const fn rx_re_sample_clk_div(&self) -> &RxReSampleClkDiv {
&self.rx_re_sample_clk_div
}
#[doc = "0x174 - "]
#[inline(always)]
pub const fn rsvd20(&self) -> &Rsvd20 {
&self.rsvd20
}
#[doc = "0x180 - "]
#[inline(always)]
pub const fn rx_re_sample(&self) -> &RxReSample {
&self.rx_re_sample
}
#[doc = "0x184 - "]
#[inline(always)]
pub const fn rsvd19(&self) -> &Rsvd19 {
&self.rsvd19
}
#[doc = "0x190 - "]
#[inline(always)]
pub const fn record_format(&self) -> &RecordFormat {
&self.record_format
}
#[doc = "0x194 - "]
#[inline(always)]
pub const fn rsvd18(&self) -> &Rsvd18 {
&self.rsvd18
}
#[doc = "0x1a0 - "]
#[inline(always)]
pub const fn rx_ch_sel(&self) -> &RxChSel {
&self.rx_ch_sel
}
#[doc = "0x1a4 - "]
#[inline(always)]
pub const fn rsvd17(&self) -> &Rsvd17 {
&self.rsvd17
}
#[doc = "0x200 - "]
#[inline(always)]
pub const fn bt_phone_ctrl(&self) -> &BtPhoneCtrl {
&self.bt_phone_ctrl
}
#[doc = "0x204 - "]
#[inline(always)]
pub const fn rsvd16(&self) -> &Rsvd16 {
&self.rsvd16
}
#[doc = "0x210 - "]
#[inline(always)]
pub const fn bb_pcm_format(&self) -> &BbPcmFormat {
&self.bb_pcm_format
}
#[doc = "0x214 - "]
#[inline(always)]
pub const fn rsvd15(&self) -> &Rsvd15 {
&self.rsvd15
}
#[doc = "0x220 - "]
#[inline(always)]
pub const fn bt_pcm_dw(&self) -> &BtPcmDw {
&self.bt_pcm_dw
}
#[doc = "0x224 - "]
#[inline(always)]
pub const fn rsvd14(&self) -> &Rsvd14 {
&self.rsvd14
}
#[doc = "0x230 - "]
#[inline(always)]
pub const fn bt_pcm_timing(&self) -> &BtPcmTiming {
&self.bt_pcm_timing
}
#[doc = "0x234 - "]
#[inline(always)]
pub const fn rsvd13(&self) -> &Rsvd13 {
&self.rsvd13
}
#[doc = "0x240 - "]
#[inline(always)]
pub const fn bt_pcm_clk_duty(&self) -> &BtPcmClkDuty {
&self.bt_pcm_clk_duty
}
#[doc = "0x244 - "]
#[inline(always)]
pub const fn rsvd12(&self) -> &Rsvd12 {
&self.rsvd12
}
#[doc = "0x250 - "]
#[inline(always)]
pub const fn bt_pcm_sync_duty(&self) -> &BtPcmSyncDuty {
&self.bt_pcm_sync_duty
}
#[doc = "0x254 - "]
#[inline(always)]
pub const fn rsvd11(&self) -> &Rsvd11 {
&self.rsvd11
}
#[doc = "0x260 - "]
#[inline(always)]
pub const fn bt_vol_ctrl(&self) -> &BtVolCtrl {
&self.bt_vol_ctrl
}
#[doc = "0x264 - "]
#[inline(always)]
pub const fn rsvd10(&self) -> &Rsvd10 {
&self.rsvd10
}
#[doc = "0x300 - "]
#[inline(always)]
pub const fn int_mask(&self) -> &IntMask {
&self.int_mask
}
#[doc = "0x304 - "]
#[inline(always)]
pub const fn rsvd9(&self) -> &Rsvd9 {
&self.rsvd9
}
#[doc = "0x310 - "]
#[inline(always)]
pub const fn int_status(&self) -> &IntStatus {
&self.int_status
}
#[doc = "0x314 - "]
#[inline(always)]
pub const fn rsvd8(&self) -> &Rsvd8 {
&self.rsvd8
}
#[doc = "0x400 - "]
#[inline(always)]
pub const fn tx_dma_entry(&self) -> &TxDmaEntry {
&self.tx_dma_entry
}
#[doc = "0x404 - "]
#[inline(always)]
pub const fn rsvd7(&self) -> &Rsvd7 {
&self.rsvd7
}
#[doc = "0x440 - "]
#[inline(always)]
pub const fn rx_dma_entry(&self) -> &RxDmaEntry {
&self.rx_dma_entry
}
#[doc = "0x444 - "]
#[inline(always)]
pub const fn rsvd6(&self) -> &Rsvd6 {
&self.rsvd6
}
#[doc = "0x480 - "]
#[inline(always)]
pub const fn dma_mask(&self) -> &DmaMask {
&self.dma_mask
}
#[doc = "0x484 - "]
#[inline(always)]
pub const fn rsvd5(&self) -> &Rsvd5 {
&self.rsvd5
}
#[doc = "0x500 - "]
#[inline(always)]
pub const fn debug_loop(&self) -> &DebugLoop {
&self.debug_loop
}
#[doc = "0x504 - "]
#[inline(always)]
pub const fn rsvd4(&self) -> &Rsvd4 {
&self.rsvd4
}
#[doc = "0x600 - "]
#[inline(always)]
pub const fn fifo_status(&self) -> &FifoStatus {
&self.fifo_status
}
#[doc = "0x604 - "]
#[inline(always)]
pub const fn rsvd3(&self) -> &Rsvd3 {
&self.rsvd3
}
#[doc = "0x700 - "]
#[inline(always)]
pub const fn tx_equalizer_en(&self) -> &TxEqualizerEn {
&self.tx_equalizer_en
}
#[doc = "0x704 - "]
#[inline(always)]
pub const fn rsvd2(&self) -> &Rsvd2 {
&self.rsvd2
}
#[doc = "0x710 - "]
#[inline(always)]
pub const fn tx_equalizer_gain1(&self) -> &TxEqualizerGain1 {
&self.tx_equalizer_gain1
}
#[doc = "0x714 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x720 - "]
#[inline(always)]
pub const fn tx_equalizer_gain2(&self) -> &TxEqualizerGain2 {
&self.tx_equalizer_gain2
}
}
#[doc = "RSVD41 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd41`]
module"]
#[doc(alias = "RSVD41")]
pub type Rsvd41 = crate::Reg<rsvd41::Rsvd41Spec>;
#[doc = ""]
pub mod rsvd41 {
#[doc = "Register `RSVD41` reader"]
pub type R = crate::R<Rsvd41Spec>;
#[doc = "Register `RSVD41` writer"]
pub type W = crate::W<Rsvd41Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd41::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd41::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd41Spec;
impl crate::RegisterSpec for Rsvd41Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd41::R`](R) reader structure"]
impl crate::Readable for Rsvd41Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd41::W`](W) writer structure"]
impl crate::Writable for Rsvd41Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD41 to value 0"]
impl crate::Resettable for Rsvd41Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_PCM_FORMAT (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm_format::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm_format::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_pcm_format`]
module"]
#[doc(alias = "TX_PCM_FORMAT")]
pub type TxPcmFormat = crate::Reg<tx_pcm_format::TxPcmFormatSpec>;
#[doc = ""]
pub mod tx_pcm_format {
#[doc = "Register `TX_PCM_FORMAT` reader"]
pub type R = crate::R<TxPcmFormatSpec>;
#[doc = "Register `TX_PCM_FORMAT` writer"]
pub type W = crate::W<TxPcmFormatSpec>;
#[doc = "Field `DW` reader - tx source pcm data width N(N>=8) common value is 8,13,14,16,18,20,22,24 This data width indicate the tx fifo output data width. When writing to tx fifo, please refer to following format: ※Mono 8 bit: fifo_data\\[31:0\\]
= {L3,L2,L1,L0}, each word contains 4 samples, so four samples need read one word ※Stereo 8 bit: fifo_data\\[31:0\\]
= { R1,L1,R0,L0 }, each word contains 2 samples, so two samples need read one word ※Mono 13/14/16 bit: fifo_data\\[31:0\\]
= {L1,L0}, each word contains 2 samples, so two samples need read one word ※Stereo 13/14/16 bit: fifo_data\\[31:0\\]
= {R0,L0}, each word contains 1 samples, so each sample need read one word ※Mono 18/20/22/24 bit: fifo_data\\[31:0\\]
= L0, each word contains 1 samples, so each sample need read one word ※Stereo 18/20/22/24 bit: fifo_data\\[31:0\\]\\[0\\]
= {L0}, fifo_data\\[31:0\\]\\[1\\]={R0}, each 2 words contain 1 samples, so each sample need read two word"]
pub type DwR = crate::FieldReader;
#[doc = "Field `DW` writer - tx source pcm data width N(N>=8) common value is 8,13,14,16,18,20,22,24 This data width indicate the tx fifo output data width. When writing to tx fifo, please refer to following format: ※Mono 8 bit: fifo_data\\[31:0\\]
= {L3,L2,L1,L0}, each word contains 4 samples, so four samples need read one word ※Stereo 8 bit: fifo_data\\[31:0\\]
= { R1,L1,R0,L0 }, each word contains 2 samples, so two samples need read one word ※Mono 13/14/16 bit: fifo_data\\[31:0\\]
= {L1,L0}, each word contains 2 samples, so two samples need read one word ※Stereo 13/14/16 bit: fifo_data\\[31:0\\]
= {R0,L0}, each word contains 1 samples, so each sample need read one word ※Mono 18/20/22/24 bit: fifo_data\\[31:0\\]
= L0, each word contains 1 samples, so each sample need read one word ※Stereo 18/20/22/24 bit: fifo_data\\[31:0\\]\\[0\\]
= {L0}, fifo_data\\[31:0\\]\\[1\\]={R0}, each 2 words contain 1 samples, so each sample need read two word"]
pub type DwW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `TRACK_FLAG` reader - 0: stereo 1: mono"]
pub type TrackFlagR = crate::BitReader;
#[doc = "Field `TRACK_FLAG` writer - 0: stereo 1: mono"]
pub type TrackFlagW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:4 - tx source pcm data width N(N>=8) common value is 8,13,14,16,18,20,22,24 This data width indicate the tx fifo output data width. When writing to tx fifo, please refer to following format: ※Mono 8 bit: fifo_data\\[31:0\\]
= {L3,L2,L1,L0}, each word contains 4 samples, so four samples need read one word ※Stereo 8 bit: fifo_data\\[31:0\\]
= { R1,L1,R0,L0 }, each word contains 2 samples, so two samples need read one word ※Mono 13/14/16 bit: fifo_data\\[31:0\\]
= {L1,L0}, each word contains 2 samples, so two samples need read one word ※Stereo 13/14/16 bit: fifo_data\\[31:0\\]
= {R0,L0}, each word contains 1 samples, so each sample need read one word ※Mono 18/20/22/24 bit: fifo_data\\[31:0\\]
= L0, each word contains 1 samples, so each sample need read one word ※Stereo 18/20/22/24 bit: fifo_data\\[31:0\\]\\[0\\]
= {L0}, fifo_data\\[31:0\\]\\[1\\]={R0}, each 2 words contain 1 samples, so each sample need read two word"]
#[inline(always)]
pub fn dw(&self) -> DwR {
DwR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 5 - 0: stereo 1: mono"]
#[inline(always)]
pub fn track_flag(&self) -> TrackFlagR {
TrackFlagR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:4 - tx source pcm data width N(N>=8) common value is 8,13,14,16,18,20,22,24 This data width indicate the tx fifo output data width. When writing to tx fifo, please refer to following format: ※Mono 8 bit: fifo_data\\[31:0\\]
= {L3,L2,L1,L0}, each word contains 4 samples, so four samples need read one word ※Stereo 8 bit: fifo_data\\[31:0\\]
= { R1,L1,R0,L0 }, each word contains 2 samples, so two samples need read one word ※Mono 13/14/16 bit: fifo_data\\[31:0\\]
= {L1,L0}, each word contains 2 samples, so two samples need read one word ※Stereo 13/14/16 bit: fifo_data\\[31:0\\]
= {R0,L0}, each word contains 1 samples, so each sample need read one word ※Mono 18/20/22/24 bit: fifo_data\\[31:0\\]
= L0, each word contains 1 samples, so each sample need read one word ※Stereo 18/20/22/24 bit: fifo_data\\[31:0\\]\\[0\\]
= {L0}, fifo_data\\[31:0\\]\\[1\\]={R0}, each 2 words contain 1 samples, so each sample need read two word"]
#[inline(always)]
#[must_use]
pub fn dw(&mut self) -> DwW<TxPcmFormatSpec> {
DwW::new(self, 0)
}
#[doc = "Bit 5 - 0: stereo 1: mono"]
#[inline(always)]
#[must_use]
pub fn track_flag(&mut self) -> TrackFlagW<TxPcmFormatSpec> {
TrackFlagW::new(self, 5)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxPcmFormatSpec> {
RsvdW::new(self, 6)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm_format::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm_format::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxPcmFormatSpec;
impl crate::RegisterSpec for TxPcmFormatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_pcm_format::R`](R) reader structure"]
impl crate::Readable for TxPcmFormatSpec {}
#[doc = "`write(|w| ..)` method takes [`tx_pcm_format::W`](W) writer structure"]
impl crate::Writable for TxPcmFormatSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_PCM_FORMAT to value 0x10"]
impl crate::Resettable for TxPcmFormatSpec {
const RESET_VALUE: u32 = 0x10;
}
}
#[doc = "RSVD40 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd40`]
module"]
#[doc(alias = "RSVD40")]
pub type Rsvd40 = crate::Reg<rsvd40::Rsvd40Spec>;
#[doc = ""]
pub mod rsvd40 {
#[doc = "Register `RSVD40` reader"]
pub type R = crate::R<Rsvd40Spec>;
#[doc = "Register `RSVD40` writer"]
pub type W = crate::W<Rsvd40Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd40::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd40::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd40Spec;
impl crate::RegisterSpec for Rsvd40Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd40::R`](R) reader structure"]
impl crate::Readable for Rsvd40Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd40::W`](W) writer structure"]
impl crate::Writable for Rsvd40Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD40 to value 0"]
impl crate::Resettable for Rsvd40Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_PCM_SAMPLE_CLK (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm_sample_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm_sample_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_pcm_sample_clk`]
module"]
#[doc(alias = "TX_PCM_SAMPLE_CLK")]
pub type TxPcmSampleClk = crate::Reg<tx_pcm_sample_clk::TxPcmSampleClkSpec>;
#[doc = ""]
pub mod tx_pcm_sample_clk {
#[doc = "Register `TX_PCM_SAMPLE_CLK` reader"]
pub type R = crate::R<TxPcmSampleClkSpec>;
#[doc = "Register `TX_PCM_SAMPLE_CLK` writer"]
pub type W = crate::W<TxPcmSampleClkSpec>;
#[doc = "Field `FS_DUTY` reader - source PCM sample clock duty cycle(with GCLK=12MHz): 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS"]
pub type FsDutyR = crate::FieldReader<u16>;
#[doc = "Field `FS_DUTY` writer - source PCM sample clock duty cycle(with GCLK=12MHz): 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS"]
pub type FsDutyW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - source PCM sample clock duty cycle(with GCLK=12MHz): 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS"]
#[inline(always)]
pub fn fs_duty(&self) -> FsDutyR {
FsDutyR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - source PCM sample clock duty cycle(with GCLK=12MHz): 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS"]
#[inline(always)]
#[must_use]
pub fn fs_duty(&mut self) -> FsDutyW<TxPcmSampleClkSpec> {
FsDutyW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxPcmSampleClkSpec> {
RsvdW::new(self, 13)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm_sample_clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm_sample_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxPcmSampleClkSpec;
impl crate::RegisterSpec for TxPcmSampleClkSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_pcm_sample_clk::R`](R) reader structure"]
impl crate::Readable for TxPcmSampleClkSpec {}
#[doc = "`write(|w| ..)` method takes [`tx_pcm_sample_clk::W`](W) writer structure"]
impl crate::Writable for TxPcmSampleClkSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_PCM_SAMPLE_CLK to value 0xfa"]
impl crate::Resettable for TxPcmSampleClkSpec {
const RESET_VALUE: u32 = 0xfa;
}
}
#[doc = "RSVD39 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd39`]
module"]
#[doc(alias = "RSVD39")]
pub type Rsvd39 = crate::Reg<rsvd39::Rsvd39Spec>;
#[doc = ""]
pub mod rsvd39 {
#[doc = "Register `RSVD39` reader"]
pub type R = crate::R<Rsvd39Spec>;
#[doc = "Register `RSVD39` writer"]
pub type W = crate::W<Rsvd39Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd39::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd39::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd39Spec;
impl crate::RegisterSpec for Rsvd39Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd39::R`](R) reader structure"]
impl crate::Readable for Rsvd39Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd39::W`](W) writer structure"]
impl crate::Writable for Rsvd39Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD39 to value 0"]
impl crate::Resettable for Rsvd39Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_RS_SMOOTH (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_rs_smooth::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_rs_smooth::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_rs_smooth`]
module"]
#[doc(alias = "TX_RS_SMOOTH")]
pub type TxRsSmooth = crate::Reg<tx_rs_smooth::TxRsSmoothSpec>;
#[doc = ""]
pub mod tx_rs_smooth {
#[doc = "Register `TX_RS_SMOOTH` reader"]
pub type R = crate::R<TxRsSmoothSpec>;
#[doc = "Register `TX_RS_SMOOTH` writer"]
pub type W = crate::W<TxRsSmoothSpec>;
#[doc = "Field `EN` reader - 0: Disable TX re-sample smooth filter 1: Enable TX re-sample smooth filter This function is not implemented."]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - 0: Disable TX re-sample smooth filter 1: Enable TX re-sample smooth filter This function is not implemented."]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - 0: Disable TX re-sample smooth filter 1: Enable TX re-sample smooth filter This function is not implemented."]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 0: Disable TX re-sample smooth filter 1: Enable TX re-sample smooth filter This function is not implemented."]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<TxRsSmoothSpec> {
EnW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxRsSmoothSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_rs_smooth::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_rs_smooth::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxRsSmoothSpec;
impl crate::RegisterSpec for TxRsSmoothSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_rs_smooth::R`](R) reader structure"]
impl crate::Readable for TxRsSmoothSpec {}
#[doc = "`write(|w| ..)` method takes [`tx_rs_smooth::W`](W) writer structure"]
impl crate::Writable for TxRsSmoothSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_RS_SMOOTH to value 0"]
impl crate::Resettable for TxRsSmoothSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD38 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd38`]
module"]
#[doc(alias = "RSVD38")]
pub type Rsvd38 = crate::Reg<rsvd38::Rsvd38Spec>;
#[doc = ""]
pub mod rsvd38 {
#[doc = "Register `RSVD38` reader"]
pub type R = crate::R<Rsvd38Spec>;
#[doc = "Register `RSVD38` writer"]
pub type W = crate::W<Rsvd38Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd38::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd38::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd38Spec;
impl crate::RegisterSpec for Rsvd38Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd38::R`](R) reader structure"]
impl crate::Readable for Rsvd38Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd38::W`](W) writer structure"]
impl crate::Writable for Rsvd38Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD38 to value 0"]
impl crate::Resettable for Rsvd38Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_PCM_CH_SEL (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm_ch_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm_ch_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_pcm_ch_sel`]
module"]
#[doc(alias = "TX_PCM_CH_SEL")]
pub type TxPcmChSel = crate::Reg<tx_pcm_ch_sel::TxPcmChSelSpec>;
#[doc = ""]
pub mod tx_pcm_ch_sel {
#[doc = "Register `TX_PCM_CH_SEL` reader"]
pub type R = crate::R<TxPcmChSelSpec>;
#[doc = "Register `TX_PCM_CH_SEL` writer"]
pub type W = crate::W<TxPcmChSelSpec>;
#[doc = "Field `RIGHT_CHANNEL_SEL` reader - TX re-sampling module setting: 00: TX right = source right 01: TX right = source left 10,11: TX right = (source left + source right)/2"]
pub type RightChannelSelR = crate::FieldReader;
#[doc = "Field `RIGHT_CHANNEL_SEL` writer - TX re-sampling module setting: 00: TX right = source right 01: TX right = source left 10,11: TX right = (source left + source right)/2"]
pub type RightChannelSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `LEFT_CHANNEL_SEL` reader - TX re-sampling module setting: 00: TX left = source left 01: TX left = source right 10,11: TX left = (source left + source right)/2"]
pub type LeftChannelSelR = crate::FieldReader;
#[doc = "Field `LEFT_CHANNEL_SEL` writer - TX re-sampling module setting: 00: TX left = source left 01: TX left = source right 10,11: TX left = (source left + source right)/2"]
pub type LeftChannelSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:1 - TX re-sampling module setting: 00: TX right = source right 01: TX right = source left 10,11: TX right = (source left + source right)/2"]
#[inline(always)]
pub fn right_channel_sel(&self) -> RightChannelSelR {
RightChannelSelR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - TX re-sampling module setting: 00: TX left = source left 01: TX left = source right 10,11: TX left = (source left + source right)/2"]
#[inline(always)]
pub fn left_channel_sel(&self) -> LeftChannelSelR {
LeftChannelSelR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:1 - TX re-sampling module setting: 00: TX right = source right 01: TX right = source left 10,11: TX right = (source left + source right)/2"]
#[inline(always)]
#[must_use]
pub fn right_channel_sel(&mut self) -> RightChannelSelW<TxPcmChSelSpec> {
RightChannelSelW::new(self, 0)
}
#[doc = "Bits 2:3 - TX re-sampling module setting: 00: TX left = source left 01: TX left = source right 10,11: TX left = (source left + source right)/2"]
#[inline(always)]
#[must_use]
pub fn left_channel_sel(&mut self) -> LeftChannelSelW<TxPcmChSelSpec> {
LeftChannelSelW::new(self, 2)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxPcmChSelSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm_ch_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm_ch_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxPcmChSelSpec;
impl crate::RegisterSpec for TxPcmChSelSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_pcm_ch_sel::R`](R) reader structure"]
impl crate::Readable for TxPcmChSelSpec {}
#[doc = "`write(|w| ..)` method takes [`tx_pcm_ch_sel::W`](W) writer structure"]
impl crate::Writable for TxPcmChSelSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_PCM_CH_SEL to value 0"]
impl crate::Resettable for TxPcmChSelSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD37 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd37`]
module"]
#[doc(alias = "RSVD37")]
pub type Rsvd37 = crate::Reg<rsvd37::Rsvd37Spec>;
#[doc = ""]
pub mod rsvd37 {
#[doc = "Register `RSVD37` reader"]
pub type R = crate::R<Rsvd37Spec>;
#[doc = "Register `RSVD37` writer"]
pub type W = crate::W<Rsvd37Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd37::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd37::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd37Spec;
impl crate::RegisterSpec for Rsvd37Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd37::R`](R) reader structure"]
impl crate::Readable for Rsvd37Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd37::W`](W) writer structure"]
impl crate::Writable for Rsvd37Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD37 to value 0"]
impl crate::Resettable for Rsvd37Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_VOL_CTRL (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_vol_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_vol_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_vol_ctrl`]
module"]
#[doc(alias = "TX_VOL_CTRL")]
pub type TxVolCtrl = crate::Reg<tx_vol_ctrl::TxVolCtrlSpec>;
#[doc = ""]
pub mod tx_vol_ctrl {
#[doc = "Register `TX_VOL_CTRL` reader"]
pub type R = crate::R<TxVolCtrlSpec>;
#[doc = "Register `TX_VOL_CTRL` writer"]
pub type W = crate::W<TxVolCtrlSpec>;
#[doc = "Field `VOL` reader - volume control: 0000: +6dB, 0001: +4.5dB, 0010: +3dB, 0011: +1.5dB, 0100: 0dB, 0101: -1.5dB, 0110: -3.0dB, 0111: -4.5dB, 1000: -6.0dB, 1001: -7.5dB, 1010: -9dB, 1011: -10.5dB, 1100: -12dB, 1101: -13.5dB, 1110: -15dB, 1111: mute Note: 1) +1.5db = 20log(1+1/4-1/16+1/1024) 2) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
pub type VolR = crate::FieldReader;
#[doc = "Field `VOL` writer - volume control: 0000: +6dB, 0001: +4.5dB, 0010: +3dB, 0011: +1.5dB, 0100: 0dB, 0101: -1.5dB, 0110: -3.0dB, 0111: -4.5dB, 1000: -6.0dB, 1001: -7.5dB, 1010: -9dB, 1011: -10.5dB, 1100: -12dB, 1101: -13.5dB, 1110: -15dB, 1111: mute Note: 1) +1.5db = 20log(1+1/4-1/16+1/1024) 2) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
pub type VolW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:3 - volume control: 0000: +6dB, 0001: +4.5dB, 0010: +3dB, 0011: +1.5dB, 0100: 0dB, 0101: -1.5dB, 0110: -3.0dB, 0111: -4.5dB, 1000: -6.0dB, 1001: -7.5dB, 1010: -9dB, 1011: -10.5dB, 1100: -12dB, 1101: -13.5dB, 1110: -15dB, 1111: mute Note: 1) +1.5db = 20log(1+1/4-1/16+1/1024) 2) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
#[inline(always)]
pub fn vol(&self) -> VolR {
VolR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:3 - volume control: 0000: +6dB, 0001: +4.5dB, 0010: +3dB, 0011: +1.5dB, 0100: 0dB, 0101: -1.5dB, 0110: -3.0dB, 0111: -4.5dB, 1000: -6.0dB, 1001: -7.5dB, 1010: -9dB, 1011: -10.5dB, 1100: -12dB, 1101: -13.5dB, 1110: -15dB, 1111: mute Note: 1) +1.5db = 20log(1+1/4-1/16+1/1024) 2) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
#[inline(always)]
#[must_use]
pub fn vol(&mut self) -> VolW<TxVolCtrlSpec> {
VolW::new(self, 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxVolCtrlSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_vol_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_vol_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxVolCtrlSpec;
impl crate::RegisterSpec for TxVolCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_vol_ctrl::R`](R) reader structure"]
impl crate::Readable for TxVolCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`tx_vol_ctrl::W`](W) writer structure"]
impl crate::Writable for TxVolCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_VOL_CTRL to value 0x0f"]
impl crate::Resettable for TxVolCtrlSpec {
const RESET_VALUE: u32 = 0x0f;
}
}
#[doc = "RSVD36 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd36`]
module"]
#[doc(alias = "RSVD36")]
pub type Rsvd36 = crate::Reg<rsvd36::Rsvd36Spec>;
#[doc = ""]
pub mod rsvd36 {
#[doc = "Register `RSVD36` reader"]
pub type R = crate::R<Rsvd36Spec>;
#[doc = "Register `RSVD36` writer"]
pub type W = crate::W<Rsvd36Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd36::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd36::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd36Spec;
impl crate::RegisterSpec for Rsvd36Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd36::R`](R) reader structure"]
impl crate::Readable for Rsvd36Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd36::W`](W) writer structure"]
impl crate::Writable for Rsvd36Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD36 to value 0"]
impl crate::Resettable for Rsvd36Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_LR_BAL_CTRL (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_lr_bal_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_lr_bal_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_lr_bal_ctrl`]
module"]
#[doc(alias = "TX_LR_BAL_CTRL")]
pub type TxLrBalCtrl = crate::Reg<tx_lr_bal_ctrl::TxLrBalCtrlSpec>;
#[doc = ""]
pub mod tx_lr_bal_ctrl {
#[doc = "Register `TX_LR_BAL_CTRL` reader"]
pub type R = crate::R<TxLrBalCtrlSpec>;
#[doc = "Register `TX_LR_BAL_CTRL` writer"]
pub type W = crate::W<TxLrBalCtrlSpec>;
#[doc = "Field `BAL_VOL` reader - Balance volume control: 0000: Reserved, 0001: -1.5dB, 0010: -3.0dB, 0011: -4.5dB, 0100: -6.0dB, 0101: -7.5dB, 0110: -9.0dB, 0111: -10.5dB, 1000: -12dB, 1001: -13.5dB, 1010: -15dB, 1011: -16.5dB, 1100: -18dB, 1101: -19.5dB, 1110: -21dB, 1111: mute Note: 1) bit\\[5:0\\]
= 101111 for left mute 2) bit\\[5:0\\]
= 011111 for right mute 3) bit\\[5:4\\]
= 00 or 11, bit\\[3:0\\]
is don't care 4) +1.5db = 20log(1+1/4-1/16+1/1024) 5) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
pub type BalVolR = crate::FieldReader;
#[doc = "Field `BAL_VOL` writer - Balance volume control: 0000: Reserved, 0001: -1.5dB, 0010: -3.0dB, 0011: -4.5dB, 0100: -6.0dB, 0101: -7.5dB, 0110: -9.0dB, 0111: -10.5dB, 1000: -12dB, 1001: -13.5dB, 1010: -15dB, 1011: -16.5dB, 1100: -18dB, 1101: -19.5dB, 1110: -21dB, 1111: mute Note: 1) bit\\[5:0\\]
= 101111 for left mute 2) bit\\[5:0\\]
= 011111 for right mute 3) bit\\[5:4\\]
= 00 or 11, bit\\[3:0\\]
is don't care 4) +1.5db = 20log(1+1/4-1/16+1/1024) 5) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
pub type BalVolW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `EN` reader - LR balance enable: 00: both left and right in full volume 10: left channel balance volume adjustment enable 01: right channel balance volume adjustment enable 11: reserved, still kepp left and right in full volume"]
pub type EnR = crate::FieldReader;
#[doc = "Field `EN` writer - LR balance enable: 00: both left and right in full volume 10: left channel balance volume adjustment enable 01: right channel balance volume adjustment enable 11: reserved, still kepp left and right in full volume"]
pub type EnW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:3 - Balance volume control: 0000: Reserved, 0001: -1.5dB, 0010: -3.0dB, 0011: -4.5dB, 0100: -6.0dB, 0101: -7.5dB, 0110: -9.0dB, 0111: -10.5dB, 1000: -12dB, 1001: -13.5dB, 1010: -15dB, 1011: -16.5dB, 1100: -18dB, 1101: -19.5dB, 1110: -21dB, 1111: mute Note: 1) bit\\[5:0\\]
= 101111 for left mute 2) bit\\[5:0\\]
= 011111 for right mute 3) bit\\[5:4\\]
= 00 or 11, bit\\[3:0\\]
is don't care 4) +1.5db = 20log(1+1/4-1/16+1/1024) 5) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
#[inline(always)]
pub fn bal_vol(&self) -> BalVolR {
BalVolR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - LR balance enable: 00: both left and right in full volume 10: left channel balance volume adjustment enable 01: right channel balance volume adjustment enable 11: reserved, still kepp left and right in full volume"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3 - Balance volume control: 0000: Reserved, 0001: -1.5dB, 0010: -3.0dB, 0011: -4.5dB, 0100: -6.0dB, 0101: -7.5dB, 0110: -9.0dB, 0111: -10.5dB, 1000: -12dB, 1001: -13.5dB, 1010: -15dB, 1011: -16.5dB, 1100: -18dB, 1101: -19.5dB, 1110: -21dB, 1111: mute Note: 1) bit\\[5:0\\]
= 101111 for left mute 2) bit\\[5:0\\]
= 011111 for right mute 3) bit\\[5:4\\]
= 00 or 11, bit\\[3:0\\]
is don't care 4) +1.5db = 20log(1+1/4-1/16+1/1024) 5) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048)"]
#[inline(always)]
#[must_use]
pub fn bal_vol(&mut self) -> BalVolW<TxLrBalCtrlSpec> {
BalVolW::new(self, 0)
}
#[doc = "Bits 4:5 - LR balance enable: 00: both left and right in full volume 10: left channel balance volume adjustment enable 01: right channel balance volume adjustment enable 11: reserved, still kepp left and right in full volume"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<TxLrBalCtrlSpec> {
EnW::new(self, 4)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxLrBalCtrlSpec> {
RsvdW::new(self, 6)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_lr_bal_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_lr_bal_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxLrBalCtrlSpec;
impl crate::RegisterSpec for TxLrBalCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_lr_bal_ctrl::R`](R) reader structure"]
impl crate::Readable for TxLrBalCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`tx_lr_bal_ctrl::W`](W) writer structure"]
impl crate::Writable for TxLrBalCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_LR_BAL_CTRL to value 0"]
impl crate::Resettable for TxLrBalCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD35 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd35`]
module"]
#[doc(alias = "RSVD35")]
pub type Rsvd35 = crate::Reg<rsvd35::Rsvd35Spec>;
#[doc = ""]
pub mod rsvd35 {
#[doc = "Register `RSVD35` reader"]
pub type R = crate::R<Rsvd35Spec>;
#[doc = "Register `RSVD35` writer"]
pub type W = crate::W<Rsvd35Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd35::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd35::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd35Spec;
impl crate::RegisterSpec for Rsvd35Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd35::R`](R) reader structure"]
impl crate::Readable for Rsvd35Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd35::W`](W) writer structure"]
impl crate::Writable for Rsvd35Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD35 to value 0"]
impl crate::Resettable for Rsvd35Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_TX_LRCK_DIV (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_lrck_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_lrck_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_tx_lrck_div`]
module"]
#[doc(alias = "AUDIO_TX_LRCK_DIV")]
pub type AudioTxLrckDiv = crate::Reg<audio_tx_lrck_div::AudioTxLrckDivSpec>;
#[doc = ""]
pub mod audio_tx_lrck_div {
#[doc = "Register `AUDIO_TX_LRCK_DIV` reader"]
pub type R = crate::R<AudioTxLrckDivSpec>;
#[doc = "Register `AUDIO_TX_LRCK_DIV` writer"]
pub type W = crate::W<AudioTxLrckDivSpec>;
#[doc = "Field `DUTY_LOW` reader - TX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
pub type DutyLowR = crate::FieldReader<u16>;
#[doc = "Field `DUTY_LOW` writer - TX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
pub type DutyLowW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DUTY_HIGH` reader - TX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
pub type DutyHighR = crate::FieldReader<u16>;
#[doc = "Field `DUTY_HIGH` writer - TX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
pub type DutyHighW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:11 - TX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
#[inline(always)]
pub fn duty_low(&self) -> DutyLowR {
DutyLowR::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bits 16:27 - TX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
#[inline(always)]
pub fn duty_high(&self) -> DutyHighR {
DutyHighR::new(((self.bits >> 16) & 0x0fff) as u16)
}
#[doc = "Bits 28:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:11 - TX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
#[inline(always)]
#[must_use]
pub fn duty_low(&mut self) -> DutyLowW<AudioTxLrckDivSpec> {
DutyLowW::new(self, 0)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<AudioTxLrckDivSpec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bits 16:27 - TX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
#[inline(always)]
#[must_use]
pub fn duty_high(&mut self) -> DutyHighW<AudioTxLrckDivSpec> {
DutyHighW::new(self, 16)
}
#[doc = "Bits 28:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioTxLrckDivSpec> {
RsvdW::new(self, 28)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_lrck_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_lrck_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioTxLrckDivSpec;
impl crate::RegisterSpec for AudioTxLrckDivSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_tx_lrck_div::R`](R) reader structure"]
impl crate::Readable for AudioTxLrckDivSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_tx_lrck_div::W`](W) writer structure"]
impl crate::Writable for AudioTxLrckDivSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_TX_LRCK_DIV to value 0x007d_007d"]
impl crate::Resettable for AudioTxLrckDivSpec {
const RESET_VALUE: u32 = 0x007d_007d;
}
}
#[doc = "RSVD34 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd34`]
module"]
#[doc(alias = "RSVD34")]
pub type Rsvd34 = crate::Reg<rsvd34::Rsvd34Spec>;
#[doc = ""]
pub mod rsvd34 {
#[doc = "Register `RSVD34` reader"]
pub type R = crate::R<Rsvd34Spec>;
#[doc = "Register `RSVD34` writer"]
pub type W = crate::W<Rsvd34Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd34::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd34::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd34Spec;
impl crate::RegisterSpec for Rsvd34Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd34::R`](R) reader structure"]
impl crate::Readable for Rsvd34Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd34::W`](W) writer structure"]
impl crate::Writable for Rsvd34Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD34 to value 0"]
impl crate::Resettable for Rsvd34Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_TX_BCLK_DIV (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_bclk_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_bclk_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_tx_bclk_div`]
module"]
#[doc(alias = "AUDIO_TX_BCLK_DIV")]
pub type AudioTxBclkDiv = crate::Reg<audio_tx_bclk_div::AudioTxBclkDivSpec>;
#[doc = ""]
pub mod audio_tx_bclk_div {
#[doc = "Register `AUDIO_TX_BCLK_DIV` reader"]
pub type R = crate::R<AudioTxBclkDivSpec>;
#[doc = "Register `AUDIO_TX_BCLK_DIV` writer"]
pub type W = crate::W<AudioTxBclkDivSpec>;
#[doc = "Field `DUTY` reader - TX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
pub type DutyR = crate::FieldReader;
#[doc = "Field `DUTY` writer - TX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
pub type DutyW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:5 - TX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
#[inline(always)]
pub fn duty(&self) -> DutyR {
DutyR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:5 - TX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
#[inline(always)]
#[must_use]
pub fn duty(&mut self) -> DutyW<AudioTxBclkDivSpec> {
DutyW::new(self, 0)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioTxBclkDivSpec> {
RsvdW::new(self, 6)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_bclk_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_bclk_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioTxBclkDivSpec;
impl crate::RegisterSpec for AudioTxBclkDivSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_tx_bclk_div::R`](R) reader structure"]
impl crate::Readable for AudioTxBclkDivSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_tx_bclk_div::W`](W) writer structure"]
impl crate::Writable for AudioTxBclkDivSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_TX_BCLK_DIV to value 0"]
impl crate::Resettable for AudioTxBclkDivSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD33 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd33`]
module"]
#[doc(alias = "RSVD33")]
pub type Rsvd33 = crate::Reg<rsvd33::Rsvd33Spec>;
#[doc = ""]
pub mod rsvd33 {
#[doc = "Register `RSVD33` reader"]
pub type R = crate::R<Rsvd33Spec>;
#[doc = "Register `RSVD33` writer"]
pub type W = crate::W<Rsvd33Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd33::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd33::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd33Spec;
impl crate::RegisterSpec for Rsvd33Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd33::R`](R) reader structure"]
impl crate::Readable for Rsvd33Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd33::W`](W) writer structure"]
impl crate::Writable for Rsvd33Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD33 to value 0"]
impl crate::Resettable for Rsvd33Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_TX_FORMAT (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_format::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_format::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_tx_format`]
module"]
#[doc(alias = "AUDIO_TX_FORMAT")]
pub type AudioTxFormat = crate::Reg<audio_tx_format::AudioTxFormatSpec>;
#[doc = ""]
pub mod audio_tx_format {
#[doc = "Register `AUDIO_TX_FORMAT` reader"]
pub type R = crate::R<AudioTxFormatSpec>;
#[doc = "Register `AUDIO_TX_FORMAT` writer"]
pub type W = crate::W<AudioTxFormatSpec>;
#[doc = "Field `PCM_DATA_WIDTH` reader - I2S out pcm data width M >= 16, common value: 16, 18, 20, 22, 24"]
pub type PcmDataWidthR = crate::FieldReader;
#[doc = "Field `PCM_DATA_WIDTH` writer - I2S out pcm data width M >= 16, common value: 16, 18, 20, 22, 24"]
pub type PcmDataWidthW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:4 - I2S out pcm data width M >= 16, common value: 16, 18, 20, 22, 24"]
#[inline(always)]
pub fn pcm_data_width(&self) -> PcmDataWidthR {
PcmDataWidthR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:4 - I2S out pcm data width M >= 16, common value: 16, 18, 20, 22, 24"]
#[inline(always)]
#[must_use]
pub fn pcm_data_width(&mut self) -> PcmDataWidthW<AudioTxFormatSpec> {
PcmDataWidthW::new(self, 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioTxFormatSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_format::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_format::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioTxFormatSpec;
impl crate::RegisterSpec for AudioTxFormatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_tx_format::R`](R) reader structure"]
impl crate::Readable for AudioTxFormatSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_tx_format::W`](W) writer structure"]
impl crate::Writable for AudioTxFormatSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_TX_FORMAT to value 0"]
impl crate::Resettable for AudioTxFormatSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD32 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd32`]
module"]
#[doc(alias = "RSVD32")]
pub type Rsvd32 = crate::Reg<rsvd32::Rsvd32Spec>;
#[doc = ""]
pub mod rsvd32 {
#[doc = "Register `RSVD32` reader"]
pub type R = crate::R<Rsvd32Spec>;
#[doc = "Register `RSVD32` writer"]
pub type W = crate::W<Rsvd32Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd32::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd32::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd32Spec;
impl crate::RegisterSpec for Rsvd32Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd32::R`](R) reader structure"]
impl crate::Readable for Rsvd32Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd32::W`](W) writer structure"]
impl crate::Writable for Rsvd32Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD32 to value 0"]
impl crate::Resettable for Rsvd32Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_SERIAL_TIMING (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_serial_timing::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_serial_timing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_serial_timing`]
module"]
#[doc(alias = "AUDIO_SERIAL_TIMING")]
pub type AudioSerialTiming = crate::Reg<audio_serial_timing::AudioSerialTimingSpec>;
#[doc = ""]
pub mod audio_serial_timing {
#[doc = "Register `AUDIO_SERIAL_TIMING` reader"]
pub type R = crate::R<AudioSerialTimingSpec>;
#[doc = "Register `AUDIO_SERIAL_TIMING` writer"]
pub type W = crate::W<AudioSerialTimingSpec>;
#[doc = "Field `TIMING` reader - 00: I2S mode 01: Left justified 10: right justified 11: reserved"]
pub type TimingR = crate::FieldReader;
#[doc = "Field `TIMING` writer - 00: I2S mode 01: Left justified 10: right justified 11: reserved"]
pub type TimingW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SLAVE_EN` reader - audio code transmit mode select. 0: master mode, 1: slave mode"]
pub type SlaveEnR = crate::BitReader;
#[doc = "Field `SLAVE_EN` writer - audio code transmit mode select. 0: master mode, 1: slave mode"]
pub type SlaveEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LRCK_POL` reader - TX LRCK polarity control. 0: disable TX_LRCK inventor 1: enable TX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
pub type LrckPolR = crate::BitReader;
#[doc = "Field `LRCK_POL` writer - TX LRCK polarity control. 0: disable TX_LRCK inventor 1: enable TX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
pub type LrckPolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:1 - 00: I2S mode 01: Left justified 10: right justified 11: reserved"]
#[inline(always)]
pub fn timing(&self) -> TimingR {
TimingR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - audio code transmit mode select. 0: master mode, 1: slave mode"]
#[inline(always)]
pub fn slave_en(&self) -> SlaveEnR {
SlaveEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - TX LRCK polarity control. 0: disable TX_LRCK inventor 1: enable TX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
#[inline(always)]
pub fn lrck_pol(&self) -> LrckPolR {
LrckPolR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:1 - 00: I2S mode 01: Left justified 10: right justified 11: reserved"]
#[inline(always)]
#[must_use]
pub fn timing(&mut self) -> TimingW<AudioSerialTimingSpec> {
TimingW::new(self, 0)
}
#[doc = "Bit 2 - audio code transmit mode select. 0: master mode, 1: slave mode"]
#[inline(always)]
#[must_use]
pub fn slave_en(&mut self) -> SlaveEnW<AudioSerialTimingSpec> {
SlaveEnW::new(self, 2)
}
#[doc = "Bit 3 - TX LRCK polarity control. 0: disable TX_LRCK inventor 1: enable TX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
#[inline(always)]
#[must_use]
pub fn lrck_pol(&mut self) -> LrckPolW<AudioSerialTimingSpec> {
LrckPolW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioSerialTimingSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_serial_timing::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_serial_timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioSerialTimingSpec;
impl crate::RegisterSpec for AudioSerialTimingSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_serial_timing::R`](R) reader structure"]
impl crate::Readable for AudioSerialTimingSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_serial_timing::W`](W) writer structure"]
impl crate::Writable for AudioSerialTimingSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_SERIAL_TIMING to value 0"]
impl crate::Resettable for AudioSerialTimingSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD31 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd31`]
module"]
#[doc(alias = "RSVD31")]
pub type Rsvd31 = crate::Reg<rsvd31::Rsvd31Spec>;
#[doc = ""]
pub mod rsvd31 {
#[doc = "Register `RSVD31` reader"]
pub type R = crate::R<Rsvd31Spec>;
#[doc = "Register `RSVD31` writer"]
pub type W = crate::W<Rsvd31Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd31::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd31::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd31Spec;
impl crate::RegisterSpec for Rsvd31Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd31::R`](R) reader structure"]
impl crate::Readable for Rsvd31Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd31::W`](W) writer structure"]
impl crate::Writable for Rsvd31Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD31 to value 0"]
impl crate::Resettable for Rsvd31Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_TX_FUNC_EN (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_func_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_func_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_tx_func_en`]
module"]
#[doc(alias = "AUDIO_TX_FUNC_EN")]
pub type AudioTxFuncEn = crate::Reg<audio_tx_func_en::AudioTxFuncEnSpec>;
#[doc = ""]
pub mod audio_tx_func_en {
#[doc = "Register `AUDIO_TX_FUNC_EN` reader"]
pub type R = crate::R<AudioTxFuncEnSpec>;
#[doc = "Register `AUDIO_TX_FUNC_EN` writer"]
pub type W = crate::W<AudioTxFuncEnSpec>;
#[doc = "Field `TX_EN` reader - 1: enable 0:disable"]
pub type TxEnR = crate::BitReader;
#[doc = "Field `TX_EN` writer - 1: enable 0:disable"]
pub type TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX_INTF_SEL` reader - 1: select external tx interface 0: select internal apb tx interface"]
pub type TxIntfSelR = crate::BitReader;
#[doc = "Field `TX_INTF_SEL` writer - 1: select external tx interface 0: select internal apb tx interface"]
pub type TxIntfSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - 1: enable 0:disable"]
#[inline(always)]
pub fn tx_en(&self) -> TxEnR {
TxEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1: select external tx interface 0: select internal apb tx interface"]
#[inline(always)]
pub fn tx_intf_sel(&self) -> TxIntfSelR {
TxIntfSelR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 1: enable 0:disable"]
#[inline(always)]
#[must_use]
pub fn tx_en(&mut self) -> TxEnW<AudioTxFuncEnSpec> {
TxEnW::new(self, 0)
}
#[doc = "Bit 1 - 1: select external tx interface 0: select internal apb tx interface"]
#[inline(always)]
#[must_use]
pub fn tx_intf_sel(&mut self) -> TxIntfSelW<AudioTxFuncEnSpec> {
TxIntfSelW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioTxFuncEnSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_func_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_func_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioTxFuncEnSpec;
impl crate::RegisterSpec for AudioTxFuncEnSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_tx_func_en::R`](R) reader structure"]
impl crate::Readable for AudioTxFuncEnSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_tx_func_en::W`](W) writer structure"]
impl crate::Writable for AudioTxFuncEnSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_TX_FUNC_EN to value 0"]
impl crate::Resettable for AudioTxFuncEnSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD30 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd30`]
module"]
#[doc(alias = "RSVD30")]
pub type Rsvd30 = crate::Reg<rsvd30::Rsvd30Spec>;
#[doc = ""]
pub mod rsvd30 {
#[doc = "Register `RSVD30` reader"]
pub type R = crate::R<Rsvd30Spec>;
#[doc = "Register `RSVD30` writer"]
pub type W = crate::W<Rsvd30Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd30::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd30::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd30Spec;
impl crate::RegisterSpec for Rsvd30Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd30::R`](R) reader structure"]
impl crate::Readable for Rsvd30Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd30::W`](W) writer structure"]
impl crate::Writable for Rsvd30Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD30 to value 0"]
impl crate::Resettable for Rsvd30Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_TX_PAUSE (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_pause::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_pause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_tx_pause`]
module"]
#[doc(alias = "AUDIO_TX_PAUSE")]
pub type AudioTxPause = crate::Reg<audio_tx_pause::AudioTxPauseSpec>;
#[doc = ""]
pub mod audio_tx_pause {
#[doc = "Register `AUDIO_TX_PAUSE` reader"]
pub type R = crate::R<AudioTxPauseSpec>;
#[doc = "Register `AUDIO_TX_PAUSE` writer"]
pub type W = crate::W<AudioTxPauseSpec>;
#[doc = "Field `TX_PAUSE` reader - TX pause control when tx_enable = 1. 1: pause 0: TX work"]
pub type TxPauseR = crate::BitReader;
#[doc = "Field `TX_PAUSE` writer - TX pause control when tx_enable = 1. 1: pause 0: TX work"]
pub type TxPauseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - TX pause control when tx_enable = 1. 1: pause 0: TX work"]
#[inline(always)]
pub fn tx_pause(&self) -> TxPauseR {
TxPauseR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - TX pause control when tx_enable = 1. 1: pause 0: TX work"]
#[inline(always)]
#[must_use]
pub fn tx_pause(&mut self) -> TxPauseW<AudioTxPauseSpec> {
TxPauseW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioTxPauseSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_tx_pause::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_tx_pause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioTxPauseSpec;
impl crate::RegisterSpec for AudioTxPauseSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_tx_pause::R`](R) reader structure"]
impl crate::Readable for AudioTxPauseSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_tx_pause::W`](W) writer structure"]
impl crate::Writable for AudioTxPauseSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_TX_PAUSE to value 0"]
impl crate::Resettable for AudioTxPauseSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD29 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd29`]
module"]
#[doc(alias = "RSVD29")]
pub type Rsvd29 = crate::Reg<rsvd29::Rsvd29Spec>;
#[doc = ""]
pub mod rsvd29 {
#[doc = "Register `RSVD29` reader"]
pub type R = crate::R<Rsvd29Spec>;
#[doc = "Register `RSVD29` writer"]
pub type W = crate::W<Rsvd29Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd29::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd29::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd29Spec;
impl crate::RegisterSpec for Rsvd29Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd29::R`](R) reader structure"]
impl crate::Readable for Rsvd29Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd29::W`](W) writer structure"]
impl crate::Writable for Rsvd29Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD29 to value 0"]
impl crate::Resettable for Rsvd29Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_I2S_SL_MERGE (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_i2s_sl_merge::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_i2s_sl_merge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_i2s_sl_merge`]
module"]
#[doc(alias = "AUDIO_I2S_SL_MERGE")]
pub type AudioI2sSlMerge = crate::Reg<audio_i2s_sl_merge::AudioI2sSlMergeSpec>;
#[doc = ""]
pub mod audio_i2s_sl_merge {
#[doc = "Register `AUDIO_I2S_SL_MERGE` reader"]
pub type R = crate::R<AudioI2sSlMergeSpec>;
#[doc = "Register `AUDIO_I2S_SL_MERGE` writer"]
pub type W = crate::W<AudioI2sSlMergeSpec>;
#[doc = "Field `SLAVE_TIMING_MERGE` reader - when work as an I2S slave, and external I2S master TX/RX share an only BCLK/LRCK, we need set this bit high. 0: I2S slave use separated timing control port. TX_BCLK_IN/TX_LRCK_IN and RX_BCLK/RX_LRCK_IN are separated. 1: I2S slave use the same BCLK/LRCK, the TX_BCLK_IN/TX_LRCK also is used for RX controller."]
pub type SlaveTimingMergeR = crate::BitReader;
#[doc = "Field `SLAVE_TIMING_MERGE` writer - when work as an I2S slave, and external I2S master TX/RX share an only BCLK/LRCK, we need set this bit high. 0: I2S slave use separated timing control port. TX_BCLK_IN/TX_LRCK_IN and RX_BCLK/RX_LRCK_IN are separated. 1: I2S slave use the same BCLK/LRCK, the TX_BCLK_IN/TX_LRCK also is used for RX controller."]
pub type SlaveTimingMergeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - when work as an I2S slave, and external I2S master TX/RX share an only BCLK/LRCK, we need set this bit high. 0: I2S slave use separated timing control port. TX_BCLK_IN/TX_LRCK_IN and RX_BCLK/RX_LRCK_IN are separated. 1: I2S slave use the same BCLK/LRCK, the TX_BCLK_IN/TX_LRCK also is used for RX controller."]
#[inline(always)]
pub fn slave_timing_merge(&self) -> SlaveTimingMergeR {
SlaveTimingMergeR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - when work as an I2S slave, and external I2S master TX/RX share an only BCLK/LRCK, we need set this bit high. 0: I2S slave use separated timing control port. TX_BCLK_IN/TX_LRCK_IN and RX_BCLK/RX_LRCK_IN are separated. 1: I2S slave use the same BCLK/LRCK, the TX_BCLK_IN/TX_LRCK also is used for RX controller."]
#[inline(always)]
#[must_use]
pub fn slave_timing_merge(&mut self) -> SlaveTimingMergeW<AudioI2sSlMergeSpec> {
SlaveTimingMergeW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioI2sSlMergeSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_i2s_sl_merge::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_i2s_sl_merge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioI2sSlMergeSpec;
impl crate::RegisterSpec for AudioI2sSlMergeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_i2s_sl_merge::R`](R) reader structure"]
impl crate::Readable for AudioI2sSlMergeSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_i2s_sl_merge::W`](W) writer structure"]
impl crate::Writable for AudioI2sSlMergeSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_I2S_SL_MERGE to value 0"]
impl crate::Resettable for AudioI2sSlMergeSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD28 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd28`]
module"]
#[doc(alias = "RSVD28")]
pub type Rsvd28 = crate::Reg<rsvd28::Rsvd28Spec>;
#[doc = ""]
pub mod rsvd28 {
#[doc = "Register `RSVD28` reader"]
pub type R = crate::R<Rsvd28Spec>;
#[doc = "Register `RSVD28` writer"]
pub type W = crate::W<Rsvd28Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd28::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd28::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd28Spec;
impl crate::RegisterSpec for Rsvd28Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd28::R`](R) reader structure"]
impl crate::Readable for Rsvd28Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd28::W`](W) writer structure"]
impl crate::Writable for Rsvd28Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD28 to value 0"]
impl crate::Resettable for Rsvd28Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_RX_FUNC_EN (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_func_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_func_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_rx_func_en`]
module"]
#[doc(alias = "AUDIO_RX_FUNC_EN")]
pub type AudioRxFuncEn = crate::Reg<audio_rx_func_en::AudioRxFuncEnSpec>;
#[doc = ""]
pub mod audio_rx_func_en {
#[doc = "Register `AUDIO_RX_FUNC_EN` reader"]
pub type R = crate::R<AudioRxFuncEnSpec>;
#[doc = "Register `AUDIO_RX_FUNC_EN` writer"]
pub type W = crate::W<AudioRxFuncEnSpec>;
#[doc = "Field `RX_EN` reader - 1: enable 0: disable"]
pub type RxEnR = crate::BitReader;
#[doc = "Field `RX_EN` writer - 1: enable 0: disable"]
pub type RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RX_INTF_SEL` reader - 1: select external rx interface 0: select internal apb rx interface"]
pub type RxIntfSelR = crate::BitReader;
#[doc = "Field `RX_INTF_SEL` writer - 1: select external rx interface 0: select internal apb rx interface"]
pub type RxIntfSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - 1: enable 0: disable"]
#[inline(always)]
pub fn rx_en(&self) -> RxEnR {
RxEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1: select external rx interface 0: select internal apb rx interface"]
#[inline(always)]
pub fn rx_intf_sel(&self) -> RxIntfSelR {
RxIntfSelR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 1: enable 0: disable"]
#[inline(always)]
#[must_use]
pub fn rx_en(&mut self) -> RxEnW<AudioRxFuncEnSpec> {
RxEnW::new(self, 0)
}
#[doc = "Bit 1 - 1: select external rx interface 0: select internal apb rx interface"]
#[inline(always)]
#[must_use]
pub fn rx_intf_sel(&mut self) -> RxIntfSelW<AudioRxFuncEnSpec> {
RxIntfSelW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioRxFuncEnSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_func_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_func_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioRxFuncEnSpec;
impl crate::RegisterSpec for AudioRxFuncEnSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_rx_func_en::R`](R) reader structure"]
impl crate::Readable for AudioRxFuncEnSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_rx_func_en::W`](W) writer structure"]
impl crate::Writable for AudioRxFuncEnSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_RX_FUNC_EN to value 0"]
impl crate::Resettable for AudioRxFuncEnSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD27 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd27`]
module"]
#[doc(alias = "RSVD27")]
pub type Rsvd27 = crate::Reg<rsvd27::Rsvd27Spec>;
#[doc = ""]
pub mod rsvd27 {
#[doc = "Register `RSVD27` reader"]
pub type R = crate::R<Rsvd27Spec>;
#[doc = "Register `RSVD27` writer"]
pub type W = crate::W<Rsvd27Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd27::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd27::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd27Spec;
impl crate::RegisterSpec for Rsvd27Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd27::R`](R) reader structure"]
impl crate::Readable for Rsvd27Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd27::W`](W) writer structure"]
impl crate::Writable for Rsvd27Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD27 to value 0"]
impl crate::Resettable for Rsvd27Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_RX_PAUSE (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_pause::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_pause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_rx_pause`]
module"]
#[doc(alias = "AUDIO_RX_PAUSE")]
pub type AudioRxPause = crate::Reg<audio_rx_pause::AudioRxPauseSpec>;
#[doc = ""]
pub mod audio_rx_pause {
#[doc = "Register `AUDIO_RX_PAUSE` reader"]
pub type R = crate::R<AudioRxPauseSpec>;
#[doc = "Register `AUDIO_RX_PAUSE` writer"]
pub type W = crate::W<AudioRxPauseSpec>;
#[doc = "Field `RX_PAUSE` reader - RX pause control when rx_enable = 1. 1: pause 0: RX work"]
pub type RxPauseR = crate::BitReader;
#[doc = "Field `RX_PAUSE` writer - RX pause control when rx_enable = 1. 1: pause 0: RX work"]
pub type RxPauseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - RX pause control when rx_enable = 1. 1: pause 0: RX work"]
#[inline(always)]
pub fn rx_pause(&self) -> RxPauseR {
RxPauseR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - RX pause control when rx_enable = 1. 1: pause 0: RX work"]
#[inline(always)]
#[must_use]
pub fn rx_pause(&mut self) -> RxPauseW<AudioRxPauseSpec> {
RxPauseW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioRxPauseSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_pause::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_pause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioRxPauseSpec;
impl crate::RegisterSpec for AudioRxPauseSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_rx_pause::R`](R) reader structure"]
impl crate::Readable for AudioRxPauseSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_rx_pause::W`](W) writer structure"]
impl crate::Writable for AudioRxPauseSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_RX_PAUSE to value 0"]
impl crate::Resettable for AudioRxPauseSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD26 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd26`]
module"]
#[doc(alias = "RSVD26")]
pub type Rsvd26 = crate::Reg<rsvd26::Rsvd26Spec>;
#[doc = ""]
pub mod rsvd26 {
#[doc = "Register `RSVD26` reader"]
pub type R = crate::R<Rsvd26Spec>;
#[doc = "Register `RSVD26` writer"]
pub type W = crate::W<Rsvd26Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd26::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd26::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd26Spec;
impl crate::RegisterSpec for Rsvd26Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd26::R`](R) reader structure"]
impl crate::Readable for Rsvd26Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd26::W`](W) writer structure"]
impl crate::Writable for Rsvd26Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD26 to value 0"]
impl crate::Resettable for Rsvd26Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_RX_SERIAL_TIMING (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_serial_timing::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_serial_timing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_rx_serial_timing`]
module"]
#[doc(alias = "AUDIO_RX_SERIAL_TIMING")]
pub type AudioRxSerialTiming = crate::Reg<audio_rx_serial_timing::AudioRxSerialTimingSpec>;
#[doc = ""]
pub mod audio_rx_serial_timing {
#[doc = "Register `AUDIO_RX_SERIAL_TIMING` reader"]
pub type R = crate::R<AudioRxSerialTimingSpec>;
#[doc = "Register `AUDIO_RX_SERIAL_TIMING` writer"]
pub type W = crate::W<AudioRxSerialTimingSpec>;
#[doc = "Field `TIMING` reader - 00: I2S 01: Left justified 10: right justified 11: reserved"]
pub type TimingR = crate::FieldReader;
#[doc = "Field `TIMING` writer - 00: I2S 01: Left justified 10: right justified 11: reserved"]
pub type TimingW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SLAVE_EN` reader - audio code receiver mode select. 0: master mode, 1: slave mode"]
pub type SlaveEnR = crate::BitReader;
#[doc = "Field `SLAVE_EN` writer - audio code receiver mode select. 0: master mode, 1: slave mode"]
pub type SlaveEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LRCK_POL` reader - RX LRCK polarity control. 0: disable RX_LRCK inventor 1: enable RX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
pub type LrckPolR = crate::BitReader;
#[doc = "Field `LRCK_POL` writer - RX LRCK polarity control. 0: disable RX_LRCK inventor 1: enable RX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
pub type LrckPolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:1 - 00: I2S 01: Left justified 10: right justified 11: reserved"]
#[inline(always)]
pub fn timing(&self) -> TimingR {
TimingR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - audio code receiver mode select. 0: master mode, 1: slave mode"]
#[inline(always)]
pub fn slave_en(&self) -> SlaveEnR {
SlaveEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RX LRCK polarity control. 0: disable RX_LRCK inventor 1: enable RX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
#[inline(always)]
pub fn lrck_pol(&self) -> LrckPolR {
LrckPolR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:1 - 00: I2S 01: Left justified 10: right justified 11: reserved"]
#[inline(always)]
#[must_use]
pub fn timing(&mut self) -> TimingW<AudioRxSerialTimingSpec> {
TimingW::new(self, 0)
}
#[doc = "Bit 2 - audio code receiver mode select. 0: master mode, 1: slave mode"]
#[inline(always)]
#[must_use]
pub fn slave_en(&mut self) -> SlaveEnW<AudioRxSerialTimingSpec> {
SlaveEnW::new(self, 2)
}
#[doc = "Bit 3 - RX LRCK polarity control. 0: disable RX_LRCK inventor 1: enable RX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih"]
#[inline(always)]
#[must_use]
pub fn lrck_pol(&mut self) -> LrckPolW<AudioRxSerialTimingSpec> {
LrckPolW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioRxSerialTimingSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_serial_timing::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_serial_timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioRxSerialTimingSpec;
impl crate::RegisterSpec for AudioRxSerialTimingSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_rx_serial_timing::R`](R) reader structure"]
impl crate::Readable for AudioRxSerialTimingSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_rx_serial_timing::W`](W) writer structure"]
impl crate::Writable for AudioRxSerialTimingSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_RX_SERIAL_TIMING to value 0x0004_0000"]
impl crate::Resettable for AudioRxSerialTimingSpec {
const RESET_VALUE: u32 = 0x0004_0000;
}
}
#[doc = "RSVD25 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd25`]
module"]
#[doc(alias = "RSVD25")]
pub type Rsvd25 = crate::Reg<rsvd25::Rsvd25Spec>;
#[doc = ""]
pub mod rsvd25 {
#[doc = "Register `RSVD25` reader"]
pub type R = crate::R<Rsvd25Spec>;
#[doc = "Register `RSVD25` writer"]
pub type W = crate::W<Rsvd25Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd25::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd25::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd25Spec;
impl crate::RegisterSpec for Rsvd25Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd25::R`](R) reader structure"]
impl crate::Readable for Rsvd25Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd25::W`](W) writer structure"]
impl crate::Writable for Rsvd25Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD25 to value 0"]
impl crate::Resettable for Rsvd25Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_RX_PCM_DW (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_pcm_dw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_pcm_dw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_rx_pcm_dw`]
module"]
#[doc(alias = "AUDIO_RX_PCM_DW")]
pub type AudioRxPcmDw = crate::Reg<audio_rx_pcm_dw::AudioRxPcmDwSpec>;
#[doc = ""]
pub mod audio_rx_pcm_dw {
#[doc = "Register `AUDIO_RX_PCM_DW` reader"]
pub type R = crate::R<AudioRxPcmDwSpec>;
#[doc = "Register `AUDIO_RX_PCM_DW` writer"]
pub type W = crate::W<AudioRxPcmDwSpec>;
#[doc = "Field `PCM_DATA_WIDTH` reader - For I2S and left justified mode, M can be 8,13,14,16 For right justified mode, M can be 8, 13, 14, 16, 18, 20, 22, 24"]
pub type PcmDataWidthR = crate::FieldReader;
#[doc = "Field `PCM_DATA_WIDTH` writer - For I2S and left justified mode, M can be 8,13,14,16 For right justified mode, M can be 8, 13, 14, 16, 18, 20, 22, 24"]
pub type PcmDataWidthW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:4 - For I2S and left justified mode, M can be 8,13,14,16 For right justified mode, M can be 8, 13, 14, 16, 18, 20, 22, 24"]
#[inline(always)]
pub fn pcm_data_width(&self) -> PcmDataWidthR {
PcmDataWidthR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:4 - For I2S and left justified mode, M can be 8,13,14,16 For right justified mode, M can be 8, 13, 14, 16, 18, 20, 22, 24"]
#[inline(always)]
#[must_use]
pub fn pcm_data_width(&mut self) -> PcmDataWidthW<AudioRxPcmDwSpec> {
PcmDataWidthW::new(self, 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioRxPcmDwSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_pcm_dw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_pcm_dw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioRxPcmDwSpec;
impl crate::RegisterSpec for AudioRxPcmDwSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_rx_pcm_dw::R`](R) reader structure"]
impl crate::Readable for AudioRxPcmDwSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_rx_pcm_dw::W`](W) writer structure"]
impl crate::Writable for AudioRxPcmDwSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_RX_PCM_DW to value 0x10"]
impl crate::Resettable for AudioRxPcmDwSpec {
const RESET_VALUE: u32 = 0x10;
}
}
#[doc = "RSVD24 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd24`]
module"]
#[doc(alias = "RSVD24")]
pub type Rsvd24 = crate::Reg<rsvd24::Rsvd24Spec>;
#[doc = ""]
pub mod rsvd24 {
#[doc = "Register `RSVD24` reader"]
pub type R = crate::R<Rsvd24Spec>;
#[doc = "Register `RSVD24` writer"]
pub type W = crate::W<Rsvd24Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd24::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd24::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd24Spec;
impl crate::RegisterSpec for Rsvd24Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd24::R`](R) reader structure"]
impl crate::Readable for Rsvd24Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd24::W`](W) writer structure"]
impl crate::Writable for Rsvd24Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD24 to value 0"]
impl crate::Resettable for Rsvd24Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_RX_LRCK_DIV (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_lrck_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_lrck_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_rx_lrck_div`]
module"]
#[doc(alias = "AUDIO_RX_LRCK_DIV")]
pub type AudioRxLrckDiv = crate::Reg<audio_rx_lrck_div::AudioRxLrckDivSpec>;
#[doc = ""]
pub mod audio_rx_lrck_div {
#[doc = "Register `AUDIO_RX_LRCK_DIV` reader"]
pub type R = crate::R<AudioRxLrckDivSpec>;
#[doc = "Register `AUDIO_RX_LRCK_DIV` writer"]
pub type W = crate::W<AudioRxLrckDivSpec>;
#[doc = "Field `DUTY_LOW` reader - RX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
pub type DutyLowR = crate::FieldReader<u16>;
#[doc = "Field `DUTY_LOW` writer - RX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
pub type DutyLowW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DUTY_HIGH` reader - RX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
pub type DutyHighR = crate::FieldReader<u16>;
#[doc = "Field `DUTY_HIGH` writer - RX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
pub type DutyHighW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:11 - RX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
#[inline(always)]
pub fn duty_low(&self) -> DutyLowR {
DutyLowR::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bits 16:27 - RX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
#[inline(always)]
pub fn duty_high(&self) -> DutyHighR {
DutyHighR::new(((self.bits >> 16) & 0x0fff) as u16)
}
#[doc = "Bits 28:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:11 - RX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS"]
#[inline(always)]
#[must_use]
pub fn duty_low(&mut self) -> DutyLowW<AudioRxLrckDivSpec> {
DutyLowW::new(self, 0)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<AudioRxLrckDivSpec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bits 16:27 - RX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS"]
#[inline(always)]
#[must_use]
pub fn duty_high(&mut self) -> DutyHighW<AudioRxLrckDivSpec> {
DutyHighW::new(self, 16)
}
#[doc = "Bits 28:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioRxLrckDivSpec> {
RsvdW::new(self, 28)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_lrck_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_lrck_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioRxLrckDivSpec;
impl crate::RegisterSpec for AudioRxLrckDivSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_rx_lrck_div::R`](R) reader structure"]
impl crate::Readable for AudioRxLrckDivSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_rx_lrck_div::W`](W) writer structure"]
impl crate::Writable for AudioRxLrckDivSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_RX_LRCK_DIV to value 0x007d_007d"]
impl crate::Resettable for AudioRxLrckDivSpec {
const RESET_VALUE: u32 = 0x007d_007d;
}
}
#[doc = "RSVD23 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd23`]
module"]
#[doc(alias = "RSVD23")]
pub type Rsvd23 = crate::Reg<rsvd23::Rsvd23Spec>;
#[doc = ""]
pub mod rsvd23 {
#[doc = "Register `RSVD23` reader"]
pub type R = crate::R<Rsvd23Spec>;
#[doc = "Register `RSVD23` writer"]
pub type W = crate::W<Rsvd23Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd23::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd23::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd23Spec;
impl crate::RegisterSpec for Rsvd23Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd23::R`](R) reader structure"]
impl crate::Readable for Rsvd23Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd23::W`](W) writer structure"]
impl crate::Writable for Rsvd23Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD23 to value 0"]
impl crate::Resettable for Rsvd23Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AUDIO_RX_BCLK_DIV (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_bclk_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_bclk_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_rx_bclk_div`]
module"]
#[doc(alias = "AUDIO_RX_BCLK_DIV")]
pub type AudioRxBclkDiv = crate::Reg<audio_rx_bclk_div::AudioRxBclkDivSpec>;
#[doc = ""]
pub mod audio_rx_bclk_div {
#[doc = "Register `AUDIO_RX_BCLK_DIV` reader"]
pub type R = crate::R<AudioRxBclkDivSpec>;
#[doc = "Register `AUDIO_RX_BCLK_DIV` writer"]
pub type W = crate::W<AudioRxBclkDivSpec>;
#[doc = "Field `DUTY` reader - RX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
pub type DutyR = crate::FieldReader<u16>;
#[doc = "Field `DUTY` writer - RX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
pub type DutyW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bits 0:9 - RX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
#[inline(always)]
pub fn duty(&self) -> DutyR {
DutyR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bits 0:9 - RX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs"]
#[inline(always)]
#[must_use]
pub fn duty(&mut self) -> DutyW<AudioRxBclkDivSpec> {
DutyW::new(self, 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AudioRxBclkDivSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_rx_bclk_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_rx_bclk_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AudioRxBclkDivSpec;
impl crate::RegisterSpec for AudioRxBclkDivSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`audio_rx_bclk_div::R`](R) reader structure"]
impl crate::Readable for AudioRxBclkDivSpec {}
#[doc = "`write(|w| ..)` method takes [`audio_rx_bclk_div::W`](W) writer structure"]
impl crate::Writable for AudioRxBclkDivSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AUDIO_RX_BCLK_DIV to value 0x05"]
impl crate::Resettable for AudioRxBclkDivSpec {
const RESET_VALUE: u32 = 0x05;
}
}
#[doc = "RSVD22 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd22`]
module"]
#[doc(alias = "RSVD22")]
pub type Rsvd22 = crate::Reg<rsvd22::Rsvd22Spec>;
#[doc = ""]
pub mod rsvd22 {
#[doc = "Register `RSVD22` reader"]
pub type R = crate::R<Rsvd22Spec>;
#[doc = "Register `RSVD22` writer"]
pub type W = crate::W<Rsvd22Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd22::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd22::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd22Spec;
impl crate::RegisterSpec for Rsvd22Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd22::R`](R) reader structure"]
impl crate::Readable for Rsvd22Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd22::W`](W) writer structure"]
impl crate::Writable for Rsvd22Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD22 to value 0"]
impl crate::Resettable for Rsvd22Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RECORD_DATA_SEL (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`record_data_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`record_data_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@record_data_sel`]
module"]
#[doc(alias = "RECORD_DATA_SEL")]
pub type RecordDataSel = crate::Reg<record_data_sel::RecordDataSelSpec>;
#[doc = ""]
pub mod record_data_sel {
#[doc = "Register `RECORD_DATA_SEL` reader"]
pub type R = crate::R<RecordDataSelSpec>;
#[doc = "Register `RECORD_DATA_SEL` writer"]
pub type W = crate::W<RecordDataSelSpec>;
#[doc = "Field `RS_DATA_SEL` reader - 0: I2S audio recording 1: BT recording"]
pub type RsDataSelR = crate::BitReader;
#[doc = "Field `RS_DATA_SEL` writer - 0: I2S audio recording 1: BT recording"]
pub type RsDataSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - 0: I2S audio recording 1: BT recording"]
#[inline(always)]
pub fn rs_data_sel(&self) -> RsDataSelR {
RsDataSelR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 0: I2S audio recording 1: BT recording"]
#[inline(always)]
#[must_use]
pub fn rs_data_sel(&mut self) -> RsDataSelW<RecordDataSelSpec> {
RsDataSelW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RecordDataSelSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`record_data_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`record_data_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RecordDataSelSpec;
impl crate::RegisterSpec for RecordDataSelSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`record_data_sel::R`](R) reader structure"]
impl crate::Readable for RecordDataSelSpec {}
#[doc = "`write(|w| ..)` method takes [`record_data_sel::W`](W) writer structure"]
impl crate::Writable for RecordDataSelSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RECORD_DATA_SEL to value 0"]
impl crate::Resettable for RecordDataSelSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD21 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd21`]
module"]
#[doc(alias = "RSVD21")]
pub type Rsvd21 = crate::Reg<rsvd21::Rsvd21Spec>;
#[doc = ""]
pub mod rsvd21 {
#[doc = "Register `RSVD21` reader"]
pub type R = crate::R<Rsvd21Spec>;
#[doc = "Register `RSVD21` writer"]
pub type W = crate::W<Rsvd21Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd21::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd21::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd21Spec;
impl crate::RegisterSpec for Rsvd21Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd21::R`](R) reader structure"]
impl crate::Readable for Rsvd21Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd21::W`](W) writer structure"]
impl crate::Writable for Rsvd21Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD21 to value 0"]
impl crate::Resettable for Rsvd21Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RX_RE_SAMPLE_CLK_DIV (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_re_sample_clk_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_re_sample_clk_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_re_sample_clk_div`]
module"]
#[doc(alias = "RX_RE_SAMPLE_CLK_DIV")]
pub type RxReSampleClkDiv = crate::Reg<rx_re_sample_clk_div::RxReSampleClkDivSpec>;
#[doc = ""]
pub mod rx_re_sample_clk_div {
#[doc = "Register `RX_RE_SAMPLE_CLK_DIV` reader"]
pub type R = crate::R<RxReSampleClkDivSpec>;
#[doc = "Register `RX_RE_SAMPLE_CLK_DIV` writer"]
pub type W = crate::W<RxReSampleClkDivSpec>;
#[doc = "Field `RS_DUTY` reader - source PCM sample clock duty cycle: 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS Note: 1)duty_cycle = 12M/FS"]
pub type RsDutyR = crate::FieldReader<u16>;
#[doc = "Field `RS_DUTY` writer - source PCM sample clock duty cycle: 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS Note: 1)duty_cycle = 12M/FS"]
pub type RsDutyW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - source PCM sample clock duty cycle: 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS Note: 1)duty_cycle = 12M/FS"]
#[inline(always)]
pub fn rs_duty(&self) -> RsDutyR {
RsDutyR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - source PCM sample clock duty cycle: 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS Note: 1)duty_cycle = 12M/FS"]
#[inline(always)]
#[must_use]
pub fn rs_duty(&mut self) -> RsDutyW<RxReSampleClkDivSpec> {
RsDutyW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RxReSampleClkDivSpec> {
RsvdW::new(self, 13)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_re_sample_clk_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_re_sample_clk_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxReSampleClkDivSpec;
impl crate::RegisterSpec for RxReSampleClkDivSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rx_re_sample_clk_div::R`](R) reader structure"]
impl crate::Readable for RxReSampleClkDivSpec {}
#[doc = "`write(|w| ..)` method takes [`rx_re_sample_clk_div::W`](W) writer structure"]
impl crate::Writable for RxReSampleClkDivSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RX_RE_SAMPLE_CLK_DIV to value 0x7d"]
impl crate::Resettable for RxReSampleClkDivSpec {
const RESET_VALUE: u32 = 0x7d;
}
}
#[doc = "RSVD20 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd20`]
module"]
#[doc(alias = "RSVD20")]
pub type Rsvd20 = crate::Reg<rsvd20::Rsvd20Spec>;
#[doc = ""]
pub mod rsvd20 {
#[doc = "Register `RSVD20` reader"]
pub type R = crate::R<Rsvd20Spec>;
#[doc = "Register `RSVD20` writer"]
pub type W = crate::W<Rsvd20Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd20::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd20::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd20Spec;
impl crate::RegisterSpec for Rsvd20Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd20::R`](R) reader structure"]
impl crate::Readable for Rsvd20Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd20::W`](W) writer structure"]
impl crate::Writable for Rsvd20Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD20 to value 0"]
impl crate::Resettable for Rsvd20Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RX_RE_SAMPLE (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_re_sample::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_re_sample::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_re_sample`]
module"]
#[doc(alias = "RX_RE_SAMPLE")]
pub type RxReSample = crate::Reg<rx_re_sample::RxReSampleSpec>;
#[doc = ""]
pub mod rx_re_sample {
#[doc = "Register `RX_RE_SAMPLE` reader"]
pub type R = crate::R<RxReSampleSpec>;
#[doc = "Register `RX_RE_SAMPLE` writer"]
pub type W = crate::W<RxReSampleSpec>;
#[doc = "Field `SMOOTH_EN` reader - 0: Disable RX re-sample smooth filter 1: Enable RX re-sample smooth filter"]
pub type SmoothEnR = crate::BitReader;
#[doc = "Field `SMOOTH_EN` writer - 0: Disable RX re-sample smooth filter 1: Enable RX re-sample smooth filter"]
pub type SmoothEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - 0: Disable RX re-sample smooth filter 1: Enable RX re-sample smooth filter"]
#[inline(always)]
pub fn smooth_en(&self) -> SmoothEnR {
SmoothEnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 0: Disable RX re-sample smooth filter 1: Enable RX re-sample smooth filter"]
#[inline(always)]
#[must_use]
pub fn smooth_en(&mut self) -> SmoothEnW<RxReSampleSpec> {
SmoothEnW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RxReSampleSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_re_sample::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_re_sample::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxReSampleSpec;
impl crate::RegisterSpec for RxReSampleSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rx_re_sample::R`](R) reader structure"]
impl crate::Readable for RxReSampleSpec {}
#[doc = "`write(|w| ..)` method takes [`rx_re_sample::W`](W) writer structure"]
impl crate::Writable for RxReSampleSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RX_RE_SAMPLE to value 0"]
impl crate::Resettable for RxReSampleSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD19 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd19`]
module"]
#[doc(alias = "RSVD19")]
pub type Rsvd19 = crate::Reg<rsvd19::Rsvd19Spec>;
#[doc = ""]
pub mod rsvd19 {
#[doc = "Register `RSVD19` reader"]
pub type R = crate::R<Rsvd19Spec>;
#[doc = "Register `RSVD19` writer"]
pub type W = crate::W<Rsvd19Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd19::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd19::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd19Spec;
impl crate::RegisterSpec for Rsvd19Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd19::R`](R) reader structure"]
impl crate::Readable for Rsvd19Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd19::W`](W) writer structure"]
impl crate::Writable for Rsvd19Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD19 to value 0"]
impl crate::Resettable for Rsvd19Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RECORD_FORMAT (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`record_format::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`record_format::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@record_format`]
module"]
#[doc(alias = "RECORD_FORMAT")]
pub type RecordFormat = crate::Reg<record_format::RecordFormatSpec>;
#[doc = ""]
pub mod record_format {
#[doc = "Register `RECORD_FORMAT` reader"]
pub type R = crate::R<RecordFormatSpec>;
#[doc = "Register `RECORD_FORMAT` writer"]
pub type W = crate::W<RecordFormatSpec>;
#[doc = "Field `DW` reader - 0: 8bit 1: 16bit RX fifo data format: ※Mono 8 bit (unsigned): RX FIFO_DIN\\[31:0\\]
= {L3,L2,L1,L0}, each four samples need one FIFO write operation ※Stereo 8 bit (unsigned): RX_FIFO_DIN\\[31:0\\]
= {R1,L1,R0,L0}, each tow samples need one FIFO write operation ※Mono 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {L1,L0}, each two samples need one FIFO write operation ※Stereo 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {R0,L0}, each sample need one FIFO write operation"]
pub type DwR = crate::BitReader;
#[doc = "Field `DW` writer - 0: 8bit 1: 16bit RX fifo data format: ※Mono 8 bit (unsigned): RX FIFO_DIN\\[31:0\\]
= {L3,L2,L1,L0}, each four samples need one FIFO write operation ※Stereo 8 bit (unsigned): RX_FIFO_DIN\\[31:0\\]
= {R1,L1,R0,L0}, each tow samples need one FIFO write operation ※Mono 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {L1,L0}, each two samples need one FIFO write operation ※Stereo 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {R0,L0}, each sample need one FIFO write operation"]
pub type DwW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRACK` reader - 1: mono recording, 0: stereo recording"]
pub type TrackR = crate::BitReader;
#[doc = "Field `TRACK` writer - 1: mono recording, 0: stereo recording"]
pub type TrackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - 0: 8bit 1: 16bit RX fifo data format: ※Mono 8 bit (unsigned): RX FIFO_DIN\\[31:0\\]
= {L3,L2,L1,L0}, each four samples need one FIFO write operation ※Stereo 8 bit (unsigned): RX_FIFO_DIN\\[31:0\\]
= {R1,L1,R0,L0}, each tow samples need one FIFO write operation ※Mono 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {L1,L0}, each two samples need one FIFO write operation ※Stereo 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {R0,L0}, each sample need one FIFO write operation"]
#[inline(always)]
pub fn dw(&self) -> DwR {
DwR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1: mono recording, 0: stereo recording"]
#[inline(always)]
pub fn track(&self) -> TrackR {
TrackR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 0: 8bit 1: 16bit RX fifo data format: ※Mono 8 bit (unsigned): RX FIFO_DIN\\[31:0\\]
= {L3,L2,L1,L0}, each four samples need one FIFO write operation ※Stereo 8 bit (unsigned): RX_FIFO_DIN\\[31:0\\]
= {R1,L1,R0,L0}, each tow samples need one FIFO write operation ※Mono 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {L1,L0}, each two samples need one FIFO write operation ※Stereo 16 bit (Signed 2’s complement): RX_FIFO_DIN\\[31:0\\]
= {R0,L0}, each sample need one FIFO write operation"]
#[inline(always)]
#[must_use]
pub fn dw(&mut self) -> DwW<RecordFormatSpec> {
DwW::new(self, 0)
}
#[doc = "Bit 1 - 1: mono recording, 0: stereo recording"]
#[inline(always)]
#[must_use]
pub fn track(&mut self) -> TrackW<RecordFormatSpec> {
TrackW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RecordFormatSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`record_format::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`record_format::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RecordFormatSpec;
impl crate::RegisterSpec for RecordFormatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`record_format::R`](R) reader structure"]
impl crate::Readable for RecordFormatSpec {}
#[doc = "`write(|w| ..)` method takes [`record_format::W`](W) writer structure"]
impl crate::Writable for RecordFormatSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RECORD_FORMAT to value 0"]
impl crate::Resettable for RecordFormatSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD18 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd18`]
module"]
#[doc(alias = "RSVD18")]
pub type Rsvd18 = crate::Reg<rsvd18::Rsvd18Spec>;
#[doc = ""]
pub mod rsvd18 {
#[doc = "Register `RSVD18` reader"]
pub type R = crate::R<Rsvd18Spec>;
#[doc = "Register `RSVD18` writer"]
pub type W = crate::W<Rsvd18Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd18::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd18::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd18Spec;
impl crate::RegisterSpec for Rsvd18Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd18::R`](R) reader structure"]
impl crate::Readable for Rsvd18Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd18::W`](W) writer structure"]
impl crate::Writable for Rsvd18Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD18 to value 0"]
impl crate::Resettable for Rsvd18Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RX_CH_SEL (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_ch_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ch_sel`]
module"]
#[doc(alias = "RX_CH_SEL")]
pub type RxChSel = crate::Reg<rx_ch_sel::RxChSelSpec>;
#[doc = ""]
pub mod rx_ch_sel {
#[doc = "Register `RX_CH_SEL` reader"]
pub type R = crate::R<RxChSelSpec>;
#[doc = "Register `RX_CH_SEL` writer"]
pub type W = crate::W<RxChSelSpec>;
#[doc = "Field `RIGHT_CHANNEL_SEL` reader - RX re-sampling module setting: 00: RD right = RX right 01: RD right = RX left 10,11: RD right = (RX left + RX right)/2"]
pub type RightChannelSelR = crate::FieldReader;
#[doc = "Field `RIGHT_CHANNEL_SEL` writer - RX re-sampling module setting: 00: RD right = RX right 01: RD right = RX left 10,11: RD right = (RX left + RX right)/2"]
pub type RightChannelSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `LEFT_CHANNEL_SEL` reader - RX re-sampling module setting: 00: RD left = RX left 01: RD left = RX right 10,11: RD left = (RX left + RX right)/2"]
pub type LeftChannelSelR = crate::FieldReader;
#[doc = "Field `LEFT_CHANNEL_SEL` writer - RX re-sampling module setting: 00: RD left = RX left 01: RD left = RX right 10,11: RD left = (RX left + RX right)/2"]
pub type LeftChannelSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:1 - RX re-sampling module setting: 00: RD right = RX right 01: RD right = RX left 10,11: RD right = (RX left + RX right)/2"]
#[inline(always)]
pub fn right_channel_sel(&self) -> RightChannelSelR {
RightChannelSelR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - RX re-sampling module setting: 00: RD left = RX left 01: RD left = RX right 10,11: RD left = (RX left + RX right)/2"]
#[inline(always)]
pub fn left_channel_sel(&self) -> LeftChannelSelR {
LeftChannelSelR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:1 - RX re-sampling module setting: 00: RD right = RX right 01: RD right = RX left 10,11: RD right = (RX left + RX right)/2"]
#[inline(always)]
#[must_use]
pub fn right_channel_sel(&mut self) -> RightChannelSelW<RxChSelSpec> {
RightChannelSelW::new(self, 0)
}
#[doc = "Bits 2:3 - RX re-sampling module setting: 00: RD left = RX left 01: RD left = RX right 10,11: RD left = (RX left + RX right)/2"]
#[inline(always)]
#[must_use]
pub fn left_channel_sel(&mut self) -> LeftChannelSelW<RxChSelSpec> {
LeftChannelSelW::new(self, 2)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RxChSelSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_ch_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxChSelSpec;
impl crate::RegisterSpec for RxChSelSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rx_ch_sel::R`](R) reader structure"]
impl crate::Readable for RxChSelSpec {}
#[doc = "`write(|w| ..)` method takes [`rx_ch_sel::W`](W) writer structure"]
impl crate::Writable for RxChSelSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RX_CH_SEL to value 0"]
impl crate::Resettable for RxChSelSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD17 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd17`]
module"]
#[doc(alias = "RSVD17")]
pub type Rsvd17 = crate::Reg<rsvd17::Rsvd17Spec>;
#[doc = ""]
pub mod rsvd17 {
#[doc = "Register `RSVD17` reader"]
pub type R = crate::R<Rsvd17Spec>;
#[doc = "Register `RSVD17` writer"]
pub type W = crate::W<Rsvd17Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd17::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd17::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd17Spec;
impl crate::RegisterSpec for Rsvd17Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd17::R`](R) reader structure"]
impl crate::Readable for Rsvd17Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd17::W`](W) writer structure"]
impl crate::Writable for Rsvd17Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD17 to value 0"]
impl crate::Resettable for Rsvd17Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BT_PHONE_CTRL (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_phone_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_phone_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_phone_ctrl`]
module"]
#[doc(alias = "BT_PHONE_CTRL")]
pub type BtPhoneCtrl = crate::Reg<bt_phone_ctrl::BtPhoneCtrlSpec>;
#[doc = ""]
pub mod bt_phone_ctrl {
#[doc = "Register `BT_PHONE_CTRL` reader"]
pub type R = crate::R<BtPhoneCtrlSpec>;
#[doc = "Register `BT_PHONE_CTRL` writer"]
pub type W = crate::W<BtPhoneCtrlSpec>;
#[doc = "Field `BT_PH_EN` reader - BT phone enable 0: disable, 1: enable"]
pub type BtPhEnR = crate::BitReader;
#[doc = "Field `BT_PH_EN` writer - BT phone enable 0: disable, 1: enable"]
pub type BtPhEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BT_BACK_MIX_EN` reader - background mixer enable 0: disable, 1: enable"]
pub type BtBackMixEnR = crate::BitReader;
#[doc = "Field `BT_BACK_MIX_EN` writer - background mixer enable 0: disable, 1: enable"]
pub type BtBackMixEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BT_MIX_SMOOTH_FILTER_EN` reader - 0: disable the smooth filter for background mixer 1: enable the smooth filer for background mixer"]
pub type BtMixSmoothFilterEnR = crate::BitReader;
#[doc = "Field `BT_MIX_SMOOTH_FILTER_EN` writer - 0: disable the smooth filter for background mixer 1: enable the smooth filer for background mixer"]
pub type BtMixSmoothFilterEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BT_PATH_SEL` reader - BT path select 0: digital path, 1: analog path"]
pub type BtPathSelR = crate::BitReader;
#[doc = "Field `BT_PATH_SEL` writer - BT path select 0: digital path, 1: analog path"]
pub type BtPathSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BT_PCM_IF_BPS` reader - bypass baseband PCM signals to BT VCI master: 0: no bypass, 1: bypass"]
pub type BtPcmIfBpsR = crate::BitReader;
#[doc = "Field `BT_PCM_IF_BPS` writer - bypass baseband PCM signals to BT VCI master: 0: no bypass, 1: bypass"]
pub type BtPcmIfBpsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BB_I2S_BPS_TO_CDC` reader - bypass baseband I2S interface to audio codec i2s interface 0: no bypass, 1: bypass"]
pub type BbI2sBpsToCdcR = crate::BitReader;
#[doc = "Field `BB_I2S_BPS_TO_CDC` writer - bypass baseband I2S interface to audio codec i2s interface 0: no bypass, 1: bypass"]
pub type BbI2sBpsToCdcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bit 0 - BT phone enable 0: disable, 1: enable"]
#[inline(always)]
pub fn bt_ph_en(&self) -> BtPhEnR {
BtPhEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - background mixer enable 0: disable, 1: enable"]
#[inline(always)]
pub fn bt_back_mix_en(&self) -> BtBackMixEnR {
BtBackMixEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 0: disable the smooth filter for background mixer 1: enable the smooth filer for background mixer"]
#[inline(always)]
pub fn bt_mix_smooth_filter_en(&self) -> BtMixSmoothFilterEnR {
BtMixSmoothFilterEnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - BT path select 0: digital path, 1: analog path"]
#[inline(always)]
pub fn bt_path_sel(&self) -> BtPathSelR {
BtPathSelR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - bypass baseband PCM signals to BT VCI master: 0: no bypass, 1: bypass"]
#[inline(always)]
pub fn bt_pcm_if_bps(&self) -> BtPcmIfBpsR {
BtPcmIfBpsR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - bypass baseband I2S interface to audio codec i2s interface 0: no bypass, 1: bypass"]
#[inline(always)]
pub fn bb_i2s_bps_to_cdc(&self) -> BbI2sBpsToCdcR {
BbI2sBpsToCdcR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - BT phone enable 0: disable, 1: enable"]
#[inline(always)]
#[must_use]
pub fn bt_ph_en(&mut self) -> BtPhEnW<BtPhoneCtrlSpec> {
BtPhEnW::new(self, 0)
}
#[doc = "Bit 1 - background mixer enable 0: disable, 1: enable"]
#[inline(always)]
#[must_use]
pub fn bt_back_mix_en(&mut self) -> BtBackMixEnW<BtPhoneCtrlSpec> {
BtBackMixEnW::new(self, 1)
}
#[doc = "Bit 2 - 0: disable the smooth filter for background mixer 1: enable the smooth filer for background mixer"]
#[inline(always)]
#[must_use]
pub fn bt_mix_smooth_filter_en(&mut self) -> BtMixSmoothFilterEnW<BtPhoneCtrlSpec> {
BtMixSmoothFilterEnW::new(self, 2)
}
#[doc = "Bit 3 - BT path select 0: digital path, 1: analog path"]
#[inline(always)]
#[must_use]
pub fn bt_path_sel(&mut self) -> BtPathSelW<BtPhoneCtrlSpec> {
BtPathSelW::new(self, 3)
}
#[doc = "Bit 4 - bypass baseband PCM signals to BT VCI master: 0: no bypass, 1: bypass"]
#[inline(always)]
#[must_use]
pub fn bt_pcm_if_bps(&mut self) -> BtPcmIfBpsW<BtPhoneCtrlSpec> {
BtPcmIfBpsW::new(self, 4)
}
#[doc = "Bit 5 - bypass baseband I2S interface to audio codec i2s interface 0: no bypass, 1: bypass"]
#[inline(always)]
#[must_use]
pub fn bb_i2s_bps_to_cdc(&mut self) -> BbI2sBpsToCdcW<BtPhoneCtrlSpec> {
BbI2sBpsToCdcW::new(self, 5)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BtPhoneCtrlSpec> {
RsvdW::new(self, 6)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_phone_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_phone_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BtPhoneCtrlSpec;
impl crate::RegisterSpec for BtPhoneCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bt_phone_ctrl::R`](R) reader structure"]
impl crate::Readable for BtPhoneCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`bt_phone_ctrl::W`](W) writer structure"]
impl crate::Writable for BtPhoneCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BT_PHONE_CTRL to value 0"]
impl crate::Resettable for BtPhoneCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD16 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd16`]
module"]
#[doc(alias = "RSVD16")]
pub type Rsvd16 = crate::Reg<rsvd16::Rsvd16Spec>;
#[doc = ""]
pub mod rsvd16 {
#[doc = "Register `RSVD16` reader"]
pub type R = crate::R<Rsvd16Spec>;
#[doc = "Register `RSVD16` writer"]
pub type W = crate::W<Rsvd16Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd16::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd16Spec;
impl crate::RegisterSpec for Rsvd16Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd16::R`](R) reader structure"]
impl crate::Readable for Rsvd16Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd16::W`](W) writer structure"]
impl crate::Writable for Rsvd16Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD16 to value 0"]
impl crate::Resettable for Rsvd16Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BB_PCM_FORMAT (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bb_pcm_format::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bb_pcm_format::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bb_pcm_format`]
module"]
#[doc(alias = "BB_PCM_FORMAT")]
pub type BbPcmFormat = crate::Reg<bb_pcm_format::BbPcmFormatSpec>;
#[doc = ""]
pub mod bb_pcm_format {
#[doc = "Register `BB_PCM_FORMAT` reader"]
pub type R = crate::R<BbPcmFormatSpec>;
#[doc = "Register `BB_PCM_FORMAT` writer"]
pub type W = crate::W<BbPcmFormatSpec>;
#[doc = "Field `PCM_DW` reader - Baseband Master PCM data width (>=8) Common value: 8, 13,14, 16, 18, 20, 22, 24. for I2S/Left Justified/Right Kistified timing, bb_pcm_dw >=16 For PCM timing, only 8, 13, 14, 16 configure value is available."]
pub type PcmDwR = crate::FieldReader;
#[doc = "Field `PCM_DW` writer - Baseband Master PCM data width (>=8) Common value: 8, 13,14, 16, 18, 20, 22, 24. for I2S/Left Justified/Right Kistified timing, bb_pcm_dw >=16 For PCM timing, only 8, 13, 14, 16 configure value is available."]
pub type PcmDwW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `PCM_TIM_SEL` reader - 00: I2S timing, 01: Left Justified 10: Right Justified, 11: PCM timing"]
pub type PcmTimSelR = crate::FieldReader;
#[doc = "Field `PCM_TIM_SEL` writer - 00: I2S timing, 01: Left Justified 10: Right Justified, 11: PCM timing"]
pub type PcmTimSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PCM_SYNC_FLAG` reader - 0: short sync, 1: long sync"]
pub type PcmSyncFlagR = crate::BitReader;
#[doc = "Field `PCM_SYNC_FLAG` writer - 0: short sync, 1: long sync"]
pub type PcmSyncFlagW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCM_LSB_FLAG` reader - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
pub type PcmLsbFlagR = crate::BitReader;
#[doc = "Field `PCM_LSB_FLAG` writer - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
pub type PcmLsbFlagW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2S_LRCK_POL` reader - 0: no bb_i2s_lrck input inventor 1: enable bb_i2s_lrck input inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to high"]
pub type I2sLrckPolR = crate::BitReader;
#[doc = "Field `I2S_LRCK_POL` writer - 0: no bb_i2s_lrck input inventor 1: enable bb_i2s_lrck input inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to high"]
pub type I2sLrckPolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCM_CLK_POL` reader - input BB pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
pub type PcmClkPolR = crate::BitReader;
#[doc = "Field `PCM_CLK_POL` writer - input BB pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
pub type PcmClkPolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bits 0:4 - Baseband Master PCM data width (>=8) Common value: 8, 13,14, 16, 18, 20, 22, 24. for I2S/Left Justified/Right Kistified timing, bb_pcm_dw >=16 For PCM timing, only 8, 13, 14, 16 configure value is available."]
#[inline(always)]
pub fn pcm_dw(&self) -> PcmDwR {
PcmDwR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:6 - 00: I2S timing, 01: Left Justified 10: Right Justified, 11: PCM timing"]
#[inline(always)]
pub fn pcm_tim_sel(&self) -> PcmTimSelR {
PcmTimSelR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - 0: short sync, 1: long sync"]
#[inline(always)]
pub fn pcm_sync_flag(&self) -> PcmSyncFlagR {
PcmSyncFlagR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
#[inline(always)]
pub fn pcm_lsb_flag(&self) -> PcmLsbFlagR {
PcmLsbFlagR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 0: no bb_i2s_lrck input inventor 1: enable bb_i2s_lrck input inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to high"]
#[inline(always)]
pub fn i2s_lrck_pol(&self) -> I2sLrckPolR {
I2sLrckPolR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - input BB pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
#[inline(always)]
pub fn pcm_clk_pol(&self) -> PcmClkPolR {
PcmClkPolR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bits 0:4 - Baseband Master PCM data width (>=8) Common value: 8, 13,14, 16, 18, 20, 22, 24. for I2S/Left Justified/Right Kistified timing, bb_pcm_dw >=16 For PCM timing, only 8, 13, 14, 16 configure value is available."]
#[inline(always)]
#[must_use]
pub fn pcm_dw(&mut self) -> PcmDwW<BbPcmFormatSpec> {
PcmDwW::new(self, 0)
}
#[doc = "Bits 5:6 - 00: I2S timing, 01: Left Justified 10: Right Justified, 11: PCM timing"]
#[inline(always)]
#[must_use]
pub fn pcm_tim_sel(&mut self) -> PcmTimSelW<BbPcmFormatSpec> {
PcmTimSelW::new(self, 5)
}
#[doc = "Bit 7 - 0: short sync, 1: long sync"]
#[inline(always)]
#[must_use]
pub fn pcm_sync_flag(&mut self) -> PcmSyncFlagW<BbPcmFormatSpec> {
PcmSyncFlagW::new(self, 7)
}
#[doc = "Bit 8 - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
#[inline(always)]
#[must_use]
pub fn pcm_lsb_flag(&mut self) -> PcmLsbFlagW<BbPcmFormatSpec> {
PcmLsbFlagW::new(self, 8)
}
#[doc = "Bit 9 - 0: no bb_i2s_lrck input inventor 1: enable bb_i2s_lrck input inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to high"]
#[inline(always)]
#[must_use]
pub fn i2s_lrck_pol(&mut self) -> I2sLrckPolW<BbPcmFormatSpec> {
I2sLrckPolW::new(self, 9)
}
#[doc = "Bit 10 - input BB pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
#[inline(always)]
#[must_use]
pub fn pcm_clk_pol(&mut self) -> PcmClkPolW<BbPcmFormatSpec> {
PcmClkPolW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BbPcmFormatSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bb_pcm_format::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bb_pcm_format::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BbPcmFormatSpec;
impl crate::RegisterSpec for BbPcmFormatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bb_pcm_format::R`](R) reader structure"]
impl crate::Readable for BbPcmFormatSpec {}
#[doc = "`write(|w| ..)` method takes [`bb_pcm_format::W`](W) writer structure"]
impl crate::Writable for BbPcmFormatSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BB_PCM_FORMAT to value 0"]
impl crate::Resettable for BbPcmFormatSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD15 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd15`]
module"]
#[doc(alias = "RSVD15")]
pub type Rsvd15 = crate::Reg<rsvd15::Rsvd15Spec>;
#[doc = ""]
pub mod rsvd15 {
#[doc = "Register `RSVD15` reader"]
pub type R = crate::R<Rsvd15Spec>;
#[doc = "Register `RSVD15` writer"]
pub type W = crate::W<Rsvd15Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd15Spec;
impl crate::RegisterSpec for Rsvd15Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd15::R`](R) reader structure"]
impl crate::Readable for Rsvd15Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd15::W`](W) writer structure"]
impl crate::Writable for Rsvd15Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD15 to value 0"]
impl crate::Resettable for Rsvd15Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BT_PCM_DW (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_dw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_dw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_pcm_dw`]
module"]
#[doc(alias = "BT_PCM_DW")]
pub type BtPcmDw = crate::Reg<bt_pcm_dw::BtPcmDwSpec>;
#[doc = ""]
pub mod bt_pcm_dw {
#[doc = "Register `BT_PCM_DW` reader"]
pub type R = crate::R<BtPcmDwSpec>;
#[doc = "Register `BT_PCM_DW` writer"]
pub type W = crate::W<BtPcmDwSpec>;
#[doc = "Field `DW` reader - BT PCM master data width (>= 8), common value: 8, 13,14, 16"]
pub type DwR = crate::FieldReader;
#[doc = "Field `DW` writer - BT PCM master data width (>= 8), common value: 8, 13,14, 16"]
pub type DwW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:4 - BT PCM master data width (>= 8), common value: 8, 13,14, 16"]
#[inline(always)]
pub fn dw(&self) -> DwR {
DwR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:4 - BT PCM master data width (>= 8), common value: 8, 13,14, 16"]
#[inline(always)]
#[must_use]
pub fn dw(&mut self) -> DwW<BtPcmDwSpec> {
DwW::new(self, 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BtPcmDwSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_dw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_dw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BtPcmDwSpec;
impl crate::RegisterSpec for BtPcmDwSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bt_pcm_dw::R`](R) reader structure"]
impl crate::Readable for BtPcmDwSpec {}
#[doc = "`write(|w| ..)` method takes [`bt_pcm_dw::W`](W) writer structure"]
impl crate::Writable for BtPcmDwSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BT_PCM_DW to value 0x10"]
impl crate::Resettable for BtPcmDwSpec {
const RESET_VALUE: u32 = 0x10;
}
}
#[doc = "RSVD14 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd14`]
module"]
#[doc(alias = "RSVD14")]
pub type Rsvd14 = crate::Reg<rsvd14::Rsvd14Spec>;
#[doc = ""]
pub mod rsvd14 {
#[doc = "Register `RSVD14` reader"]
pub type R = crate::R<Rsvd14Spec>;
#[doc = "Register `RSVD14` writer"]
pub type W = crate::W<Rsvd14Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd14Spec;
impl crate::RegisterSpec for Rsvd14Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd14::R`](R) reader structure"]
impl crate::Readable for Rsvd14Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd14::W`](W) writer structure"]
impl crate::Writable for Rsvd14Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD14 to value 0"]
impl crate::Resettable for Rsvd14Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BT_PCM_TIMING (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_timing::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_timing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_pcm_timing`]
module"]
#[doc(alias = "BT_PCM_TIMING")]
pub type BtPcmTiming = crate::Reg<bt_pcm_timing::BtPcmTimingSpec>;
#[doc = ""]
pub mod bt_pcm_timing {
#[doc = "Register `BT_PCM_TIMING` reader"]
pub type R = crate::R<BtPcmTimingSpec>;
#[doc = "Register `BT_PCM_TIMING` writer"]
pub type W = crate::W<BtPcmTimingSpec>;
#[doc = "Field `LSB_FLAG` reader - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
pub type LsbFlagR = crate::BitReader;
#[doc = "Field `LSB_FLAG` writer - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
pub type LsbFlagW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYNC_FLAG` reader - 0: short sync, 1: long sync"]
pub type SyncFlagR = crate::BitReader;
#[doc = "Field `SYNC_FLAG` writer - 0: short sync, 1: long sync"]
pub type SyncFlagW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_POL` reader - BT PCM master output pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
pub type ClkPolR = crate::BitReader;
#[doc = "Field `CLK_POL` writer - BT PCM master output pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
pub type ClkPolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bit 0 - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
#[inline(always)]
pub fn lsb_flag(&self) -> LsbFlagR {
LsbFlagR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 0: short sync, 1: long sync"]
#[inline(always)]
pub fn sync_flag(&self) -> SyncFlagR {
SyncFlagR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - BT PCM master output pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
#[inline(always)]
pub fn clk_pol(&self) -> ClkPolR {
ClkPolR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Serial PCM data bit sequence. 0: MSB first, 1: LSB first"]
#[inline(always)]
#[must_use]
pub fn lsb_flag(&mut self) -> LsbFlagW<BtPcmTimingSpec> {
LsbFlagW::new(self, 0)
}
#[doc = "Bit 1 - 0: short sync, 1: long sync"]
#[inline(always)]
#[must_use]
pub fn sync_flag(&mut self) -> SyncFlagW<BtPcmTimingSpec> {
SyncFlagW::new(self, 1)
}
#[doc = "Bit 2 - BT PCM master output pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting"]
#[inline(always)]
#[must_use]
pub fn clk_pol(&mut self) -> ClkPolW<BtPcmTimingSpec> {
ClkPolW::new(self, 2)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BtPcmTimingSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_timing::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BtPcmTimingSpec;
impl crate::RegisterSpec for BtPcmTimingSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bt_pcm_timing::R`](R) reader structure"]
impl crate::Readable for BtPcmTimingSpec {}
#[doc = "`write(|w| ..)` method takes [`bt_pcm_timing::W`](W) writer structure"]
impl crate::Writable for BtPcmTimingSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BT_PCM_TIMING to value 0"]
impl crate::Resettable for BtPcmTimingSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD13 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd13`]
module"]
#[doc(alias = "RSVD13")]
pub type Rsvd13 = crate::Reg<rsvd13::Rsvd13Spec>;
#[doc = ""]
pub mod rsvd13 {
#[doc = "Register `RSVD13` reader"]
pub type R = crate::R<Rsvd13Spec>;
#[doc = "Register `RSVD13` writer"]
pub type W = crate::W<Rsvd13Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd13Spec;
impl crate::RegisterSpec for Rsvd13Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd13::R`](R) reader structure"]
impl crate::Readable for Rsvd13Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd13::W`](W) writer structure"]
impl crate::Writable for Rsvd13Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD13 to value 0"]
impl crate::Resettable for Rsvd13Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BT_PCM_CLK_DUTY (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_clk_duty::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_clk_duty::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_pcm_clk_duty`]
module"]
#[doc(alias = "BT_PCM_CLK_DUTY")]
pub type BtPcmClkDuty = crate::Reg<bt_pcm_clk_duty::BtPcmClkDutySpec>;
#[doc = ""]
pub mod bt_pcm_clk_duty {
#[doc = "Register `BT_PCM_CLK_DUTY` reader"]
pub type R = crate::R<BtPcmClkDutySpec>;
#[doc = "Register `BT_PCM_CLK_DUTY` writer"]
pub type W = crate::W<BtPcmClkDutySpec>;
#[doc = "Field `CLK_DUTY` reader - BT_PCM_CLK duty cycle <= (GCLK/(bt_pcm_sync*bt_pcm_dw))"]
pub type ClkDutyR = crate::FieldReader<u16>;
#[doc = "Field `CLK_DUTY` writer - BT_PCM_CLK duty cycle <= (GCLK/(bt_pcm_sync*bt_pcm_dw))"]
pub type ClkDutyW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bits 0:9 - BT_PCM_CLK duty cycle <= (GCLK/(bt_pcm_sync*bt_pcm_dw))"]
#[inline(always)]
pub fn clk_duty(&self) -> ClkDutyR {
ClkDutyR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bits 0:9 - BT_PCM_CLK duty cycle <= (GCLK/(bt_pcm_sync*bt_pcm_dw))"]
#[inline(always)]
#[must_use]
pub fn clk_duty(&mut self) -> ClkDutyW<BtPcmClkDutySpec> {
ClkDutyW::new(self, 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BtPcmClkDutySpec> {
RsvdW::new(self, 10)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_clk_duty::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_clk_duty::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BtPcmClkDutySpec;
impl crate::RegisterSpec for BtPcmClkDutySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bt_pcm_clk_duty::R`](R) reader structure"]
impl crate::Readable for BtPcmClkDutySpec {}
#[doc = "`write(|w| ..)` method takes [`bt_pcm_clk_duty::W`](W) writer structure"]
impl crate::Writable for BtPcmClkDutySpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BT_PCM_CLK_DUTY to value 0"]
impl crate::Resettable for BtPcmClkDutySpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD12 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd12`]
module"]
#[doc(alias = "RSVD12")]
pub type Rsvd12 = crate::Reg<rsvd12::Rsvd12Spec>;
#[doc = ""]
pub mod rsvd12 {
#[doc = "Register `RSVD12` reader"]
pub type R = crate::R<Rsvd12Spec>;
#[doc = "Register `RSVD12` writer"]
pub type W = crate::W<Rsvd12Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd12Spec;
impl crate::RegisterSpec for Rsvd12Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd12::R`](R) reader structure"]
impl crate::Readable for Rsvd12Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd12::W`](W) writer structure"]
impl crate::Writable for Rsvd12Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD12 to value 0"]
impl crate::Resettable for Rsvd12Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BT_PCM_SYNC_DUTY (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_sync_duty::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_sync_duty::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_pcm_sync_duty`]
module"]
#[doc(alias = "BT_PCM_SYNC_DUTY")]
pub type BtPcmSyncDuty = crate::Reg<bt_pcm_sync_duty::BtPcmSyncDutySpec>;
#[doc = ""]
pub mod bt_pcm_sync_duty {
#[doc = "Register `BT_PCM_SYNC_DUTY` reader"]
pub type R = crate::R<BtPcmSyncDutySpec>;
#[doc = "Register `BT_PCM_SYNC_DUTY` writer"]
pub type W = crate::W<BtPcmSyncDutySpec>;
#[doc = "Field `SYNC_DUTY` reader - PCM_SYNC duty cycle (bt_pcm_sync frequency = bt_pclk_clk/bt_pcm_sync_duty)"]
pub type SyncDutyR = crate::FieldReader;
#[doc = "Field `SYNC_DUTY` writer - PCM_SYNC duty cycle (bt_pcm_sync frequency = bt_pclk_clk/bt_pcm_sync_duty)"]
pub type SyncDutyW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:5 - PCM_SYNC duty cycle (bt_pcm_sync frequency = bt_pclk_clk/bt_pcm_sync_duty)"]
#[inline(always)]
pub fn sync_duty(&self) -> SyncDutyR {
SyncDutyR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:5 - PCM_SYNC duty cycle (bt_pcm_sync frequency = bt_pclk_clk/bt_pcm_sync_duty)"]
#[inline(always)]
#[must_use]
pub fn sync_duty(&mut self) -> SyncDutyW<BtPcmSyncDutySpec> {
SyncDutyW::new(self, 0)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BtPcmSyncDutySpec> {
RsvdW::new(self, 6)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_pcm_sync_duty::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_pcm_sync_duty::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BtPcmSyncDutySpec;
impl crate::RegisterSpec for BtPcmSyncDutySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bt_pcm_sync_duty::R`](R) reader structure"]
impl crate::Readable for BtPcmSyncDutySpec {}
#[doc = "`write(|w| ..)` method takes [`bt_pcm_sync_duty::W`](W) writer structure"]
impl crate::Writable for BtPcmSyncDutySpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BT_PCM_SYNC_DUTY to value 0"]
impl crate::Resettable for BtPcmSyncDutySpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD11 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd11`]
module"]
#[doc(alias = "RSVD11")]
pub type Rsvd11 = crate::Reg<rsvd11::Rsvd11Spec>;
#[doc = ""]
pub mod rsvd11 {
#[doc = "Register `RSVD11` reader"]
pub type R = crate::R<Rsvd11Spec>;
#[doc = "Register `RSVD11` writer"]
pub type W = crate::W<Rsvd11Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd11Spec;
impl crate::RegisterSpec for Rsvd11Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd11::R`](R) reader structure"]
impl crate::Readable for Rsvd11Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd11::W`](W) writer structure"]
impl crate::Writable for Rsvd11Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD11 to value 0"]
impl crate::Resettable for Rsvd11Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BT_VOL_CTRL (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_vol_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_vol_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_vol_ctrl`]
module"]
#[doc(alias = "BT_VOL_CTRL")]
pub type BtVolCtrl = crate::Reg<bt_vol_ctrl::BtVolCtrlSpec>;
#[doc = ""]
pub mod bt_vol_ctrl {
#[doc = "Register `BT_VOL_CTRL` reader"]
pub type R = crate::R<BtVolCtrlSpec>;
#[doc = "Register `BT_VOL_CTRL` writer"]
pub type W = crate::W<BtVolCtrlSpec>;
#[doc = "Field `VOL` reader - BT master volume"]
pub type VolR = crate::FieldReader;
#[doc = "Field `VOL` writer - BT master volume"]
pub type VolW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `VOL_ADJ_EN` reader - BT volume adjust enable"]
pub type VolAdjEnR = crate::BitReader;
#[doc = "Field `VOL_ADJ_EN` writer - BT volume adjust enable"]
pub type VolAdjEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:2 - BT master volume"]
#[inline(always)]
pub fn vol(&self) -> VolR {
VolR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - BT volume adjust enable"]
#[inline(always)]
pub fn vol_adj_en(&self) -> VolAdjEnR {
VolAdjEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:2 - BT master volume"]
#[inline(always)]
#[must_use]
pub fn vol(&mut self) -> VolW<BtVolCtrlSpec> {
VolW::new(self, 0)
}
#[doc = "Bit 3 - BT volume adjust enable"]
#[inline(always)]
#[must_use]
pub fn vol_adj_en(&mut self) -> VolAdjEnW<BtVolCtrlSpec> {
VolAdjEnW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BtVolCtrlSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_vol_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_vol_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BtVolCtrlSpec;
impl crate::RegisterSpec for BtVolCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bt_vol_ctrl::R`](R) reader structure"]
impl crate::Readable for BtVolCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`bt_vol_ctrl::W`](W) writer structure"]
impl crate::Writable for BtVolCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BT_VOL_CTRL to value 0"]
impl crate::Resettable for BtVolCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD10 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd10`]
module"]
#[doc(alias = "RSVD10")]
pub type Rsvd10 = crate::Reg<rsvd10::Rsvd10Spec>;
#[doc = ""]
pub mod rsvd10 {
#[doc = "Register `RSVD10` reader"]
pub type R = crate::R<Rsvd10Spec>;
#[doc = "Register `RSVD10` writer"]
pub type W = crate::W<Rsvd10Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd10Spec;
impl crate::RegisterSpec for Rsvd10Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd10::R`](R) reader structure"]
impl crate::Readable for Rsvd10Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd10::W`](W) writer structure"]
impl crate::Writable for Rsvd10Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD10 to value 0"]
impl crate::Resettable for Rsvd10Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INT_MASK (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_mask`]
module"]
#[doc(alias = "INT_MASK")]
pub type IntMask = crate::Reg<int_mask::IntMaskSpec>;
#[doc = ""]
pub mod int_mask {
#[doc = "Register `INT_MASK` reader"]
pub type R = crate::R<IntMaskSpec>;
#[doc = "Register `INT_MASK` writer"]
pub type W = crate::W<IntMaskSpec>;
#[doc = "Field `RX_FIFO_INT_MASK` reader - Interrupt mask for RX FIFO push overflow, high active"]
pub type RxFifoIntMaskR = crate::BitReader;
#[doc = "Field `RX_FIFO_INT_MASK` writer - Interrupt mask for RX FIFO push overflow, high active"]
pub type RxFifoIntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX_FIFO_INT_MASK` reader - Interrupt mask for TX FIFO pop underflow, high active"]
pub type TxFifoIntMaskR = crate::BitReader;
#[doc = "Field `TX_FIFO_INT_MASK` writer - Interrupt mask for TX FIFO pop underflow, high active"]
pub type TxFifoIntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - Interrupt mask for RX FIFO push overflow, high active"]
#[inline(always)]
pub fn rx_fifo_int_mask(&self) -> RxFifoIntMaskR {
RxFifoIntMaskR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt mask for TX FIFO pop underflow, high active"]
#[inline(always)]
pub fn tx_fifo_int_mask(&self) -> TxFifoIntMaskR {
TxFifoIntMaskR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Interrupt mask for RX FIFO push overflow, high active"]
#[inline(always)]
#[must_use]
pub fn rx_fifo_int_mask(&mut self) -> RxFifoIntMaskW<IntMaskSpec> {
RxFifoIntMaskW::new(self, 0)
}
#[doc = "Bit 1 - Interrupt mask for TX FIFO pop underflow, high active"]
#[inline(always)]
#[must_use]
pub fn tx_fifo_int_mask(&mut self) -> TxFifoIntMaskW<IntMaskSpec> {
TxFifoIntMaskW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IntMaskSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntMaskSpec;
impl crate::RegisterSpec for IntMaskSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_mask::R`](R) reader structure"]
impl crate::Readable for IntMaskSpec {}
#[doc = "`write(|w| ..)` method takes [`int_mask::W`](W) writer structure"]
impl crate::Writable for IntMaskSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_MASK to value 0x03"]
impl crate::Resettable for IntMaskSpec {
const RESET_VALUE: u32 = 0x03;
}
}
#[doc = "RSVD9 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd9`]
module"]
#[doc(alias = "RSVD9")]
pub type Rsvd9 = crate::Reg<rsvd9::Rsvd9Spec>;
#[doc = ""]
pub mod rsvd9 {
#[doc = "Register `RSVD9` reader"]
pub type R = crate::R<Rsvd9Spec>;
#[doc = "Register `RSVD9` writer"]
pub type W = crate::W<Rsvd9Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd9Spec;
impl crate::RegisterSpec for Rsvd9Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd9::R`](R) reader structure"]
impl crate::Readable for Rsvd9Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd9::W`](W) writer structure"]
impl crate::Writable for Rsvd9Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD9 to value 0"]
impl crate::Resettable for Rsvd9Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INT_STATUS (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`]
module"]
#[doc(alias = "INT_STATUS")]
pub type IntStatus = crate::Reg<int_status::IntStatusSpec>;
#[doc = ""]
pub mod int_status {
#[doc = "Register `INT_STATUS` reader"]
pub type R = crate::R<IntStatusSpec>;
#[doc = "Register `INT_STATUS` writer"]
pub type W = crate::W<IntStatusSpec>;
#[doc = "Field `RX_FIFO_OVERFLOW` reader - RX FIFO push overflow"]
pub type RxFifoOverflowR = crate::BitReader;
#[doc = "Field `RX_FIFO_OVERFLOW` writer - RX FIFO push overflow"]
pub type RxFifoOverflowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX_FIFO_UNDERFLOW` reader - TX FIFO pop underflow"]
pub type TxFifoUnderflowR = crate::BitReader;
#[doc = "Field `TX_FIFO_UNDERFLOW` writer - TX FIFO pop underflow"]
pub type TxFifoUnderflowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - RX FIFO push overflow"]
#[inline(always)]
pub fn rx_fifo_overflow(&self) -> RxFifoOverflowR {
RxFifoOverflowR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TX FIFO pop underflow"]
#[inline(always)]
pub fn tx_fifo_underflow(&self) -> TxFifoUnderflowR {
TxFifoUnderflowR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - RX FIFO push overflow"]
#[inline(always)]
#[must_use]
pub fn rx_fifo_overflow(&mut self) -> RxFifoOverflowW<IntStatusSpec> {
RxFifoOverflowW::new(self, 0)
}
#[doc = "Bit 1 - TX FIFO pop underflow"]
#[inline(always)]
#[must_use]
pub fn tx_fifo_underflow(&mut self) -> TxFifoUnderflowW<IntStatusSpec> {
TxFifoUnderflowW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IntStatusSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntStatusSpec;
impl crate::RegisterSpec for IntStatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_status::R`](R) reader structure"]
impl crate::Readable for IntStatusSpec {}
#[doc = "`write(|w| ..)` method takes [`int_status::W`](W) writer structure"]
impl crate::Writable for IntStatusSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_STATUS to value 0"]
impl crate::Resettable for IntStatusSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd8`]
module"]
#[doc(alias = "RSVD8")]
pub type Rsvd8 = crate::Reg<rsvd8::Rsvd8Spec>;
#[doc = ""]
pub mod rsvd8 {
#[doc = "Register `RSVD8` reader"]
pub type R = crate::R<Rsvd8Spec>;
#[doc = "Register `RSVD8` writer"]
pub type W = crate::W<Rsvd8Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd8Spec;
impl crate::RegisterSpec for Rsvd8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd8::R`](R) reader structure"]
impl crate::Readable for Rsvd8Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd8::W`](W) writer structure"]
impl crate::Writable for Rsvd8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD8 to value 0"]
impl crate::Resettable for Rsvd8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_DMA_ENTRY (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_dma_entry::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_dma_entry::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_dma_entry`]
module"]
#[doc(alias = "TX_DMA_ENTRY")]
pub type TxDmaEntry = crate::Reg<tx_dma_entry::TxDmaEntrySpec>;
#[doc = ""]
pub mod tx_dma_entry {
#[doc = "Register `TX_DMA_ENTRY` reader"]
pub type R = crate::R<TxDmaEntrySpec>;
#[doc = "Register `TX_DMA_ENTRY` writer"]
pub type W = crate::W<TxDmaEntrySpec>;
#[doc = "Field `TX_DMA_ENTRY` reader - TX DMA entry"]
pub type TxDmaEntryR = crate::FieldReader<u32>;
#[doc = "Field `TX_DMA_ENTRY` writer - TX DMA entry"]
pub type TxDmaEntryW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - TX DMA entry"]
#[inline(always)]
pub fn tx_dma_entry(&self) -> TxDmaEntryR {
TxDmaEntryR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - TX DMA entry"]
#[inline(always)]
#[must_use]
pub fn tx_dma_entry(&mut self) -> TxDmaEntryW<TxDmaEntrySpec> {
TxDmaEntryW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_dma_entry::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_dma_entry::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxDmaEntrySpec;
impl crate::RegisterSpec for TxDmaEntrySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_dma_entry::R`](R) reader structure"]
impl crate::Readable for TxDmaEntrySpec {}
#[doc = "`write(|w| ..)` method takes [`tx_dma_entry::W`](W) writer structure"]
impl crate::Writable for TxDmaEntrySpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_DMA_ENTRY to value 0"]
impl crate::Resettable for TxDmaEntrySpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd7`]
module"]
#[doc(alias = "RSVD7")]
pub type Rsvd7 = crate::Reg<rsvd7::Rsvd7Spec>;
#[doc = ""]
pub mod rsvd7 {
#[doc = "Register `RSVD7` reader"]
pub type R = crate::R<Rsvd7Spec>;
#[doc = "Register `RSVD7` writer"]
pub type W = crate::W<Rsvd7Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd7Spec;
impl crate::RegisterSpec for Rsvd7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd7::R`](R) reader structure"]
impl crate::Readable for Rsvd7Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd7::W`](W) writer structure"]
impl crate::Writable for Rsvd7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD7 to value 0"]
impl crate::Resettable for Rsvd7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RX_DMA_ENTRY (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_dma_entry::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_dma_entry::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_dma_entry`]
module"]
#[doc(alias = "RX_DMA_ENTRY")]
pub type RxDmaEntry = crate::Reg<rx_dma_entry::RxDmaEntrySpec>;
#[doc = ""]
pub mod rx_dma_entry {
#[doc = "Register `RX_DMA_ENTRY` reader"]
pub type R = crate::R<RxDmaEntrySpec>;
#[doc = "Register `RX_DMA_ENTRY` writer"]
pub type W = crate::W<RxDmaEntrySpec>;
#[doc = "Field `RX_DMA_ENTRY` reader - RX DMA entry"]
pub type RxDmaEntryR = crate::FieldReader<u32>;
#[doc = "Field `RX_DMA_ENTRY` writer - RX DMA entry"]
pub type RxDmaEntryW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - RX DMA entry"]
#[inline(always)]
pub fn rx_dma_entry(&self) -> RxDmaEntryR {
RxDmaEntryR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - RX DMA entry"]
#[inline(always)]
#[must_use]
pub fn rx_dma_entry(&mut self) -> RxDmaEntryW<RxDmaEntrySpec> {
RxDmaEntryW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_dma_entry::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_dma_entry::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxDmaEntrySpec;
impl crate::RegisterSpec for RxDmaEntrySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rx_dma_entry::R`](R) reader structure"]
impl crate::Readable for RxDmaEntrySpec {}
#[doc = "`write(|w| ..)` method takes [`rx_dma_entry::W`](W) writer structure"]
impl crate::Writable for RxDmaEntrySpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RX_DMA_ENTRY to value 0"]
impl crate::Resettable for RxDmaEntrySpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd6`]
module"]
#[doc(alias = "RSVD6")]
pub type Rsvd6 = crate::Reg<rsvd6::Rsvd6Spec>;
#[doc = ""]
pub mod rsvd6 {
#[doc = "Register `RSVD6` reader"]
pub type R = crate::R<Rsvd6Spec>;
#[doc = "Register `RSVD6` writer"]
pub type W = crate::W<Rsvd6Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd6Spec;
impl crate::RegisterSpec for Rsvd6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd6::R`](R) reader structure"]
impl crate::Readable for Rsvd6Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd6::W`](W) writer structure"]
impl crate::Writable for Rsvd6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD6 to value 0"]
impl crate::Resettable for Rsvd6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DMA_MASK (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_mask`]
module"]
#[doc(alias = "DMA_MASK")]
pub type DmaMask = crate::Reg<dma_mask::DmaMaskSpec>;
#[doc = ""]
pub mod dma_mask {
#[doc = "Register `DMA_MASK` reader"]
pub type R = crate::R<DmaMaskSpec>;
#[doc = "Register `DMA_MASK` writer"]
pub type W = crate::W<DmaMaskSpec>;
#[doc = "Field `RX_DMA_MASK` reader - RX DMA mask enable:1: mask0: do not mask"]
pub type RxDmaMaskR = crate::BitReader;
#[doc = "Field `RX_DMA_MASK` writer - RX DMA mask enable:1: mask0: do not mask"]
pub type RxDmaMaskW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX_DMA_MASK` reader - TX DMA mask enable:1: mask0: do not mask"]
pub type TxDmaMaskR = crate::BitReader;
#[doc = "Field `TX_DMA_MASK` writer - TX DMA mask enable:1: mask0: do not mask"]
pub type TxDmaMaskW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - RX DMA mask enable:1: mask0: do not mask"]
#[inline(always)]
pub fn rx_dma_mask(&self) -> RxDmaMaskR {
RxDmaMaskR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TX DMA mask enable:1: mask0: do not mask"]
#[inline(always)]
pub fn tx_dma_mask(&self) -> TxDmaMaskR {
TxDmaMaskR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - RX DMA mask enable:1: mask0: do not mask"]
#[inline(always)]
#[must_use]
pub fn rx_dma_mask(&mut self) -> RxDmaMaskW<DmaMaskSpec> {
RxDmaMaskW::new(self, 0)
}
#[doc = "Bit 1 - TX DMA mask enable:1: mask0: do not mask"]
#[inline(always)]
#[must_use]
pub fn tx_dma_mask(&mut self) -> TxDmaMaskW<DmaMaskSpec> {
TxDmaMaskW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DmaMaskSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DmaMaskSpec;
impl crate::RegisterSpec for DmaMaskSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma_mask::R`](R) reader structure"]
impl crate::Readable for DmaMaskSpec {}
#[doc = "`write(|w| ..)` method takes [`dma_mask::W`](W) writer structure"]
impl crate::Writable for DmaMaskSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DMA_MASK to value 0x03"]
impl crate::Resettable for DmaMaskSpec {
const RESET_VALUE: u32 = 0x03;
}
}
#[doc = "RSVD5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd5`]
module"]
#[doc(alias = "RSVD5")]
pub type Rsvd5 = crate::Reg<rsvd5::Rsvd5Spec>;
#[doc = ""]
pub mod rsvd5 {
#[doc = "Register `RSVD5` reader"]
pub type R = crate::R<Rsvd5Spec>;
#[doc = "Register `RSVD5` writer"]
pub type W = crate::W<Rsvd5Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd5Spec;
impl crate::RegisterSpec for Rsvd5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd5::R`](R) reader structure"]
impl crate::Readable for Rsvd5Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd5::W`](W) writer structure"]
impl crate::Writable for Rsvd5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD5 to value 0"]
impl crate::Resettable for Rsvd5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DEBUG_LOOP (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_loop::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug_loop::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_loop`]
module"]
#[doc(alias = "DEBUG_LOOP")]
pub type DebugLoop = crate::Reg<debug_loop::DebugLoopSpec>;
#[doc = ""]
pub mod debug_loop {
#[doc = "Register `DEBUG_LOOP` reader"]
pub type R = crate::R<DebugLoopSpec>;
#[doc = "Register `DEBUG_LOOP` writer"]
pub type W = crate::W<DebugLoopSpec>;
#[doc = "Field `DA2AD_LOOP_BACK` reader - TX-->RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI"]
pub type Da2adLoopBackR = crate::BitReader;
#[doc = "Field `DA2AD_LOOP_BACK` writer - TX-->RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI"]
pub type Da2adLoopBackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AD2DA_LOOP_BACK` reader - RX-->TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input"]
pub type Ad2daLoopBackR = crate::BitReader;
#[doc = "Field `AD2DA_LOOP_BACK` writer - RX-->TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input"]
pub type Ad2daLoopBackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SP_CLK_SEL` reader - clock select 0: xtal clock 1: pll clock"]
pub type SpClkSelR = crate::BitReader;
#[doc = "Field `SP_CLK_SEL` writer - clock select 0: xtal clock 1: pll clock"]
pub type SpClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `SP_CLK_DIV_UPDATE` reader - update sp clock divider"]
pub type SpClkDivUpdateR = crate::BitReader;
#[doc = "Field `SP_CLK_DIV_UPDATE` writer - update sp clock divider"]
pub type SpClkDivUpdateW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `SP_CLK_DIV` reader - sp clock divider value"]
pub type SpClkDivR = crate::FieldReader;
#[doc = "Field `SP_CLK_DIV` writer - sp clock divider value"]
pub type SpClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bit 0 - TX-->RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI"]
#[inline(always)]
pub fn da2ad_loop_back(&self) -> Da2adLoopBackR {
Da2adLoopBackR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RX-->TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input"]
#[inline(always)]
pub fn ad2da_loop_back(&self) -> Ad2daLoopBackR {
Ad2daLoopBackR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - clock select 0: xtal clock 1: pll clock"]
#[inline(always)]
pub fn sp_clk_sel(&self) -> SpClkSelR {
SpClkSelR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 3) & 0x1f) as u8)
}
#[doc = "Bit 8 - update sp clock divider"]
#[inline(always)]
pub fn sp_clk_div_update(&self) -> SpClkDivUpdateR {
SpClkDivUpdateR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 9) & 0x7f) as u8)
}
#[doc = "Bits 16:23 - sp clock divider value"]
#[inline(always)]
pub fn sp_clk_div(&self) -> SpClkDivR {
SpClkDivR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0 - TX-->RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI"]
#[inline(always)]
#[must_use]
pub fn da2ad_loop_back(&mut self) -> Da2adLoopBackW<DebugLoopSpec> {
Da2adLoopBackW::new(self, 0)
}
#[doc = "Bit 1 - RX-->TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input"]
#[inline(always)]
#[must_use]
pub fn ad2da_loop_back(&mut self) -> Ad2daLoopBackW<DebugLoopSpec> {
Ad2daLoopBackW::new(self, 1)
}
#[doc = "Bit 2 - clock select 0: xtal clock 1: pll clock"]
#[inline(always)]
#[must_use]
pub fn sp_clk_sel(&mut self) -> SpClkSelW<DebugLoopSpec> {
SpClkSelW::new(self, 2)
}
#[doc = "Bits 3:7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<DebugLoopSpec> {
Rsvd3W::new(self, 3)
}
#[doc = "Bit 8 - update sp clock divider"]
#[inline(always)]
#[must_use]
pub fn sp_clk_div_update(&mut self) -> SpClkDivUpdateW<DebugLoopSpec> {
SpClkDivUpdateW::new(self, 8)
}
#[doc = "Bits 9:15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DebugLoopSpec> {
Rsvd2W::new(self, 9)
}
#[doc = "Bits 16:23 - sp clock divider value"]
#[inline(always)]
#[must_use]
pub fn sp_clk_div(&mut self) -> SpClkDivW<DebugLoopSpec> {
SpClkDivW::new(self, 16)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DebugLoopSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_loop::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug_loop::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DebugLoopSpec;
impl crate::RegisterSpec for DebugLoopSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`debug_loop::R`](R) reader structure"]
impl crate::Readable for DebugLoopSpec {}
#[doc = "`write(|w| ..)` method takes [`debug_loop::W`](W) writer structure"]
impl crate::Writable for DebugLoopSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DEBUG_LOOP to value 0"]
impl crate::Resettable for DebugLoopSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd4`]
module"]
#[doc(alias = "RSVD4")]
pub type Rsvd4 = crate::Reg<rsvd4::Rsvd4Spec>;
#[doc = ""]
pub mod rsvd4 {
#[doc = "Register `RSVD4` reader"]
pub type R = crate::R<Rsvd4Spec>;
#[doc = "Register `RSVD4` writer"]
pub type W = crate::W<Rsvd4Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd4Spec;
impl crate::RegisterSpec for Rsvd4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd4::R`](R) reader structure"]
impl crate::Readable for Rsvd4Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd4::W`](W) writer structure"]
impl crate::Writable for Rsvd4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD4 to value 0"]
impl crate::Resettable for Rsvd4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO_STATUS (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_status`]
module"]
#[doc(alias = "FIFO_STATUS")]
pub type FifoStatus = crate::Reg<fifo_status::FifoStatusSpec>;
#[doc = ""]
pub mod fifo_status {
#[doc = "Register `FIFO_STATUS` reader"]
pub type R = crate::R<FifoStatusSpec>;
#[doc = "Register `FIFO_STATUS` writer"]
pub type W = crate::W<FifoStatusSpec>;
#[doc = "Field `FIFO_STATUS_OUT` reader - FIFO Status output: Bit \\[7:0\\]
= {tx_full,tx_empty,tx_almost_full,tx_almost_empty,rx_full,rx_empty,rx_almost_full,rx_almost_empty}"]
pub type FifoStatusOutR = crate::FieldReader;
#[doc = "Field `FIFO_STATUS_OUT` writer - FIFO Status output: Bit \\[7:0\\]
= {tx_full,tx_empty,tx_almost_full,tx_almost_empty,rx_full,rx_empty,rx_almost_full,rx_almost_empty}"]
pub type FifoStatusOutW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - FIFO Status output: Bit \\[7:0\\]
= {tx_full,tx_empty,tx_almost_full,tx_almost_empty,rx_full,rx_empty,rx_almost_full,rx_almost_empty}"]
#[inline(always)]
pub fn fifo_status_out(&self) -> FifoStatusOutR {
FifoStatusOutR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - FIFO Status output: Bit \\[7:0\\]
= {tx_full,tx_empty,tx_almost_full,tx_almost_empty,rx_full,rx_empty,rx_almost_full,rx_almost_empty}"]
#[inline(always)]
#[must_use]
pub fn fifo_status_out(&mut self) -> FifoStatusOutW<FifoStatusSpec> {
FifoStatusOutW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoStatusSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoStatusSpec;
impl crate::RegisterSpec for FifoStatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo_status::R`](R) reader structure"]
impl crate::Readable for FifoStatusSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo_status::W`](W) writer structure"]
impl crate::Writable for FifoStatusSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO_STATUS to value 0"]
impl crate::Resettable for FifoStatusSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd3`]
module"]
#[doc(alias = "RSVD3")]
pub type Rsvd3 = crate::Reg<rsvd3::Rsvd3Spec>;
#[doc = ""]
pub mod rsvd3 {
#[doc = "Register `RSVD3` reader"]
pub type R = crate::R<Rsvd3Spec>;
#[doc = "Register `RSVD3` writer"]
pub type W = crate::W<Rsvd3Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd3Spec;
impl crate::RegisterSpec for Rsvd3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd3::R`](R) reader structure"]
impl crate::Readable for Rsvd3Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd3::W`](W) writer structure"]
impl crate::Writable for Rsvd3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD3 to value 0"]
impl crate::Resettable for Rsvd3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_EQUALIZER_EN (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_equalizer_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_equalizer_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_equalizer_en`]
module"]
#[doc(alias = "TX_EQUALIZER_EN")]
pub type TxEqualizerEn = crate::Reg<tx_equalizer_en::TxEqualizerEnSpec>;
#[doc = ""]
pub mod tx_equalizer_en {
#[doc = "Register `TX_EQUALIZER_EN` reader"]
pub type R = crate::R<TxEqualizerEnSpec>;
#[doc = "Register `TX_EQUALIZER_EN` writer"]
pub type W = crate::W<TxEqualizerEnSpec>;
#[doc = "Field `TX_EQUALIZER_EN` reader - 0: Disable TX equalizer 1: Enable TX equalizer equalizer is not implemented"]
pub type TxEqualizerEnR = crate::BitReader;
#[doc = "Field `TX_EQUALIZER_EN` writer - 0: Disable TX equalizer 1: Enable TX equalizer equalizer is not implemented"]
pub type TxEqualizerEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - 0: Disable TX equalizer 1: Enable TX equalizer equalizer is not implemented"]
#[inline(always)]
pub fn tx_equalizer_en(&self) -> TxEqualizerEnR {
TxEqualizerEnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 0: Disable TX equalizer 1: Enable TX equalizer equalizer is not implemented"]
#[inline(always)]
#[must_use]
pub fn tx_equalizer_en(&mut self) -> TxEqualizerEnW<TxEqualizerEnSpec> {
TxEqualizerEnW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxEqualizerEnSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_equalizer_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_equalizer_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxEqualizerEnSpec;
impl crate::RegisterSpec for TxEqualizerEnSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_equalizer_en::R`](R) reader structure"]
impl crate::Readable for TxEqualizerEnSpec {}
#[doc = "`write(|w| ..)` method takes [`tx_equalizer_en::W`](W) writer structure"]
impl crate::Writable for TxEqualizerEnSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_EQUALIZER_EN to value 0"]
impl crate::Resettable for TxEqualizerEnSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd2`]
module"]
#[doc(alias = "RSVD2")]
pub type Rsvd2 = crate::Reg<rsvd2::Rsvd2Spec>;
#[doc = ""]
pub mod rsvd2 {
#[doc = "Register `RSVD2` reader"]
pub type R = crate::R<Rsvd2Spec>;
#[doc = "Register `RSVD2` writer"]
pub type W = crate::W<Rsvd2Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd2Spec;
impl crate::RegisterSpec for Rsvd2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd2::R`](R) reader structure"]
impl crate::Readable for Rsvd2Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd2::W`](W) writer structure"]
impl crate::Writable for Rsvd2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD2 to value 0"]
impl crate::Resettable for Rsvd2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_EQUALIZER_GAIN1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_equalizer_gain1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_equalizer_gain1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_equalizer_gain1`]
module"]
#[doc(alias = "TX_EQUALIZER_GAIN1")]
pub type TxEqualizerGain1 = crate::Reg<tx_equalizer_gain1::TxEqualizerGain1Spec>;
#[doc = ""]
pub mod tx_equalizer_gain1 {
#[doc = "Register `TX_EQUALIZER_GAIN1` reader"]
pub type R = crate::R<TxEqualizerGain1Spec>;
#[doc = "Register `TX_EQUALIZER_GAIN1` writer"]
pub type W = crate::W<TxEqualizerGain1Spec>;
#[doc = "Field `BAND1_GAIN` reader - "]
pub type Band1GainR = crate::FieldReader;
#[doc = "Field `BAND1_GAIN` writer - "]
pub type Band1GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND2_GAIN` reader - "]
pub type Band2GainR = crate::FieldReader;
#[doc = "Field `BAND2_GAIN` writer - "]
pub type Band2GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND3_GAIN` reader - "]
pub type Band3GainR = crate::FieldReader;
#[doc = "Field `BAND3_GAIN` writer - "]
pub type Band3GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND4_GAIN` reader - "]
pub type Band4GainR = crate::FieldReader;
#[doc = "Field `BAND4_GAIN` writer - "]
pub type Band4GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND5_GAIN` reader - "]
pub type Band5GainR = crate::FieldReader;
#[doc = "Field `BAND5_GAIN` writer - "]
pub type Band5GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND6_GAIN` reader - "]
pub type Band6GainR = crate::FieldReader;
#[doc = "Field `BAND6_GAIN` writer - "]
pub type Band6GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn band1_gain(&self) -> Band1GainR {
Band1GainR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9"]
#[inline(always)]
pub fn band2_gain(&self) -> Band2GainR {
Band2GainR::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:14"]
#[inline(always)]
pub fn band3_gain(&self) -> Band3GainR {
Band3GainR::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bits 15:19"]
#[inline(always)]
pub fn band4_gain(&self) -> Band4GainR {
Band4GainR::new(((self.bits >> 15) & 0x1f) as u8)
}
#[doc = "Bits 20:24"]
#[inline(always)]
pub fn band5_gain(&self) -> Band5GainR {
Band5GainR::new(((self.bits >> 20) & 0x1f) as u8)
}
#[doc = "Bits 25:29"]
#[inline(always)]
pub fn band6_gain(&self) -> Band6GainR {
Band6GainR::new(((self.bits >> 25) & 0x1f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn band1_gain(&mut self) -> Band1GainW<TxEqualizerGain1Spec> {
Band1GainW::new(self, 0)
}
#[doc = "Bits 5:9"]
#[inline(always)]
#[must_use]
pub fn band2_gain(&mut self) -> Band2GainW<TxEqualizerGain1Spec> {
Band2GainW::new(self, 5)
}
#[doc = "Bits 10:14"]
#[inline(always)]
#[must_use]
pub fn band3_gain(&mut self) -> Band3GainW<TxEqualizerGain1Spec> {
Band3GainW::new(self, 10)
}
#[doc = "Bits 15:19"]
#[inline(always)]
#[must_use]
pub fn band4_gain(&mut self) -> Band4GainW<TxEqualizerGain1Spec> {
Band4GainW::new(self, 15)
}
#[doc = "Bits 20:24"]
#[inline(always)]
#[must_use]
pub fn band5_gain(&mut self) -> Band5GainW<TxEqualizerGain1Spec> {
Band5GainW::new(self, 20)
}
#[doc = "Bits 25:29"]
#[inline(always)]
#[must_use]
pub fn band6_gain(&mut self) -> Band6GainW<TxEqualizerGain1Spec> {
Band6GainW::new(self, 25)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxEqualizerGain1Spec> {
RsvdW::new(self, 30)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_equalizer_gain1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_equalizer_gain1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxEqualizerGain1Spec;
impl crate::RegisterSpec for TxEqualizerGain1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_equalizer_gain1::R`](R) reader structure"]
impl crate::Readable for TxEqualizerGain1Spec {}
#[doc = "`write(|w| ..)` method takes [`tx_equalizer_gain1::W`](W) writer structure"]
impl crate::Writable for TxEqualizerGain1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_EQUALIZER_GAIN1 to value 0"]
impl crate::Resettable for TxEqualizerGain1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TX_EQUALIZER_GAIN2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_equalizer_gain2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_equalizer_gain2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_equalizer_gain2`]
module"]
#[doc(alias = "TX_EQUALIZER_GAIN2")]
pub type TxEqualizerGain2 = crate::Reg<tx_equalizer_gain2::TxEqualizerGain2Spec>;
#[doc = ""]
pub mod tx_equalizer_gain2 {
#[doc = "Register `TX_EQUALIZER_GAIN2` reader"]
pub type R = crate::R<TxEqualizerGain2Spec>;
#[doc = "Register `TX_EQUALIZER_GAIN2` writer"]
pub type W = crate::W<TxEqualizerGain2Spec>;
#[doc = "Field `BAND7_GAIN` reader - "]
pub type Band7GainR = crate::FieldReader;
#[doc = "Field `BAND7_GAIN` writer - "]
pub type Band7GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND8_GAIN` reader - "]
pub type Band8GainR = crate::FieldReader;
#[doc = "Field `BAND8_GAIN` writer - "]
pub type Band8GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND9_GAIN` reader - "]
pub type Band9GainR = crate::FieldReader;
#[doc = "Field `BAND9_GAIN` writer - "]
pub type Band9GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `BAND10_GAIN` reader - "]
pub type Band10GainR = crate::FieldReader;
#[doc = "Field `BAND10_GAIN` writer - "]
pub type Band10GainW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn band7_gain(&self) -> Band7GainR {
Band7GainR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9"]
#[inline(always)]
pub fn band8_gain(&self) -> Band8GainR {
Band8GainR::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:14"]
#[inline(always)]
pub fn band9_gain(&self) -> Band9GainR {
Band9GainR::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bits 15:19"]
#[inline(always)]
pub fn band10_gain(&self) -> Band10GainR {
Band10GainR::new(((self.bits >> 15) & 0x1f) as u8)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn band7_gain(&mut self) -> Band7GainW<TxEqualizerGain2Spec> {
Band7GainW::new(self, 0)
}
#[doc = "Bits 5:9"]
#[inline(always)]
#[must_use]
pub fn band8_gain(&mut self) -> Band8GainW<TxEqualizerGain2Spec> {
Band8GainW::new(self, 5)
}
#[doc = "Bits 10:14"]
#[inline(always)]
#[must_use]
pub fn band9_gain(&mut self) -> Band9GainW<TxEqualizerGain2Spec> {
Band9GainW::new(self, 10)
}
#[doc = "Bits 15:19"]
#[inline(always)]
#[must_use]
pub fn band10_gain(&mut self) -> Band10GainW<TxEqualizerGain2Spec> {
Band10GainW::new(self, 15)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TxEqualizerGain2Spec> {
RsvdW::new(self, 20)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_equalizer_gain2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_equalizer_gain2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxEqualizerGain2Spec;
impl crate::RegisterSpec for TxEqualizerGain2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_equalizer_gain2::R`](R) reader structure"]
impl crate::Readable for TxEqualizerGain2Spec {}
#[doc = "`write(|w| ..)` method takes [`tx_equalizer_gain2::W`](W) writer structure"]
impl crate::Writable for TxEqualizerGain2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TX_EQUALIZER_GAIN2 to value 0"]
impl crate::Resettable for TxEqualizerGain2Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "HPSYS_CFG"]
pub struct HpsysCfg {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for HpsysCfg {}
impl HpsysCfg {
#[doc = r"Pointer to the register block"]
pub const PTR: *const hpsys_cfg::RegisterBlock = 0x5000_b000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const hpsys_cfg::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for HpsysCfg {
type Target = hpsys_cfg::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for HpsysCfg {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HpsysCfg").finish()
}
}
#[doc = "HPSYS_CFG"]
pub mod hpsys_cfg {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
bmr: Bmr,
idr: Idr,
rsvd2: Rsvd2,
_reserved3: [u8; 0x04],
syscr: Syscr,
rtc_tr: RtcTr,
rtc_dr: RtcDr,
rsvd1: Rsvd1,
_reserved7: [u8; 0x28],
i2c1_pinr: I2c1Pinr,
i2c2_pinr: I2c2Pinr,
i2c3_pinr: I2c3Pinr,
i2c4_pinr: I2c4Pinr,
usart1_pinr: Usart1Pinr,
usart2_pinr: Usart2Pinr,
usart3_pinr: Usart3Pinr,
gptim1_pinr: Gptim1Pinr,
gptim2_pinr: Gptim2Pinr,
etr_pinr: EtrPinr,
lptim1_pinr: Lptim1Pinr,
lptim2_pinr: Lptim2Pinr,
atim1_pinr1: Atim1Pinr1,
atim1_pinr2: Atim1Pinr2,
atim1_pinr3: Atim1Pinr3,
}
impl RegisterBlock {
#[doc = "0x00 - Boot Mode Register"]
#[inline(always)]
pub const fn bmr(&self) -> &Bmr {
&self.bmr
}
#[doc = "0x04 - ID Register"]
#[inline(always)]
pub const fn idr(&self) -> &Idr {
&self.idr
}
#[doc = "0x08 - "]
#[inline(always)]
pub const fn rsvd2(&self) -> &Rsvd2 {
&self.rsvd2
}
#[doc = "0x10 - System Configure Register"]
#[inline(always)]
pub const fn syscr(&self) -> &Syscr {
&self.syscr
}
#[doc = "0x14 - RTC Time Register"]
#[inline(always)]
pub const fn rtc_tr(&self) -> &RtcTr {
&self.rtc_tr
}
#[doc = "0x18 - RTC Date Register"]
#[inline(always)]
pub const fn rtc_dr(&self) -> &RtcDr {
&self.rtc_dr
}
#[doc = "0x1c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x48 - I2C1 Pin Register"]
#[inline(always)]
pub const fn i2c1_pinr(&self) -> &I2c1Pinr {
&self.i2c1_pinr
}
#[doc = "0x4c - I2C2 Pin Register"]
#[inline(always)]
pub const fn i2c2_pinr(&self) -> &I2c2Pinr {
&self.i2c2_pinr
}
#[doc = "0x50 - I2C3 Pin Register"]
#[inline(always)]
pub const fn i2c3_pinr(&self) -> &I2c3Pinr {
&self.i2c3_pinr
}
#[doc = "0x54 - I2C4 Pin Register"]
#[inline(always)]
pub const fn i2c4_pinr(&self) -> &I2c4Pinr {
&self.i2c4_pinr
}
#[doc = "0x58 - USART1 Pin Register"]
#[inline(always)]
pub const fn usart1_pinr(&self) -> &Usart1Pinr {
&self.usart1_pinr
}
#[doc = "0x5c - USART2 Pin Register"]
#[inline(always)]
pub const fn usart2_pinr(&self) -> &Usart2Pinr {
&self.usart2_pinr
}
#[doc = "0x60 - USART3 Pin Register"]
#[inline(always)]
pub const fn usart3_pinr(&self) -> &Usart3Pinr {
&self.usart3_pinr
}
#[doc = "0x64 - GPTIM1 Pin Register"]
#[inline(always)]
pub const fn gptim1_pinr(&self) -> &Gptim1Pinr {
&self.gptim1_pinr
}
#[doc = "0x68 - GPTIM2 Pin Register"]
#[inline(always)]
pub const fn gptim2_pinr(&self) -> &Gptim2Pinr {
&self.gptim2_pinr
}
#[doc = "0x6c - GPTIM ETR Pin Register"]
#[inline(always)]
pub const fn etr_pinr(&self) -> &EtrPinr {
&self.etr_pinr
}
#[doc = "0x70 - LPTIM1 Pin Register"]
#[inline(always)]
pub const fn lptim1_pinr(&self) -> &Lptim1Pinr {
&self.lptim1_pinr
}
#[doc = "0x74 - LPTIM2 Pin Register"]
#[inline(always)]
pub const fn lptim2_pinr(&self) -> &Lptim2Pinr {
&self.lptim2_pinr
}
#[doc = "0x78 - ATIM1 Pin Register 1"]
#[inline(always)]
pub const fn atim1_pinr1(&self) -> &Atim1Pinr1 {
&self.atim1_pinr1
}
#[doc = "0x7c - ATIM1 Pin Register 2"]
#[inline(always)]
pub const fn atim1_pinr2(&self) -> &Atim1Pinr2 {
&self.atim1_pinr2
}
#[doc = "0x80 - ATIM1 Pin Register 3"]
#[inline(always)]
pub const fn atim1_pinr3(&self) -> &Atim1Pinr3 {
&self.atim1_pinr3
}
}
#[doc = "BMR (rw) register accessor: Boot Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmr`]
module"]
#[doc(alias = "BMR")]
pub type Bmr = crate::Reg<bmr::BmrSpec>;
#[doc = "Boot Mode Register"]
pub mod bmr {
#[doc = "Register `BMR` reader"]
pub type R = crate::R<BmrSpec>;
#[doc = "Register `BMR` writer"]
pub type W = crate::W<BmrSpec>;
#[doc = "Field `BOOT_MODE` reader - 0 - normal mode, 1 - download mode"]
pub type BootModeR = crate::BitReader;
#[doc = "Field `BOOT_MODE` writer - 0 - normal mode, 1 - download mode"]
pub type BootModeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - 0 - normal mode, 1 - download mode"]
#[inline(always)]
pub fn boot_mode(&self) -> BootModeR {
BootModeR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 0 - normal mode, 1 - download mode"]
#[inline(always)]
#[must_use]
pub fn boot_mode(&mut self) -> BootModeW<BmrSpec> {
BootModeW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BmrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "Boot Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BmrSpec;
impl crate::RegisterSpec for BmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bmr::R`](R) reader structure"]
impl crate::Readable for BmrSpec {}
#[doc = "`write(|w| ..)` method takes [`bmr::W`](W) writer structure"]
impl crate::Writable for BmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BMR to value 0"]
impl crate::Resettable for BmrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IDR (rw) register accessor: ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idr`]
module"]
#[doc(alias = "IDR")]
pub type Idr = crate::Reg<idr::IdrSpec>;
#[doc = "ID Register"]
pub mod idr {
#[doc = "Register `IDR` reader"]
pub type R = crate::R<IdrSpec>;
#[doc = "Register `IDR` writer"]
pub type W = crate::W<IdrSpec>;
#[doc = "Field `REVID` reader - Revision ID"]
pub type RevidR = crate::FieldReader;
#[doc = "Field `REVID` writer - Revision ID"]
pub type RevidW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `PID` reader - Package ID"]
pub type PidR = crate::FieldReader;
#[doc = "Field `PID` writer - Package ID"]
pub type PidW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `CID` reader - Chip ID"]
pub type CidR = crate::FieldReader;
#[doc = "Field `CID` writer - Chip ID"]
pub type CidW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SID` reader - Series ID"]
pub type SidR = crate::FieldReader;
#[doc = "Field `SID` writer - Series ID"]
pub type SidW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Revision ID"]
#[inline(always)]
pub fn revid(&self) -> RevidR {
RevidR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Package ID"]
#[inline(always)]
pub fn pid(&self) -> PidR {
PidR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Chip ID"]
#[inline(always)]
pub fn cid(&self) -> CidR {
CidR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Series ID"]
#[inline(always)]
pub fn sid(&self) -> SidR {
SidR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Revision ID"]
#[inline(always)]
#[must_use]
pub fn revid(&mut self) -> RevidW<IdrSpec> {
RevidW::new(self, 0)
}
#[doc = "Bits 8:15 - Package ID"]
#[inline(always)]
#[must_use]
pub fn pid(&mut self) -> PidW<IdrSpec> {
PidW::new(self, 8)
}
#[doc = "Bits 16:23 - Chip ID"]
#[inline(always)]
#[must_use]
pub fn cid(&mut self) -> CidW<IdrSpec> {
CidW::new(self, 16)
}
#[doc = "Bits 24:31 - Series ID"]
#[inline(always)]
#[must_use]
pub fn sid(&mut self) -> SidW<IdrSpec> {
SidW::new(self, 24)
}
}
#[doc = "ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IdrSpec;
impl crate::RegisterSpec for IdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`idr::R`](R) reader structure"]
impl crate::Readable for IdrSpec {}
#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"]
impl crate::Writable for IdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IDR to value 0"]
impl crate::Resettable for IdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd2`]
module"]
#[doc(alias = "RSVD2")]
pub type Rsvd2 = crate::Reg<rsvd2::Rsvd2Spec>;
#[doc = ""]
pub mod rsvd2 {
#[doc = "Register `RSVD2` reader"]
pub type R = crate::R<Rsvd2Spec>;
#[doc = "Register `RSVD2` writer"]
pub type W = crate::W<Rsvd2Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd2Spec;
impl crate::RegisterSpec for Rsvd2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd2::R`](R) reader structure"]
impl crate::Readable for Rsvd2Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd2::W`](W) writer structure"]
impl crate::Writable for Rsvd2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD2 to value 0"]
impl crate::Resettable for Rsvd2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SYSCR (rw) register accessor: System Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syscr`]
module"]
#[doc(alias = "SYSCR")]
pub type Syscr = crate::Reg<syscr::SyscrSpec>;
#[doc = "System Configure Register"]
pub mod syscr {
#[doc = "Register `SYSCR` reader"]
pub type R = crate::R<SyscrSpec>;
#[doc = "Register `SYSCR` writer"]
pub type W = crate::W<SyscrSpec>;
#[doc = "Field `WDT1_REBOOT` reader - If set to 1, WDT1 reset will reboot the whole chip"]
pub type Wdt1RebootR = crate::BitReader;
#[doc = "Field `WDT1_REBOOT` writer - If set to 1, WDT1 reset will reboot the whole chip"]
pub type Wdt1RebootW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SDNAND` reader - If set to 1, MPI2 memory space is allocated to SDMMC1"]
pub type SdnandR = crate::BitReader;
#[doc = "Field `SDNAND` writer - If set to 1, MPI2 memory space is allocated to SDMMC1"]
pub type SdnandW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LDO_VSEL` reader - select work mode 0: D0/D1 1: S0/S1"]
pub type LdoVselR = crate::BitReader;
#[doc = "Field `LDO_VSEL` writer - select work mode 0: D0/D1 1: S0/S1"]
pub type LdoVselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bit 0 - If set to 1, WDT1 reset will reboot the whole chip"]
#[inline(always)]
pub fn wdt1_reboot(&self) -> Wdt1RebootR {
Wdt1RebootR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - If set to 1, MPI2 memory space is allocated to SDMMC1"]
#[inline(always)]
pub fn sdnand(&self) -> SdnandR {
SdnandR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - select work mode 0: D0/D1 1: S0/S1"]
#[inline(always)]
pub fn ldo_vsel(&self) -> LdoVselR {
LdoVselR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - If set to 1, WDT1 reset will reboot the whole chip"]
#[inline(always)]
#[must_use]
pub fn wdt1_reboot(&mut self) -> Wdt1RebootW<SyscrSpec> {
Wdt1RebootW::new(self, 0)
}
#[doc = "Bit 1 - If set to 1, MPI2 memory space is allocated to SDMMC1"]
#[inline(always)]
#[must_use]
pub fn sdnand(&mut self) -> SdnandW<SyscrSpec> {
SdnandW::new(self, 1)
}
#[doc = "Bit 2 - select work mode 0: D0/D1 1: S0/S1"]
#[inline(always)]
#[must_use]
pub fn ldo_vsel(&mut self) -> LdoVselW<SyscrSpec> {
LdoVselW::new(self, 2)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SyscrSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "System Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyscrSpec;
impl crate::RegisterSpec for SyscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`syscr::R`](R) reader structure"]
impl crate::Readable for SyscrSpec {}
#[doc = "`write(|w| ..)` method takes [`syscr::W`](W) writer structure"]
impl crate::Writable for SyscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SYSCR to value 0"]
impl crate::Resettable for SyscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RTC_TR (rw) register accessor: RTC Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_tr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_tr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_tr`]
module"]
#[doc(alias = "RTC_TR")]
pub type RtcTr = crate::Reg<rtc_tr::RtcTrSpec>;
#[doc = "RTC Time Register"]
pub mod rtc_tr {
#[doc = "Register `RTC_TR` reader"]
pub type R = crate::R<RtcTrSpec>;
#[doc = "Register `RTC_TR` writer"]
pub type W = crate::W<RtcTrSpec>;
#[doc = "Field `SS` reader - "]
pub type SsR = crate::FieldReader<u16>;
#[doc = "Field `SS` writer - "]
pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SU` reader - "]
pub type SuR = crate::FieldReader;
#[doc = "Field `SU` writer - "]
pub type SuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `ST` reader - "]
pub type StR = crate::FieldReader;
#[doc = "Field `ST` writer - "]
pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `MNU` reader - "]
pub type MnuR = crate::FieldReader;
#[doc = "Field `MNU` writer - "]
pub type MnuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MNT` reader - "]
pub type MntR = crate::FieldReader;
#[doc = "Field `MNT` writer - "]
pub type MntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `HU` reader - "]
pub type HuR = crate::FieldReader;
#[doc = "Field `HU` writer - "]
pub type HuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `HT` reader - "]
pub type HtR = crate::FieldReader;
#[doc = "Field `HT` writer - "]
pub type HtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PM` reader - "]
pub type PmR = crate::BitReader;
#[doc = "Field `PM` writer - "]
pub type PmW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn ss(&self) -> SsR {
SsR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:14"]
#[inline(always)]
pub fn su(&self) -> SuR {
SuR::new(((self.bits >> 11) & 0x0f) as u8)
}
#[doc = "Bits 15:17"]
#[inline(always)]
pub fn st(&self) -> StR {
StR::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:21"]
#[inline(always)]
pub fn mnu(&self) -> MnuR {
MnuR::new(((self.bits >> 18) & 0x0f) as u8)
}
#[doc = "Bits 22:24"]
#[inline(always)]
pub fn mnt(&self) -> MntR {
MntR::new(((self.bits >> 22) & 7) as u8)
}
#[doc = "Bits 25:28"]
#[inline(always)]
pub fn hu(&self) -> HuR {
HuR::new(((self.bits >> 25) & 0x0f) as u8)
}
#[doc = "Bits 29:30"]
#[inline(always)]
pub fn ht(&self) -> HtR {
HtR::new(((self.bits >> 29) & 3) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn pm(&self) -> PmR {
PmR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn ss(&mut self) -> SsW<RtcTrSpec> {
SsW::new(self, 0)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RtcTrSpec> {
RsvdW::new(self, 10)
}
#[doc = "Bits 11:14"]
#[inline(always)]
#[must_use]
pub fn su(&mut self) -> SuW<RtcTrSpec> {
SuW::new(self, 11)
}
#[doc = "Bits 15:17"]
#[inline(always)]
#[must_use]
pub fn st(&mut self) -> StW<RtcTrSpec> {
StW::new(self, 15)
}
#[doc = "Bits 18:21"]
#[inline(always)]
#[must_use]
pub fn mnu(&mut self) -> MnuW<RtcTrSpec> {
MnuW::new(self, 18)
}
#[doc = "Bits 22:24"]
#[inline(always)]
#[must_use]
pub fn mnt(&mut self) -> MntW<RtcTrSpec> {
MntW::new(self, 22)
}
#[doc = "Bits 25:28"]
#[inline(always)]
#[must_use]
pub fn hu(&mut self) -> HuW<RtcTrSpec> {
HuW::new(self, 25)
}
#[doc = "Bits 29:30"]
#[inline(always)]
#[must_use]
pub fn ht(&mut self) -> HtW<RtcTrSpec> {
HtW::new(self, 29)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn pm(&mut self) -> PmW<RtcTrSpec> {
PmW::new(self, 31)
}
}
#[doc = "RTC Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_tr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_tr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcTrSpec;
impl crate::RegisterSpec for RtcTrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_tr::R`](R) reader structure"]
impl crate::Readable for RtcTrSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_tr::W`](W) writer structure"]
impl crate::Writable for RtcTrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTC_TR to value 0"]
impl crate::Resettable for RtcTrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RTC_DR (rw) register accessor: RTC Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_dr`]
module"]
#[doc(alias = "RTC_DR")]
pub type RtcDr = crate::Reg<rtc_dr::RtcDrSpec>;
#[doc = "RTC Date Register"]
pub mod rtc_dr {
#[doc = "Register `RTC_DR` reader"]
pub type R = crate::R<RtcDrSpec>;
#[doc = "Register `RTC_DR` writer"]
pub type W = crate::W<RtcDrSpec>;
#[doc = "Field `DU` reader - "]
pub type DuR = crate::FieldReader;
#[doc = "Field `DU` writer - "]
pub type DuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DT` reader - "]
pub type DtR = crate::FieldReader;
#[doc = "Field `DT` writer - "]
pub type DtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MU` reader - "]
pub type MuR = crate::FieldReader;
#[doc = "Field `MU` writer - "]
pub type MuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MT` reader - "]
pub type MtR = crate::BitReader;
#[doc = "Field `MT` writer - "]
pub type MtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WD` reader - "]
pub type WdR = crate::FieldReader;
#[doc = "Field `WD` writer - "]
pub type WdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `YU` reader - "]
pub type YuR = crate::FieldReader;
#[doc = "Field `YU` writer - "]
pub type YuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `YT` reader - "]
pub type YtR = crate::FieldReader;
#[doc = "Field `YT` writer - "]
pub type YtW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CB` reader - "]
pub type CbR = crate::BitReader;
#[doc = "Field `CB` writer - "]
pub type CbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `ERR` reader - "]
pub type ErrR = crate::BitReader;
#[doc = "Field `ERR` writer - "]
pub type ErrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn du(&self) -> DuR {
DuR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn dt(&self) -> DtR {
DtR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn mu(&self) -> MuR {
MuR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn mt(&self) -> MtR {
MtR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15"]
#[inline(always)]
pub fn wd(&self) -> WdR {
WdR::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn yu(&self) -> YuR {
YuR::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23"]
#[inline(always)]
pub fn yt(&self) -> YtR {
YtR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn cb(&self) -> CbR {
CbR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 25) & 0x3f) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn err(&self) -> ErrR {
ErrR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn du(&mut self) -> DuW<RtcDrSpec> {
DuW::new(self, 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn dt(&mut self) -> DtW<RtcDrSpec> {
DtW::new(self, 4)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<RtcDrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn mu(&mut self) -> MuW<RtcDrSpec> {
MuW::new(self, 8)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn mt(&mut self) -> MtW<RtcDrSpec> {
MtW::new(self, 12)
}
#[doc = "Bits 13:15"]
#[inline(always)]
#[must_use]
pub fn wd(&mut self) -> WdW<RtcDrSpec> {
WdW::new(self, 13)
}
#[doc = "Bits 16:19"]
#[inline(always)]
#[must_use]
pub fn yu(&mut self) -> YuW<RtcDrSpec> {
YuW::new(self, 16)
}
#[doc = "Bits 20:23"]
#[inline(always)]
#[must_use]
pub fn yt(&mut self) -> YtW<RtcDrSpec> {
YtW::new(self, 20)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn cb(&mut self) -> CbW<RtcDrSpec> {
CbW::new(self, 24)
}
#[doc = "Bits 25:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RtcDrSpec> {
RsvdW::new(self, 25)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn err(&mut self) -> ErrW<RtcDrSpec> {
ErrW::new(self, 31)
}
}
#[doc = "RTC Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcDrSpec;
impl crate::RegisterSpec for RtcDrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_dr::R`](R) reader structure"]
impl crate::Readable for RtcDrSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_dr::W`](W) writer structure"]
impl crate::Writable for RtcDrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTC_DR to value 0"]
impl crate::Resettable for RtcDrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2C1_PINR (rw) register accessor: I2C1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_pinr`]
module"]
#[doc(alias = "I2C1_PINR")]
pub type I2c1Pinr = crate::Reg<i2c1_pinr::I2c1PinrSpec>;
#[doc = "I2C1 Pin Register"]
pub mod i2c1_pinr {
#[doc = "Register `I2C1_PINR` reader"]
pub type R = crate::R<I2c1PinrSpec>;
#[doc = "Register `I2C1_PINR` writer"]
pub type W = crate::W<I2c1PinrSpec>;
#[doc = "Field `SCL_PIN` reader - select PA. 0 for PA00, 44 for PA44."]
pub type SclPinR = crate::FieldReader;
#[doc = "Field `SCL_PIN` writer - select PA. 0 for PA00, 44 for PA44."]
pub type SclPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SDA_PIN` reader - "]
pub type SdaPinR = crate::FieldReader;
#[doc = "Field `SDA_PIN` writer - "]
pub type SdaPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:5 - select PA. 0 for PA00, 44 for PA44."]
#[inline(always)]
pub fn scl_pin(&self) -> SclPinR {
SclPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn sda_pin(&self) -> SdaPinR {
SdaPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:5 - select PA. 0 for PA00, 44 for PA44."]
#[inline(always)]
#[must_use]
pub fn scl_pin(&mut self) -> SclPinW<I2c1PinrSpec> {
SclPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<I2c1PinrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn sda_pin(&mut self) -> SdaPinW<I2c1PinrSpec> {
SdaPinW::new(self, 8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<I2c1PinrSpec> {
RsvdW::new(self, 14)
}
}
#[doc = "I2C1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2c1PinrSpec;
impl crate::RegisterSpec for I2c1PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2c1_pinr::R`](R) reader structure"]
impl crate::Readable for I2c1PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`i2c1_pinr::W`](W) writer structure"]
impl crate::Writable for I2c1PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2C1_PINR to value 0"]
impl crate::Resettable for I2c1PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2C2_PINR (rw) register accessor: I2C2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c2_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c2_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c2_pinr`]
module"]
#[doc(alias = "I2C2_PINR")]
pub type I2c2Pinr = crate::Reg<i2c2_pinr::I2c2PinrSpec>;
#[doc = "I2C2 Pin Register"]
pub mod i2c2_pinr {
#[doc = "Register `I2C2_PINR` reader"]
pub type R = crate::R<I2c2PinrSpec>;
#[doc = "Register `I2C2_PINR` writer"]
pub type W = crate::W<I2c2PinrSpec>;
#[doc = "Field `SCL_PIN` reader - "]
pub type SclPinR = crate::FieldReader;
#[doc = "Field `SCL_PIN` writer - "]
pub type SclPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SDA_PIN` reader - "]
pub type SdaPinR = crate::FieldReader;
#[doc = "Field `SDA_PIN` writer - "]
pub type SdaPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn scl_pin(&self) -> SclPinR {
SclPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn sda_pin(&self) -> SdaPinR {
SdaPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn scl_pin(&mut self) -> SclPinW<I2c2PinrSpec> {
SclPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<I2c2PinrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn sda_pin(&mut self) -> SdaPinW<I2c2PinrSpec> {
SdaPinW::new(self, 8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<I2c2PinrSpec> {
RsvdW::new(self, 14)
}
}
#[doc = "I2C2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c2_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c2_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2c2PinrSpec;
impl crate::RegisterSpec for I2c2PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2c2_pinr::R`](R) reader structure"]
impl crate::Readable for I2c2PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`i2c2_pinr::W`](W) writer structure"]
impl crate::Writable for I2c2PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2C2_PINR to value 0"]
impl crate::Resettable for I2c2PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2C3_PINR (rw) register accessor: I2C3 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c3_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c3_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c3_pinr`]
module"]
#[doc(alias = "I2C3_PINR")]
pub type I2c3Pinr = crate::Reg<i2c3_pinr::I2c3PinrSpec>;
#[doc = "I2C3 Pin Register"]
pub mod i2c3_pinr {
#[doc = "Register `I2C3_PINR` reader"]
pub type R = crate::R<I2c3PinrSpec>;
#[doc = "Register `I2C3_PINR` writer"]
pub type W = crate::W<I2c3PinrSpec>;
#[doc = "Field `SCL_PIN` reader - "]
pub type SclPinR = crate::FieldReader;
#[doc = "Field `SCL_PIN` writer - "]
pub type SclPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SDA_PIN` reader - "]
pub type SdaPinR = crate::FieldReader;
#[doc = "Field `SDA_PIN` writer - "]
pub type SdaPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn scl_pin(&self) -> SclPinR {
SclPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn sda_pin(&self) -> SdaPinR {
SdaPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn scl_pin(&mut self) -> SclPinW<I2c3PinrSpec> {
SclPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<I2c3PinrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn sda_pin(&mut self) -> SdaPinW<I2c3PinrSpec> {
SdaPinW::new(self, 8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<I2c3PinrSpec> {
RsvdW::new(self, 14)
}
}
#[doc = "I2C3 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c3_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c3_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2c3PinrSpec;
impl crate::RegisterSpec for I2c3PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2c3_pinr::R`](R) reader structure"]
impl crate::Readable for I2c3PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`i2c3_pinr::W`](W) writer structure"]
impl crate::Writable for I2c3PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2C3_PINR to value 0"]
impl crate::Resettable for I2c3PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2C4_PINR (rw) register accessor: I2C4 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c4_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c4_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c4_pinr`]
module"]
#[doc(alias = "I2C4_PINR")]
pub type I2c4Pinr = crate::Reg<i2c4_pinr::I2c4PinrSpec>;
#[doc = "I2C4 Pin Register"]
pub mod i2c4_pinr {
#[doc = "Register `I2C4_PINR` reader"]
pub type R = crate::R<I2c4PinrSpec>;
#[doc = "Register `I2C4_PINR` writer"]
pub type W = crate::W<I2c4PinrSpec>;
#[doc = "Field `SCL_PIN` reader - "]
pub type SclPinR = crate::FieldReader;
#[doc = "Field `SCL_PIN` writer - "]
pub type SclPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SDA_PIN` reader - "]
pub type SdaPinR = crate::FieldReader;
#[doc = "Field `SDA_PIN` writer - "]
pub type SdaPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn scl_pin(&self) -> SclPinR {
SclPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn sda_pin(&self) -> SdaPinR {
SdaPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn scl_pin(&mut self) -> SclPinW<I2c4PinrSpec> {
SclPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<I2c4PinrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn sda_pin(&mut self) -> SdaPinW<I2c4PinrSpec> {
SdaPinW::new(self, 8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<I2c4PinrSpec> {
RsvdW::new(self, 14)
}
}
#[doc = "I2C4 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c4_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c4_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2c4PinrSpec;
impl crate::RegisterSpec for I2c4PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2c4_pinr::R`](R) reader structure"]
impl crate::Readable for I2c4PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`i2c4_pinr::W`](W) writer structure"]
impl crate::Writable for I2c4PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2C4_PINR to value 0"]
impl crate::Resettable for I2c4PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "USART1_PINR (rw) register accessor: USART1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usart1_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usart1_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usart1_pinr`]
module"]
#[doc(alias = "USART1_PINR")]
pub type Usart1Pinr = crate::Reg<usart1_pinr::Usart1PinrSpec>;
#[doc = "USART1 Pin Register"]
pub mod usart1_pinr {
#[doc = "Register `USART1_PINR` reader"]
pub type R = crate::R<Usart1PinrSpec>;
#[doc = "Register `USART1_PINR` writer"]
pub type W = crate::W<Usart1PinrSpec>;
#[doc = "Field `TXD_PIN` reader - "]
pub type TxdPinR = crate::FieldReader;
#[doc = "Field `TXD_PIN` writer - "]
pub type TxdPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RXD_PIN` reader - "]
pub type RxdPinR = crate::FieldReader;
#[doc = "Field `RXD_PIN` writer - "]
pub type RxdPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RTS_PIN` reader - "]
pub type RtsPinR = crate::FieldReader;
#[doc = "Field `RTS_PIN` writer - "]
pub type RtsPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTS_PIN` reader - "]
pub type CtsPinR = crate::FieldReader;
#[doc = "Field `CTS_PIN` writer - "]
pub type CtsPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn txd_pin(&self) -> TxdPinR {
TxdPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn rxd_pin(&self) -> RxdPinR {
RxdPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn rts_pin(&self) -> RtsPinR {
RtsPinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn cts_pin(&self) -> CtsPinR {
CtsPinR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn txd_pin(&mut self) -> TxdPinW<Usart1PinrSpec> {
TxdPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Usart1PinrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn rxd_pin(&mut self) -> RxdPinW<Usart1PinrSpec> {
RxdPinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Usart1PinrSpec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn rts_pin(&mut self) -> RtsPinW<Usart1PinrSpec> {
RtsPinW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Usart1PinrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn cts_pin(&mut self) -> CtsPinW<Usart1PinrSpec> {
CtsPinW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Usart1PinrSpec> {
RsvdW::new(self, 30)
}
}
#[doc = "USART1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usart1_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usart1_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Usart1PinrSpec;
impl crate::RegisterSpec for Usart1PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usart1_pinr::R`](R) reader structure"]
impl crate::Readable for Usart1PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`usart1_pinr::W`](W) writer structure"]
impl crate::Writable for Usart1PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets USART1_PINR to value 0"]
impl crate::Resettable for Usart1PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "USART2_PINR (rw) register accessor: USART2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usart2_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usart2_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usart2_pinr`]
module"]
#[doc(alias = "USART2_PINR")]
pub type Usart2Pinr = crate::Reg<usart2_pinr::Usart2PinrSpec>;
#[doc = "USART2 Pin Register"]
pub mod usart2_pinr {
#[doc = "Register `USART2_PINR` reader"]
pub type R = crate::R<Usart2PinrSpec>;
#[doc = "Register `USART2_PINR` writer"]
pub type W = crate::W<Usart2PinrSpec>;
#[doc = "Field `TXD_PIN` reader - "]
pub type TxdPinR = crate::FieldReader;
#[doc = "Field `TXD_PIN` writer - "]
pub type TxdPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RXD_PIN` reader - "]
pub type RxdPinR = crate::FieldReader;
#[doc = "Field `RXD_PIN` writer - "]
pub type RxdPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RTS_PIN` reader - "]
pub type RtsPinR = crate::FieldReader;
#[doc = "Field `RTS_PIN` writer - "]
pub type RtsPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTS_PIN` reader - "]
pub type CtsPinR = crate::FieldReader;
#[doc = "Field `CTS_PIN` writer - "]
pub type CtsPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn txd_pin(&self) -> TxdPinR {
TxdPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn rxd_pin(&self) -> RxdPinR {
RxdPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn rts_pin(&self) -> RtsPinR {
RtsPinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn cts_pin(&self) -> CtsPinR {
CtsPinR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn txd_pin(&mut self) -> TxdPinW<Usart2PinrSpec> {
TxdPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Usart2PinrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn rxd_pin(&mut self) -> RxdPinW<Usart2PinrSpec> {
RxdPinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Usart2PinrSpec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn rts_pin(&mut self) -> RtsPinW<Usart2PinrSpec> {
RtsPinW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Usart2PinrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn cts_pin(&mut self) -> CtsPinW<Usart2PinrSpec> {
CtsPinW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Usart2PinrSpec> {
RsvdW::new(self, 30)
}
}
#[doc = "USART2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usart2_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usart2_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Usart2PinrSpec;
impl crate::RegisterSpec for Usart2PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usart2_pinr::R`](R) reader structure"]
impl crate::Readable for Usart2PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`usart2_pinr::W`](W) writer structure"]
impl crate::Writable for Usart2PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets USART2_PINR to value 0"]
impl crate::Resettable for Usart2PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "USART3_PINR (rw) register accessor: USART3 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usart3_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usart3_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usart3_pinr`]
module"]
#[doc(alias = "USART3_PINR")]
pub type Usart3Pinr = crate::Reg<usart3_pinr::Usart3PinrSpec>;
#[doc = "USART3 Pin Register"]
pub mod usart3_pinr {
#[doc = "Register `USART3_PINR` reader"]
pub type R = crate::R<Usart3PinrSpec>;
#[doc = "Register `USART3_PINR` writer"]
pub type W = crate::W<Usart3PinrSpec>;
#[doc = "Field `TXD_PIN` reader - "]
pub type TxdPinR = crate::FieldReader;
#[doc = "Field `TXD_PIN` writer - "]
pub type TxdPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RXD_PIN` reader - "]
pub type RxdPinR = crate::FieldReader;
#[doc = "Field `RXD_PIN` writer - "]
pub type RxdPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RTS_PIN` reader - "]
pub type RtsPinR = crate::FieldReader;
#[doc = "Field `RTS_PIN` writer - "]
pub type RtsPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTS_PIN` reader - "]
pub type CtsPinR = crate::FieldReader;
#[doc = "Field `CTS_PIN` writer - "]
pub type CtsPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn txd_pin(&self) -> TxdPinR {
TxdPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn rxd_pin(&self) -> RxdPinR {
RxdPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn rts_pin(&self) -> RtsPinR {
RtsPinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn cts_pin(&self) -> CtsPinR {
CtsPinR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn txd_pin(&mut self) -> TxdPinW<Usart3PinrSpec> {
TxdPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Usart3PinrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn rxd_pin(&mut self) -> RxdPinW<Usart3PinrSpec> {
RxdPinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Usart3PinrSpec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn rts_pin(&mut self) -> RtsPinW<Usart3PinrSpec> {
RtsPinW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Usart3PinrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn cts_pin(&mut self) -> CtsPinW<Usart3PinrSpec> {
CtsPinW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Usart3PinrSpec> {
RsvdW::new(self, 30)
}
}
#[doc = "USART3 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usart3_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usart3_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Usart3PinrSpec;
impl crate::RegisterSpec for Usart3PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usart3_pinr::R`](R) reader structure"]
impl crate::Readable for Usart3PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`usart3_pinr::W`](W) writer structure"]
impl crate::Writable for Usart3PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets USART3_PINR to value 0"]
impl crate::Resettable for Usart3PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GPTIM1_PINR (rw) register accessor: GPTIM1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptim1_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptim1_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptim1_pinr`]
module"]
#[doc(alias = "GPTIM1_PINR")]
pub type Gptim1Pinr = crate::Reg<gptim1_pinr::Gptim1PinrSpec>;
#[doc = "GPTIM1 Pin Register"]
pub mod gptim1_pinr {
#[doc = "Register `GPTIM1_PINR` reader"]
pub type R = crate::R<Gptim1PinrSpec>;
#[doc = "Register `GPTIM1_PINR` writer"]
pub type W = crate::W<Gptim1PinrSpec>;
#[doc = "Field `CH1_PIN` reader - "]
pub type Ch1PinR = crate::FieldReader;
#[doc = "Field `CH1_PIN` writer - "]
pub type Ch1PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH2_PIN` reader - "]
pub type Ch2PinR = crate::FieldReader;
#[doc = "Field `CH2_PIN` writer - "]
pub type Ch2PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH3_PIN` reader - "]
pub type Ch3PinR = crate::FieldReader;
#[doc = "Field `CH3_PIN` writer - "]
pub type Ch3PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH4_PIN` reader - "]
pub type Ch4PinR = crate::FieldReader;
#[doc = "Field `CH4_PIN` writer - "]
pub type Ch4PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn ch1_pin(&self) -> Ch1PinR {
Ch1PinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn ch2_pin(&self) -> Ch2PinR {
Ch2PinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn ch3_pin(&self) -> Ch3PinR {
Ch3PinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn ch4_pin(&self) -> Ch4PinR {
Ch4PinR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn ch1_pin(&mut self) -> Ch1PinW<Gptim1PinrSpec> {
Ch1PinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Gptim1PinrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn ch2_pin(&mut self) -> Ch2PinW<Gptim1PinrSpec> {
Ch2PinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Gptim1PinrSpec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn ch3_pin(&mut self) -> Ch3PinW<Gptim1PinrSpec> {
Ch3PinW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Gptim1PinrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn ch4_pin(&mut self) -> Ch4PinW<Gptim1PinrSpec> {
Ch4PinW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Gptim1PinrSpec> {
RsvdW::new(self, 30)
}
}
#[doc = "GPTIM1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptim1_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptim1_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptim1PinrSpec;
impl crate::RegisterSpec for Gptim1PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptim1_pinr::R`](R) reader structure"]
impl crate::Readable for Gptim1PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`gptim1_pinr::W`](W) writer structure"]
impl crate::Writable for Gptim1PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GPTIM1_PINR to value 0"]
impl crate::Resettable for Gptim1PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GPTIM2_PINR (rw) register accessor: GPTIM2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptim2_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptim2_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptim2_pinr`]
module"]
#[doc(alias = "GPTIM2_PINR")]
pub type Gptim2Pinr = crate::Reg<gptim2_pinr::Gptim2PinrSpec>;
#[doc = "GPTIM2 Pin Register"]
pub mod gptim2_pinr {
#[doc = "Register `GPTIM2_PINR` reader"]
pub type R = crate::R<Gptim2PinrSpec>;
#[doc = "Register `GPTIM2_PINR` writer"]
pub type W = crate::W<Gptim2PinrSpec>;
#[doc = "Field `CH1_PIN` reader - "]
pub type Ch1PinR = crate::FieldReader;
#[doc = "Field `CH1_PIN` writer - "]
pub type Ch1PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH2_PIN` reader - "]
pub type Ch2PinR = crate::FieldReader;
#[doc = "Field `CH2_PIN` writer - "]
pub type Ch2PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH3_PIN` reader - "]
pub type Ch3PinR = crate::FieldReader;
#[doc = "Field `CH3_PIN` writer - "]
pub type Ch3PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH4_PIN` reader - "]
pub type Ch4PinR = crate::FieldReader;
#[doc = "Field `CH4_PIN` writer - "]
pub type Ch4PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn ch1_pin(&self) -> Ch1PinR {
Ch1PinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn ch2_pin(&self) -> Ch2PinR {
Ch2PinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn ch3_pin(&self) -> Ch3PinR {
Ch3PinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn ch4_pin(&self) -> Ch4PinR {
Ch4PinR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn ch1_pin(&mut self) -> Ch1PinW<Gptim2PinrSpec> {
Ch1PinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Gptim2PinrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn ch2_pin(&mut self) -> Ch2PinW<Gptim2PinrSpec> {
Ch2PinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Gptim2PinrSpec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn ch3_pin(&mut self) -> Ch3PinW<Gptim2PinrSpec> {
Ch3PinW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Gptim2PinrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn ch4_pin(&mut self) -> Ch4PinW<Gptim2PinrSpec> {
Ch4PinW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Gptim2PinrSpec> {
RsvdW::new(self, 30)
}
}
#[doc = "GPTIM2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptim2_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptim2_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptim2PinrSpec;
impl crate::RegisterSpec for Gptim2PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptim2_pinr::R`](R) reader structure"]
impl crate::Readable for Gptim2PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`gptim2_pinr::W`](W) writer structure"]
impl crate::Writable for Gptim2PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GPTIM2_PINR to value 0"]
impl crate::Resettable for Gptim2PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ETR_PINR (rw) register accessor: GPTIM ETR Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etr_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etr_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etr_pinr`]
module"]
#[doc(alias = "ETR_PINR")]
pub type EtrPinr = crate::Reg<etr_pinr::EtrPinrSpec>;
#[doc = "GPTIM ETR Pin Register"]
pub mod etr_pinr {
#[doc = "Register `ETR_PINR` reader"]
pub type R = crate::R<EtrPinrSpec>;
#[doc = "Register `ETR_PINR` writer"]
pub type W = crate::W<EtrPinrSpec>;
#[doc = "Field `ETR1_PIN` reader - GPTIM1_ETR"]
pub type Etr1PinR = crate::FieldReader;
#[doc = "Field `ETR1_PIN` writer - GPTIM1_ETR"]
pub type Etr1PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ETR2_PIN` reader - GPTIM2_ETR"]
pub type Etr2PinR = crate::FieldReader;
#[doc = "Field `ETR2_PIN` writer - GPTIM2_ETR"]
pub type Etr2PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:5 - GPTIM1_ETR"]
#[inline(always)]
pub fn etr1_pin(&self) -> Etr1PinR {
Etr1PinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13 - GPTIM2_ETR"]
#[inline(always)]
pub fn etr2_pin(&self) -> Etr2PinR {
Etr2PinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:5 - GPTIM1_ETR"]
#[inline(always)]
#[must_use]
pub fn etr1_pin(&mut self) -> Etr1PinW<EtrPinrSpec> {
Etr1PinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<EtrPinrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:13 - GPTIM2_ETR"]
#[inline(always)]
#[must_use]
pub fn etr2_pin(&mut self) -> Etr2PinW<EtrPinrSpec> {
Etr2PinW::new(self, 8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<EtrPinrSpec> {
RsvdW::new(self, 14)
}
}
#[doc = "GPTIM ETR Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etr_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etr_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EtrPinrSpec;
impl crate::RegisterSpec for EtrPinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`etr_pinr::R`](R) reader structure"]
impl crate::Readable for EtrPinrSpec {}
#[doc = "`write(|w| ..)` method takes [`etr_pinr::W`](W) writer structure"]
impl crate::Writable for EtrPinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ETR_PINR to value 0"]
impl crate::Resettable for EtrPinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "LPTIM1_PINR (rw) register accessor: LPTIM1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lptim1_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lptim1_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lptim1_pinr`]
module"]
#[doc(alias = "LPTIM1_PINR")]
pub type Lptim1Pinr = crate::Reg<lptim1_pinr::Lptim1PinrSpec>;
#[doc = "LPTIM1 Pin Register"]
pub mod lptim1_pinr {
#[doc = "Register `LPTIM1_PINR` reader"]
pub type R = crate::R<Lptim1PinrSpec>;
#[doc = "Register `LPTIM1_PINR` writer"]
pub type W = crate::W<Lptim1PinrSpec>;
#[doc = "Field `IN_PIN` reader - "]
pub type InPinR = crate::FieldReader;
#[doc = "Field `IN_PIN` writer - "]
pub type InPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OUT_PIN` reader - "]
pub type OutPinR = crate::FieldReader;
#[doc = "Field `OUT_PIN` writer - "]
pub type OutPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ETR_PIN` reader - "]
pub type EtrPinR = crate::FieldReader;
#[doc = "Field `ETR_PIN` writer - "]
pub type EtrPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn in_pin(&self) -> InPinR {
InPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn out_pin(&self) -> OutPinR {
OutPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn etr_pin(&self) -> EtrPinR {
EtrPinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn in_pin(&mut self) -> InPinW<Lptim1PinrSpec> {
InPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Lptim1PinrSpec> {
Rsvd3W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn out_pin(&mut self) -> OutPinW<Lptim1PinrSpec> {
OutPinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Lptim1PinrSpec> {
Rsvd2W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn etr_pin(&mut self) -> EtrPinW<Lptim1PinrSpec> {
EtrPinW::new(self, 16)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Lptim1PinrSpec> {
RsvdW::new(self, 22)
}
}
#[doc = "LPTIM1 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lptim1_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lptim1_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lptim1PinrSpec;
impl crate::RegisterSpec for Lptim1PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lptim1_pinr::R`](R) reader structure"]
impl crate::Readable for Lptim1PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`lptim1_pinr::W`](W) writer structure"]
impl crate::Writable for Lptim1PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LPTIM1_PINR to value 0"]
impl crate::Resettable for Lptim1PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "LPTIM2_PINR (rw) register accessor: LPTIM2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lptim2_pinr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lptim2_pinr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lptim2_pinr`]
module"]
#[doc(alias = "LPTIM2_PINR")]
pub type Lptim2Pinr = crate::Reg<lptim2_pinr::Lptim2PinrSpec>;
#[doc = "LPTIM2 Pin Register"]
pub mod lptim2_pinr {
#[doc = "Register `LPTIM2_PINR` reader"]
pub type R = crate::R<Lptim2PinrSpec>;
#[doc = "Register `LPTIM2_PINR` writer"]
pub type W = crate::W<Lptim2PinrSpec>;
#[doc = "Field `IN_PIN` reader - "]
pub type InPinR = crate::FieldReader;
#[doc = "Field `IN_PIN` writer - "]
pub type InPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `OUT_PIN` reader - "]
pub type OutPinR = crate::FieldReader;
#[doc = "Field `OUT_PIN` writer - "]
pub type OutPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ETR_PIN` reader - "]
pub type EtrPinR = crate::FieldReader;
#[doc = "Field `ETR_PIN` writer - "]
pub type EtrPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn in_pin(&self) -> InPinR {
InPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn out_pin(&self) -> OutPinR {
OutPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn etr_pin(&self) -> EtrPinR {
EtrPinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn in_pin(&mut self) -> InPinW<Lptim2PinrSpec> {
InPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Lptim2PinrSpec> {
Rsvd3W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn out_pin(&mut self) -> OutPinW<Lptim2PinrSpec> {
OutPinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Lptim2PinrSpec> {
Rsvd2W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn etr_pin(&mut self) -> EtrPinW<Lptim2PinrSpec> {
EtrPinW::new(self, 16)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Lptim2PinrSpec> {
RsvdW::new(self, 22)
}
}
#[doc = "LPTIM2 Pin Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lptim2_pinr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lptim2_pinr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Lptim2PinrSpec;
impl crate::RegisterSpec for Lptim2PinrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lptim2_pinr::R`](R) reader structure"]
impl crate::Readable for Lptim2PinrSpec {}
#[doc = "`write(|w| ..)` method takes [`lptim2_pinr::W`](W) writer structure"]
impl crate::Writable for Lptim2PinrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LPTIM2_PINR to value 0"]
impl crate::Resettable for Lptim2PinrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ATIM1_PINR1 (rw) register accessor: ATIM1 Pin Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atim1_pinr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atim1_pinr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atim1_pinr1`]
module"]
#[doc(alias = "ATIM1_PINR1")]
pub type Atim1Pinr1 = crate::Reg<atim1_pinr1::Atim1Pinr1Spec>;
#[doc = "ATIM1 Pin Register 1"]
pub mod atim1_pinr1 {
#[doc = "Register `ATIM1_PINR1` reader"]
pub type R = crate::R<Atim1Pinr1Spec>;
#[doc = "Register `ATIM1_PINR1` writer"]
pub type W = crate::W<Atim1Pinr1Spec>;
#[doc = "Field `CH1_PIN` reader - "]
pub type Ch1PinR = crate::FieldReader;
#[doc = "Field `CH1_PIN` writer - "]
pub type Ch1PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH2_PIN` reader - "]
pub type Ch2PinR = crate::FieldReader;
#[doc = "Field `CH2_PIN` writer - "]
pub type Ch2PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH3_PIN` reader - "]
pub type Ch3PinR = crate::FieldReader;
#[doc = "Field `CH3_PIN` writer - "]
pub type Ch3PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH4_PIN` reader - "]
pub type Ch4PinR = crate::FieldReader;
#[doc = "Field `CH4_PIN` writer - "]
pub type Ch4PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn ch1_pin(&self) -> Ch1PinR {
Ch1PinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn ch2_pin(&self) -> Ch2PinR {
Ch2PinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn ch3_pin(&self) -> Ch3PinR {
Ch3PinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn ch4_pin(&self) -> Ch4PinR {
Ch4PinR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn ch1_pin(&mut self) -> Ch1PinW<Atim1Pinr1Spec> {
Ch1PinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Atim1Pinr1Spec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn ch2_pin(&mut self) -> Ch2PinW<Atim1Pinr1Spec> {
Ch2PinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Atim1Pinr1Spec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn ch3_pin(&mut self) -> Ch3PinW<Atim1Pinr1Spec> {
Ch3PinW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Atim1Pinr1Spec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn ch4_pin(&mut self) -> Ch4PinW<Atim1Pinr1Spec> {
Ch4PinW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Atim1Pinr1Spec> {
RsvdW::new(self, 30)
}
}
#[doc = "ATIM1 Pin Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atim1_pinr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atim1_pinr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Atim1Pinr1Spec;
impl crate::RegisterSpec for Atim1Pinr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`atim1_pinr1::R`](R) reader structure"]
impl crate::Readable for Atim1Pinr1Spec {}
#[doc = "`write(|w| ..)` method takes [`atim1_pinr1::W`](W) writer structure"]
impl crate::Writable for Atim1Pinr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ATIM1_PINR1 to value 0"]
impl crate::Resettable for Atim1Pinr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ATIM1_PINR2 (rw) register accessor: ATIM1 Pin Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atim1_pinr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atim1_pinr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atim1_pinr2`]
module"]
#[doc(alias = "ATIM1_PINR2")]
pub type Atim1Pinr2 = crate::Reg<atim1_pinr2::Atim1Pinr2Spec>;
#[doc = "ATIM1 Pin Register 2"]
pub mod atim1_pinr2 {
#[doc = "Register `ATIM1_PINR2` reader"]
pub type R = crate::R<Atim1Pinr2Spec>;
#[doc = "Register `ATIM1_PINR2` writer"]
pub type W = crate::W<Atim1Pinr2Spec>;
#[doc = "Field `CH1N_PIN` reader - "]
pub type Ch1nPinR = crate::FieldReader;
#[doc = "Field `CH1N_PIN` writer - "]
pub type Ch1nPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH2N_PIN` reader - "]
pub type Ch2nPinR = crate::FieldReader;
#[doc = "Field `CH2N_PIN` writer - "]
pub type Ch2nPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CH3N_PIN` reader - "]
pub type Ch3nPinR = crate::FieldReader;
#[doc = "Field `CH3N_PIN` writer - "]
pub type Ch3nPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn ch1n_pin(&self) -> Ch1nPinR {
Ch1nPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn ch2n_pin(&self) -> Ch2nPinR {
Ch2nPinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn ch3n_pin(&self) -> Ch3nPinR {
Ch3nPinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn ch1n_pin(&mut self) -> Ch1nPinW<Atim1Pinr2Spec> {
Ch1nPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Atim1Pinr2Spec> {
Rsvd3W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn ch2n_pin(&mut self) -> Ch2nPinW<Atim1Pinr2Spec> {
Ch2nPinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Atim1Pinr2Spec> {
Rsvd2W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn ch3n_pin(&mut self) -> Ch3nPinW<Atim1Pinr2Spec> {
Ch3nPinW::new(self, 16)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Atim1Pinr2Spec> {
RsvdW::new(self, 22)
}
}
#[doc = "ATIM1 Pin Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atim1_pinr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atim1_pinr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Atim1Pinr2Spec;
impl crate::RegisterSpec for Atim1Pinr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`atim1_pinr2::R`](R) reader structure"]
impl crate::Readable for Atim1Pinr2Spec {}
#[doc = "`write(|w| ..)` method takes [`atim1_pinr2::W`](W) writer structure"]
impl crate::Writable for Atim1Pinr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ATIM1_PINR2 to value 0"]
impl crate::Resettable for Atim1Pinr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ATIM1_PINR3 (rw) register accessor: ATIM1 Pin Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atim1_pinr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atim1_pinr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atim1_pinr3`]
module"]
#[doc(alias = "ATIM1_PINR3")]
pub type Atim1Pinr3 = crate::Reg<atim1_pinr3::Atim1Pinr3Spec>;
#[doc = "ATIM1 Pin Register 3"]
pub mod atim1_pinr3 {
#[doc = "Register `ATIM1_PINR3` reader"]
pub type R = crate::R<Atim1Pinr3Spec>;
#[doc = "Register `ATIM1_PINR3` writer"]
pub type W = crate::W<Atim1Pinr3Spec>;
#[doc = "Field `BK_PIN` reader - "]
pub type BkPinR = crate::FieldReader;
#[doc = "Field `BK_PIN` writer - "]
pub type BkPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `BK2_PIN` reader - "]
pub type Bk2PinR = crate::FieldReader;
#[doc = "Field `BK2_PIN` writer - "]
pub type Bk2PinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ETR_PIN` reader - "]
pub type EtrPinR = crate::FieldReader;
#[doc = "Field `ETR_PIN` writer - "]
pub type EtrPinW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn bk_pin(&self) -> BkPinR {
BkPinR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn bk2_pin(&self) -> Bk2PinR {
Bk2PinR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn etr_pin(&self) -> EtrPinR {
EtrPinR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn bk_pin(&mut self) -> BkPinW<Atim1Pinr3Spec> {
BkPinW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Atim1Pinr3Spec> {
Rsvd3W::new(self, 6)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn bk2_pin(&mut self) -> Bk2PinW<Atim1Pinr3Spec> {
Bk2PinW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Atim1Pinr3Spec> {
Rsvd2W::new(self, 14)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn etr_pin(&mut self) -> EtrPinW<Atim1Pinr3Spec> {
EtrPinW::new(self, 16)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Atim1Pinr3Spec> {
RsvdW::new(self, 22)
}
}
#[doc = "ATIM1 Pin Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atim1_pinr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atim1_pinr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Atim1Pinr3Spec;
impl crate::RegisterSpec for Atim1Pinr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`atim1_pinr3::R`](R) reader structure"]
impl crate::Readable for Atim1Pinr3Spec {}
#[doc = "`write(|w| ..)` method takes [`atim1_pinr3::W`](W) writer structure"]
impl crate::Writable for Atim1Pinr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ATIM1_PINR3 to value 0"]
impl crate::Resettable for Atim1Pinr3Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "MPI1"]
pub struct Mpi1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Mpi1 {}
impl Mpi1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const mpi1::RegisterBlock = 0x5004_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const mpi1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Mpi1 {
type Target = mpi1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Mpi1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mpi1").finish()
}
}
#[doc = "MPI1"]
pub mod mpi1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr: Cr,
dr: Dr,
dcr: Dcr,
psclr: Psclr,
sr: Sr,
scr: Scr,
cmdr1: Cmdr1,
ar1: Ar1,
abr1: Abr1,
dlr1: Dlr1,
ccr1: Ccr1,
cmdr2: Cmdr2,
ar2: Ar2,
abr2: Abr2,
dlr2: Dlr2,
ccr2: Ccr2,
hcmdr: Hcmdr,
hrabr: Hrabr,
hrccr: Hrccr,
hwabr: Hwabr,
hwccr: Hwccr,
fifocr: Fifocr,
miscr: Miscr,
ctrsar: Ctrsar,
ctrear: Ctrear,
noncea: Noncea,
nonceb: Nonceb,
aasar: Aasar,
aaear: Aaear,
aaoar: Aaoar,
cir: Cir,
smr: Smr,
smkr: Smkr,
timr: Timr,
wdtr: Wdtr,
prsar: Prsar,
prear: Prear,
calcr: Calcr,
caldor: Caldor,
apm32cr: Apm32cr,
cr2: Cr2,
}
impl RegisterBlock {
#[doc = "0x00 - Control Register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x04 - Data Register"]
#[inline(always)]
pub const fn dr(&self) -> &Dr {
&self.dr
}
#[doc = "0x08 - Device Control Register"]
#[inline(always)]
pub const fn dcr(&self) -> &Dcr {
&self.dcr
}
#[doc = "0x0c - Prescaler Register"]
#[inline(always)]
pub const fn psclr(&self) -> &Psclr {
&self.psclr
}
#[doc = "0x10 - Status Register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Status Clear Register"]
#[inline(always)]
pub const fn scr(&self) -> &Scr {
&self.scr
}
#[doc = "0x18 - Command Register"]
#[inline(always)]
pub const fn cmdr1(&self) -> &Cmdr1 {
&self.cmdr1
}
#[doc = "0x1c - Address Register"]
#[inline(always)]
pub const fn ar1(&self) -> &Ar1 {
&self.ar1
}
#[doc = "0x20 - Alternate Byte Register"]
#[inline(always)]
pub const fn abr1(&self) -> &Abr1 {
&self.abr1
}
#[doc = "0x24 - Data Length Register"]
#[inline(always)]
pub const fn dlr1(&self) -> &Dlr1 {
&self.dlr1
}
#[doc = "0x28 - Communication Configuration Register"]
#[inline(always)]
pub const fn ccr1(&self) -> &Ccr1 {
&self.ccr1
}
#[doc = "0x2c - Command Register"]
#[inline(always)]
pub const fn cmdr2(&self) -> &Cmdr2 {
&self.cmdr2
}
#[doc = "0x30 - Address Register"]
#[inline(always)]
pub const fn ar2(&self) -> &Ar2 {
&self.ar2
}
#[doc = "0x34 - Alternate Byte Register"]
#[inline(always)]
pub const fn abr2(&self) -> &Abr2 {
&self.abr2
}
#[doc = "0x38 - Data Length Register"]
#[inline(always)]
pub const fn dlr2(&self) -> &Dlr2 {
&self.dlr2
}
#[doc = "0x3c - Communication Configuration Register"]
#[inline(always)]
pub const fn ccr2(&self) -> &Ccr2 {
&self.ccr2
}
#[doc = "0x40 - AHB Command Register"]
#[inline(always)]
pub const fn hcmdr(&self) -> &Hcmdr {
&self.hcmdr
}
#[doc = "0x44 - AHB Read Alternate Byte Register"]
#[inline(always)]
pub const fn hrabr(&self) -> &Hrabr {
&self.hrabr
}
#[doc = "0x48 - AHB Read Communication Configuration Register"]
#[inline(always)]
pub const fn hrccr(&self) -> &Hrccr {
&self.hrccr
}
#[doc = "0x4c - AHB Write Alternate Byte Register"]
#[inline(always)]
pub const fn hwabr(&self) -> &Hwabr {
&self.hwabr
}
#[doc = "0x50 - AHB Write Communication Configuration Register"]
#[inline(always)]
pub const fn hwccr(&self) -> &Hwccr {
&self.hwccr
}
#[doc = "0x54 - FIFO Control Register"]
#[inline(always)]
pub const fn fifocr(&self) -> &Fifocr {
&self.fifocr
}
#[doc = "0x58 - Miscelaneous Register"]
#[inline(always)]
pub const fn miscr(&self) -> &Miscr {
&self.miscr
}
#[doc = "0x5c - "]
#[inline(always)]
pub const fn ctrsar(&self) -> &Ctrsar {
&self.ctrsar
}
#[doc = "0x60 - "]
#[inline(always)]
pub const fn ctrear(&self) -> &Ctrear {
&self.ctrear
}
#[doc = "0x64 - "]
#[inline(always)]
pub const fn noncea(&self) -> &Noncea {
&self.noncea
}
#[doc = "0x68 - "]
#[inline(always)]
pub const fn nonceb(&self) -> &Nonceb {
&self.nonceb
}
#[doc = "0x6c - "]
#[inline(always)]
pub const fn aasar(&self) -> &Aasar {
&self.aasar
}
#[doc = "0x70 - "]
#[inline(always)]
pub const fn aaear(&self) -> &Aaear {
&self.aaear
}
#[doc = "0x74 - "]
#[inline(always)]
pub const fn aaoar(&self) -> &Aaoar {
&self.aaoar
}
#[doc = "0x78 - Command Interval Register"]
#[inline(always)]
pub const fn cir(&self) -> &Cir {
&self.cir
}
#[doc = "0x7c - Status Match Register"]
#[inline(always)]
pub const fn smr(&self) -> &Smr {
&self.smr
}
#[doc = "0x80 - Status Mask Register"]
#[inline(always)]
pub const fn smkr(&self) -> &Smkr {
&self.smkr
}
#[doc = "0x84 - "]
#[inline(always)]
pub const fn timr(&self) -> &Timr {
&self.timr
}
#[doc = "0x88 - WDT Register"]
#[inline(always)]
pub const fn wdtr(&self) -> &Wdtr {
&self.wdtr
}
#[doc = "0x8c - "]
#[inline(always)]
pub const fn prsar(&self) -> &Prsar {
&self.prsar
}
#[doc = "0x90 - "]
#[inline(always)]
pub const fn prear(&self) -> &Prear {
&self.prear
}
#[doc = "0x94 - Calibration Control Register"]
#[inline(always)]
pub const fn calcr(&self) -> &Calcr {
&self.calcr
}
#[doc = "0x98 - "]
#[inline(always)]
pub const fn caldor(&self) -> &Caldor {
&self.caldor
}
#[doc = "0x9c - APM32 Control Register"]
#[inline(always)]
pub const fn apm32cr(&self) -> &Apm32cr {
&self.apm32cr
}
#[doc = "0xa0 - "]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
}
#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `EN` reader - Enable MPI"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - Enable MPI"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::FieldReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DMAE` reader - DMA enable in FIFO mode"]
pub type DmaeR = crate::BitReader;
#[doc = "Field `DMAE` writer - DMA enable in FIFO mode"]
pub type DmaeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRE` reader - AES-CTR on-the-fly decryption enable"]
pub type CtreR = crate::BitReader;
#[doc = "Field `CTRE` writer - AES-CTR on-the-fly decryption enable"]
pub type CtreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRM` reader - AES-CTR mode. 0 - AES128, 1 - AES256"]
pub type CtrmR = crate::BitReader;
#[doc = "Field `CTRM` writer - AES-CTR mode. 0 - AES128, 1 - AES256"]
pub type CtrmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SMIE` reader - Status match interrupt enable"]
pub type SmieR = crate::BitReader;
#[doc = "Field `SMIE` writer - Status match interrupt enable"]
pub type SmieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CMD2E` reader - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
pub type Cmd2eR = crate::BitReader;
#[doc = "Field `CMD2E` writer - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
pub type Cmd2eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SME1` reader - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
pub type Sme1R = crate::BitReader;
#[doc = "Field `SME1` writer - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
pub type Sme1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SME2` reader - "]
pub type Sme2R = crate::BitReader;
#[doc = "Field `SME2` writer - "]
pub type Sme2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SMM` reader - Status match mode: 0 - AND mode; 1 - OR mode"]
pub type SmmR = crate::BitReader;
#[doc = "Field `SMM` writer - Status match mode: 0 - AND mode; 1 - OR mode"]
pub type SmmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HWIFE` reader - Hardware interface enable"]
pub type HwifeR = crate::BitReader;
#[doc = "Field `HWIFE` writer - Hardware interface enable"]
pub type HwifeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OPIE` reader - OPI interface enable"]
pub type OpieR = crate::BitReader;
#[doc = "Field `OPIE` writer - OPI interface enable"]
pub type OpieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MX16` reader - Mode X16"]
pub type Mx16R = crate::BitReader;
#[doc = "Field `MX16` writer - Mode X16"]
pub type Mx16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DFM` reader - Dual Flash Mode"]
pub type DfmR = crate::BitReader;
#[doc = "Field `DFM` writer - Dual Flash Mode"]
pub type DfmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `ABORT` reader - "]
pub type AbortR = crate::BitReader;
#[doc = "Field `ABORT` writer - "]
pub type AbortW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Enable MPI"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:4"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 1) & 0x0f) as u8)
}
#[doc = "Bit 5 - DMA enable in FIFO mode"]
#[inline(always)]
pub fn dmae(&self) -> DmaeR {
DmaeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - AES-CTR on-the-fly decryption enable"]
#[inline(always)]
pub fn ctre(&self) -> CtreR {
CtreR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - AES-CTR mode. 0 - AES128, 1 - AES256"]
#[inline(always)]
pub fn ctrm(&self) -> CtrmR {
CtrmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Status match interrupt enable"]
#[inline(always)]
pub fn smie(&self) -> SmieR {
SmieR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bit 16 - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
#[inline(always)]
pub fn cmd2e(&self) -> Cmd2eR {
Cmd2eR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
#[inline(always)]
pub fn sme1(&self) -> Sme1R {
Sme1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn sme2(&self) -> Sme2R {
Sme2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Status match mode: 0 - AND mode; 1 - OR mode"]
#[inline(always)]
pub fn smm(&self) -> SmmR {
SmmR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Hardware interface enable"]
#[inline(always)]
pub fn hwife(&self) -> HwifeR {
HwifeR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - OPI interface enable"]
#[inline(always)]
pub fn opie(&self) -> OpieR {
OpieR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Mode X16"]
#[inline(always)]
pub fn mx16(&self) -> Mx16R {
Mx16R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Dual Flash Mode"]
#[inline(always)]
pub fn dfm(&self) -> DfmR {
DfmR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 25) & 0x3f) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn abort(&self) -> AbortR {
AbortR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Enable MPI"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<CrSpec> {
EnW::new(self, 0)
}
#[doc = "Bits 1:4"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<CrSpec> {
Rsvd5W::new(self, 1)
}
#[doc = "Bit 5 - DMA enable in FIFO mode"]
#[inline(always)]
#[must_use]
pub fn dmae(&mut self) -> DmaeW<CrSpec> {
DmaeW::new(self, 5)
}
#[doc = "Bit 6 - AES-CTR on-the-fly decryption enable"]
#[inline(always)]
#[must_use]
pub fn ctre(&mut self) -> CtreW<CrSpec> {
CtreW::new(self, 6)
}
#[doc = "Bit 7 - AES-CTR mode. 0 - AES128, 1 - AES256"]
#[inline(always)]
#[must_use]
pub fn ctrm(&mut self) -> CtrmW<CrSpec> {
CtrmW::new(self, 7)
}
#[doc = "Bit 8 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<CrSpec> {
TcieW::new(self, 8)
}
#[doc = "Bits 9:10"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CrSpec> {
Rsvd4W::new(self, 9)
}
#[doc = "Bit 11 - Status match interrupt enable"]
#[inline(always)]
#[must_use]
pub fn smie(&mut self) -> SmieW<CrSpec> {
SmieW::new(self, 11)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CrSpec> {
Rsvd3W::new(self, 12)
}
#[doc = "Bit 16 - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
#[inline(always)]
#[must_use]
pub fn cmd2e(&mut self) -> Cmd2eW<CrSpec> {
Cmd2eW::new(self, 16)
}
#[doc = "Bit 17 - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
#[inline(always)]
#[must_use]
pub fn sme1(&mut self) -> Sme1W<CrSpec> {
Sme1W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn sme2(&mut self) -> Sme2W<CrSpec> {
Sme2W::new(self, 18)
}
#[doc = "Bit 19 - Status match mode: 0 - AND mode; 1 - OR mode"]
#[inline(always)]
#[must_use]
pub fn smm(&mut self) -> SmmW<CrSpec> {
SmmW::new(self, 19)
}
#[doc = "Bit 20 - Hardware interface enable"]
#[inline(always)]
#[must_use]
pub fn hwife(&mut self) -> HwifeW<CrSpec> {
HwifeW::new(self, 20)
}
#[doc = "Bit 21 - OPI interface enable"]
#[inline(always)]
#[must_use]
pub fn opie(&mut self) -> OpieW<CrSpec> {
OpieW::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bit 23 - Mode X16"]
#[inline(always)]
#[must_use]
pub fn mx16(&mut self) -> Mx16W<CrSpec> {
Mx16W::new(self, 23)
}
#[doc = "Bit 24 - Dual Flash Mode"]
#[inline(always)]
#[must_use]
pub fn dfm(&mut self) -> DfmW<CrSpec> {
DfmW::new(self, 24)
}
#[doc = "Bits 25:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 25)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn abort(&mut self) -> AbortW<CrSpec> {
AbortW::new(self, 31)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DR (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`]
module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "Data Register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `DATA` reader - "]
pub type DataR = crate::FieldReader<u32>;
#[doc = "Field `DATA` writer - "]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DrSpec> {
DataW::new(self, 0)
}
}
#[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DCR (rw) register accessor: Device Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcr`]
module"]
#[doc(alias = "DCR")]
pub type Dcr = crate::Reg<dcr::DcrSpec>;
#[doc = "Device Control Register"]
pub mod dcr {
#[doc = "Register `DCR` reader"]
pub type R = crate::R<DcrSpec>;
#[doc = "Register `DCR` writer"]
pub type W = crate::W<DcrSpec>;
#[doc = "Field `RBSIZE` reader - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
pub type RbsizeR = crate::FieldReader;
#[doc = "Field `RBSIZE` writer - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
pub type RbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `DQSE` reader - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
pub type DqseR = crate::BitReader;
#[doc = "Field `DQSE` writer - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
pub type DqseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HYPER` reader - HyperBus protocol"]
pub type HyperR = crate::BitReader;
#[doc = "Field `HYPER` writer - HyperBus protocol"]
pub type HyperW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `XLEGACY` reader - Xccela legacy protocol"]
pub type XlegacyR = crate::BitReader;
#[doc = "Field `XLEGACY` writer - Xccela legacy protocol"]
pub type XlegacyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CSLMAX` reader - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
pub type CslmaxR = crate::FieldReader<u16>;
#[doc = "Field `CSLMAX` writer - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
pub type CslmaxW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `CSLMIN` reader - Minimum CS low active time. N - (n+1) cycles"]
pub type CslminR = crate::FieldReader;
#[doc = "Field `CSLMIN` writer - Minimum CS low active time. N - (n+1) cycles"]
pub type CslminW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CSHMIN` reader - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
pub type CshminR = crate::FieldReader;
#[doc = "Field `CSHMIN` writer - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
pub type CshminW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TRCMIN` reader - Write/Read cycle minimum time"]
pub type TrcminR = crate::FieldReader;
#[doc = "Field `TRCMIN` writer - Write/Read cycle minimum time"]
pub type TrcminW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `FIXLAT` reader - Indicate PSRAM is fixed latency or variable latency"]
pub type FixlatR = crate::BitReader;
#[doc = "Field `FIXLAT` writer - Indicate PSRAM is fixed latency or variable latency"]
pub type FixlatW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
#[inline(always)]
pub fn rbsize(&self) -> RbsizeR {
RbsizeR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
#[inline(always)]
pub fn dqse(&self) -> DqseR {
DqseR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - HyperBus protocol"]
#[inline(always)]
pub fn hyper(&self) -> HyperR {
HyperR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Xccela legacy protocol"]
#[inline(always)]
pub fn xlegacy(&self) -> XlegacyR {
XlegacyR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:17 - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
#[inline(always)]
pub fn cslmax(&self) -> CslmaxR {
CslmaxR::new(((self.bits >> 6) & 0x0fff) as u16)
}
#[doc = "Bits 18:21 - Minimum CS low active time. N - (n+1) cycles"]
#[inline(always)]
pub fn cslmin(&self) -> CslminR {
CslminR::new(((self.bits >> 18) & 0x0f) as u8)
}
#[doc = "Bits 22:25 - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
#[inline(always)]
pub fn cshmin(&self) -> CshminR {
CshminR::new(((self.bits >> 22) & 0x0f) as u8)
}
#[doc = "Bits 26:30 - Write/Read cycle minimum time"]
#[inline(always)]
pub fn trcmin(&self) -> TrcminR {
TrcminR::new(((self.bits >> 26) & 0x1f) as u8)
}
#[doc = "Bit 31 - Indicate PSRAM is fixed latency or variable latency"]
#[inline(always)]
pub fn fixlat(&self) -> FixlatR {
FixlatR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
#[inline(always)]
#[must_use]
pub fn rbsize(&mut self) -> RbsizeW<DcrSpec> {
RbsizeW::new(self, 0)
}
#[doc = "Bit 3 - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
#[inline(always)]
#[must_use]
pub fn dqse(&mut self) -> DqseW<DcrSpec> {
DqseW::new(self, 3)
}
#[doc = "Bit 4 - HyperBus protocol"]
#[inline(always)]
#[must_use]
pub fn hyper(&mut self) -> HyperW<DcrSpec> {
HyperW::new(self, 4)
}
#[doc = "Bit 5 - Xccela legacy protocol"]
#[inline(always)]
#[must_use]
pub fn xlegacy(&mut self) -> XlegacyW<DcrSpec> {
XlegacyW::new(self, 5)
}
#[doc = "Bits 6:17 - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
#[inline(always)]
#[must_use]
pub fn cslmax(&mut self) -> CslmaxW<DcrSpec> {
CslmaxW::new(self, 6)
}
#[doc = "Bits 18:21 - Minimum CS low active time. N - (n+1) cycles"]
#[inline(always)]
#[must_use]
pub fn cslmin(&mut self) -> CslminW<DcrSpec> {
CslminW::new(self, 18)
}
#[doc = "Bits 22:25 - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
#[inline(always)]
#[must_use]
pub fn cshmin(&mut self) -> CshminW<DcrSpec> {
CshminW::new(self, 22)
}
#[doc = "Bits 26:30 - Write/Read cycle minimum time"]
#[inline(always)]
#[must_use]
pub fn trcmin(&mut self) -> TrcminW<DcrSpec> {
TrcminW::new(self, 26)
}
#[doc = "Bit 31 - Indicate PSRAM is fixed latency or variable latency"]
#[inline(always)]
#[must_use]
pub fn fixlat(&mut self) -> FixlatW<DcrSpec> {
FixlatW::new(self, 31)
}
}
#[doc = "Device Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcrSpec;
impl crate::RegisterSpec for DcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dcr::R`](R) reader structure"]
impl crate::Readable for DcrSpec {}
#[doc = "`write(|w| ..)` method takes [`dcr::W`](W) writer structure"]
impl crate::Writable for DcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DCR to value 0"]
impl crate::Resettable for DcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSCLR (rw) register accessor: Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psclr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psclr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psclr`]
module"]
#[doc(alias = "PSCLR")]
pub type Psclr = crate::Reg<psclr::PsclrSpec>;
#[doc = "Prescaler Register"]
pub mod psclr {
#[doc = "Register `PSCLR` reader"]
pub type R = crate::R<PsclrSpec>;
#[doc = "Register `PSCLR` writer"]
pub type W = crate::W<PsclrSpec>;
#[doc = "Field `DIV` reader - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
pub type DivR = crate::FieldReader;
#[doc = "Field `DIV` writer - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
#[inline(always)]
pub fn div(&self) -> DivR {
DivR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
#[inline(always)]
#[must_use]
pub fn div(&mut self) -> DivW<PsclrSpec> {
DivW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PsclrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psclr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psclr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsclrSpec;
impl crate::RegisterSpec for PsclrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psclr::R`](R) reader structure"]
impl crate::Readable for PsclrSpec {}
#[doc = "`write(|w| ..)` method takes [`psclr::W`](W) writer structure"]
impl crate::Writable for PsclrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSCLR to value 0"]
impl crate::Resettable for PsclrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status Register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `TCF` reader - Transfer complete flag"]
pub type TcfR = crate::BitReader;
#[doc = "Field `TCF` writer - Transfer complete flag"]
pub type TcfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SMF` reader - Status match flag in Polling Mode"]
pub type SmfR = crate::BitReader;
#[doc = "Field `SMF` writer - Status match flag in Polling Mode"]
pub type SmfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
#[doc = "Field `BUSY` reader - "]
pub type BusyR = crate::BitReader;
#[doc = "Field `BUSY` writer - "]
pub type BusyW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Transfer complete flag"]
#[inline(always)]
pub fn tcf(&self) -> TcfR {
TcfR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3 - Status match flag in Polling Mode"]
#[inline(always)]
pub fn smf(&self) -> SmfR {
SmfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x07ff_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn busy(&self) -> BusyR {
BusyR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcf(&mut self) -> TcfW<SrSpec> {
TcfW::new(self, 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SrSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 3 - Status match flag in Polling Mode"]
#[inline(always)]
#[must_use]
pub fn smf(&mut self) -> SmfW<SrSpec> {
SmfW::new(self, 3)
}
#[doc = "Bits 4:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 4)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn busy(&mut self) -> BusyW<SrSpec> {
BusyW::new(self, 31)
}
}
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SCR (rw) register accessor: Status Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`]
module"]
#[doc(alias = "SCR")]
pub type Scr = crate::Reg<scr::ScrSpec>;
#[doc = "Status Clear Register"]
pub mod scr {
#[doc = "Register `SCR` reader"]
pub type R = crate::R<ScrSpec>;
#[doc = "Register `SCR` writer"]
pub type W = crate::W<ScrSpec>;
#[doc = "Field `TCFC` reader - Write 1 to clear corresponding flag in SR"]
pub type TcfcR = crate::BitReader;
#[doc = "Field `TCFC` writer - Write 1 to clear corresponding flag in SR"]
pub type TcfcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SMFC` reader - "]
pub type SmfcR = crate::BitReader;
#[doc = "Field `SMFC` writer - "]
pub type SmfcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - Write 1 to clear corresponding flag in SR"]
#[inline(always)]
pub fn tcfc(&self) -> TcfcR {
TcfcR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn smfc(&self) -> SmfcR {
SmfcR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Write 1 to clear corresponding flag in SR"]
#[inline(always)]
#[must_use]
pub fn tcfc(&mut self) -> TcfcW<ScrSpec> {
TcfcW::new(self, 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<ScrSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn smfc(&mut self) -> SmfcW<ScrSpec> {
SmfcW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ScrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "Status Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScrSpec;
impl crate::RegisterSpec for ScrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`scr::R`](R) reader structure"]
impl crate::Readable for ScrSpec {}
#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"]
impl crate::Writable for ScrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SCR to value 0"]
impl crate::Resettable for ScrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CMDR1 (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdr1`]
module"]
#[doc(alias = "CMDR1")]
pub type Cmdr1 = crate::Reg<cmdr1::Cmdr1Spec>;
#[doc = "Command Register"]
pub mod cmdr1 {
#[doc = "Register `CMDR1` reader"]
pub type R = crate::R<Cmdr1Spec>;
#[doc = "Register `CMDR1` writer"]
pub type W = crate::W<Cmdr1Spec>;
#[doc = "Field `CMD` reader - command"]
pub type CmdR = crate::FieldReader;
#[doc = "Field `CMD` writer - command"]
pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
pub fn cmd(&self) -> CmdR {
CmdR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
#[must_use]
pub fn cmd(&mut self) -> CmdW<Cmdr1Spec> {
CmdW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cmdr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmdr1Spec;
impl crate::RegisterSpec for Cmdr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cmdr1::R`](R) reader structure"]
impl crate::Readable for Cmdr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cmdr1::W`](W) writer structure"]
impl crate::Writable for Cmdr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMDR1 to value 0"]
impl crate::Resettable for Cmdr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AR1 (rw) register accessor: Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ar1`]
module"]
#[doc(alias = "AR1")]
pub type Ar1 = crate::Reg<ar1::Ar1Spec>;
#[doc = "Address Register"]
pub mod ar1 {
#[doc = "Register `AR1` reader"]
pub type R = crate::R<Ar1Spec>;
#[doc = "Register `AR1` writer"]
pub type W = crate::W<Ar1Spec>;
#[doc = "Field `ADDR` reader - address to be sent to the external Flash memory"]
pub type AddrR = crate::FieldReader<u32>;
#[doc = "Field `ADDR` writer - address to be sent to the external Flash memory"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<Ar1Spec> {
AddrW::new(self, 0)
}
}
#[doc = "Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ar1Spec;
impl crate::RegisterSpec for Ar1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ar1::R`](R) reader structure"]
impl crate::Readable for Ar1Spec {}
#[doc = "`write(|w| ..)` method takes [`ar1::W`](W) writer structure"]
impl crate::Writable for Ar1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AR1 to value 0"]
impl crate::Resettable for Ar1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ABR1 (rw) register accessor: Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abr1`]
module"]
#[doc(alias = "ABR1")]
pub type Abr1 = crate::Reg<abr1::Abr1Spec>;
#[doc = "Alternate Byte Register"]
pub mod abr1 {
#[doc = "Register `ABR1` reader"]
pub type R = crate::R<Abr1Spec>;
#[doc = "Register `ABR1` writer"]
pub type W = crate::W<Abr1Spec>;
#[doc = "Field `ABYTE` reader - Alternate byte"]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - Alternate byte"]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<Abr1Spec> {
AbyteW::new(self, 0)
}
}
#[doc = "Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Abr1Spec;
impl crate::RegisterSpec for Abr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`abr1::R`](R) reader structure"]
impl crate::Readable for Abr1Spec {}
#[doc = "`write(|w| ..)` method takes [`abr1::W`](W) writer structure"]
impl crate::Writable for Abr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ABR1 to value 0"]
impl crate::Resettable for Abr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DLR1 (rw) register accessor: Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlr1`]
module"]
#[doc(alias = "DLR1")]
pub type Dlr1 = crate::Reg<dlr1::Dlr1Spec>;
#[doc = "Data Length Register"]
pub mod dlr1 {
#[doc = "Register `DLR1` reader"]
pub type R = crate::R<Dlr1Spec>;
#[doc = "Register `DLR1` writer"]
pub type W = crate::W<Dlr1Spec>;
#[doc = "Field `DLEN` reader - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenR = crate::FieldReader<u32>;
#[doc = "Field `DLEN` writer - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
pub fn dlen(&self) -> DlenR {
DlenR::new(self.bits & 0x000f_ffff)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
#[must_use]
pub fn dlen(&mut self) -> DlenW<Dlr1Spec> {
DlenW::new(self, 0)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dlr1Spec> {
RsvdW::new(self, 20)
}
}
#[doc = "Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dlr1Spec;
impl crate::RegisterSpec for Dlr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dlr1::R`](R) reader structure"]
impl crate::Readable for Dlr1Spec {}
#[doc = "`write(|w| ..)` method takes [`dlr1::W`](W) writer structure"]
impl crate::Writable for Dlr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DLR1 to value 0"]
impl crate::Resettable for Dlr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR1 (rw) register accessor: Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`]
module"]
#[doc(alias = "CCR1")]
pub type Ccr1 = crate::Reg<ccr1::Ccr1Spec>;
#[doc = "Communication Configuration Register"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub type R = crate::R<Ccr1Spec>;
#[doc = "Register `CCR1` writer"]
pub type W = crate::W<Ccr1Spec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `FMODE` reader - 0 - read mode, 1 - write mode"]
pub type FmodeR = crate::BitReader;
#[doc = "Field `FMODE` writer - 0 - read mode, 1 - write mode"]
pub type FmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
pub fn fmode(&self) -> FmodeR {
FmodeR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<Ccr1Spec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<Ccr1Spec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<Ccr1Spec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<Ccr1Spec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<Ccr1Spec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<Ccr1Spec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<Ccr1Spec> {
DmodeW::new(self, 18)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
#[must_use]
pub fn fmode(&mut self) -> FmodeW<Ccr1Spec> {
FmodeW::new(self, 21)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr1Spec> {
RsvdW::new(self, 22)
}
}
#[doc = "Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr1Spec;
impl crate::RegisterSpec for Ccr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"]
impl crate::Readable for Ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"]
impl crate::Writable for Ccr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for Ccr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CMDR2 (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdr2`]
module"]
#[doc(alias = "CMDR2")]
pub type Cmdr2 = crate::Reg<cmdr2::Cmdr2Spec>;
#[doc = "Command Register"]
pub mod cmdr2 {
#[doc = "Register `CMDR2` reader"]
pub type R = crate::R<Cmdr2Spec>;
#[doc = "Register `CMDR2` writer"]
pub type W = crate::W<Cmdr2Spec>;
#[doc = "Field `CMD` reader - command"]
pub type CmdR = crate::FieldReader;
#[doc = "Field `CMD` writer - command"]
pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
pub fn cmd(&self) -> CmdR {
CmdR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
#[must_use]
pub fn cmd(&mut self) -> CmdW<Cmdr2Spec> {
CmdW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cmdr2Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmdr2Spec;
impl crate::RegisterSpec for Cmdr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cmdr2::R`](R) reader structure"]
impl crate::Readable for Cmdr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cmdr2::W`](W) writer structure"]
impl crate::Writable for Cmdr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMDR2 to value 0"]
impl crate::Resettable for Cmdr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AR2 (rw) register accessor: Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ar2`]
module"]
#[doc(alias = "AR2")]
pub type Ar2 = crate::Reg<ar2::Ar2Spec>;
#[doc = "Address Register"]
pub mod ar2 {
#[doc = "Register `AR2` reader"]
pub type R = crate::R<Ar2Spec>;
#[doc = "Register `AR2` writer"]
pub type W = crate::W<Ar2Spec>;
#[doc = "Field `ADDR` reader - address to be sent to the external Flash memory"]
pub type AddrR = crate::FieldReader<u32>;
#[doc = "Field `ADDR` writer - address to be sent to the external Flash memory"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<Ar2Spec> {
AddrW::new(self, 0)
}
}
#[doc = "Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ar2Spec;
impl crate::RegisterSpec for Ar2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ar2::R`](R) reader structure"]
impl crate::Readable for Ar2Spec {}
#[doc = "`write(|w| ..)` method takes [`ar2::W`](W) writer structure"]
impl crate::Writable for Ar2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AR2 to value 0"]
impl crate::Resettable for Ar2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ABR2 (rw) register accessor: Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abr2`]
module"]
#[doc(alias = "ABR2")]
pub type Abr2 = crate::Reg<abr2::Abr2Spec>;
#[doc = "Alternate Byte Register"]
pub mod abr2 {
#[doc = "Register `ABR2` reader"]
pub type R = crate::R<Abr2Spec>;
#[doc = "Register `ABR2` writer"]
pub type W = crate::W<Abr2Spec>;
#[doc = "Field `ABYTE` reader - Alternate byte"]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - Alternate byte"]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<Abr2Spec> {
AbyteW::new(self, 0)
}
}
#[doc = "Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Abr2Spec;
impl crate::RegisterSpec for Abr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`abr2::R`](R) reader structure"]
impl crate::Readable for Abr2Spec {}
#[doc = "`write(|w| ..)` method takes [`abr2::W`](W) writer structure"]
impl crate::Writable for Abr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ABR2 to value 0"]
impl crate::Resettable for Abr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DLR2 (rw) register accessor: Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlr2`]
module"]
#[doc(alias = "DLR2")]
pub type Dlr2 = crate::Reg<dlr2::Dlr2Spec>;
#[doc = "Data Length Register"]
pub mod dlr2 {
#[doc = "Register `DLR2` reader"]
pub type R = crate::R<Dlr2Spec>;
#[doc = "Register `DLR2` writer"]
pub type W = crate::W<Dlr2Spec>;
#[doc = "Field `DLEN` reader - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenR = crate::FieldReader<u32>;
#[doc = "Field `DLEN` writer - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
pub fn dlen(&self) -> DlenR {
DlenR::new(self.bits & 0x000f_ffff)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
#[must_use]
pub fn dlen(&mut self) -> DlenW<Dlr2Spec> {
DlenW::new(self, 0)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dlr2Spec> {
RsvdW::new(self, 20)
}
}
#[doc = "Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dlr2Spec;
impl crate::RegisterSpec for Dlr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dlr2::R`](R) reader structure"]
impl crate::Readable for Dlr2Spec {}
#[doc = "`write(|w| ..)` method takes [`dlr2::W`](W) writer structure"]
impl crate::Writable for Dlr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DLR2 to value 0"]
impl crate::Resettable for Dlr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR2 (rw) register accessor: Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`]
module"]
#[doc(alias = "CCR2")]
pub type Ccr2 = crate::Reg<ccr2::Ccr2Spec>;
#[doc = "Communication Configuration Register"]
pub mod ccr2 {
#[doc = "Register `CCR2` reader"]
pub type R = crate::R<Ccr2Spec>;
#[doc = "Register `CCR2` writer"]
pub type W = crate::W<Ccr2Spec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `FMODE` reader - 0 - read mode, 1 - write mode"]
pub type FmodeR = crate::BitReader;
#[doc = "Field `FMODE` writer - 0 - read mode, 1 - write mode"]
pub type FmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
pub fn fmode(&self) -> FmodeR {
FmodeR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<Ccr2Spec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<Ccr2Spec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<Ccr2Spec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<Ccr2Spec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<Ccr2Spec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<Ccr2Spec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<Ccr2Spec> {
DmodeW::new(self, 18)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
#[must_use]
pub fn fmode(&mut self) -> FmodeW<Ccr2Spec> {
FmodeW::new(self, 21)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr2Spec> {
RsvdW::new(self, 22)
}
}
#[doc = "Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr2Spec;
impl crate::RegisterSpec for Ccr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"]
impl crate::Readable for Ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"]
impl crate::Writable for Ccr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR2 to value 0"]
impl crate::Resettable for Ccr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HCMDR (rw) register accessor: AHB Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcmdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcmdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcmdr`]
module"]
#[doc(alias = "HCMDR")]
pub type Hcmdr = crate::Reg<hcmdr::HcmdrSpec>;
#[doc = "AHB Command Register"]
pub mod hcmdr {
#[doc = "Register `HCMDR` reader"]
pub type R = crate::R<HcmdrSpec>;
#[doc = "Register `HCMDR` writer"]
pub type W = crate::W<HcmdrSpec>;
#[doc = "Field `RCMD` reader - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
pub type RcmdR = crate::FieldReader;
#[doc = "Field `RCMD` writer - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
pub type RcmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `WCMD` reader - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
pub type WcmdR = crate::FieldReader;
#[doc = "Field `WCMD` writer - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
pub type WcmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:7 - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
#[inline(always)]
pub fn rcmd(&self) -> RcmdR {
RcmdR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
#[inline(always)]
pub fn wcmd(&self) -> WcmdR {
WcmdR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:7 - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
#[inline(always)]
#[must_use]
pub fn rcmd(&mut self) -> RcmdW<HcmdrSpec> {
RcmdW::new(self, 0)
}
#[doc = "Bits 8:15 - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
#[inline(always)]
#[must_use]
pub fn wcmd(&mut self) -> WcmdW<HcmdrSpec> {
WcmdW::new(self, 8)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<HcmdrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "AHB Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcmdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcmdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HcmdrSpec;
impl crate::RegisterSpec for HcmdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hcmdr::R`](R) reader structure"]
impl crate::Readable for HcmdrSpec {}
#[doc = "`write(|w| ..)` method takes [`hcmdr::W`](W) writer structure"]
impl crate::Writable for HcmdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HCMDR to value 0"]
impl crate::Resettable for HcmdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HRABR (rw) register accessor: AHB Read Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrabr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrabr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hrabr`]
module"]
#[doc(alias = "HRABR")]
pub type Hrabr = crate::Reg<hrabr::HrabrSpec>;
#[doc = "AHB Read Alternate Byte Register"]
pub mod hrabr {
#[doc = "Register `HRABR` reader"]
pub type R = crate::R<HrabrSpec>;
#[doc = "Register `HRABR` writer"]
pub type W = crate::W<HrabrSpec>;
#[doc = "Field `ABYTE` reader - "]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - "]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<HrabrSpec> {
AbyteW::new(self, 0)
}
}
#[doc = "AHB Read Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrabr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrabr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HrabrSpec;
impl crate::RegisterSpec for HrabrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hrabr::R`](R) reader structure"]
impl crate::Readable for HrabrSpec {}
#[doc = "`write(|w| ..)` method takes [`hrabr::W`](W) writer structure"]
impl crate::Writable for HrabrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HRABR to value 0"]
impl crate::Resettable for HrabrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HRCCR (rw) register accessor: AHB Read Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hrccr`]
module"]
#[doc(alias = "HRCCR")]
pub type Hrccr = crate::Reg<hrccr::HrccrSpec>;
#[doc = "AHB Read Communication Configuration Register"]
pub mod hrccr {
#[doc = "Register `HRCCR` reader"]
pub type R = crate::R<HrccrSpec>;
#[doc = "Register `HRCCR` writer"]
pub type W = crate::W<HrccrSpec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 21) & 0x07ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<HrccrSpec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<HrccrSpec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<HrccrSpec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<HrccrSpec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<HrccrSpec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<HrccrSpec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<HrccrSpec> {
DmodeW::new(self, 18)
}
#[doc = "Bits 21:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<HrccrSpec> {
RsvdW::new(self, 21)
}
}
#[doc = "AHB Read Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HrccrSpec;
impl crate::RegisterSpec for HrccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hrccr::R`](R) reader structure"]
impl crate::Readable for HrccrSpec {}
#[doc = "`write(|w| ..)` method takes [`hrccr::W`](W) writer structure"]
impl crate::Writable for HrccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HRCCR to value 0"]
impl crate::Resettable for HrccrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HWABR (rw) register accessor: AHB Write Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwabr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwabr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwabr`]
module"]
#[doc(alias = "HWABR")]
pub type Hwabr = crate::Reg<hwabr::HwabrSpec>;
#[doc = "AHB Write Alternate Byte Register"]
pub mod hwabr {
#[doc = "Register `HWABR` reader"]
pub type R = crate::R<HwabrSpec>;
#[doc = "Register `HWABR` writer"]
pub type W = crate::W<HwabrSpec>;
#[doc = "Field `ABYTE` reader - "]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - "]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<HwabrSpec> {
AbyteW::new(self, 0)
}
}
#[doc = "AHB Write Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwabr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwabr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwabrSpec;
impl crate::RegisterSpec for HwabrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hwabr::R`](R) reader structure"]
impl crate::Readable for HwabrSpec {}
#[doc = "`write(|w| ..)` method takes [`hwabr::W`](W) writer structure"]
impl crate::Writable for HwabrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HWABR to value 0"]
impl crate::Resettable for HwabrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HWCCR (rw) register accessor: AHB Write Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwccr`]
module"]
#[doc(alias = "HWCCR")]
pub type Hwccr = crate::Reg<hwccr::HwccrSpec>;
#[doc = "AHB Write Communication Configuration Register"]
pub mod hwccr {
#[doc = "Register `HWCCR` reader"]
pub type R = crate::R<HwccrSpec>;
#[doc = "Register `HWCCR` writer"]
pub type W = crate::W<HwccrSpec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 21) & 0x07ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<HwccrSpec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<HwccrSpec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<HwccrSpec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<HwccrSpec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<HwccrSpec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<HwccrSpec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<HwccrSpec> {
DmodeW::new(self, 18)
}
#[doc = "Bits 21:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<HwccrSpec> {
RsvdW::new(self, 21)
}
}
#[doc = "AHB Write Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwccrSpec;
impl crate::RegisterSpec for HwccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hwccr::R`](R) reader structure"]
impl crate::Readable for HwccrSpec {}
#[doc = "`write(|w| ..)` method takes [`hwccr::W`](W) writer structure"]
impl crate::Writable for HwccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HWCCR to value 0"]
impl crate::Resettable for HwccrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFOCR (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifocr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifocr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifocr`]
module"]
#[doc(alias = "FIFOCR")]
pub type Fifocr = crate::Reg<fifocr::FifocrSpec>;
#[doc = "FIFO Control Register"]
pub mod fifocr {
#[doc = "Register `FIFOCR` reader"]
pub type R = crate::R<FifocrSpec>;
#[doc = "Register `FIFOCR` writer"]
pub type W = crate::W<FifocrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifocrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifocr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifocr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifocrSpec;
impl crate::RegisterSpec for FifocrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifocr::R`](R) reader structure"]
impl crate::Readable for FifocrSpec {}
#[doc = "`write(|w| ..)` method takes [`fifocr::W`](W) writer structure"]
impl crate::Writable for FifocrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFOCR to value 0"]
impl crate::Resettable for FifocrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "MISCR (rw) register accessor: Miscelaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscr`]
module"]
#[doc(alias = "MISCR")]
pub type Miscr = crate::Reg<miscr::MiscrSpec>;
#[doc = "Miscelaneous Register"]
pub mod miscr {
#[doc = "Register `MISCR` reader"]
pub type R = crate::R<MiscrSpec>;
#[doc = "Register `MISCR` writer"]
pub type W = crate::W<MiscrSpec>;
#[doc = "Field `RXCLKDLY` reader - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
pub type RxclkdlyR = crate::FieldReader;
#[doc = "Field `RXCLKDLY` writer - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
pub type RxclkdlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SCKDLY` reader - Add delay on SCK (fine tune). Effective 7-bit"]
pub type SckdlyR = crate::FieldReader;
#[doc = "Field `SCKDLY` writer - Add delay on SCK (fine tune). Effective 7-bit"]
pub type SckdlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `DQSDLY` reader - select delayed version of DQS. Effective 7-bit"]
pub type DqsdlyR = crate::FieldReader;
#[doc = "Field `DQSDLY` writer - select delayed version of DQS. Effective 7-bit"]
pub type DqsdlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RXCLKINV` reader - Invert FCLK as Rx sampling clock (coarse tune)"]
pub type RxclkinvR = crate::BitReader;
#[doc = "Field `RXCLKINV` writer - Invert FCLK as Rx sampling clock (coarse tune)"]
pub type RxclkinvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCKINV` reader - Invert FCLK as SCK (coarse tune)"]
pub type SckinvR = crate::BitReader;
#[doc = "Field `SCKINV` writer - Invert FCLK as SCK (coarse tune)"]
pub type SckinvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DTRPRE` reader - Enable pre-sampling for DTR (for slow frequency)"]
pub type DtrpreR = crate::BitReader;
#[doc = "Field `DTRPRE` writer - Enable pre-sampling for DTR (for slow frequency)"]
pub type DtrpreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
#[doc = "Bits 0:7 - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
#[inline(always)]
pub fn rxclkdly(&self) -> RxclkdlyR {
RxclkdlyR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Add delay on SCK (fine tune). Effective 7-bit"]
#[inline(always)]
pub fn sckdly(&self) -> SckdlyR {
SckdlyR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - select delayed version of DQS. Effective 7-bit"]
#[inline(always)]
pub fn dqsdly(&self) -> DqsdlyR {
DqsdlyR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bit 24 - Invert FCLK as Rx sampling clock (coarse tune)"]
#[inline(always)]
pub fn rxclkinv(&self) -> RxclkinvR {
RxclkinvR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Invert FCLK as SCK (coarse tune)"]
#[inline(always)]
pub fn sckinv(&self) -> SckinvR {
SckinvR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Enable pre-sampling for DTR (for slow frequency)"]
#[inline(always)]
pub fn dtrpre(&self) -> DtrpreR {
DtrpreR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bits 27:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 27) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
#[inline(always)]
#[must_use]
pub fn rxclkdly(&mut self) -> RxclkdlyW<MiscrSpec> {
RxclkdlyW::new(self, 0)
}
#[doc = "Bits 8:15 - Add delay on SCK (fine tune). Effective 7-bit"]
#[inline(always)]
#[must_use]
pub fn sckdly(&mut self) -> SckdlyW<MiscrSpec> {
SckdlyW::new(self, 8)
}
#[doc = "Bits 16:23 - select delayed version of DQS. Effective 7-bit"]
#[inline(always)]
#[must_use]
pub fn dqsdly(&mut self) -> DqsdlyW<MiscrSpec> {
DqsdlyW::new(self, 16)
}
#[doc = "Bit 24 - Invert FCLK as Rx sampling clock (coarse tune)"]
#[inline(always)]
#[must_use]
pub fn rxclkinv(&mut self) -> RxclkinvW<MiscrSpec> {
RxclkinvW::new(self, 24)
}
#[doc = "Bit 25 - Invert FCLK as SCK (coarse tune)"]
#[inline(always)]
#[must_use]
pub fn sckinv(&mut self) -> SckinvW<MiscrSpec> {
SckinvW::new(self, 25)
}
#[doc = "Bit 26 - Enable pre-sampling for DTR (for slow frequency)"]
#[inline(always)]
#[must_use]
pub fn dtrpre(&mut self) -> DtrpreW<MiscrSpec> {
DtrpreW::new(self, 26)
}
#[doc = "Bits 27:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<MiscrSpec> {
RsvdW::new(self, 27)
}
}
#[doc = "Miscelaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscrSpec;
impl crate::RegisterSpec for MiscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miscr::R`](R) reader structure"]
impl crate::Readable for MiscrSpec {}
#[doc = "`write(|w| ..)` method takes [`miscr::W`](W) writer structure"]
impl crate::Writable for MiscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISCR to value 0"]
impl crate::Resettable for MiscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CTRSAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrsar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrsar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrsar`]
module"]
#[doc(alias = "CTRSAR")]
pub type Ctrsar = crate::Reg<ctrsar::CtrsarSpec>;
#[doc = ""]
pub mod ctrsar {
#[doc = "Register `CTRSAR` reader"]
pub type R = crate::R<CtrsarSpec>;
#[doc = "Register `CTRSAR` writer"]
pub type W = crate::W<CtrsarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CtrsarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrsar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrsar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrsarSpec;
impl crate::RegisterSpec for CtrsarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrsar::R`](R) reader structure"]
impl crate::Readable for CtrsarSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrsar::W`](W) writer structure"]
impl crate::Writable for CtrsarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTRSAR to value 0"]
impl crate::Resettable for CtrsarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CTREAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrear`]
module"]
#[doc(alias = "CTREAR")]
pub type Ctrear = crate::Reg<ctrear::CtrearSpec>;
#[doc = ""]
pub mod ctrear {
#[doc = "Register `CTREAR` reader"]
pub type R = crate::R<CtrearSpec>;
#[doc = "Register `CTREAR` writer"]
pub type W = crate::W<CtrearSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CtrearSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrearSpec;
impl crate::RegisterSpec for CtrearSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrear::R`](R) reader structure"]
impl crate::Readable for CtrearSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrear::W`](W) writer structure"]
impl crate::Writable for CtrearSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTREAR to value 0"]
impl crate::Resettable for CtrearSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "NONCEA (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`noncea::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`noncea::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@noncea`]
module"]
#[doc(alias = "NONCEA")]
pub type Noncea = crate::Reg<noncea::NonceaSpec>;
#[doc = ""]
pub mod noncea {
#[doc = "Register `NONCEA` reader"]
pub type R = crate::R<NonceaSpec>;
#[doc = "Register `NONCEA` writer"]
pub type W = crate::W<NonceaSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<NonceaSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`noncea::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`noncea::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NonceaSpec;
impl crate::RegisterSpec for NonceaSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`noncea::R`](R) reader structure"]
impl crate::Readable for NonceaSpec {}
#[doc = "`write(|w| ..)` method takes [`noncea::W`](W) writer structure"]
impl crate::Writable for NonceaSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets NONCEA to value 0"]
impl crate::Resettable for NonceaSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "NONCEB (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nonceb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nonceb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nonceb`]
module"]
#[doc(alias = "NONCEB")]
pub type Nonceb = crate::Reg<nonceb::NoncebSpec>;
#[doc = ""]
pub mod nonceb {
#[doc = "Register `NONCEB` reader"]
pub type R = crate::R<NoncebSpec>;
#[doc = "Register `NONCEB` writer"]
pub type W = crate::W<NoncebSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<NoncebSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nonceb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nonceb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NoncebSpec;
impl crate::RegisterSpec for NoncebSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`nonceb::R`](R) reader structure"]
impl crate::Readable for NoncebSpec {}
#[doc = "`write(|w| ..)` method takes [`nonceb::W`](W) writer structure"]
impl crate::Writable for NoncebSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets NONCEB to value 0"]
impl crate::Resettable for NoncebSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AASAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aasar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aasar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aasar`]
module"]
#[doc(alias = "AASAR")]
pub type Aasar = crate::Reg<aasar::AasarSpec>;
#[doc = ""]
pub mod aasar {
#[doc = "Register `AASAR` reader"]
pub type R = crate::R<AasarSpec>;
#[doc = "Register `AASAR` writer"]
pub type W = crate::W<AasarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AasarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aasar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aasar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AasarSpec;
impl crate::RegisterSpec for AasarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`aasar::R`](R) reader structure"]
impl crate::Readable for AasarSpec {}
#[doc = "`write(|w| ..)` method takes [`aasar::W`](W) writer structure"]
impl crate::Writable for AasarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AASAR to value 0"]
impl crate::Resettable for AasarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AAEAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aaear`]
module"]
#[doc(alias = "AAEAR")]
pub type Aaear = crate::Reg<aaear::AaearSpec>;
#[doc = ""]
pub mod aaear {
#[doc = "Register `AAEAR` reader"]
pub type R = crate::R<AaearSpec>;
#[doc = "Register `AAEAR` writer"]
pub type W = crate::W<AaearSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AaearSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AaearSpec;
impl crate::RegisterSpec for AaearSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`aaear::R`](R) reader structure"]
impl crate::Readable for AaearSpec {}
#[doc = "`write(|w| ..)` method takes [`aaear::W`](W) writer structure"]
impl crate::Writable for AaearSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AAEAR to value 0"]
impl crate::Resettable for AaearSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AAOAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaoar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaoar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aaoar`]
module"]
#[doc(alias = "AAOAR")]
pub type Aaoar = crate::Reg<aaoar::AaoarSpec>;
#[doc = ""]
pub mod aaoar {
#[doc = "Register `AAOAR` reader"]
pub type R = crate::R<AaoarSpec>;
#[doc = "Register `AAOAR` writer"]
pub type W = crate::W<AaoarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AaoarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaoar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaoar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AaoarSpec;
impl crate::RegisterSpec for AaoarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`aaoar::R`](R) reader structure"]
impl crate::Readable for AaoarSpec {}
#[doc = "`write(|w| ..)` method takes [`aaoar::W`](W) writer structure"]
impl crate::Writable for AaoarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AAOAR to value 0"]
impl crate::Resettable for AaoarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CIR (rw) register accessor: Command Interval Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir`]
module"]
#[doc(alias = "CIR")]
pub type Cir = crate::Reg<cir::CirSpec>;
#[doc = "Command Interval Register"]
pub mod cir {
#[doc = "Register `CIR` reader"]
pub type R = crate::R<CirSpec>;
#[doc = "Register `CIR` writer"]
pub type W = crate::W<CirSpec>;
#[doc = "Field `INTERVAL1` reader - "]
pub type Interval1R = crate::FieldReader<u16>;
#[doc = "Field `INTERVAL1` writer - "]
pub type Interval1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `INTERVAL2` reader - "]
pub type Interval2R = crate::FieldReader<u16>;
#[doc = "Field `INTERVAL2` writer - "]
pub type Interval2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn interval1(&self) -> Interval1R {
Interval1R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn interval2(&self) -> Interval2R {
Interval2R::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn interval1(&mut self) -> Interval1W<CirSpec> {
Interval1W::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn interval2(&mut self) -> Interval2W<CirSpec> {
Interval2W::new(self, 16)
}
}
#[doc = "Command Interval Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CirSpec;
impl crate::RegisterSpec for CirSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cir::R`](R) reader structure"]
impl crate::Readable for CirSpec {}
#[doc = "`write(|w| ..)` method takes [`cir::W`](W) writer structure"]
impl crate::Writable for CirSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CIR to value 0"]
impl crate::Resettable for CirSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMR (rw) register accessor: Status Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smr`]
module"]
#[doc(alias = "SMR")]
pub type Smr = crate::Reg<smr::SmrSpec>;
#[doc = "Status Match Register"]
pub mod smr {
#[doc = "Register `SMR` reader"]
pub type R = crate::R<SmrSpec>;
#[doc = "Register `SMR` writer"]
pub type W = crate::W<SmrSpec>;
#[doc = "Field `STATUS` reader - "]
pub type StatusR = crate::FieldReader<u32>;
#[doc = "Field `STATUS` writer - "]
pub type StatusW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn status(&self) -> StatusR {
StatusR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn status(&mut self) -> StatusW<SmrSpec> {
StatusW::new(self, 0)
}
}
#[doc = "Status Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmrSpec;
impl crate::RegisterSpec for SmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smr::R`](R) reader structure"]
impl crate::Readable for SmrSpec {}
#[doc = "`write(|w| ..)` method takes [`smr::W`](W) writer structure"]
impl crate::Writable for SmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMR to value 0"]
impl crate::Resettable for SmrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMKR (rw) register accessor: Status Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smkr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smkr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smkr`]
module"]
#[doc(alias = "SMKR")]
pub type Smkr = crate::Reg<smkr::SmkrSpec>;
#[doc = "Status Mask Register"]
pub mod smkr {
#[doc = "Register `SMKR` reader"]
pub type R = crate::R<SmkrSpec>;
#[doc = "Register `SMKR` writer"]
pub type W = crate::W<SmkrSpec>;
#[doc = "Field `MASK` reader - 0 - not considered; 1 - considered"]
pub type MaskR = crate::FieldReader<u32>;
#[doc = "Field `MASK` writer - 0 - not considered; 1 - considered"]
pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - 0 - not considered; 1 - considered"]
#[inline(always)]
pub fn mask(&self) -> MaskR {
MaskR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - 0 - not considered; 1 - considered"]
#[inline(always)]
#[must_use]
pub fn mask(&mut self) -> MaskW<SmkrSpec> {
MaskW::new(self, 0)
}
}
#[doc = "Status Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smkr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smkr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmkrSpec;
impl crate::RegisterSpec for SmkrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smkr::R`](R) reader structure"]
impl crate::Readable for SmkrSpec {}
#[doc = "`write(|w| ..)` method takes [`smkr::W`](W) writer structure"]
impl crate::Writable for SmkrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMKR to value 0"]
impl crate::Resettable for SmkrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TIMR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timr`]
module"]
#[doc(alias = "TIMR")]
pub type Timr = crate::Reg<timr::TimrSpec>;
#[doc = ""]
pub mod timr {
#[doc = "Register `TIMR` reader"]
pub type R = crate::R<TimrSpec>;
#[doc = "Register `TIMR` writer"]
pub type W = crate::W<TimrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TimrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimrSpec;
impl crate::RegisterSpec for TimrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timr::R`](R) reader structure"]
impl crate::Readable for TimrSpec {}
#[doc = "`write(|w| ..)` method takes [`timr::W`](W) writer structure"]
impl crate::Writable for TimrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TIMR to value 0"]
impl crate::Resettable for TimrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDTR (rw) register accessor: WDT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtr`]
module"]
#[doc(alias = "WDTR")]
pub type Wdtr = crate::Reg<wdtr::WdtrSpec>;
#[doc = "WDT Register"]
pub mod wdtr {
#[doc = "Register `WDTR` reader"]
pub type R = crate::R<WdtrSpec>;
#[doc = "Register `WDTR` writer"]
pub type W = crate::W<WdtrSpec>;
#[doc = "Field `TIMEOUT` reader - Set AHB timeout value in number of clk_wdt cycles"]
pub type TimeoutR = crate::FieldReader<u16>;
#[doc = "Field `TIMEOUT` writer - Set AHB timeout value in number of clk_wdt cycles"]
pub type TimeoutW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `EN` reader - WDT enable"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - WDT enable"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `TOF` reader - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
pub type TofR = crate::BitReader;
#[doc = "Field `TOF` writer - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
pub type TofW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:15 - Set AHB timeout value in number of clk_wdt cycles"]
#[inline(always)]
pub fn timeout(&self) -> TimeoutR {
TimeoutR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 16 - WDT enable"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 17) & 0x3fff) as u16)
}
#[doc = "Bit 31 - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
#[inline(always)]
pub fn tof(&self) -> TofR {
TofR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15 - Set AHB timeout value in number of clk_wdt cycles"]
#[inline(always)]
#[must_use]
pub fn timeout(&mut self) -> TimeoutW<WdtrSpec> {
TimeoutW::new(self, 0)
}
#[doc = "Bit 16 - WDT enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<WdtrSpec> {
EnW::new(self, 16)
}
#[doc = "Bits 17:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtrSpec> {
RsvdW::new(self, 17)
}
#[doc = "Bit 31 - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
#[inline(always)]
#[must_use]
pub fn tof(&mut self) -> TofW<WdtrSpec> {
TofW::new(self, 31)
}
}
#[doc = "WDT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtrSpec;
impl crate::RegisterSpec for WdtrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdtr::R`](R) reader structure"]
impl crate::Readable for WdtrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdtr::W`](W) writer structure"]
impl crate::Writable for WdtrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDTR to value 0"]
impl crate::Resettable for WdtrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PRSAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prsar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prsar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prsar`]
module"]
#[doc(alias = "PRSAR")]
pub type Prsar = crate::Reg<prsar::PrsarSpec>;
#[doc = ""]
pub mod prsar {
#[doc = "Register `PRSAR` reader"]
pub type R = crate::R<PrsarSpec>;
#[doc = "Register `PRSAR` writer"]
pub type W = crate::W<PrsarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PrsarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prsar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prsar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrsarSpec;
impl crate::RegisterSpec for PrsarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`prsar::R`](R) reader structure"]
impl crate::Readable for PrsarSpec {}
#[doc = "`write(|w| ..)` method takes [`prsar::W`](W) writer structure"]
impl crate::Writable for PrsarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PRSAR to value 0"]
impl crate::Resettable for PrsarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PREAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prear`]
module"]
#[doc(alias = "PREAR")]
pub type Prear = crate::Reg<prear::PrearSpec>;
#[doc = ""]
pub mod prear {
#[doc = "Register `PREAR` reader"]
pub type R = crate::R<PrearSpec>;
#[doc = "Register `PREAR` writer"]
pub type W = crate::W<PrearSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PrearSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrearSpec;
impl crate::RegisterSpec for PrearSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`prear::R`](R) reader structure"]
impl crate::Readable for PrearSpec {}
#[doc = "`write(|w| ..)` method takes [`prear::W`](W) writer structure"]
impl crate::Writable for PrearSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PREAR to value 0"]
impl crate::Resettable for PrearSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CALCR (rw) register accessor: Calibration Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calcr`]
module"]
#[doc(alias = "CALCR")]
pub type Calcr = crate::Reg<calcr::CalcrSpec>;
#[doc = "Calibration Control Register"]
pub mod calcr {
#[doc = "Register `CALCR` reader"]
pub type R = crate::R<CalcrSpec>;
#[doc = "Register `CALCR` writer"]
pub type W = crate::W<CalcrSpec>;
#[doc = "Field `DELAY` reader - calibration delay result"]
pub type DelayR = crate::FieldReader;
#[doc = "Field `DELAY` writer - calibration delay result"]
pub type DelayW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `DONE` reader - calibration done"]
pub type DoneR = crate::BitReader;
#[doc = "Field `DONE` writer - calibration done"]
pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
#[doc = "Field `EN` reader - calibration enable"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - calibration enable"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:7 - calibration delay result"]
#[inline(always)]
pub fn delay(&self) -> DelayR {
DelayR::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - calibration done"]
#[inline(always)]
pub fn done(&self) -> DoneR {
DoneR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x003f_ffff)
}
#[doc = "Bit 31 - calibration enable"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7 - calibration delay result"]
#[inline(always)]
#[must_use]
pub fn delay(&mut self) -> DelayW<CalcrSpec> {
DelayW::new(self, 0)
}
#[doc = "Bit 8 - calibration done"]
#[inline(always)]
#[must_use]
pub fn done(&mut self) -> DoneW<CalcrSpec> {
DoneW::new(self, 8)
}
#[doc = "Bits 9:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CalcrSpec> {
RsvdW::new(self, 9)
}
#[doc = "Bit 31 - calibration enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<CalcrSpec> {
EnW::new(self, 31)
}
}
#[doc = "Calibration Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CalcrSpec;
impl crate::RegisterSpec for CalcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`calcr::R`](R) reader structure"]
impl crate::Readable for CalcrSpec {}
#[doc = "`write(|w| ..)` method takes [`calcr::W`](W) writer structure"]
impl crate::Writable for CalcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CALCR to value 0"]
impl crate::Resettable for CalcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CALDOR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`caldor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`caldor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@caldor`]
module"]
#[doc(alias = "CALDOR")]
pub type Caldor = crate::Reg<caldor::CaldorSpec>;
#[doc = ""]
pub mod caldor {
#[doc = "Register `CALDOR` reader"]
pub type R = crate::R<CaldorSpec>;
#[doc = "Register `CALDOR` writer"]
pub type W = crate::W<CaldorSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CaldorSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`caldor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`caldor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CaldorSpec;
impl crate::RegisterSpec for CaldorSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`caldor::R`](R) reader structure"]
impl crate::Readable for CaldorSpec {}
#[doc = "`write(|w| ..)` method takes [`caldor::W`](W) writer structure"]
impl crate::Writable for CaldorSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CALDOR to value 0"]
impl crate::Resettable for CaldorSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "APM32CR (rw) register accessor: APM32 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apm32cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apm32cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apm32cr`]
module"]
#[doc(alias = "APM32CR")]
pub type Apm32cr = crate::Reg<apm32cr::Apm32crSpec>;
#[doc = "APM32 Control Register"]
pub mod apm32cr {
#[doc = "Register `APM32CR` reader"]
pub type R = crate::R<Apm32crSpec>;
#[doc = "Register `APM32CR` writer"]
pub type W = crate::W<Apm32crSpec>;
#[doc = "Field `TCPHR` reader - "]
pub type TcphrR = crate::FieldReader;
#[doc = "Field `TCPHR` writer - "]
pub type TcphrW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TCPHW` reader - "]
pub type TcphwR = crate::FieldReader;
#[doc = "Field `TCPHW` writer - "]
pub type TcphwW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn tcphr(&self) -> TcphrR {
TcphrR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn tcphw(&self) -> TcphwR {
TcphwR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn tcphr(&mut self) -> TcphrW<Apm32crSpec> {
TcphrW::new(self, 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn tcphw(&mut self) -> TcphwW<Apm32crSpec> {
TcphwW::new(self, 4)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Apm32crSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "APM32 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apm32cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apm32cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Apm32crSpec;
impl crate::RegisterSpec for Apm32crSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`apm32cr::R`](R) reader structure"]
impl crate::Readable for Apm32crSpec {}
#[doc = "`write(|w| ..)` method takes [`apm32cr::W`](W) writer structure"]
impl crate::Writable for Apm32crSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets APM32CR to value 0"]
impl crate::Resettable for Apm32crSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = ""]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "MPI2"]
pub struct Mpi2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Mpi2 {}
impl Mpi2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const mpi2::RegisterBlock = 0x5004_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const mpi2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Mpi2 {
type Target = mpi2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Mpi2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mpi2").finish()
}
}
#[doc = "MPI2"]
pub mod mpi2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr: Cr,
dr: Dr,
dcr: Dcr,
psclr: Psclr,
sr: Sr,
scr: Scr,
cmdr1: Cmdr1,
ar1: Ar1,
abr1: Abr1,
dlr1: Dlr1,
ccr1: Ccr1,
cmdr2: Cmdr2,
ar2: Ar2,
abr2: Abr2,
dlr2: Dlr2,
ccr2: Ccr2,
hcmdr: Hcmdr,
hrabr: Hrabr,
hrccr: Hrccr,
hwabr: Hwabr,
hwccr: Hwccr,
fifocr: Fifocr,
miscr: Miscr,
ctrsar: Ctrsar,
ctrear: Ctrear,
noncea: Noncea,
nonceb: Nonceb,
aasar: Aasar,
aaear: Aaear,
aaoar: Aaoar,
cir: Cir,
smr: Smr,
smkr: Smkr,
timr: Timr,
wdtr: Wdtr,
prsar: Prsar,
prear: Prear,
calcr: Calcr,
caldor: Caldor,
apm32cr: Apm32cr,
cr2: Cr2,
}
impl RegisterBlock {
#[doc = "0x00 - Control Register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x04 - Data Register"]
#[inline(always)]
pub const fn dr(&self) -> &Dr {
&self.dr
}
#[doc = "0x08 - Device Control Register"]
#[inline(always)]
pub const fn dcr(&self) -> &Dcr {
&self.dcr
}
#[doc = "0x0c - Prescaler Register"]
#[inline(always)]
pub const fn psclr(&self) -> &Psclr {
&self.psclr
}
#[doc = "0x10 - Status Register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Status Clear Register"]
#[inline(always)]
pub const fn scr(&self) -> &Scr {
&self.scr
}
#[doc = "0x18 - Command Register"]
#[inline(always)]
pub const fn cmdr1(&self) -> &Cmdr1 {
&self.cmdr1
}
#[doc = "0x1c - Address Register"]
#[inline(always)]
pub const fn ar1(&self) -> &Ar1 {
&self.ar1
}
#[doc = "0x20 - Alternate Byte Register"]
#[inline(always)]
pub const fn abr1(&self) -> &Abr1 {
&self.abr1
}
#[doc = "0x24 - Data Length Register"]
#[inline(always)]
pub const fn dlr1(&self) -> &Dlr1 {
&self.dlr1
}
#[doc = "0x28 - Communication Configuration Register"]
#[inline(always)]
pub const fn ccr1(&self) -> &Ccr1 {
&self.ccr1
}
#[doc = "0x2c - Command Register"]
#[inline(always)]
pub const fn cmdr2(&self) -> &Cmdr2 {
&self.cmdr2
}
#[doc = "0x30 - Address Register"]
#[inline(always)]
pub const fn ar2(&self) -> &Ar2 {
&self.ar2
}
#[doc = "0x34 - Alternate Byte Register"]
#[inline(always)]
pub const fn abr2(&self) -> &Abr2 {
&self.abr2
}
#[doc = "0x38 - Data Length Register"]
#[inline(always)]
pub const fn dlr2(&self) -> &Dlr2 {
&self.dlr2
}
#[doc = "0x3c - Communication Configuration Register"]
#[inline(always)]
pub const fn ccr2(&self) -> &Ccr2 {
&self.ccr2
}
#[doc = "0x40 - AHB Command Register"]
#[inline(always)]
pub const fn hcmdr(&self) -> &Hcmdr {
&self.hcmdr
}
#[doc = "0x44 - AHB Read Alternate Byte Register"]
#[inline(always)]
pub const fn hrabr(&self) -> &Hrabr {
&self.hrabr
}
#[doc = "0x48 - AHB Read Communication Configuration Register"]
#[inline(always)]
pub const fn hrccr(&self) -> &Hrccr {
&self.hrccr
}
#[doc = "0x4c - AHB Write Alternate Byte Register"]
#[inline(always)]
pub const fn hwabr(&self) -> &Hwabr {
&self.hwabr
}
#[doc = "0x50 - AHB Write Communication Configuration Register"]
#[inline(always)]
pub const fn hwccr(&self) -> &Hwccr {
&self.hwccr
}
#[doc = "0x54 - FIFO Control Register"]
#[inline(always)]
pub const fn fifocr(&self) -> &Fifocr {
&self.fifocr
}
#[doc = "0x58 - Miscelaneous Register"]
#[inline(always)]
pub const fn miscr(&self) -> &Miscr {
&self.miscr
}
#[doc = "0x5c - "]
#[inline(always)]
pub const fn ctrsar(&self) -> &Ctrsar {
&self.ctrsar
}
#[doc = "0x60 - "]
#[inline(always)]
pub const fn ctrear(&self) -> &Ctrear {
&self.ctrear
}
#[doc = "0x64 - "]
#[inline(always)]
pub const fn noncea(&self) -> &Noncea {
&self.noncea
}
#[doc = "0x68 - "]
#[inline(always)]
pub const fn nonceb(&self) -> &Nonceb {
&self.nonceb
}
#[doc = "0x6c - "]
#[inline(always)]
pub const fn aasar(&self) -> &Aasar {
&self.aasar
}
#[doc = "0x70 - "]
#[inline(always)]
pub const fn aaear(&self) -> &Aaear {
&self.aaear
}
#[doc = "0x74 - "]
#[inline(always)]
pub const fn aaoar(&self) -> &Aaoar {
&self.aaoar
}
#[doc = "0x78 - Command Interval Register"]
#[inline(always)]
pub const fn cir(&self) -> &Cir {
&self.cir
}
#[doc = "0x7c - Status Match Register"]
#[inline(always)]
pub const fn smr(&self) -> &Smr {
&self.smr
}
#[doc = "0x80 - Status Mask Register"]
#[inline(always)]
pub const fn smkr(&self) -> &Smkr {
&self.smkr
}
#[doc = "0x84 - "]
#[inline(always)]
pub const fn timr(&self) -> &Timr {
&self.timr
}
#[doc = "0x88 - WDT Register"]
#[inline(always)]
pub const fn wdtr(&self) -> &Wdtr {
&self.wdtr
}
#[doc = "0x8c - "]
#[inline(always)]
pub const fn prsar(&self) -> &Prsar {
&self.prsar
}
#[doc = "0x90 - "]
#[inline(always)]
pub const fn prear(&self) -> &Prear {
&self.prear
}
#[doc = "0x94 - Calibration Control Register"]
#[inline(always)]
pub const fn calcr(&self) -> &Calcr {
&self.calcr
}
#[doc = "0x98 - "]
#[inline(always)]
pub const fn caldor(&self) -> &Caldor {
&self.caldor
}
#[doc = "0x9c - APM32 Control Register"]
#[inline(always)]
pub const fn apm32cr(&self) -> &Apm32cr {
&self.apm32cr
}
#[doc = "0xa0 - "]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
}
#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `EN` reader - Enable MPI"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - Enable MPI"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::FieldReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DMAE` reader - DMA enable in FIFO mode"]
pub type DmaeR = crate::BitReader;
#[doc = "Field `DMAE` writer - DMA enable in FIFO mode"]
pub type DmaeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRE` reader - AES-CTR on-the-fly decryption enable"]
pub type CtreR = crate::BitReader;
#[doc = "Field `CTRE` writer - AES-CTR on-the-fly decryption enable"]
pub type CtreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRM` reader - AES-CTR mode. 0 - AES128, 1 - AES256"]
pub type CtrmR = crate::BitReader;
#[doc = "Field `CTRM` writer - AES-CTR mode. 0 - AES128, 1 - AES256"]
pub type CtrmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - Transfer complete interrupt enable"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - Transfer complete interrupt enable"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SMIE` reader - Status match interrupt enable"]
pub type SmieR = crate::BitReader;
#[doc = "Field `SMIE` writer - Status match interrupt enable"]
pub type SmieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CMD2E` reader - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
pub type Cmd2eR = crate::BitReader;
#[doc = "Field `CMD2E` writer - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
pub type Cmd2eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SME1` reader - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
pub type Sme1R = crate::BitReader;
#[doc = "Field `SME1` writer - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
pub type Sme1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SME2` reader - "]
pub type Sme2R = crate::BitReader;
#[doc = "Field `SME2` writer - "]
pub type Sme2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SMM` reader - Status match mode: 0 - AND mode; 1 - OR mode"]
pub type SmmR = crate::BitReader;
#[doc = "Field `SMM` writer - Status match mode: 0 - AND mode; 1 - OR mode"]
pub type SmmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HWIFE` reader - Hardware interface enable"]
pub type HwifeR = crate::BitReader;
#[doc = "Field `HWIFE` writer - Hardware interface enable"]
pub type HwifeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OPIE` reader - OPI interface enable"]
pub type OpieR = crate::BitReader;
#[doc = "Field `OPIE` writer - OPI interface enable"]
pub type OpieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MX16` reader - Mode X16"]
pub type Mx16R = crate::BitReader;
#[doc = "Field `MX16` writer - Mode X16"]
pub type Mx16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DFM` reader - Dual Flash Mode"]
pub type DfmR = crate::BitReader;
#[doc = "Field `DFM` writer - Dual Flash Mode"]
pub type DfmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `ABORT` reader - "]
pub type AbortR = crate::BitReader;
#[doc = "Field `ABORT` writer - "]
pub type AbortW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Enable MPI"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:4"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new(((self.bits >> 1) & 0x0f) as u8)
}
#[doc = "Bit 5 - DMA enable in FIFO mode"]
#[inline(always)]
pub fn dmae(&self) -> DmaeR {
DmaeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - AES-CTR on-the-fly decryption enable"]
#[inline(always)]
pub fn ctre(&self) -> CtreR {
CtreR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - AES-CTR mode. 0 - AES128, 1 - AES256"]
#[inline(always)]
pub fn ctrm(&self) -> CtrmR {
CtrmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Transfer complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Status match interrupt enable"]
#[inline(always)]
pub fn smie(&self) -> SmieR {
SmieR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bit 16 - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
#[inline(always)]
pub fn cmd2e(&self) -> Cmd2eR {
Cmd2eR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
#[inline(always)]
pub fn sme1(&self) -> Sme1R {
Sme1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn sme2(&self) -> Sme2R {
Sme2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Status match mode: 0 - AND mode; 1 - OR mode"]
#[inline(always)]
pub fn smm(&self) -> SmmR {
SmmR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Hardware interface enable"]
#[inline(always)]
pub fn hwife(&self) -> HwifeR {
HwifeR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - OPI interface enable"]
#[inline(always)]
pub fn opie(&self) -> OpieR {
OpieR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Mode X16"]
#[inline(always)]
pub fn mx16(&self) -> Mx16R {
Mx16R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Dual Flash Mode"]
#[inline(always)]
pub fn dfm(&self) -> DfmR {
DfmR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 25) & 0x3f) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn abort(&self) -> AbortR {
AbortR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Enable MPI"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<CrSpec> {
EnW::new(self, 0)
}
#[doc = "Bits 1:4"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<CrSpec> {
Rsvd5W::new(self, 1)
}
#[doc = "Bit 5 - DMA enable in FIFO mode"]
#[inline(always)]
#[must_use]
pub fn dmae(&mut self) -> DmaeW<CrSpec> {
DmaeW::new(self, 5)
}
#[doc = "Bit 6 - AES-CTR on-the-fly decryption enable"]
#[inline(always)]
#[must_use]
pub fn ctre(&mut self) -> CtreW<CrSpec> {
CtreW::new(self, 6)
}
#[doc = "Bit 7 - AES-CTR mode. 0 - AES128, 1 - AES256"]
#[inline(always)]
#[must_use]
pub fn ctrm(&mut self) -> CtrmW<CrSpec> {
CtrmW::new(self, 7)
}
#[doc = "Bit 8 - Transfer complete interrupt enable"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<CrSpec> {
TcieW::new(self, 8)
}
#[doc = "Bits 9:10"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CrSpec> {
Rsvd4W::new(self, 9)
}
#[doc = "Bit 11 - Status match interrupt enable"]
#[inline(always)]
#[must_use]
pub fn smie(&mut self) -> SmieW<CrSpec> {
SmieW::new(self, 11)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CrSpec> {
Rsvd3W::new(self, 12)
}
#[doc = "Bit 16 - Enable CMD2. If set to 1, CMD2 will be issued after CMD1 with an interval of TI2"]
#[inline(always)]
#[must_use]
pub fn cmd2e(&mut self) -> Cmd2eW<CrSpec> {
Cmd2eW::new(self, 16)
}
#[doc = "Bit 17 - Status match enable. SME\\[0\\]
enables CMD1, SME\\[1\\]
enable CMD2. Only one CMD can be used as SM CMD"]
#[inline(always)]
#[must_use]
pub fn sme1(&mut self) -> Sme1W<CrSpec> {
Sme1W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn sme2(&mut self) -> Sme2W<CrSpec> {
Sme2W::new(self, 18)
}
#[doc = "Bit 19 - Status match mode: 0 - AND mode; 1 - OR mode"]
#[inline(always)]
#[must_use]
pub fn smm(&mut self) -> SmmW<CrSpec> {
SmmW::new(self, 19)
}
#[doc = "Bit 20 - Hardware interface enable"]
#[inline(always)]
#[must_use]
pub fn hwife(&mut self) -> HwifeW<CrSpec> {
HwifeW::new(self, 20)
}
#[doc = "Bit 21 - OPI interface enable"]
#[inline(always)]
#[must_use]
pub fn opie(&mut self) -> OpieW<CrSpec> {
OpieW::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bit 23 - Mode X16"]
#[inline(always)]
#[must_use]
pub fn mx16(&mut self) -> Mx16W<CrSpec> {
Mx16W::new(self, 23)
}
#[doc = "Bit 24 - Dual Flash Mode"]
#[inline(always)]
#[must_use]
pub fn dfm(&mut self) -> DfmW<CrSpec> {
DfmW::new(self, 24)
}
#[doc = "Bits 25:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 25)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn abort(&mut self) -> AbortW<CrSpec> {
AbortW::new(self, 31)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DR (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`]
module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "Data Register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `DATA` reader - "]
pub type DataR = crate::FieldReader<u32>;
#[doc = "Field `DATA` writer - "]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DrSpec> {
DataW::new(self, 0)
}
}
#[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DCR (rw) register accessor: Device Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcr`]
module"]
#[doc(alias = "DCR")]
pub type Dcr = crate::Reg<dcr::DcrSpec>;
#[doc = "Device Control Register"]
pub mod dcr {
#[doc = "Register `DCR` reader"]
pub type R = crate::R<DcrSpec>;
#[doc = "Register `DCR` writer"]
pub type W = crate::W<DcrSpec>;
#[doc = "Field `RBSIZE` reader - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
pub type RbsizeR = crate::FieldReader;
#[doc = "Field `RBSIZE` writer - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
pub type RbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `DQSE` reader - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
pub type DqseR = crate::BitReader;
#[doc = "Field `DQSE` writer - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
pub type DqseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HYPER` reader - HyperBus protocol"]
pub type HyperR = crate::BitReader;
#[doc = "Field `HYPER` writer - HyperBus protocol"]
pub type HyperW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `XLEGACY` reader - Xccela legacy protocol"]
pub type XlegacyR = crate::BitReader;
#[doc = "Field `XLEGACY` writer - Xccela legacy protocol"]
pub type XlegacyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CSLMAX` reader - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
pub type CslmaxR = crate::FieldReader<u16>;
#[doc = "Field `CSLMAX` writer - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
pub type CslmaxW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `CSLMIN` reader - Minimum CS low active time. N - (n+1) cycles"]
pub type CslminR = crate::FieldReader;
#[doc = "Field `CSLMIN` writer - Minimum CS low active time. N - (n+1) cycles"]
pub type CslminW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CSHMIN` reader - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
pub type CshminR = crate::FieldReader;
#[doc = "Field `CSHMIN` writer - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
pub type CshminW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TRCMIN` reader - Write/Read cycle minimum time"]
pub type TrcminR = crate::FieldReader;
#[doc = "Field `TRCMIN` writer - Write/Read cycle minimum time"]
pub type TrcminW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `FIXLAT` reader - Indicate PSRAM is fixed latency or variable latency"]
pub type FixlatR = crate::BitReader;
#[doc = "Field `FIXLAT` writer - Indicate PSRAM is fixed latency or variable latency"]
pub type FixlatW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
#[inline(always)]
pub fn rbsize(&self) -> RbsizeR {
RbsizeR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
#[inline(always)]
pub fn dqse(&self) -> DqseR {
DqseR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - HyperBus protocol"]
#[inline(always)]
pub fn hyper(&self) -> HyperR {
HyperR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Xccela legacy protocol"]
#[inline(always)]
pub fn xlegacy(&self) -> XlegacyR {
XlegacyR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:17 - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
#[inline(always)]
pub fn cslmax(&self) -> CslmaxR {
CslmaxR::new(((self.bits >> 6) & 0x0fff) as u16)
}
#[doc = "Bits 18:21 - Minimum CS low active time. N - (n+1) cycles"]
#[inline(always)]
pub fn cslmin(&self) -> CslminR {
CslminR::new(((self.bits >> 18) & 0x0f) as u8)
}
#[doc = "Bits 22:25 - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
#[inline(always)]
pub fn cshmin(&self) -> CshminR {
CshminR::new(((self.bits >> 22) & 0x0f) as u8)
}
#[doc = "Bits 26:30 - Write/Read cycle minimum time"]
#[inline(always)]
pub fn trcmin(&self) -> TrcminR {
TrcminR::new(((self.bits >> 26) & 0x1f) as u8)
}
#[doc = "Bit 31 - Indicate PSRAM is fixed latency or variable latency"]
#[inline(always)]
pub fn fixlat(&self) -> FixlatR {
FixlatR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes"]
#[inline(always)]
#[must_use]
pub fn rbsize(&mut self) -> RbsizeW<DcrSpec> {
RbsizeW::new(self, 0)
}
#[doc = "Bit 3 - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching"]
#[inline(always)]
#[must_use]
pub fn dqse(&mut self) -> DqseW<DcrSpec> {
DqseW::new(self, 3)
}
#[doc = "Bit 4 - HyperBus protocol"]
#[inline(always)]
#[must_use]
pub fn hyper(&mut self) -> HyperW<DcrSpec> {
HyperW::new(self, 4)
}
#[doc = "Bit 5 - Xccela legacy protocol"]
#[inline(always)]
#[must_use]
pub fn xlegacy(&mut self) -> XlegacyW<DcrSpec> {
XlegacyW::new(self, 5)
}
#[doc = "Bits 6:17 - Maximum CS low active time. 0 - no limit, n - (n+1) cycles"]
#[inline(always)]
#[must_use]
pub fn cslmax(&mut self) -> CslmaxW<DcrSpec> {
CslmaxW::new(self, 6)
}
#[doc = "Bits 18:21 - Minimum CS low active time. N - (n+1) cycles"]
#[inline(always)]
#[must_use]
pub fn cslmin(&mut self) -> CslminW<DcrSpec> {
CslminW::new(self, 18)
}
#[doc = "Bits 22:25 - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc."]
#[inline(always)]
#[must_use]
pub fn cshmin(&mut self) -> CshminW<DcrSpec> {
CshminW::new(self, 22)
}
#[doc = "Bits 26:30 - Write/Read cycle minimum time"]
#[inline(always)]
#[must_use]
pub fn trcmin(&mut self) -> TrcminW<DcrSpec> {
TrcminW::new(self, 26)
}
#[doc = "Bit 31 - Indicate PSRAM is fixed latency or variable latency"]
#[inline(always)]
#[must_use]
pub fn fixlat(&mut self) -> FixlatW<DcrSpec> {
FixlatW::new(self, 31)
}
}
#[doc = "Device Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcrSpec;
impl crate::RegisterSpec for DcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dcr::R`](R) reader structure"]
impl crate::Readable for DcrSpec {}
#[doc = "`write(|w| ..)` method takes [`dcr::W`](W) writer structure"]
impl crate::Writable for DcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DCR to value 0"]
impl crate::Resettable for DcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSCLR (rw) register accessor: Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psclr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psclr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psclr`]
module"]
#[doc(alias = "PSCLR")]
pub type Psclr = crate::Reg<psclr::PsclrSpec>;
#[doc = "Prescaler Register"]
pub mod psclr {
#[doc = "Register `PSCLR` reader"]
pub type R = crate::R<PsclrSpec>;
#[doc = "Register `PSCLR` writer"]
pub type W = crate::W<PsclrSpec>;
#[doc = "Field `DIV` reader - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
pub type DivR = crate::FieldReader;
#[doc = "Field `DIV` writer - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
#[inline(always)]
pub fn div(&self) -> DivR {
DivR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - FCLK divided by DIV. 0/1 - SCLK=FCLK, 2 - SCLK=FCLK/2, n - SCLK=FCLK/n"]
#[inline(always)]
#[must_use]
pub fn div(&mut self) -> DivW<PsclrSpec> {
DivW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PsclrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psclr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psclr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsclrSpec;
impl crate::RegisterSpec for PsclrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psclr::R`](R) reader structure"]
impl crate::Readable for PsclrSpec {}
#[doc = "`write(|w| ..)` method takes [`psclr::W`](W) writer structure"]
impl crate::Writable for PsclrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSCLR to value 0"]
impl crate::Resettable for PsclrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status Register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `TCF` reader - Transfer complete flag"]
pub type TcfR = crate::BitReader;
#[doc = "Field `TCF` writer - Transfer complete flag"]
pub type TcfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SMF` reader - Status match flag in Polling Mode"]
pub type SmfR = crate::BitReader;
#[doc = "Field `SMF` writer - Status match flag in Polling Mode"]
pub type SmfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
#[doc = "Field `BUSY` reader - "]
pub type BusyR = crate::BitReader;
#[doc = "Field `BUSY` writer - "]
pub type BusyW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Transfer complete flag"]
#[inline(always)]
pub fn tcf(&self) -> TcfR {
TcfR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3 - Status match flag in Polling Mode"]
#[inline(always)]
pub fn smf(&self) -> SmfR {
SmfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x07ff_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn busy(&self) -> BusyR {
BusyR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcf(&mut self) -> TcfW<SrSpec> {
TcfW::new(self, 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SrSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 3 - Status match flag in Polling Mode"]
#[inline(always)]
#[must_use]
pub fn smf(&mut self) -> SmfW<SrSpec> {
SmfW::new(self, 3)
}
#[doc = "Bits 4:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 4)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn busy(&mut self) -> BusyW<SrSpec> {
BusyW::new(self, 31)
}
}
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SCR (rw) register accessor: Status Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`]
module"]
#[doc(alias = "SCR")]
pub type Scr = crate::Reg<scr::ScrSpec>;
#[doc = "Status Clear Register"]
pub mod scr {
#[doc = "Register `SCR` reader"]
pub type R = crate::R<ScrSpec>;
#[doc = "Register `SCR` writer"]
pub type W = crate::W<ScrSpec>;
#[doc = "Field `TCFC` reader - Write 1 to clear corresponding flag in SR"]
pub type TcfcR = crate::BitReader;
#[doc = "Field `TCFC` writer - Write 1 to clear corresponding flag in SR"]
pub type TcfcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SMFC` reader - "]
pub type SmfcR = crate::BitReader;
#[doc = "Field `SMFC` writer - "]
pub type SmfcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - Write 1 to clear corresponding flag in SR"]
#[inline(always)]
pub fn tcfc(&self) -> TcfcR {
TcfcR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn smfc(&self) -> SmfcR {
SmfcR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Write 1 to clear corresponding flag in SR"]
#[inline(always)]
#[must_use]
pub fn tcfc(&mut self) -> TcfcW<ScrSpec> {
TcfcW::new(self, 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<ScrSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn smfc(&mut self) -> SmfcW<ScrSpec> {
SmfcW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ScrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "Status Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScrSpec;
impl crate::RegisterSpec for ScrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`scr::R`](R) reader structure"]
impl crate::Readable for ScrSpec {}
#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"]
impl crate::Writable for ScrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SCR to value 0"]
impl crate::Resettable for ScrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CMDR1 (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdr1`]
module"]
#[doc(alias = "CMDR1")]
pub type Cmdr1 = crate::Reg<cmdr1::Cmdr1Spec>;
#[doc = "Command Register"]
pub mod cmdr1 {
#[doc = "Register `CMDR1` reader"]
pub type R = crate::R<Cmdr1Spec>;
#[doc = "Register `CMDR1` writer"]
pub type W = crate::W<Cmdr1Spec>;
#[doc = "Field `CMD` reader - command"]
pub type CmdR = crate::FieldReader;
#[doc = "Field `CMD` writer - command"]
pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
pub fn cmd(&self) -> CmdR {
CmdR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
#[must_use]
pub fn cmd(&mut self) -> CmdW<Cmdr1Spec> {
CmdW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cmdr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmdr1Spec;
impl crate::RegisterSpec for Cmdr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cmdr1::R`](R) reader structure"]
impl crate::Readable for Cmdr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cmdr1::W`](W) writer structure"]
impl crate::Writable for Cmdr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMDR1 to value 0"]
impl crate::Resettable for Cmdr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AR1 (rw) register accessor: Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ar1`]
module"]
#[doc(alias = "AR1")]
pub type Ar1 = crate::Reg<ar1::Ar1Spec>;
#[doc = "Address Register"]
pub mod ar1 {
#[doc = "Register `AR1` reader"]
pub type R = crate::R<Ar1Spec>;
#[doc = "Register `AR1` writer"]
pub type W = crate::W<Ar1Spec>;
#[doc = "Field `ADDR` reader - address to be sent to the external Flash memory"]
pub type AddrR = crate::FieldReader<u32>;
#[doc = "Field `ADDR` writer - address to be sent to the external Flash memory"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<Ar1Spec> {
AddrW::new(self, 0)
}
}
#[doc = "Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ar1Spec;
impl crate::RegisterSpec for Ar1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ar1::R`](R) reader structure"]
impl crate::Readable for Ar1Spec {}
#[doc = "`write(|w| ..)` method takes [`ar1::W`](W) writer structure"]
impl crate::Writable for Ar1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AR1 to value 0"]
impl crate::Resettable for Ar1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ABR1 (rw) register accessor: Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abr1`]
module"]
#[doc(alias = "ABR1")]
pub type Abr1 = crate::Reg<abr1::Abr1Spec>;
#[doc = "Alternate Byte Register"]
pub mod abr1 {
#[doc = "Register `ABR1` reader"]
pub type R = crate::R<Abr1Spec>;
#[doc = "Register `ABR1` writer"]
pub type W = crate::W<Abr1Spec>;
#[doc = "Field `ABYTE` reader - Alternate byte"]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - Alternate byte"]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<Abr1Spec> {
AbyteW::new(self, 0)
}
}
#[doc = "Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Abr1Spec;
impl crate::RegisterSpec for Abr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`abr1::R`](R) reader structure"]
impl crate::Readable for Abr1Spec {}
#[doc = "`write(|w| ..)` method takes [`abr1::W`](W) writer structure"]
impl crate::Writable for Abr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ABR1 to value 0"]
impl crate::Resettable for Abr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DLR1 (rw) register accessor: Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlr1`]
module"]
#[doc(alias = "DLR1")]
pub type Dlr1 = crate::Reg<dlr1::Dlr1Spec>;
#[doc = "Data Length Register"]
pub mod dlr1 {
#[doc = "Register `DLR1` reader"]
pub type R = crate::R<Dlr1Spec>;
#[doc = "Register `DLR1` writer"]
pub type W = crate::W<Dlr1Spec>;
#[doc = "Field `DLEN` reader - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenR = crate::FieldReader<u32>;
#[doc = "Field `DLEN` writer - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
pub fn dlen(&self) -> DlenR {
DlenR::new(self.bits & 0x000f_ffff)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
#[must_use]
pub fn dlen(&mut self) -> DlenW<Dlr1Spec> {
DlenW::new(self, 0)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dlr1Spec> {
RsvdW::new(self, 20)
}
}
#[doc = "Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dlr1Spec;
impl crate::RegisterSpec for Dlr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dlr1::R`](R) reader structure"]
impl crate::Readable for Dlr1Spec {}
#[doc = "`write(|w| ..)` method takes [`dlr1::W`](W) writer structure"]
impl crate::Writable for Dlr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DLR1 to value 0"]
impl crate::Resettable for Dlr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR1 (rw) register accessor: Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`]
module"]
#[doc(alias = "CCR1")]
pub type Ccr1 = crate::Reg<ccr1::Ccr1Spec>;
#[doc = "Communication Configuration Register"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub type R = crate::R<Ccr1Spec>;
#[doc = "Register `CCR1` writer"]
pub type W = crate::W<Ccr1Spec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `FMODE` reader - 0 - read mode, 1 - write mode"]
pub type FmodeR = crate::BitReader;
#[doc = "Field `FMODE` writer - 0 - read mode, 1 - write mode"]
pub type FmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
pub fn fmode(&self) -> FmodeR {
FmodeR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<Ccr1Spec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<Ccr1Spec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<Ccr1Spec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<Ccr1Spec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<Ccr1Spec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<Ccr1Spec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<Ccr1Spec> {
DmodeW::new(self, 18)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
#[must_use]
pub fn fmode(&mut self) -> FmodeW<Ccr1Spec> {
FmodeW::new(self, 21)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr1Spec> {
RsvdW::new(self, 22)
}
}
#[doc = "Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr1Spec;
impl crate::RegisterSpec for Ccr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"]
impl crate::Readable for Ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"]
impl crate::Writable for Ccr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for Ccr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CMDR2 (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdr2`]
module"]
#[doc(alias = "CMDR2")]
pub type Cmdr2 = crate::Reg<cmdr2::Cmdr2Spec>;
#[doc = "Command Register"]
pub mod cmdr2 {
#[doc = "Register `CMDR2` reader"]
pub type R = crate::R<Cmdr2Spec>;
#[doc = "Register `CMDR2` writer"]
pub type W = crate::W<Cmdr2Spec>;
#[doc = "Field `CMD` reader - command"]
pub type CmdR = crate::FieldReader;
#[doc = "Field `CMD` writer - command"]
pub type CmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
pub fn cmd(&self) -> CmdR {
CmdR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - command"]
#[inline(always)]
#[must_use]
pub fn cmd(&mut self) -> CmdW<Cmdr2Spec> {
CmdW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cmdr2Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cmdr2Spec;
impl crate::RegisterSpec for Cmdr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cmdr2::R`](R) reader structure"]
impl crate::Readable for Cmdr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cmdr2::W`](W) writer structure"]
impl crate::Writable for Cmdr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMDR2 to value 0"]
impl crate::Resettable for Cmdr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AR2 (rw) register accessor: Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ar2`]
module"]
#[doc(alias = "AR2")]
pub type Ar2 = crate::Reg<ar2::Ar2Spec>;
#[doc = "Address Register"]
pub mod ar2 {
#[doc = "Register `AR2` reader"]
pub type R = crate::R<Ar2Spec>;
#[doc = "Register `AR2` writer"]
pub type W = crate::W<Ar2Spec>;
#[doc = "Field `ADDR` reader - address to be sent to the external Flash memory"]
pub type AddrR = crate::FieldReader<u32>;
#[doc = "Field `ADDR` writer - address to be sent to the external Flash memory"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - address to be sent to the external Flash memory"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<Ar2Spec> {
AddrW::new(self, 0)
}
}
#[doc = "Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ar2Spec;
impl crate::RegisterSpec for Ar2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ar2::R`](R) reader structure"]
impl crate::Readable for Ar2Spec {}
#[doc = "`write(|w| ..)` method takes [`ar2::W`](W) writer structure"]
impl crate::Writable for Ar2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AR2 to value 0"]
impl crate::Resettable for Ar2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ABR2 (rw) register accessor: Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abr2`]
module"]
#[doc(alias = "ABR2")]
pub type Abr2 = crate::Reg<abr2::Abr2Spec>;
#[doc = "Alternate Byte Register"]
pub mod abr2 {
#[doc = "Register `ABR2` reader"]
pub type R = crate::R<Abr2Spec>;
#[doc = "Register `ABR2` writer"]
pub type W = crate::W<Abr2Spec>;
#[doc = "Field `ABYTE` reader - Alternate byte"]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - Alternate byte"]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Alternate byte"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<Abr2Spec> {
AbyteW::new(self, 0)
}
}
#[doc = "Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Abr2Spec;
impl crate::RegisterSpec for Abr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`abr2::R`](R) reader structure"]
impl crate::Readable for Abr2Spec {}
#[doc = "`write(|w| ..)` method takes [`abr2::W`](W) writer structure"]
impl crate::Writable for Abr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ABR2 to value 0"]
impl crate::Resettable for Abr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DLR2 (rw) register accessor: Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlr2`]
module"]
#[doc(alias = "DLR2")]
pub type Dlr2 = crate::Reg<dlr2::Dlr2Spec>;
#[doc = "Data Length Register"]
pub mod dlr2 {
#[doc = "Register `DLR2` reader"]
pub type R = crate::R<Dlr2Spec>;
#[doc = "Register `DLR2` writer"]
pub type W = crate::W<Dlr2Spec>;
#[doc = "Field `DLEN` reader - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenR = crate::FieldReader<u32>;
#[doc = "Field `DLEN` writer - 0 - one byte to be transferred; 1 - two bytes"]
pub type DlenW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
pub fn dlen(&self) -> DlenR {
DlenR::new(self.bits & 0x000f_ffff)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:19 - 0 - one byte to be transferred; 1 - two bytes"]
#[inline(always)]
#[must_use]
pub fn dlen(&mut self) -> DlenW<Dlr2Spec> {
DlenW::new(self, 0)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dlr2Spec> {
RsvdW::new(self, 20)
}
}
#[doc = "Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dlr2Spec;
impl crate::RegisterSpec for Dlr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dlr2::R`](R) reader structure"]
impl crate::Readable for Dlr2Spec {}
#[doc = "`write(|w| ..)` method takes [`dlr2::W`](W) writer structure"]
impl crate::Writable for Dlr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DLR2 to value 0"]
impl crate::Resettable for Dlr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR2 (rw) register accessor: Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`]
module"]
#[doc(alias = "CCR2")]
pub type Ccr2 = crate::Reg<ccr2::Ccr2Spec>;
#[doc = "Communication Configuration Register"]
pub mod ccr2 {
#[doc = "Register `CCR2` reader"]
pub type R = crate::R<Ccr2Spec>;
#[doc = "Register `CCR2` writer"]
pub type W = crate::W<Ccr2Spec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `FMODE` reader - 0 - read mode, 1 - write mode"]
pub type FmodeR = crate::BitReader;
#[doc = "Field `FMODE` writer - 0 - read mode, 1 - write mode"]
pub type FmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
pub fn fmode(&self) -> FmodeR {
FmodeR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bits 22:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 22) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<Ccr2Spec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<Ccr2Spec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<Ccr2Spec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<Ccr2Spec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<Ccr2Spec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<Ccr2Spec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<Ccr2Spec> {
DmodeW::new(self, 18)
}
#[doc = "Bit 21 - 0 - read mode, 1 - write mode"]
#[inline(always)]
#[must_use]
pub fn fmode(&mut self) -> FmodeW<Ccr2Spec> {
FmodeW::new(self, 21)
}
#[doc = "Bits 22:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr2Spec> {
RsvdW::new(self, 22)
}
}
#[doc = "Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr2Spec;
impl crate::RegisterSpec for Ccr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"]
impl crate::Readable for Ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"]
impl crate::Writable for Ccr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR2 to value 0"]
impl crate::Resettable for Ccr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HCMDR (rw) register accessor: AHB Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcmdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcmdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcmdr`]
module"]
#[doc(alias = "HCMDR")]
pub type Hcmdr = crate::Reg<hcmdr::HcmdrSpec>;
#[doc = "AHB Command Register"]
pub mod hcmdr {
#[doc = "Register `HCMDR` reader"]
pub type R = crate::R<HcmdrSpec>;
#[doc = "Register `HCMDR` writer"]
pub type W = crate::W<HcmdrSpec>;
#[doc = "Field `RCMD` reader - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
pub type RcmdR = crate::FieldReader;
#[doc = "Field `RCMD` writer - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
pub type RcmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `WCMD` reader - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
pub type WcmdR = crate::FieldReader;
#[doc = "Field `WCMD` writer - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
pub type WcmdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:7 - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
#[inline(always)]
pub fn rcmd(&self) -> RcmdR {
RcmdR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
#[inline(always)]
pub fn wcmd(&self) -> WcmdR {
WcmdR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:7 - During XIP, the AHB read transaction will be translated into this Read Command on SPI interface"]
#[inline(always)]
#[must_use]
pub fn rcmd(&mut self) -> RcmdW<HcmdrSpec> {
RcmdW::new(self, 0)
}
#[doc = "Bits 8:15 - During XIP, the AHB write transaction will be translated into this Write Command on SPI interface"]
#[inline(always)]
#[must_use]
pub fn wcmd(&mut self) -> WcmdW<HcmdrSpec> {
WcmdW::new(self, 8)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<HcmdrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "AHB Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcmdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcmdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HcmdrSpec;
impl crate::RegisterSpec for HcmdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hcmdr::R`](R) reader structure"]
impl crate::Readable for HcmdrSpec {}
#[doc = "`write(|w| ..)` method takes [`hcmdr::W`](W) writer structure"]
impl crate::Writable for HcmdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HCMDR to value 0"]
impl crate::Resettable for HcmdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HRABR (rw) register accessor: AHB Read Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrabr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrabr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hrabr`]
module"]
#[doc(alias = "HRABR")]
pub type Hrabr = crate::Reg<hrabr::HrabrSpec>;
#[doc = "AHB Read Alternate Byte Register"]
pub mod hrabr {
#[doc = "Register `HRABR` reader"]
pub type R = crate::R<HrabrSpec>;
#[doc = "Register `HRABR` writer"]
pub type W = crate::W<HrabrSpec>;
#[doc = "Field `ABYTE` reader - "]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - "]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<HrabrSpec> {
AbyteW::new(self, 0)
}
}
#[doc = "AHB Read Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrabr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrabr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HrabrSpec;
impl crate::RegisterSpec for HrabrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hrabr::R`](R) reader structure"]
impl crate::Readable for HrabrSpec {}
#[doc = "`write(|w| ..)` method takes [`hrabr::W`](W) writer structure"]
impl crate::Writable for HrabrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HRABR to value 0"]
impl crate::Resettable for HrabrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HRCCR (rw) register accessor: AHB Read Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hrccr`]
module"]
#[doc(alias = "HRCCR")]
pub type Hrccr = crate::Reg<hrccr::HrccrSpec>;
#[doc = "AHB Read Communication Configuration Register"]
pub mod hrccr {
#[doc = "Register `HRCCR` reader"]
pub type R = crate::R<HrccrSpec>;
#[doc = "Register `HRCCR` writer"]
pub type W = crate::W<HrccrSpec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 21) & 0x07ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<HrccrSpec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<HrccrSpec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<HrccrSpec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<HrccrSpec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<HrccrSpec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<HrccrSpec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<HrccrSpec> {
DmodeW::new(self, 18)
}
#[doc = "Bits 21:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<HrccrSpec> {
RsvdW::new(self, 21)
}
}
#[doc = "AHB Read Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HrccrSpec;
impl crate::RegisterSpec for HrccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hrccr::R`](R) reader structure"]
impl crate::Readable for HrccrSpec {}
#[doc = "`write(|w| ..)` method takes [`hrccr::W`](W) writer structure"]
impl crate::Writable for HrccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HRCCR to value 0"]
impl crate::Resettable for HrccrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HWABR (rw) register accessor: AHB Write Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwabr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwabr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwabr`]
module"]
#[doc(alias = "HWABR")]
pub type Hwabr = crate::Reg<hwabr::HwabrSpec>;
#[doc = "AHB Write Alternate Byte Register"]
pub mod hwabr {
#[doc = "Register `HWABR` reader"]
pub type R = crate::R<HwabrSpec>;
#[doc = "Register `HWABR` writer"]
pub type W = crate::W<HwabrSpec>;
#[doc = "Field `ABYTE` reader - "]
pub type AbyteR = crate::FieldReader<u32>;
#[doc = "Field `ABYTE` writer - "]
pub type AbyteW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn abyte(&self) -> AbyteR {
AbyteR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn abyte(&mut self) -> AbyteW<HwabrSpec> {
AbyteW::new(self, 0)
}
}
#[doc = "AHB Write Alternate Byte Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwabr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwabr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwabrSpec;
impl crate::RegisterSpec for HwabrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hwabr::R`](R) reader structure"]
impl crate::Readable for HwabrSpec {}
#[doc = "`write(|w| ..)` method takes [`hwabr::W`](W) writer structure"]
impl crate::Writable for HwabrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HWABR to value 0"]
impl crate::Resettable for HwabrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HWCCR (rw) register accessor: AHB Write Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwccr`]
module"]
#[doc(alias = "HWCCR")]
pub type Hwccr = crate::Reg<hwccr::HwccrSpec>;
#[doc = "AHB Write Communication Configuration Register"]
pub mod hwccr {
#[doc = "Register `HWCCR` reader"]
pub type R = crate::R<HwccrSpec>;
#[doc = "Register `HWCCR` writer"]
pub type W = crate::W<HwccrSpec>;
#[doc = "Field `IMODE` reader - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeR = crate::FieldReader;
#[doc = "Field `IMODE` writer - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
pub type ImodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADMODE` reader - Address mode"]
pub type AdmodeR = crate::FieldReader;
#[doc = "Field `ADMODE` writer - Address mode"]
pub type AdmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ADSIZE` reader - "]
pub type AdsizeR = crate::FieldReader;
#[doc = "Field `ADSIZE` writer - "]
pub type AdsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ABMODE` reader - "]
pub type AbmodeR = crate::FieldReader;
#[doc = "Field `ABMODE` writer - "]
pub type AbmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ABSIZE` reader - "]
pub type AbsizeR = crate::FieldReader;
#[doc = "Field `ABSIZE` writer - "]
pub type AbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DCYC` reader - "]
pub type DcycR = crate::FieldReader;
#[doc = "Field `DCYC` writer - "]
pub type DcycW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMODE` reader - "]
pub type DmodeR = crate::FieldReader;
#[doc = "Field `DMODE` writer - "]
pub type DmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
pub fn imode(&self) -> ImodeR {
ImodeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn adsize(&self) -> AdsizeR {
AdsizeR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn abmode(&self) -> AbmodeR {
AbmodeR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
pub fn absize(&self) -> AbsizeR {
AbsizeR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn dcyc(&self) -> DcycR {
DcycR::new(((self.bits >> 13) & 0x1f) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn dmode(&self) -> DmodeR {
DmodeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 21) & 0x07ff) as u16)
}
}
impl W {
#[doc = "Bits 0:2 - Instruction mode. 0 - No instruction; 1 - single line; 2 - two lines; 3 - four lines; 4/5/6 - reserved; 7 - four lines DDR"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> ImodeW<HwccrSpec> {
ImodeW::new(self, 0)
}
#[doc = "Bits 3:5 - Address mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<HwccrSpec> {
AdmodeW::new(self, 3)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> AdsizeW<HwccrSpec> {
AdsizeW::new(self, 6)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> AbmodeW<HwccrSpec> {
AbmodeW::new(self, 8)
}
#[doc = "Bits 11:12"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> AbsizeW<HwccrSpec> {
AbsizeW::new(self, 11)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn dcyc(&mut self) -> DcycW<HwccrSpec> {
DcycW::new(self, 13)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DmodeW<HwccrSpec> {
DmodeW::new(self, 18)
}
#[doc = "Bits 21:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<HwccrSpec> {
RsvdW::new(self, 21)
}
}
#[doc = "AHB Write Communication Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HwccrSpec;
impl crate::RegisterSpec for HwccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hwccr::R`](R) reader structure"]
impl crate::Readable for HwccrSpec {}
#[doc = "`write(|w| ..)` method takes [`hwccr::W`](W) writer structure"]
impl crate::Writable for HwccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HWCCR to value 0"]
impl crate::Resettable for HwccrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFOCR (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifocr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifocr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifocr`]
module"]
#[doc(alias = "FIFOCR")]
pub type Fifocr = crate::Reg<fifocr::FifocrSpec>;
#[doc = "FIFO Control Register"]
pub mod fifocr {
#[doc = "Register `FIFOCR` reader"]
pub type R = crate::R<FifocrSpec>;
#[doc = "Register `FIFOCR` writer"]
pub type W = crate::W<FifocrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifocrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifocr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifocr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifocrSpec;
impl crate::RegisterSpec for FifocrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifocr::R`](R) reader structure"]
impl crate::Readable for FifocrSpec {}
#[doc = "`write(|w| ..)` method takes [`fifocr::W`](W) writer structure"]
impl crate::Writable for FifocrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFOCR to value 0"]
impl crate::Resettable for FifocrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "MISCR (rw) register accessor: Miscelaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscr`]
module"]
#[doc(alias = "MISCR")]
pub type Miscr = crate::Reg<miscr::MiscrSpec>;
#[doc = "Miscelaneous Register"]
pub mod miscr {
#[doc = "Register `MISCR` reader"]
pub type R = crate::R<MiscrSpec>;
#[doc = "Register `MISCR` writer"]
pub type W = crate::W<MiscrSpec>;
#[doc = "Field `RXCLKDLY` reader - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
pub type RxclkdlyR = crate::FieldReader;
#[doc = "Field `RXCLKDLY` writer - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
pub type RxclkdlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SCKDLY` reader - Add delay on SCK (fine tune). Effective 7-bit"]
pub type SckdlyR = crate::FieldReader;
#[doc = "Field `SCKDLY` writer - Add delay on SCK (fine tune). Effective 7-bit"]
pub type SckdlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `DQSDLY` reader - select delayed version of DQS. Effective 7-bit"]
pub type DqsdlyR = crate::FieldReader;
#[doc = "Field `DQSDLY` writer - select delayed version of DQS. Effective 7-bit"]
pub type DqsdlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RXCLKINV` reader - Invert FCLK as Rx sampling clock (coarse tune)"]
pub type RxclkinvR = crate::BitReader;
#[doc = "Field `RXCLKINV` writer - Invert FCLK as Rx sampling clock (coarse tune)"]
pub type RxclkinvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCKINV` reader - Invert FCLK as SCK (coarse tune)"]
pub type SckinvR = crate::BitReader;
#[doc = "Field `SCKINV` writer - Invert FCLK as SCK (coarse tune)"]
pub type SckinvW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DTRPRE` reader - Enable pre-sampling for DTR (for slow frequency)"]
pub type DtrpreR = crate::BitReader;
#[doc = "Field `DTRPRE` writer - Enable pre-sampling for DTR (for slow frequency)"]
pub type DtrpreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
#[doc = "Bits 0:7 - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
#[inline(always)]
pub fn rxclkdly(&self) -> RxclkdlyR {
RxclkdlyR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Add delay on SCK (fine tune). Effective 7-bit"]
#[inline(always)]
pub fn sckdly(&self) -> SckdlyR {
SckdlyR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - select delayed version of DQS. Effective 7-bit"]
#[inline(always)]
pub fn dqsdly(&self) -> DqsdlyR {
DqsdlyR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bit 24 - Invert FCLK as Rx sampling clock (coarse tune)"]
#[inline(always)]
pub fn rxclkinv(&self) -> RxclkinvR {
RxclkinvR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Invert FCLK as SCK (coarse tune)"]
#[inline(always)]
pub fn sckinv(&self) -> SckinvR {
SckinvR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Enable pre-sampling for DTR (for slow frequency)"]
#[inline(always)]
pub fn dtrpre(&self) -> DtrpreR {
DtrpreR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bits 27:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 27) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Add delay on Rx sampling clock (fine tune). Effective 5-bit"]
#[inline(always)]
#[must_use]
pub fn rxclkdly(&mut self) -> RxclkdlyW<MiscrSpec> {
RxclkdlyW::new(self, 0)
}
#[doc = "Bits 8:15 - Add delay on SCK (fine tune). Effective 7-bit"]
#[inline(always)]
#[must_use]
pub fn sckdly(&mut self) -> SckdlyW<MiscrSpec> {
SckdlyW::new(self, 8)
}
#[doc = "Bits 16:23 - select delayed version of DQS. Effective 7-bit"]
#[inline(always)]
#[must_use]
pub fn dqsdly(&mut self) -> DqsdlyW<MiscrSpec> {
DqsdlyW::new(self, 16)
}
#[doc = "Bit 24 - Invert FCLK as Rx sampling clock (coarse tune)"]
#[inline(always)]
#[must_use]
pub fn rxclkinv(&mut self) -> RxclkinvW<MiscrSpec> {
RxclkinvW::new(self, 24)
}
#[doc = "Bit 25 - Invert FCLK as SCK (coarse tune)"]
#[inline(always)]
#[must_use]
pub fn sckinv(&mut self) -> SckinvW<MiscrSpec> {
SckinvW::new(self, 25)
}
#[doc = "Bit 26 - Enable pre-sampling for DTR (for slow frequency)"]
#[inline(always)]
#[must_use]
pub fn dtrpre(&mut self) -> DtrpreW<MiscrSpec> {
DtrpreW::new(self, 26)
}
#[doc = "Bits 27:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<MiscrSpec> {
RsvdW::new(self, 27)
}
}
#[doc = "Miscelaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscrSpec;
impl crate::RegisterSpec for MiscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miscr::R`](R) reader structure"]
impl crate::Readable for MiscrSpec {}
#[doc = "`write(|w| ..)` method takes [`miscr::W`](W) writer structure"]
impl crate::Writable for MiscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISCR to value 0"]
impl crate::Resettable for MiscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CTRSAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrsar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrsar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrsar`]
module"]
#[doc(alias = "CTRSAR")]
pub type Ctrsar = crate::Reg<ctrsar::CtrsarSpec>;
#[doc = ""]
pub mod ctrsar {
#[doc = "Register `CTRSAR` reader"]
pub type R = crate::R<CtrsarSpec>;
#[doc = "Register `CTRSAR` writer"]
pub type W = crate::W<CtrsarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CtrsarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrsar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrsar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrsarSpec;
impl crate::RegisterSpec for CtrsarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrsar::R`](R) reader structure"]
impl crate::Readable for CtrsarSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrsar::W`](W) writer structure"]
impl crate::Writable for CtrsarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTRSAR to value 0"]
impl crate::Resettable for CtrsarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CTREAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrear`]
module"]
#[doc(alias = "CTREAR")]
pub type Ctrear = crate::Reg<ctrear::CtrearSpec>;
#[doc = ""]
pub mod ctrear {
#[doc = "Register `CTREAR` reader"]
pub type R = crate::R<CtrearSpec>;
#[doc = "Register `CTREAR` writer"]
pub type W = crate::W<CtrearSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CtrearSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrearSpec;
impl crate::RegisterSpec for CtrearSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrear::R`](R) reader structure"]
impl crate::Readable for CtrearSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrear::W`](W) writer structure"]
impl crate::Writable for CtrearSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTREAR to value 0"]
impl crate::Resettable for CtrearSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "NONCEA (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`noncea::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`noncea::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@noncea`]
module"]
#[doc(alias = "NONCEA")]
pub type Noncea = crate::Reg<noncea::NonceaSpec>;
#[doc = ""]
pub mod noncea {
#[doc = "Register `NONCEA` reader"]
pub type R = crate::R<NonceaSpec>;
#[doc = "Register `NONCEA` writer"]
pub type W = crate::W<NonceaSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<NonceaSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`noncea::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`noncea::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NonceaSpec;
impl crate::RegisterSpec for NonceaSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`noncea::R`](R) reader structure"]
impl crate::Readable for NonceaSpec {}
#[doc = "`write(|w| ..)` method takes [`noncea::W`](W) writer structure"]
impl crate::Writable for NonceaSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets NONCEA to value 0"]
impl crate::Resettable for NonceaSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "NONCEB (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nonceb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nonceb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nonceb`]
module"]
#[doc(alias = "NONCEB")]
pub type Nonceb = crate::Reg<nonceb::NoncebSpec>;
#[doc = ""]
pub mod nonceb {
#[doc = "Register `NONCEB` reader"]
pub type R = crate::R<NoncebSpec>;
#[doc = "Register `NONCEB` writer"]
pub type W = crate::W<NoncebSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<NoncebSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nonceb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nonceb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NoncebSpec;
impl crate::RegisterSpec for NoncebSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`nonceb::R`](R) reader structure"]
impl crate::Readable for NoncebSpec {}
#[doc = "`write(|w| ..)` method takes [`nonceb::W`](W) writer structure"]
impl crate::Writable for NoncebSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets NONCEB to value 0"]
impl crate::Resettable for NoncebSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AASAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aasar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aasar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aasar`]
module"]
#[doc(alias = "AASAR")]
pub type Aasar = crate::Reg<aasar::AasarSpec>;
#[doc = ""]
pub mod aasar {
#[doc = "Register `AASAR` reader"]
pub type R = crate::R<AasarSpec>;
#[doc = "Register `AASAR` writer"]
pub type W = crate::W<AasarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AasarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aasar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aasar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AasarSpec;
impl crate::RegisterSpec for AasarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`aasar::R`](R) reader structure"]
impl crate::Readable for AasarSpec {}
#[doc = "`write(|w| ..)` method takes [`aasar::W`](W) writer structure"]
impl crate::Writable for AasarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AASAR to value 0"]
impl crate::Resettable for AasarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AAEAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aaear`]
module"]
#[doc(alias = "AAEAR")]
pub type Aaear = crate::Reg<aaear::AaearSpec>;
#[doc = ""]
pub mod aaear {
#[doc = "Register `AAEAR` reader"]
pub type R = crate::R<AaearSpec>;
#[doc = "Register `AAEAR` writer"]
pub type W = crate::W<AaearSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AaearSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AaearSpec;
impl crate::RegisterSpec for AaearSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`aaear::R`](R) reader structure"]
impl crate::Readable for AaearSpec {}
#[doc = "`write(|w| ..)` method takes [`aaear::W`](W) writer structure"]
impl crate::Writable for AaearSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AAEAR to value 0"]
impl crate::Resettable for AaearSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AAOAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaoar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaoar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aaoar`]
module"]
#[doc(alias = "AAOAR")]
pub type Aaoar = crate::Reg<aaoar::AaoarSpec>;
#[doc = ""]
pub mod aaoar {
#[doc = "Register `AAOAR` reader"]
pub type R = crate::R<AaoarSpec>;
#[doc = "Register `AAOAR` writer"]
pub type W = crate::W<AaoarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AaoarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aaoar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aaoar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AaoarSpec;
impl crate::RegisterSpec for AaoarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`aaoar::R`](R) reader structure"]
impl crate::Readable for AaoarSpec {}
#[doc = "`write(|w| ..)` method takes [`aaoar::W`](W) writer structure"]
impl crate::Writable for AaoarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AAOAR to value 0"]
impl crate::Resettable for AaoarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CIR (rw) register accessor: Command Interval Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cir`]
module"]
#[doc(alias = "CIR")]
pub type Cir = crate::Reg<cir::CirSpec>;
#[doc = "Command Interval Register"]
pub mod cir {
#[doc = "Register `CIR` reader"]
pub type R = crate::R<CirSpec>;
#[doc = "Register `CIR` writer"]
pub type W = crate::W<CirSpec>;
#[doc = "Field `INTERVAL1` reader - "]
pub type Interval1R = crate::FieldReader<u16>;
#[doc = "Field `INTERVAL1` writer - "]
pub type Interval1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `INTERVAL2` reader - "]
pub type Interval2R = crate::FieldReader<u16>;
#[doc = "Field `INTERVAL2` writer - "]
pub type Interval2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn interval1(&self) -> Interval1R {
Interval1R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn interval2(&self) -> Interval2R {
Interval2R::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn interval1(&mut self) -> Interval1W<CirSpec> {
Interval1W::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn interval2(&mut self) -> Interval2W<CirSpec> {
Interval2W::new(self, 16)
}
}
#[doc = "Command Interval Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CirSpec;
impl crate::RegisterSpec for CirSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cir::R`](R) reader structure"]
impl crate::Readable for CirSpec {}
#[doc = "`write(|w| ..)` method takes [`cir::W`](W) writer structure"]
impl crate::Writable for CirSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CIR to value 0"]
impl crate::Resettable for CirSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMR (rw) register accessor: Status Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smr`]
module"]
#[doc(alias = "SMR")]
pub type Smr = crate::Reg<smr::SmrSpec>;
#[doc = "Status Match Register"]
pub mod smr {
#[doc = "Register `SMR` reader"]
pub type R = crate::R<SmrSpec>;
#[doc = "Register `SMR` writer"]
pub type W = crate::W<SmrSpec>;
#[doc = "Field `STATUS` reader - "]
pub type StatusR = crate::FieldReader<u32>;
#[doc = "Field `STATUS` writer - "]
pub type StatusW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn status(&self) -> StatusR {
StatusR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn status(&mut self) -> StatusW<SmrSpec> {
StatusW::new(self, 0)
}
}
#[doc = "Status Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmrSpec;
impl crate::RegisterSpec for SmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smr::R`](R) reader structure"]
impl crate::Readable for SmrSpec {}
#[doc = "`write(|w| ..)` method takes [`smr::W`](W) writer structure"]
impl crate::Writable for SmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMR to value 0"]
impl crate::Resettable for SmrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMKR (rw) register accessor: Status Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smkr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smkr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smkr`]
module"]
#[doc(alias = "SMKR")]
pub type Smkr = crate::Reg<smkr::SmkrSpec>;
#[doc = "Status Mask Register"]
pub mod smkr {
#[doc = "Register `SMKR` reader"]
pub type R = crate::R<SmkrSpec>;
#[doc = "Register `SMKR` writer"]
pub type W = crate::W<SmkrSpec>;
#[doc = "Field `MASK` reader - 0 - not considered; 1 - considered"]
pub type MaskR = crate::FieldReader<u32>;
#[doc = "Field `MASK` writer - 0 - not considered; 1 - considered"]
pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - 0 - not considered; 1 - considered"]
#[inline(always)]
pub fn mask(&self) -> MaskR {
MaskR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - 0 - not considered; 1 - considered"]
#[inline(always)]
#[must_use]
pub fn mask(&mut self) -> MaskW<SmkrSpec> {
MaskW::new(self, 0)
}
}
#[doc = "Status Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smkr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smkr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmkrSpec;
impl crate::RegisterSpec for SmkrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smkr::R`](R) reader structure"]
impl crate::Readable for SmkrSpec {}
#[doc = "`write(|w| ..)` method takes [`smkr::W`](W) writer structure"]
impl crate::Writable for SmkrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMKR to value 0"]
impl crate::Resettable for SmkrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TIMR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timr`]
module"]
#[doc(alias = "TIMR")]
pub type Timr = crate::Reg<timr::TimrSpec>;
#[doc = ""]
pub mod timr {
#[doc = "Register `TIMR` reader"]
pub type R = crate::R<TimrSpec>;
#[doc = "Register `TIMR` writer"]
pub type W = crate::W<TimrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TimrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimrSpec;
impl crate::RegisterSpec for TimrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timr::R`](R) reader structure"]
impl crate::Readable for TimrSpec {}
#[doc = "`write(|w| ..)` method takes [`timr::W`](W) writer structure"]
impl crate::Writable for TimrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TIMR to value 0"]
impl crate::Resettable for TimrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDTR (rw) register accessor: WDT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtr`]
module"]
#[doc(alias = "WDTR")]
pub type Wdtr = crate::Reg<wdtr::WdtrSpec>;
#[doc = "WDT Register"]
pub mod wdtr {
#[doc = "Register `WDTR` reader"]
pub type R = crate::R<WdtrSpec>;
#[doc = "Register `WDTR` writer"]
pub type W = crate::W<WdtrSpec>;
#[doc = "Field `TIMEOUT` reader - Set AHB timeout value in number of clk_wdt cycles"]
pub type TimeoutR = crate::FieldReader<u16>;
#[doc = "Field `TIMEOUT` writer - Set AHB timeout value in number of clk_wdt cycles"]
pub type TimeoutW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `EN` reader - WDT enable"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - WDT enable"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `TOF` reader - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
pub type TofR = crate::BitReader;
#[doc = "Field `TOF` writer - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
pub type TofW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:15 - Set AHB timeout value in number of clk_wdt cycles"]
#[inline(always)]
pub fn timeout(&self) -> TimeoutR {
TimeoutR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 16 - WDT enable"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 17) & 0x3fff) as u16)
}
#[doc = "Bit 31 - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
#[inline(always)]
pub fn tof(&self) -> TofR {
TofR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15 - Set AHB timeout value in number of clk_wdt cycles"]
#[inline(always)]
#[must_use]
pub fn timeout(&mut self) -> TimeoutW<WdtrSpec> {
TimeoutW::new(self, 0)
}
#[doc = "Bit 16 - WDT enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<WdtrSpec> {
EnW::new(self, 16)
}
#[doc = "Bits 17:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtrSpec> {
RsvdW::new(self, 17)
}
#[doc = "Bit 31 - Timeout flag. Self cleared when the HREADYOUT being monitored becomes ready"]
#[inline(always)]
#[must_use]
pub fn tof(&mut self) -> TofW<WdtrSpec> {
TofW::new(self, 31)
}
}
#[doc = "WDT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtrSpec;
impl crate::RegisterSpec for WdtrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdtr::R`](R) reader structure"]
impl crate::Readable for WdtrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdtr::W`](W) writer structure"]
impl crate::Writable for WdtrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDTR to value 0"]
impl crate::Resettable for WdtrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PRSAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prsar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prsar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prsar`]
module"]
#[doc(alias = "PRSAR")]
pub type Prsar = crate::Reg<prsar::PrsarSpec>;
#[doc = ""]
pub mod prsar {
#[doc = "Register `PRSAR` reader"]
pub type R = crate::R<PrsarSpec>;
#[doc = "Register `PRSAR` writer"]
pub type W = crate::W<PrsarSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PrsarSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prsar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prsar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrsarSpec;
impl crate::RegisterSpec for PrsarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`prsar::R`](R) reader structure"]
impl crate::Readable for PrsarSpec {}
#[doc = "`write(|w| ..)` method takes [`prsar::W`](W) writer structure"]
impl crate::Writable for PrsarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PRSAR to value 0"]
impl crate::Resettable for PrsarSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PREAR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prear`]
module"]
#[doc(alias = "PREAR")]
pub type Prear = crate::Reg<prear::PrearSpec>;
#[doc = ""]
pub mod prear {
#[doc = "Register `PREAR` reader"]
pub type R = crate::R<PrearSpec>;
#[doc = "Register `PREAR` writer"]
pub type W = crate::W<PrearSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PrearSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrearSpec;
impl crate::RegisterSpec for PrearSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`prear::R`](R) reader structure"]
impl crate::Readable for PrearSpec {}
#[doc = "`write(|w| ..)` method takes [`prear::W`](W) writer structure"]
impl crate::Writable for PrearSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PREAR to value 0"]
impl crate::Resettable for PrearSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CALCR (rw) register accessor: Calibration Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@calcr`]
module"]
#[doc(alias = "CALCR")]
pub type Calcr = crate::Reg<calcr::CalcrSpec>;
#[doc = "Calibration Control Register"]
pub mod calcr {
#[doc = "Register `CALCR` reader"]
pub type R = crate::R<CalcrSpec>;
#[doc = "Register `CALCR` writer"]
pub type W = crate::W<CalcrSpec>;
#[doc = "Field `DELAY` reader - calibration delay result"]
pub type DelayR = crate::FieldReader;
#[doc = "Field `DELAY` writer - calibration delay result"]
pub type DelayW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `DONE` reader - calibration done"]
pub type DoneR = crate::BitReader;
#[doc = "Field `DONE` writer - calibration done"]
pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
#[doc = "Field `EN` reader - calibration enable"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - calibration enable"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:7 - calibration delay result"]
#[inline(always)]
pub fn delay(&self) -> DelayR {
DelayR::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - calibration done"]
#[inline(always)]
pub fn done(&self) -> DoneR {
DoneR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x003f_ffff)
}
#[doc = "Bit 31 - calibration enable"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7 - calibration delay result"]
#[inline(always)]
#[must_use]
pub fn delay(&mut self) -> DelayW<CalcrSpec> {
DelayW::new(self, 0)
}
#[doc = "Bit 8 - calibration done"]
#[inline(always)]
#[must_use]
pub fn done(&mut self) -> DoneW<CalcrSpec> {
DoneW::new(self, 8)
}
#[doc = "Bits 9:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CalcrSpec> {
RsvdW::new(self, 9)
}
#[doc = "Bit 31 - calibration enable"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<CalcrSpec> {
EnW::new(self, 31)
}
}
#[doc = "Calibration Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CalcrSpec;
impl crate::RegisterSpec for CalcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`calcr::R`](R) reader structure"]
impl crate::Readable for CalcrSpec {}
#[doc = "`write(|w| ..)` method takes [`calcr::W`](W) writer structure"]
impl crate::Writable for CalcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CALCR to value 0"]
impl crate::Resettable for CalcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CALDOR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`caldor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`caldor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@caldor`]
module"]
#[doc(alias = "CALDOR")]
pub type Caldor = crate::Reg<caldor::CaldorSpec>;
#[doc = ""]
pub mod caldor {
#[doc = "Register `CALDOR` reader"]
pub type R = crate::R<CaldorSpec>;
#[doc = "Register `CALDOR` writer"]
pub type W = crate::W<CaldorSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CaldorSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`caldor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`caldor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CaldorSpec;
impl crate::RegisterSpec for CaldorSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`caldor::R`](R) reader structure"]
impl crate::Readable for CaldorSpec {}
#[doc = "`write(|w| ..)` method takes [`caldor::W`](W) writer structure"]
impl crate::Writable for CaldorSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CALDOR to value 0"]
impl crate::Resettable for CaldorSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "APM32CR (rw) register accessor: APM32 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apm32cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apm32cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apm32cr`]
module"]
#[doc(alias = "APM32CR")]
pub type Apm32cr = crate::Reg<apm32cr::Apm32crSpec>;
#[doc = "APM32 Control Register"]
pub mod apm32cr {
#[doc = "Register `APM32CR` reader"]
pub type R = crate::R<Apm32crSpec>;
#[doc = "Register `APM32CR` writer"]
pub type W = crate::W<Apm32crSpec>;
#[doc = "Field `TCPHR` reader - "]
pub type TcphrR = crate::FieldReader;
#[doc = "Field `TCPHR` writer - "]
pub type TcphrW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TCPHW` reader - "]
pub type TcphwR = crate::FieldReader;
#[doc = "Field `TCPHW` writer - "]
pub type TcphwW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn tcphr(&self) -> TcphrR {
TcphrR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn tcphw(&self) -> TcphwR {
TcphwR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn tcphr(&mut self) -> TcphrW<Apm32crSpec> {
TcphrW::new(self, 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn tcphw(&mut self) -> TcphwW<Apm32crSpec> {
TcphwW::new(self, 4)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Apm32crSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "APM32 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apm32cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apm32cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Apm32crSpec;
impl crate::RegisterSpec for Apm32crSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`apm32cr::R`](R) reader structure"]
impl crate::Readable for Apm32crSpec {}
#[doc = "`write(|w| ..)` method takes [`apm32cr::W`](W) writer structure"]
impl crate::Writable for Apm32crSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets APM32CR to value 0"]
impl crate::Resettable for Apm32crSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = ""]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "CRC1"]
pub struct Crc1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Crc1 {}
impl Crc1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const crc1::RegisterBlock = 0x5004_8000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const crc1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Crc1 {
type Target = crc1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Crc1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crc1").finish()
}
}
#[doc = "CRC1"]
pub mod crc1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
dr: Dr,
sr: Sr,
cr: Cr,
rsvd1: Rsvd1,
init: Init,
pol: Pol,
}
impl RegisterBlock {
#[doc = "0x00 - Data register"]
#[inline(always)]
pub const fn dr(&self) -> &Dr {
&self.dr
}
#[doc = "0x04 - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x08 - Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x0c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x10 - Initial CRC value"]
#[inline(always)]
pub const fn init(&self) -> &Init {
&self.init
}
#[doc = "0x14 - CRC polynomial"]
#[inline(always)]
pub const fn pol(&self) -> &Pol {
&self.pol
}
}
#[doc = "DR (rw) register accessor: Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`]
module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "Data register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `DR` reader - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
pub type DrR = crate::FieldReader<u32>;
#[doc = "Field `DR` writer - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
pub type DrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
#[inline(always)]
pub fn dr(&self) -> DrR {
DrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
#[inline(always)]
#[must_use]
pub fn dr(&mut self) -> DrW<DrSpec> {
DrW::new(self, 0)
}
}
#[doc = "Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `DONE` reader - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
pub type DoneR = crate::BitReader;
#[doc = "Field `DONE` writer - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVERFLOW` reader - Overflow when new data arrive while last calculation not done yet"]
pub type OverflowR = crate::BitReader;
#[doc = "Field `OVERFLOW` writer - Overflow when new data arrive while last calculation not done yet"]
pub type OverflowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
#[inline(always)]
pub fn done(&self) -> DoneR {
DoneR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow when new data arrive while last calculation not done yet"]
#[inline(always)]
pub fn overflow(&self) -> OverflowR {
OverflowR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
#[inline(always)]
#[must_use]
pub fn done(&mut self) -> DoneW<SrSpec> {
DoneW::new(self, 0)
}
#[doc = "Bit 1 - Overflow when new data arrive while last calculation not done yet"]
#[inline(always)]
#[must_use]
pub fn overflow(&mut self) -> OverflowW<SrSpec> {
OverflowW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `RESET` reader - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
pub type ResetR = crate::BitReader;
#[doc = "Field `RESET` writer - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATASIZE` reader - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
pub type DatasizeR = crate::FieldReader;
#[doc = "Field `DATASIZE` writer - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
pub type DatasizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `POLYSIZE` reader - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
pub type PolysizeR = crate::FieldReader;
#[doc = "Field `POLYSIZE` writer - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
pub type PolysizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `REV_IN` reader - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
pub type RevInR = crate::FieldReader;
#[doc = "Field `REV_IN` writer - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
pub type RevInW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `REV_OUT` reader - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
pub type RevOutR = crate::BitReader;
#[doc = "Field `REV_OUT` writer - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
pub type RevOutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
#[inline(always)]
pub fn reset(&self) -> ResetR {
ResetR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
#[inline(always)]
pub fn datasize(&self) -> DatasizeR {
DatasizeR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:4 - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
#[inline(always)]
pub fn polysize(&self) -> PolysizeR {
PolysizeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bits 5:6 - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
#[inline(always)]
pub fn rev_in(&self) -> RevInR {
RevInR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
#[inline(always)]
pub fn rev_out(&self) -> RevOutR {
RevOutR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
#[inline(always)]
#[must_use]
pub fn reset(&mut self) -> ResetW<CrSpec> {
ResetW::new(self, 0)
}
#[doc = "Bits 1:2 - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
#[inline(always)]
#[must_use]
pub fn datasize(&mut self) -> DatasizeW<CrSpec> {
DatasizeW::new(self, 1)
}
#[doc = "Bits 3:4 - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
#[inline(always)]
#[must_use]
pub fn polysize(&mut self) -> PolysizeW<CrSpec> {
PolysizeW::new(self, 3)
}
#[doc = "Bits 5:6 - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
#[inline(always)]
#[must_use]
pub fn rev_in(&mut self) -> RevInW<CrSpec> {
RevInW::new(self, 5)
}
#[doc = "Bit 7 - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
#[inline(always)]
#[must_use]
pub fn rev_out(&mut self) -> RevOutW<CrSpec> {
RevOutW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INIT (rw) register accessor: Initial CRC value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`init::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`init::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@init`]
module"]
#[doc(alias = "INIT")]
pub type Init = crate::Reg<init::InitSpec>;
#[doc = "Initial CRC value"]
pub mod init {
#[doc = "Register `INIT` reader"]
pub type R = crate::R<InitSpec>;
#[doc = "Register `INIT` writer"]
pub type W = crate::W<InitSpec>;
#[doc = "Field `INIT` reader - Programmable initial CRC value"]
pub type InitR = crate::FieldReader<u32>;
#[doc = "Field `INIT` writer - Programmable initial CRC value"]
pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Programmable initial CRC value"]
#[inline(always)]
pub fn init(&self) -> InitR {
InitR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Programmable initial CRC value"]
#[inline(always)]
#[must_use]
pub fn init(&mut self) -> InitW<InitSpec> {
InitW::new(self, 0)
}
}
#[doc = "Initial CRC value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`init::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`init::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct InitSpec;
impl crate::RegisterSpec for InitSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`init::R`](R) reader structure"]
impl crate::Readable for InitSpec {}
#[doc = "`write(|w| ..)` method takes [`init::W`](W) writer structure"]
impl crate::Writable for InitSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INIT to value 0"]
impl crate::Resettable for InitSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "POL (rw) register accessor: CRC polynomial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pol::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pol::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pol`]
module"]
#[doc(alias = "POL")]
pub type Pol = crate::Reg<pol::PolSpec>;
#[doc = "CRC polynomial"]
pub mod pol {
#[doc = "Register `POL` reader"]
pub type R = crate::R<PolSpec>;
#[doc = "Register `POL` writer"]
pub type W = crate::W<PolSpec>;
#[doc = "Field `POL` reader - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
pub type PolR = crate::FieldReader<u32>;
#[doc = "Field `POL` writer - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
pub type PolW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
#[inline(always)]
pub fn pol(&self) -> PolR {
PolR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
#[inline(always)]
#[must_use]
pub fn pol(&mut self) -> PolW<PolSpec> {
PolW::new(self, 0)
}
}
#[doc = "CRC polynomial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pol::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PolSpec;
impl crate::RegisterSpec for PolSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pol::R`](R) reader structure"]
impl crate::Readable for PolSpec {}
#[doc = "`write(|w| ..)` method takes [`pol::W`](W) writer structure"]
impl crate::Writable for PolSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets POL to value 0"]
impl crate::Resettable for PolSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "DMAC1"]
pub struct Dmac1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Dmac1 {}
impl Dmac1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dmac1::RegisterBlock = 0x5008_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dmac1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Dmac1 {
type Target = dmac1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Dmac1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dmac1").finish()
}
}
#[doc = "DMAC1"]
pub mod dmac1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
isr: Isr,
ifcr: Ifcr,
ccr1: Ccr1,
cndtr1: Cndtr1,
cpar1: Cpar1,
cm0ar1: Cm0ar1,
cbsr1: Cbsr1,
ccr2: Ccr2,
cndtr2: Cndtr2,
cpar2: Cpar2,
cm0ar2: Cm0ar2,
cbsr2: Cbsr2,
ccr3: Ccr3,
cndtr3: Cndtr3,
cpar3: Cpar3,
cm0ar3: Cm0ar3,
cbsr3: Cbsr3,
ccr4: Ccr4,
cndtr4: Cndtr4,
cpar4: Cpar4,
cm0ar4: Cm0ar4,
cbsr4: Cbsr4,
ccr5: Ccr5,
cndtr5: Cndtr5,
cpar5: Cpar5,
cm0ar5: Cm0ar5,
cbsr5: Cbsr5,
ccr6: Ccr6,
cndtr6: Cndtr6,
cpar6: Cpar6,
cm0ar6: Cm0ar6,
cbsr6: Cbsr6,
ccr7: Ccr7,
cndtr7: Cndtr7,
cpar7: Cpar7,
cm0ar7: Cm0ar7,
cbsr7: Cbsr7,
ccr8: Ccr8,
cndtr8: Cndtr8,
cpar8: Cpar8,
cm0ar8: Cm0ar8,
cbsr8: Cbsr8,
cselr1: Cselr1,
cselr2: Cselr2,
}
impl RegisterBlock {
#[doc = "0x00 - "]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x04 - "]
#[inline(always)]
pub const fn ifcr(&self) -> &Ifcr {
&self.ifcr
}
#[doc = "0x08 - "]
#[inline(always)]
pub const fn ccr1(&self) -> &Ccr1 {
&self.ccr1
}
#[doc = "0x0c - "]
#[inline(always)]
pub const fn cndtr1(&self) -> &Cndtr1 {
&self.cndtr1
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn cpar1(&self) -> &Cpar1 {
&self.cpar1
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn cm0ar1(&self) -> &Cm0ar1 {
&self.cm0ar1
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn cbsr1(&self) -> &Cbsr1 {
&self.cbsr1
}
#[doc = "0x1c - "]
#[inline(always)]
pub const fn ccr2(&self) -> &Ccr2 {
&self.ccr2
}
#[doc = "0x20 - "]
#[inline(always)]
pub const fn cndtr2(&self) -> &Cndtr2 {
&self.cndtr2
}
#[doc = "0x24 - "]
#[inline(always)]
pub const fn cpar2(&self) -> &Cpar2 {
&self.cpar2
}
#[doc = "0x28 - "]
#[inline(always)]
pub const fn cm0ar2(&self) -> &Cm0ar2 {
&self.cm0ar2
}
#[doc = "0x2c - "]
#[inline(always)]
pub const fn cbsr2(&self) -> &Cbsr2 {
&self.cbsr2
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn ccr3(&self) -> &Ccr3 {
&self.ccr3
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn cndtr3(&self) -> &Cndtr3 {
&self.cndtr3
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn cpar3(&self) -> &Cpar3 {
&self.cpar3
}
#[doc = "0x3c - "]
#[inline(always)]
pub const fn cm0ar3(&self) -> &Cm0ar3 {
&self.cm0ar3
}
#[doc = "0x40 - "]
#[inline(always)]
pub const fn cbsr3(&self) -> &Cbsr3 {
&self.cbsr3
}
#[doc = "0x44 - "]
#[inline(always)]
pub const fn ccr4(&self) -> &Ccr4 {
&self.ccr4
}
#[doc = "0x48 - "]
#[inline(always)]
pub const fn cndtr4(&self) -> &Cndtr4 {
&self.cndtr4
}
#[doc = "0x4c - "]
#[inline(always)]
pub const fn cpar4(&self) -> &Cpar4 {
&self.cpar4
}
#[doc = "0x50 - "]
#[inline(always)]
pub const fn cm0ar4(&self) -> &Cm0ar4 {
&self.cm0ar4
}
#[doc = "0x54 - "]
#[inline(always)]
pub const fn cbsr4(&self) -> &Cbsr4 {
&self.cbsr4
}
#[doc = "0x58 - "]
#[inline(always)]
pub const fn ccr5(&self) -> &Ccr5 {
&self.ccr5
}
#[doc = "0x5c - "]
#[inline(always)]
pub const fn cndtr5(&self) -> &Cndtr5 {
&self.cndtr5
}
#[doc = "0x60 - "]
#[inline(always)]
pub const fn cpar5(&self) -> &Cpar5 {
&self.cpar5
}
#[doc = "0x64 - "]
#[inline(always)]
pub const fn cm0ar5(&self) -> &Cm0ar5 {
&self.cm0ar5
}
#[doc = "0x68 - "]
#[inline(always)]
pub const fn cbsr5(&self) -> &Cbsr5 {
&self.cbsr5
}
#[doc = "0x6c - "]
#[inline(always)]
pub const fn ccr6(&self) -> &Ccr6 {
&self.ccr6
}
#[doc = "0x70 - "]
#[inline(always)]
pub const fn cndtr6(&self) -> &Cndtr6 {
&self.cndtr6
}
#[doc = "0x74 - "]
#[inline(always)]
pub const fn cpar6(&self) -> &Cpar6 {
&self.cpar6
}
#[doc = "0x78 - "]
#[inline(always)]
pub const fn cm0ar6(&self) -> &Cm0ar6 {
&self.cm0ar6
}
#[doc = "0x7c - "]
#[inline(always)]
pub const fn cbsr6(&self) -> &Cbsr6 {
&self.cbsr6
}
#[doc = "0x80 - "]
#[inline(always)]
pub const fn ccr7(&self) -> &Ccr7 {
&self.ccr7
}
#[doc = "0x84 - "]
#[inline(always)]
pub const fn cndtr7(&self) -> &Cndtr7 {
&self.cndtr7
}
#[doc = "0x88 - "]
#[inline(always)]
pub const fn cpar7(&self) -> &Cpar7 {
&self.cpar7
}
#[doc = "0x8c - "]
#[inline(always)]
pub const fn cm0ar7(&self) -> &Cm0ar7 {
&self.cm0ar7
}
#[doc = "0x90 - "]
#[inline(always)]
pub const fn cbsr7(&self) -> &Cbsr7 {
&self.cbsr7
}
#[doc = "0x94 - "]
#[inline(always)]
pub const fn ccr8(&self) -> &Ccr8 {
&self.ccr8
}
#[doc = "0x98 - "]
#[inline(always)]
pub const fn cndtr8(&self) -> &Cndtr8 {
&self.cndtr8
}
#[doc = "0x9c - "]
#[inline(always)]
pub const fn cpar8(&self) -> &Cpar8 {
&self.cpar8
}
#[doc = "0xa0 - "]
#[inline(always)]
pub const fn cm0ar8(&self) -> &Cm0ar8 {
&self.cm0ar8
}
#[doc = "0xa4 - "]
#[inline(always)]
pub const fn cbsr8(&self) -> &Cbsr8 {
&self.cbsr8
}
#[doc = "0xa8 - "]
#[inline(always)]
pub const fn cselr1(&self) -> &Cselr1 {
&self.cselr1
}
#[doc = "0xac - "]
#[inline(always)]
pub const fn cselr2(&self) -> &Cselr2 {
&self.cselr2
}
}
#[doc = "ISR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = ""]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `GIF1` reader - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
pub type Gif1R = crate::BitReader;
#[doc = "Field `GIF1` writer - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
pub type Gif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF1` reader - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
pub type Tcif1R = crate::BitReader;
#[doc = "Field `TCIF1` writer - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
pub type Tcif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF1` reader - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
pub type Htif1R = crate::BitReader;
#[doc = "Field `HTIF1` writer - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
pub type Htif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF1` reader - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
pub type Teif1R = crate::BitReader;
#[doc = "Field `TEIF1` writer - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
pub type Teif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF2` reader - channel global interrupt flag"]
pub type Gif2R = crate::BitReader;
#[doc = "Field `GIF2` writer - channel global interrupt flag"]
pub type Gif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF2` reader - channel transfer complete flag"]
pub type Tcif2R = crate::BitReader;
#[doc = "Field `TCIF2` writer - channel transfer complete flag"]
pub type Tcif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF2` reader - channel half transfer flag"]
pub type Htif2R = crate::BitReader;
#[doc = "Field `HTIF2` writer - channel half transfer flag"]
pub type Htif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF2` reader - channel transfer error flag"]
pub type Teif2R = crate::BitReader;
#[doc = "Field `TEIF2` writer - channel transfer error flag"]
pub type Teif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF3` reader - channel global interrupt flag"]
pub type Gif3R = crate::BitReader;
#[doc = "Field `GIF3` writer - channel global interrupt flag"]
pub type Gif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF3` reader - channel transfer complete flag"]
pub type Tcif3R = crate::BitReader;
#[doc = "Field `TCIF3` writer - channel transfer complete flag"]
pub type Tcif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF3` reader - channel half transfer flag"]
pub type Htif3R = crate::BitReader;
#[doc = "Field `HTIF3` writer - channel half transfer flag"]
pub type Htif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF3` reader - channel transfer error flag"]
pub type Teif3R = crate::BitReader;
#[doc = "Field `TEIF3` writer - channel transfer error flag"]
pub type Teif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF4` reader - channel global interrupt flag"]
pub type Gif4R = crate::BitReader;
#[doc = "Field `GIF4` writer - channel global interrupt flag"]
pub type Gif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF4` reader - channel transfer complete flag"]
pub type Tcif4R = crate::BitReader;
#[doc = "Field `TCIF4` writer - channel transfer complete flag"]
pub type Tcif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF4` reader - channel half transfer flag"]
pub type Htif4R = crate::BitReader;
#[doc = "Field `HTIF4` writer - channel half transfer flag"]
pub type Htif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF4` reader - channel transfer error flag"]
pub type Teif4R = crate::BitReader;
#[doc = "Field `TEIF4` writer - channel transfer error flag"]
pub type Teif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF5` reader - channel global interrupt flag"]
pub type Gif5R = crate::BitReader;
#[doc = "Field `GIF5` writer - channel global interrupt flag"]
pub type Gif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF5` reader - channel transfer complete flag"]
pub type Tcif5R = crate::BitReader;
#[doc = "Field `TCIF5` writer - channel transfer complete flag"]
pub type Tcif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF5` reader - channel half transfer flag"]
pub type Htif5R = crate::BitReader;
#[doc = "Field `HTIF5` writer - channel half transfer flag"]
pub type Htif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF5` reader - channel transfer error flag"]
pub type Teif5R = crate::BitReader;
#[doc = "Field `TEIF5` writer - channel transfer error flag"]
pub type Teif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF6` reader - channel global interrupt flag"]
pub type Gif6R = crate::BitReader;
#[doc = "Field `GIF6` writer - channel global interrupt flag"]
pub type Gif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF6` reader - channel transfer complete flag"]
pub type Tcif6R = crate::BitReader;
#[doc = "Field `TCIF6` writer - channel transfer complete flag"]
pub type Tcif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF6` reader - channel half transfer flag"]
pub type Htif6R = crate::BitReader;
#[doc = "Field `HTIF6` writer - channel half transfer flag"]
pub type Htif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF6` reader - channel transfer error flag"]
pub type Teif6R = crate::BitReader;
#[doc = "Field `TEIF6` writer - channel transfer error flag"]
pub type Teif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF7` reader - channel global interrupt flag"]
pub type Gif7R = crate::BitReader;
#[doc = "Field `GIF7` writer - channel global interrupt flag"]
pub type Gif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF7` reader - channel transfer complete flag"]
pub type Tcif7R = crate::BitReader;
#[doc = "Field `TCIF7` writer - channel transfer complete flag"]
pub type Tcif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF7` reader - channel half transfer flag"]
pub type Htif7R = crate::BitReader;
#[doc = "Field `HTIF7` writer - channel half transfer flag"]
pub type Htif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF7` reader - channel transfer error flag"]
pub type Teif7R = crate::BitReader;
#[doc = "Field `TEIF7` writer - channel transfer error flag"]
pub type Teif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF8` reader - channel global interrupt flag"]
pub type Gif8R = crate::BitReader;
#[doc = "Field `GIF8` writer - channel global interrupt flag"]
pub type Gif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF8` reader - channel transfer complete flag"]
pub type Tcif8R = crate::BitReader;
#[doc = "Field `TCIF8` writer - channel transfer complete flag"]
pub type Tcif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF8` reader - channel half transfer flag"]
pub type Htif8R = crate::BitReader;
#[doc = "Field `HTIF8` writer - channel half transfer flag"]
pub type Htif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF8` reader - channel transfer error flag"]
pub type Teif8R = crate::BitReader;
#[doc = "Field `TEIF8` writer - channel transfer error flag"]
pub type Teif8W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
#[inline(always)]
pub fn gif1(&self) -> Gif1R {
Gif1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
#[inline(always)]
pub fn tcif1(&self) -> Tcif1R {
Tcif1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
#[inline(always)]
pub fn htif1(&self) -> Htif1R {
Htif1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
#[inline(always)]
pub fn teif1(&self) -> Teif1R {
Teif1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - channel global interrupt flag"]
#[inline(always)]
pub fn gif2(&self) -> Gif2R {
Gif2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif2(&self) -> Tcif2R {
Tcif2R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - channel half transfer flag"]
#[inline(always)]
pub fn htif2(&self) -> Htif2R {
Htif2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - channel transfer error flag"]
#[inline(always)]
pub fn teif2(&self) -> Teif2R {
Teif2R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - channel global interrupt flag"]
#[inline(always)]
pub fn gif3(&self) -> Gif3R {
Gif3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif3(&self) -> Tcif3R {
Tcif3R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - channel half transfer flag"]
#[inline(always)]
pub fn htif3(&self) -> Htif3R {
Htif3R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - channel transfer error flag"]
#[inline(always)]
pub fn teif3(&self) -> Teif3R {
Teif3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - channel global interrupt flag"]
#[inline(always)]
pub fn gif4(&self) -> Gif4R {
Gif4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif4(&self) -> Tcif4R {
Tcif4R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - channel half transfer flag"]
#[inline(always)]
pub fn htif4(&self) -> Htif4R {
Htif4R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - channel transfer error flag"]
#[inline(always)]
pub fn teif4(&self) -> Teif4R {
Teif4R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - channel global interrupt flag"]
#[inline(always)]
pub fn gif5(&self) -> Gif5R {
Gif5R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif5(&self) -> Tcif5R {
Tcif5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - channel half transfer flag"]
#[inline(always)]
pub fn htif5(&self) -> Htif5R {
Htif5R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - channel transfer error flag"]
#[inline(always)]
pub fn teif5(&self) -> Teif5R {
Teif5R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - channel global interrupt flag"]
#[inline(always)]
pub fn gif6(&self) -> Gif6R {
Gif6R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif6(&self) -> Tcif6R {
Tcif6R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - channel half transfer flag"]
#[inline(always)]
pub fn htif6(&self) -> Htif6R {
Htif6R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - channel transfer error flag"]
#[inline(always)]
pub fn teif6(&self) -> Teif6R {
Teif6R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - channel global interrupt flag"]
#[inline(always)]
pub fn gif7(&self) -> Gif7R {
Gif7R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif7(&self) -> Tcif7R {
Tcif7R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - channel half transfer flag"]
#[inline(always)]
pub fn htif7(&self) -> Htif7R {
Htif7R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - channel transfer error flag"]
#[inline(always)]
pub fn teif7(&self) -> Teif7R {
Teif7R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - channel global interrupt flag"]
#[inline(always)]
pub fn gif8(&self) -> Gif8R {
Gif8R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif8(&self) -> Tcif8R {
Tcif8R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - channel half transfer flag"]
#[inline(always)]
pub fn htif8(&self) -> Htif8R {
Htif8R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - channel transfer error flag"]
#[inline(always)]
pub fn teif8(&self) -> Teif8R {
Teif8R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
#[inline(always)]
#[must_use]
pub fn gif1(&mut self) -> Gif1W<IsrSpec> {
Gif1W::new(self, 0)
}
#[doc = "Bit 1 - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
#[inline(always)]
#[must_use]
pub fn tcif1(&mut self) -> Tcif1W<IsrSpec> {
Tcif1W::new(self, 1)
}
#[doc = "Bit 2 - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
#[inline(always)]
#[must_use]
pub fn htif1(&mut self) -> Htif1W<IsrSpec> {
Htif1W::new(self, 2)
}
#[doc = "Bit 3 - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
#[inline(always)]
#[must_use]
pub fn teif1(&mut self) -> Teif1W<IsrSpec> {
Teif1W::new(self, 3)
}
#[doc = "Bit 4 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif2(&mut self) -> Gif2W<IsrSpec> {
Gif2W::new(self, 4)
}
#[doc = "Bit 5 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif2(&mut self) -> Tcif2W<IsrSpec> {
Tcif2W::new(self, 5)
}
#[doc = "Bit 6 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif2(&mut self) -> Htif2W<IsrSpec> {
Htif2W::new(self, 6)
}
#[doc = "Bit 7 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif2(&mut self) -> Teif2W<IsrSpec> {
Teif2W::new(self, 7)
}
#[doc = "Bit 8 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif3(&mut self) -> Gif3W<IsrSpec> {
Gif3W::new(self, 8)
}
#[doc = "Bit 9 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif3(&mut self) -> Tcif3W<IsrSpec> {
Tcif3W::new(self, 9)
}
#[doc = "Bit 10 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif3(&mut self) -> Htif3W<IsrSpec> {
Htif3W::new(self, 10)
}
#[doc = "Bit 11 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif3(&mut self) -> Teif3W<IsrSpec> {
Teif3W::new(self, 11)
}
#[doc = "Bit 12 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif4(&mut self) -> Gif4W<IsrSpec> {
Gif4W::new(self, 12)
}
#[doc = "Bit 13 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif4(&mut self) -> Tcif4W<IsrSpec> {
Tcif4W::new(self, 13)
}
#[doc = "Bit 14 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif4(&mut self) -> Htif4W<IsrSpec> {
Htif4W::new(self, 14)
}
#[doc = "Bit 15 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif4(&mut self) -> Teif4W<IsrSpec> {
Teif4W::new(self, 15)
}
#[doc = "Bit 16 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif5(&mut self) -> Gif5W<IsrSpec> {
Gif5W::new(self, 16)
}
#[doc = "Bit 17 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif5(&mut self) -> Tcif5W<IsrSpec> {
Tcif5W::new(self, 17)
}
#[doc = "Bit 18 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif5(&mut self) -> Htif5W<IsrSpec> {
Htif5W::new(self, 18)
}
#[doc = "Bit 19 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif5(&mut self) -> Teif5W<IsrSpec> {
Teif5W::new(self, 19)
}
#[doc = "Bit 20 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif6(&mut self) -> Gif6W<IsrSpec> {
Gif6W::new(self, 20)
}
#[doc = "Bit 21 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif6(&mut self) -> Tcif6W<IsrSpec> {
Tcif6W::new(self, 21)
}
#[doc = "Bit 22 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif6(&mut self) -> Htif6W<IsrSpec> {
Htif6W::new(self, 22)
}
#[doc = "Bit 23 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif6(&mut self) -> Teif6W<IsrSpec> {
Teif6W::new(self, 23)
}
#[doc = "Bit 24 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif7(&mut self) -> Gif7W<IsrSpec> {
Gif7W::new(self, 24)
}
#[doc = "Bit 25 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif7(&mut self) -> Tcif7W<IsrSpec> {
Tcif7W::new(self, 25)
}
#[doc = "Bit 26 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif7(&mut self) -> Htif7W<IsrSpec> {
Htif7W::new(self, 26)
}
#[doc = "Bit 27 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif7(&mut self) -> Teif7W<IsrSpec> {
Teif7W::new(self, 27)
}
#[doc = "Bit 28 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif8(&mut self) -> Gif8W<IsrSpec> {
Gif8W::new(self, 28)
}
#[doc = "Bit 29 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif8(&mut self) -> Tcif8W<IsrSpec> {
Tcif8W::new(self, 29)
}
#[doc = "Bit 30 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif8(&mut self) -> Htif8W<IsrSpec> {
Htif8W::new(self, 30)
}
#[doc = "Bit 31 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif8(&mut self) -> Teif8W<IsrSpec> {
Teif8W::new(self, 31)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IFCR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifcr`]
module"]
#[doc(alias = "IFCR")]
pub type Ifcr = crate::Reg<ifcr::IfcrSpec>;
#[doc = ""]
pub mod ifcr {
#[doc = "Register `IFCR` reader"]
pub type R = crate::R<IfcrSpec>;
#[doc = "Register `IFCR` writer"]
pub type W = crate::W<IfcrSpec>;
#[doc = "Field `CGIF1` reader - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
pub type Cgif1R = crate::BitReader;
#[doc = "Field `CGIF1` writer - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
pub type Cgif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF1` reader - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
pub type Ctcif1R = crate::BitReader;
#[doc = "Field `CTCIF1` writer - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
pub type Ctcif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF1` reader - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
pub type Chtif1R = crate::BitReader;
#[doc = "Field `CHTIF1` writer - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
pub type Chtif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF1` reader - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
pub type Cteif1R = crate::BitReader;
#[doc = "Field `CTEIF1` writer - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
pub type Cteif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF2` reader - CGIF, global interrupt flag clear"]
pub type Cgif2R = crate::BitReader;
#[doc = "Field `CGIF2` writer - CGIF, global interrupt flag clear"]
pub type Cgif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF2` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif2R = crate::BitReader;
#[doc = "Field `CTCIF2` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF2` reader - CHTIF, half transfer flag clear"]
pub type Chtif2R = crate::BitReader;
#[doc = "Field `CHTIF2` writer - CHTIF, half transfer flag clear"]
pub type Chtif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF2` reader - CTEIF, transfer error flag clear"]
pub type Cteif2R = crate::BitReader;
#[doc = "Field `CTEIF2` writer - CTEIF, transfer error flag clear"]
pub type Cteif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF3` reader - CGIF, global interrupt flag clear"]
pub type Cgif3R = crate::BitReader;
#[doc = "Field `CGIF3` writer - CGIF, global interrupt flag clear"]
pub type Cgif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF3` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif3R = crate::BitReader;
#[doc = "Field `CTCIF3` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF3` reader - CHTIF, half transfer flag clear"]
pub type Chtif3R = crate::BitReader;
#[doc = "Field `CHTIF3` writer - CHTIF, half transfer flag clear"]
pub type Chtif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF3` reader - CTEIF, transfer error flag clear"]
pub type Cteif3R = crate::BitReader;
#[doc = "Field `CTEIF3` writer - CTEIF, transfer error flag clear"]
pub type Cteif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF4` reader - CGIF, global interrupt flag clear"]
pub type Cgif4R = crate::BitReader;
#[doc = "Field `CGIF4` writer - CGIF, global interrupt flag clear"]
pub type Cgif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF4` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif4R = crate::BitReader;
#[doc = "Field `CTCIF4` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF4` reader - CHTIF, half transfer flag clear"]
pub type Chtif4R = crate::BitReader;
#[doc = "Field `CHTIF4` writer - CHTIF, half transfer flag clear"]
pub type Chtif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF4` reader - CTEIF, transfer error flag clear"]
pub type Cteif4R = crate::BitReader;
#[doc = "Field `CTEIF4` writer - CTEIF, transfer error flag clear"]
pub type Cteif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF5` reader - CGIF, global interrupt flag clear"]
pub type Cgif5R = crate::BitReader;
#[doc = "Field `CGIF5` writer - CGIF, global interrupt flag clear"]
pub type Cgif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF5` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif5R = crate::BitReader;
#[doc = "Field `CTCIF5` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF5` reader - CHTIF, half transfer flag clear"]
pub type Chtif5R = crate::BitReader;
#[doc = "Field `CHTIF5` writer - CHTIF, half transfer flag clear"]
pub type Chtif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF5` reader - CTEIF, transfer error flag clear"]
pub type Cteif5R = crate::BitReader;
#[doc = "Field `CTEIF5` writer - CTEIF, transfer error flag clear"]
pub type Cteif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF6` reader - CGIF, global interrupt flag clear"]
pub type Cgif6R = crate::BitReader;
#[doc = "Field `CGIF6` writer - CGIF, global interrupt flag clear"]
pub type Cgif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF6` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif6R = crate::BitReader;
#[doc = "Field `CTCIF6` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF6` reader - CHTIF, half transfer flag clear"]
pub type Chtif6R = crate::BitReader;
#[doc = "Field `CHTIF6` writer - CHTIF, half transfer flag clear"]
pub type Chtif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF6` reader - CTEIF, transfer error flag clear"]
pub type Cteif6R = crate::BitReader;
#[doc = "Field `CTEIF6` writer - CTEIF, transfer error flag clear"]
pub type Cteif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF7` reader - CGIF, global interrupt flag clear"]
pub type Cgif7R = crate::BitReader;
#[doc = "Field `CGIF7` writer - CGIF, global interrupt flag clear"]
pub type Cgif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF7` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif7R = crate::BitReader;
#[doc = "Field `CTCIF7` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF7` reader - CHTIF, half transfer flag clear"]
pub type Chtif7R = crate::BitReader;
#[doc = "Field `CHTIF7` writer - CHTIF, half transfer flag clear"]
pub type Chtif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF7` reader - CTEIF, transfer error flag clear"]
pub type Cteif7R = crate::BitReader;
#[doc = "Field `CTEIF7` writer - CTEIF, transfer error flag clear"]
pub type Cteif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF8` reader - CGIF, global interrupt flag clear"]
pub type Cgif8R = crate::BitReader;
#[doc = "Field `CGIF8` writer - CGIF, global interrupt flag clear"]
pub type Cgif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF8` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif8R = crate::BitReader;
#[doc = "Field `CTCIF8` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF8` reader - CHTIF, half transfer flag clear"]
pub type Chtif8R = crate::BitReader;
#[doc = "Field `CHTIF8` writer - CHTIF, half transfer flag clear"]
pub type Chtif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF8` reader - CTEIF, transfer error flag clear"]
pub type Cteif8R = crate::BitReader;
#[doc = "Field `CTEIF8` writer - CTEIF, transfer error flag clear"]
pub type Cteif8W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
#[inline(always)]
pub fn cgif1(&self) -> Cgif1R {
Cgif1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
#[inline(always)]
pub fn ctcif1(&self) -> Ctcif1R {
Ctcif1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
#[inline(always)]
pub fn chtif1(&self) -> Chtif1R {
Chtif1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
#[inline(always)]
pub fn cteif1(&self) -> Cteif1R {
Cteif1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif2(&self) -> Cgif2R {
Cgif2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif2(&self) -> Ctcif2R {
Ctcif2R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif2(&self) -> Chtif2R {
Chtif2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif2(&self) -> Cteif2R {
Cteif2R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif3(&self) -> Cgif3R {
Cgif3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif3(&self) -> Ctcif3R {
Ctcif3R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif3(&self) -> Chtif3R {
Chtif3R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif3(&self) -> Cteif3R {
Cteif3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif4(&self) -> Cgif4R {
Cgif4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif4(&self) -> Ctcif4R {
Ctcif4R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif4(&self) -> Chtif4R {
Chtif4R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif4(&self) -> Cteif4R {
Cteif4R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif5(&self) -> Cgif5R {
Cgif5R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif5(&self) -> Ctcif5R {
Ctcif5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif5(&self) -> Chtif5R {
Chtif5R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif5(&self) -> Cteif5R {
Cteif5R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif6(&self) -> Cgif6R {
Cgif6R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif6(&self) -> Ctcif6R {
Ctcif6R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif6(&self) -> Chtif6R {
Chtif6R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif6(&self) -> Cteif6R {
Cteif6R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif7(&self) -> Cgif7R {
Cgif7R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif7(&self) -> Ctcif7R {
Ctcif7R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif7(&self) -> Chtif7R {
Chtif7R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif7(&self) -> Cteif7R {
Cteif7R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif8(&self) -> Cgif8R {
Cgif8R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif8(&self) -> Ctcif8R {
Ctcif8R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif8(&self) -> Chtif8R {
Chtif8R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif8(&self) -> Cteif8R {
Cteif8R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
#[inline(always)]
#[must_use]
pub fn cgif1(&mut self) -> Cgif1W<IfcrSpec> {
Cgif1W::new(self, 0)
}
#[doc = "Bit 1 - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
#[inline(always)]
#[must_use]
pub fn ctcif1(&mut self) -> Ctcif1W<IfcrSpec> {
Ctcif1W::new(self, 1)
}
#[doc = "Bit 2 - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
#[inline(always)]
#[must_use]
pub fn chtif1(&mut self) -> Chtif1W<IfcrSpec> {
Chtif1W::new(self, 2)
}
#[doc = "Bit 3 - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
#[inline(always)]
#[must_use]
pub fn cteif1(&mut self) -> Cteif1W<IfcrSpec> {
Cteif1W::new(self, 3)
}
#[doc = "Bit 4 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif2(&mut self) -> Cgif2W<IfcrSpec> {
Cgif2W::new(self, 4)
}
#[doc = "Bit 5 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif2(&mut self) -> Ctcif2W<IfcrSpec> {
Ctcif2W::new(self, 5)
}
#[doc = "Bit 6 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif2(&mut self) -> Chtif2W<IfcrSpec> {
Chtif2W::new(self, 6)
}
#[doc = "Bit 7 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif2(&mut self) -> Cteif2W<IfcrSpec> {
Cteif2W::new(self, 7)
}
#[doc = "Bit 8 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif3(&mut self) -> Cgif3W<IfcrSpec> {
Cgif3W::new(self, 8)
}
#[doc = "Bit 9 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif3(&mut self) -> Ctcif3W<IfcrSpec> {
Ctcif3W::new(self, 9)
}
#[doc = "Bit 10 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif3(&mut self) -> Chtif3W<IfcrSpec> {
Chtif3W::new(self, 10)
}
#[doc = "Bit 11 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif3(&mut self) -> Cteif3W<IfcrSpec> {
Cteif3W::new(self, 11)
}
#[doc = "Bit 12 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif4(&mut self) -> Cgif4W<IfcrSpec> {
Cgif4W::new(self, 12)
}
#[doc = "Bit 13 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif4(&mut self) -> Ctcif4W<IfcrSpec> {
Ctcif4W::new(self, 13)
}
#[doc = "Bit 14 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif4(&mut self) -> Chtif4W<IfcrSpec> {
Chtif4W::new(self, 14)
}
#[doc = "Bit 15 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif4(&mut self) -> Cteif4W<IfcrSpec> {
Cteif4W::new(self, 15)
}
#[doc = "Bit 16 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif5(&mut self) -> Cgif5W<IfcrSpec> {
Cgif5W::new(self, 16)
}
#[doc = "Bit 17 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif5(&mut self) -> Ctcif5W<IfcrSpec> {
Ctcif5W::new(self, 17)
}
#[doc = "Bit 18 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif5(&mut self) -> Chtif5W<IfcrSpec> {
Chtif5W::new(self, 18)
}
#[doc = "Bit 19 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif5(&mut self) -> Cteif5W<IfcrSpec> {
Cteif5W::new(self, 19)
}
#[doc = "Bit 20 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif6(&mut self) -> Cgif6W<IfcrSpec> {
Cgif6W::new(self, 20)
}
#[doc = "Bit 21 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif6(&mut self) -> Ctcif6W<IfcrSpec> {
Ctcif6W::new(self, 21)
}
#[doc = "Bit 22 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif6(&mut self) -> Chtif6W<IfcrSpec> {
Chtif6W::new(self, 22)
}
#[doc = "Bit 23 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif6(&mut self) -> Cteif6W<IfcrSpec> {
Cteif6W::new(self, 23)
}
#[doc = "Bit 24 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif7(&mut self) -> Cgif7W<IfcrSpec> {
Cgif7W::new(self, 24)
}
#[doc = "Bit 25 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif7(&mut self) -> Ctcif7W<IfcrSpec> {
Ctcif7W::new(self, 25)
}
#[doc = "Bit 26 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif7(&mut self) -> Chtif7W<IfcrSpec> {
Chtif7W::new(self, 26)
}
#[doc = "Bit 27 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif7(&mut self) -> Cteif7W<IfcrSpec> {
Cteif7W::new(self, 27)
}
#[doc = "Bit 28 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif8(&mut self) -> Cgif8W<IfcrSpec> {
Cgif8W::new(self, 28)
}
#[doc = "Bit 29 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif8(&mut self) -> Ctcif8W<IfcrSpec> {
Ctcif8W::new(self, 29)
}
#[doc = "Bit 30 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif8(&mut self) -> Chtif8W<IfcrSpec> {
Chtif8W::new(self, 30)
}
#[doc = "Bit 31 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif8(&mut self) -> Cteif8W<IfcrSpec> {
Cteif8W::new(self, 31)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IfcrSpec;
impl crate::RegisterSpec for IfcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ifcr::R`](R) reader structure"]
impl crate::Readable for IfcrSpec {}
#[doc = "`write(|w| ..)` method takes [`ifcr::W`](W) writer structure"]
impl crate::Writable for IfcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IFCR to value 0"]
impl crate::Resettable for IfcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`]
module"]
#[doc(alias = "CCR1")]
pub type Ccr1 = crate::Reg<ccr1::Ccr1Spec>;
#[doc = ""]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub type R = crate::R<Ccr1Spec>;
#[doc = "Register `CCR1` writer"]
pub type W = crate::W<Ccr1Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr1Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr1Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr1Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr1Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr1Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr1Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr1Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr1Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr1Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr1Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr1Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr1Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr1Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr1Spec;
impl crate::RegisterSpec for Ccr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"]
impl crate::Readable for Ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"]
impl crate::Writable for Ccr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for Ccr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr1`]
module"]
#[doc(alias = "CNDTR1")]
pub type Cndtr1 = crate::Reg<cndtr1::Cndtr1Spec>;
#[doc = ""]
pub mod cndtr1 {
#[doc = "Register `CNDTR1` reader"]
pub type R = crate::R<Cndtr1Spec>;
#[doc = "Register `CNDTR1` writer"]
pub type W = crate::W<Cndtr1Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr1Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr1Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr1Spec;
impl crate::RegisterSpec for Cndtr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr1::R`](R) reader structure"]
impl crate::Readable for Cndtr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr1::W`](W) writer structure"]
impl crate::Writable for Cndtr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR1 to value 0"]
impl crate::Resettable for Cndtr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar1`]
module"]
#[doc(alias = "CPAR1")]
pub type Cpar1 = crate::Reg<cpar1::Cpar1Spec>;
#[doc = ""]
pub mod cpar1 {
#[doc = "Register `CPAR1` reader"]
pub type R = crate::R<Cpar1Spec>;
#[doc = "Register `CPAR1` writer"]
pub type W = crate::W<Cpar1Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar1Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar1Spec;
impl crate::RegisterSpec for Cpar1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar1::R`](R) reader structure"]
impl crate::Readable for Cpar1Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar1::W`](W) writer structure"]
impl crate::Writable for Cpar1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR1 to value 0"]
impl crate::Resettable for Cpar1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar1`]
module"]
#[doc(alias = "CM0AR1")]
pub type Cm0ar1 = crate::Reg<cm0ar1::Cm0ar1Spec>;
#[doc = ""]
pub mod cm0ar1 {
#[doc = "Register `CM0AR1` reader"]
pub type R = crate::R<Cm0ar1Spec>;
#[doc = "Register `CM0AR1` writer"]
pub type W = crate::W<Cm0ar1Spec>;
#[doc = "Field `MA` reader - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar1Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar1Spec;
impl crate::RegisterSpec for Cm0ar1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar1::R`](R) reader structure"]
impl crate::Readable for Cm0ar1Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar1::W`](W) writer structure"]
impl crate::Writable for Cm0ar1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR1 to value 0"]
impl crate::Resettable for Cm0ar1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr1`]
module"]
#[doc(alias = "CBSR1")]
pub type Cbsr1 = crate::Reg<cbsr1::Cbsr1Spec>;
#[doc = ""]
pub mod cbsr1 {
#[doc = "Register `CBSR1` reader"]
pub type R = crate::R<Cbsr1Spec>;
#[doc = "Register `CBSR1` writer"]
pub type W = crate::W<Cbsr1Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr1Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr1Spec;
impl crate::RegisterSpec for Cbsr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr1::R`](R) reader structure"]
impl crate::Readable for Cbsr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr1::W`](W) writer structure"]
impl crate::Writable for Cbsr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR1 to value 0"]
impl crate::Resettable for Cbsr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`]
module"]
#[doc(alias = "CCR2")]
pub type Ccr2 = crate::Reg<ccr2::Ccr2Spec>;
#[doc = ""]
pub mod ccr2 {
#[doc = "Register `CCR2` reader"]
pub type R = crate::R<Ccr2Spec>;
#[doc = "Register `CCR2` writer"]
pub type W = crate::W<Ccr2Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr2Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr2Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr2Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr2Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr2Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr2Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr2Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr2Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr2Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr2Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr2Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr2Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr2Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr2Spec;
impl crate::RegisterSpec for Ccr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"]
impl crate::Readable for Ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"]
impl crate::Writable for Ccr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR2 to value 0"]
impl crate::Resettable for Ccr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr2`]
module"]
#[doc(alias = "CNDTR2")]
pub type Cndtr2 = crate::Reg<cndtr2::Cndtr2Spec>;
#[doc = ""]
pub mod cndtr2 {
#[doc = "Register `CNDTR2` reader"]
pub type R = crate::R<Cndtr2Spec>;
#[doc = "Register `CNDTR2` writer"]
pub type W = crate::W<Cndtr2Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr2Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr2Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr2Spec;
impl crate::RegisterSpec for Cndtr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr2::R`](R) reader structure"]
impl crate::Readable for Cndtr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr2::W`](W) writer structure"]
impl crate::Writable for Cndtr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR2 to value 0"]
impl crate::Resettable for Cndtr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar2`]
module"]
#[doc(alias = "CPAR2")]
pub type Cpar2 = crate::Reg<cpar2::Cpar2Spec>;
#[doc = ""]
pub mod cpar2 {
#[doc = "Register `CPAR2` reader"]
pub type R = crate::R<Cpar2Spec>;
#[doc = "Register `CPAR2` writer"]
pub type W = crate::W<Cpar2Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar2Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar2Spec;
impl crate::RegisterSpec for Cpar2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar2::R`](R) reader structure"]
impl crate::Readable for Cpar2Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar2::W`](W) writer structure"]
impl crate::Writable for Cpar2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR2 to value 0"]
impl crate::Resettable for Cpar2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar2`]
module"]
#[doc(alias = "CM0AR2")]
pub type Cm0ar2 = crate::Reg<cm0ar2::Cm0ar2Spec>;
#[doc = ""]
pub mod cm0ar2 {
#[doc = "Register `CM0AR2` reader"]
pub type R = crate::R<Cm0ar2Spec>;
#[doc = "Register `CM0AR2` writer"]
pub type W = crate::W<Cm0ar2Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar2Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar2Spec;
impl crate::RegisterSpec for Cm0ar2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar2::R`](R) reader structure"]
impl crate::Readable for Cm0ar2Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar2::W`](W) writer structure"]
impl crate::Writable for Cm0ar2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR2 to value 0"]
impl crate::Resettable for Cm0ar2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr2`]
module"]
#[doc(alias = "CBSR2")]
pub type Cbsr2 = crate::Reg<cbsr2::Cbsr2Spec>;
#[doc = ""]
pub mod cbsr2 {
#[doc = "Register `CBSR2` reader"]
pub type R = crate::R<Cbsr2Spec>;
#[doc = "Register `CBSR2` writer"]
pub type W = crate::W<Cbsr2Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr2Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr2Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr2Spec;
impl crate::RegisterSpec for Cbsr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr2::R`](R) reader structure"]
impl crate::Readable for Cbsr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr2::W`](W) writer structure"]
impl crate::Writable for Cbsr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR2 to value 0"]
impl crate::Resettable for Cbsr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr3`]
module"]
#[doc(alias = "CCR3")]
pub type Ccr3 = crate::Reg<ccr3::Ccr3Spec>;
#[doc = ""]
pub mod ccr3 {
#[doc = "Register `CCR3` reader"]
pub type R = crate::R<Ccr3Spec>;
#[doc = "Register `CCR3` writer"]
pub type W = crate::W<Ccr3Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr3Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr3Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr3Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr3Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr3Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr3Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr3Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr3Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr3Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr3Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr3Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr3Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr3Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr3Spec;
impl crate::RegisterSpec for Ccr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr3::R`](R) reader structure"]
impl crate::Readable for Ccr3Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr3::W`](W) writer structure"]
impl crate::Writable for Ccr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR3 to value 0"]
impl crate::Resettable for Ccr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr3`]
module"]
#[doc(alias = "CNDTR3")]
pub type Cndtr3 = crate::Reg<cndtr3::Cndtr3Spec>;
#[doc = ""]
pub mod cndtr3 {
#[doc = "Register `CNDTR3` reader"]
pub type R = crate::R<Cndtr3Spec>;
#[doc = "Register `CNDTR3` writer"]
pub type W = crate::W<Cndtr3Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr3Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr3Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr3Spec;
impl crate::RegisterSpec for Cndtr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr3::R`](R) reader structure"]
impl crate::Readable for Cndtr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr3::W`](W) writer structure"]
impl crate::Writable for Cndtr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR3 to value 0"]
impl crate::Resettable for Cndtr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar3`]
module"]
#[doc(alias = "CPAR3")]
pub type Cpar3 = crate::Reg<cpar3::Cpar3Spec>;
#[doc = ""]
pub mod cpar3 {
#[doc = "Register `CPAR3` reader"]
pub type R = crate::R<Cpar3Spec>;
#[doc = "Register `CPAR3` writer"]
pub type W = crate::W<Cpar3Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar3Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar3Spec;
impl crate::RegisterSpec for Cpar3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar3::R`](R) reader structure"]
impl crate::Readable for Cpar3Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar3::W`](W) writer structure"]
impl crate::Writable for Cpar3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR3 to value 0"]
impl crate::Resettable for Cpar3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar3`]
module"]
#[doc(alias = "CM0AR3")]
pub type Cm0ar3 = crate::Reg<cm0ar3::Cm0ar3Spec>;
#[doc = ""]
pub mod cm0ar3 {
#[doc = "Register `CM0AR3` reader"]
pub type R = crate::R<Cm0ar3Spec>;
#[doc = "Register `CM0AR3` writer"]
pub type W = crate::W<Cm0ar3Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar3Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar3Spec;
impl crate::RegisterSpec for Cm0ar3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar3::R`](R) reader structure"]
impl crate::Readable for Cm0ar3Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar3::W`](W) writer structure"]
impl crate::Writable for Cm0ar3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR3 to value 0"]
impl crate::Resettable for Cm0ar3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr3`]
module"]
#[doc(alias = "CBSR3")]
pub type Cbsr3 = crate::Reg<cbsr3::Cbsr3Spec>;
#[doc = ""]
pub mod cbsr3 {
#[doc = "Register `CBSR3` reader"]
pub type R = crate::R<Cbsr3Spec>;
#[doc = "Register `CBSR3` writer"]
pub type W = crate::W<Cbsr3Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr3Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr3Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr3Spec;
impl crate::RegisterSpec for Cbsr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr3::R`](R) reader structure"]
impl crate::Readable for Cbsr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr3::W`](W) writer structure"]
impl crate::Writable for Cbsr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR3 to value 0"]
impl crate::Resettable for Cbsr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr4`]
module"]
#[doc(alias = "CCR4")]
pub type Ccr4 = crate::Reg<ccr4::Ccr4Spec>;
#[doc = ""]
pub mod ccr4 {
#[doc = "Register `CCR4` reader"]
pub type R = crate::R<Ccr4Spec>;
#[doc = "Register `CCR4` writer"]
pub type W = crate::W<Ccr4Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr4Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr4Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr4Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr4Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr4Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr4Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr4Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr4Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr4Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr4Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr4Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr4Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr4Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr4Spec;
impl crate::RegisterSpec for Ccr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr4::R`](R) reader structure"]
impl crate::Readable for Ccr4Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr4::W`](W) writer structure"]
impl crate::Writable for Ccr4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR4 to value 0"]
impl crate::Resettable for Ccr4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr4`]
module"]
#[doc(alias = "CNDTR4")]
pub type Cndtr4 = crate::Reg<cndtr4::Cndtr4Spec>;
#[doc = ""]
pub mod cndtr4 {
#[doc = "Register `CNDTR4` reader"]
pub type R = crate::R<Cndtr4Spec>;
#[doc = "Register `CNDTR4` writer"]
pub type W = crate::W<Cndtr4Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr4Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr4Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr4Spec;
impl crate::RegisterSpec for Cndtr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr4::R`](R) reader structure"]
impl crate::Readable for Cndtr4Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr4::W`](W) writer structure"]
impl crate::Writable for Cndtr4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR4 to value 0"]
impl crate::Resettable for Cndtr4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar4`]
module"]
#[doc(alias = "CPAR4")]
pub type Cpar4 = crate::Reg<cpar4::Cpar4Spec>;
#[doc = ""]
pub mod cpar4 {
#[doc = "Register `CPAR4` reader"]
pub type R = crate::R<Cpar4Spec>;
#[doc = "Register `CPAR4` writer"]
pub type W = crate::W<Cpar4Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar4Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar4Spec;
impl crate::RegisterSpec for Cpar4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar4::R`](R) reader structure"]
impl crate::Readable for Cpar4Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar4::W`](W) writer structure"]
impl crate::Writable for Cpar4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR4 to value 0"]
impl crate::Resettable for Cpar4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar4`]
module"]
#[doc(alias = "CM0AR4")]
pub type Cm0ar4 = crate::Reg<cm0ar4::Cm0ar4Spec>;
#[doc = ""]
pub mod cm0ar4 {
#[doc = "Register `CM0AR4` reader"]
pub type R = crate::R<Cm0ar4Spec>;
#[doc = "Register `CM0AR4` writer"]
pub type W = crate::W<Cm0ar4Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar4Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar4Spec;
impl crate::RegisterSpec for Cm0ar4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar4::R`](R) reader structure"]
impl crate::Readable for Cm0ar4Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar4::W`](W) writer structure"]
impl crate::Writable for Cm0ar4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR4 to value 0"]
impl crate::Resettable for Cm0ar4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr4`]
module"]
#[doc(alias = "CBSR4")]
pub type Cbsr4 = crate::Reg<cbsr4::Cbsr4Spec>;
#[doc = ""]
pub mod cbsr4 {
#[doc = "Register `CBSR4` reader"]
pub type R = crate::R<Cbsr4Spec>;
#[doc = "Register `CBSR4` writer"]
pub type W = crate::W<Cbsr4Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr4Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr4Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr4Spec;
impl crate::RegisterSpec for Cbsr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr4::R`](R) reader structure"]
impl crate::Readable for Cbsr4Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr4::W`](W) writer structure"]
impl crate::Writable for Cbsr4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR4 to value 0"]
impl crate::Resettable for Cbsr4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr5`]
module"]
#[doc(alias = "CCR5")]
pub type Ccr5 = crate::Reg<ccr5::Ccr5Spec>;
#[doc = ""]
pub mod ccr5 {
#[doc = "Register `CCR5` reader"]
pub type R = crate::R<Ccr5Spec>;
#[doc = "Register `CCR5` writer"]
pub type W = crate::W<Ccr5Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr5Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr5Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr5Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr5Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr5Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr5Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr5Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr5Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr5Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr5Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr5Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr5Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr5Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr5Spec;
impl crate::RegisterSpec for Ccr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr5::R`](R) reader structure"]
impl crate::Readable for Ccr5Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr5::W`](W) writer structure"]
impl crate::Writable for Ccr5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR5 to value 0"]
impl crate::Resettable for Ccr5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr5`]
module"]
#[doc(alias = "CNDTR5")]
pub type Cndtr5 = crate::Reg<cndtr5::Cndtr5Spec>;
#[doc = ""]
pub mod cndtr5 {
#[doc = "Register `CNDTR5` reader"]
pub type R = crate::R<Cndtr5Spec>;
#[doc = "Register `CNDTR5` writer"]
pub type W = crate::W<Cndtr5Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr5Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr5Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr5Spec;
impl crate::RegisterSpec for Cndtr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr5::R`](R) reader structure"]
impl crate::Readable for Cndtr5Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr5::W`](W) writer structure"]
impl crate::Writable for Cndtr5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR5 to value 0"]
impl crate::Resettable for Cndtr5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar5`]
module"]
#[doc(alias = "CPAR5")]
pub type Cpar5 = crate::Reg<cpar5::Cpar5Spec>;
#[doc = ""]
pub mod cpar5 {
#[doc = "Register `CPAR5` reader"]
pub type R = crate::R<Cpar5Spec>;
#[doc = "Register `CPAR5` writer"]
pub type W = crate::W<Cpar5Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar5Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar5Spec;
impl crate::RegisterSpec for Cpar5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar5::R`](R) reader structure"]
impl crate::Readable for Cpar5Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar5::W`](W) writer structure"]
impl crate::Writable for Cpar5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR5 to value 0"]
impl crate::Resettable for Cpar5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar5`]
module"]
#[doc(alias = "CM0AR5")]
pub type Cm0ar5 = crate::Reg<cm0ar5::Cm0ar5Spec>;
#[doc = ""]
pub mod cm0ar5 {
#[doc = "Register `CM0AR5` reader"]
pub type R = crate::R<Cm0ar5Spec>;
#[doc = "Register `CM0AR5` writer"]
pub type W = crate::W<Cm0ar5Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar5Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar5Spec;
impl crate::RegisterSpec for Cm0ar5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar5::R`](R) reader structure"]
impl crate::Readable for Cm0ar5Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar5::W`](W) writer structure"]
impl crate::Writable for Cm0ar5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR5 to value 0"]
impl crate::Resettable for Cm0ar5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr5`]
module"]
#[doc(alias = "CBSR5")]
pub type Cbsr5 = crate::Reg<cbsr5::Cbsr5Spec>;
#[doc = ""]
pub mod cbsr5 {
#[doc = "Register `CBSR5` reader"]
pub type R = crate::R<Cbsr5Spec>;
#[doc = "Register `CBSR5` writer"]
pub type W = crate::W<Cbsr5Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr5Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr5Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr5Spec;
impl crate::RegisterSpec for Cbsr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr5::R`](R) reader structure"]
impl crate::Readable for Cbsr5Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr5::W`](W) writer structure"]
impl crate::Writable for Cbsr5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR5 to value 0"]
impl crate::Resettable for Cbsr5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr6`]
module"]
#[doc(alias = "CCR6")]
pub type Ccr6 = crate::Reg<ccr6::Ccr6Spec>;
#[doc = ""]
pub mod ccr6 {
#[doc = "Register `CCR6` reader"]
pub type R = crate::R<Ccr6Spec>;
#[doc = "Register `CCR6` writer"]
pub type W = crate::W<Ccr6Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr6Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr6Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr6Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr6Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr6Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr6Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr6Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr6Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr6Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr6Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr6Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr6Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr6Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr6Spec;
impl crate::RegisterSpec for Ccr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr6::R`](R) reader structure"]
impl crate::Readable for Ccr6Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr6::W`](W) writer structure"]
impl crate::Writable for Ccr6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR6 to value 0"]
impl crate::Resettable for Ccr6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr6`]
module"]
#[doc(alias = "CNDTR6")]
pub type Cndtr6 = crate::Reg<cndtr6::Cndtr6Spec>;
#[doc = ""]
pub mod cndtr6 {
#[doc = "Register `CNDTR6` reader"]
pub type R = crate::R<Cndtr6Spec>;
#[doc = "Register `CNDTR6` writer"]
pub type W = crate::W<Cndtr6Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr6Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr6Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr6Spec;
impl crate::RegisterSpec for Cndtr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr6::R`](R) reader structure"]
impl crate::Readable for Cndtr6Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr6::W`](W) writer structure"]
impl crate::Writable for Cndtr6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR6 to value 0"]
impl crate::Resettable for Cndtr6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar6`]
module"]
#[doc(alias = "CPAR6")]
pub type Cpar6 = crate::Reg<cpar6::Cpar6Spec>;
#[doc = ""]
pub mod cpar6 {
#[doc = "Register `CPAR6` reader"]
pub type R = crate::R<Cpar6Spec>;
#[doc = "Register `CPAR6` writer"]
pub type W = crate::W<Cpar6Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar6Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar6Spec;
impl crate::RegisterSpec for Cpar6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar6::R`](R) reader structure"]
impl crate::Readable for Cpar6Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar6::W`](W) writer structure"]
impl crate::Writable for Cpar6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR6 to value 0"]
impl crate::Resettable for Cpar6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar6`]
module"]
#[doc(alias = "CM0AR6")]
pub type Cm0ar6 = crate::Reg<cm0ar6::Cm0ar6Spec>;
#[doc = ""]
pub mod cm0ar6 {
#[doc = "Register `CM0AR6` reader"]
pub type R = crate::R<Cm0ar6Spec>;
#[doc = "Register `CM0AR6` writer"]
pub type W = crate::W<Cm0ar6Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar6Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar6Spec;
impl crate::RegisterSpec for Cm0ar6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar6::R`](R) reader structure"]
impl crate::Readable for Cm0ar6Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar6::W`](W) writer structure"]
impl crate::Writable for Cm0ar6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR6 to value 0"]
impl crate::Resettable for Cm0ar6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr6`]
module"]
#[doc(alias = "CBSR6")]
pub type Cbsr6 = crate::Reg<cbsr6::Cbsr6Spec>;
#[doc = ""]
pub mod cbsr6 {
#[doc = "Register `CBSR6` reader"]
pub type R = crate::R<Cbsr6Spec>;
#[doc = "Register `CBSR6` writer"]
pub type W = crate::W<Cbsr6Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr6Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr6Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr6Spec;
impl crate::RegisterSpec for Cbsr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr6::R`](R) reader structure"]
impl crate::Readable for Cbsr6Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr6::W`](W) writer structure"]
impl crate::Writable for Cbsr6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR6 to value 0"]
impl crate::Resettable for Cbsr6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr7`]
module"]
#[doc(alias = "CCR7")]
pub type Ccr7 = crate::Reg<ccr7::Ccr7Spec>;
#[doc = ""]
pub mod ccr7 {
#[doc = "Register `CCR7` reader"]
pub type R = crate::R<Ccr7Spec>;
#[doc = "Register `CCR7` writer"]
pub type W = crate::W<Ccr7Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr7Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr7Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr7Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr7Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr7Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr7Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr7Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr7Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr7Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr7Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr7Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr7Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr7Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr7Spec;
impl crate::RegisterSpec for Ccr7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr7::R`](R) reader structure"]
impl crate::Readable for Ccr7Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr7::W`](W) writer structure"]
impl crate::Writable for Ccr7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR7 to value 0"]
impl crate::Resettable for Ccr7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr7`]
module"]
#[doc(alias = "CNDTR7")]
pub type Cndtr7 = crate::Reg<cndtr7::Cndtr7Spec>;
#[doc = ""]
pub mod cndtr7 {
#[doc = "Register `CNDTR7` reader"]
pub type R = crate::R<Cndtr7Spec>;
#[doc = "Register `CNDTR7` writer"]
pub type W = crate::W<Cndtr7Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr7Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr7Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr7Spec;
impl crate::RegisterSpec for Cndtr7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr7::R`](R) reader structure"]
impl crate::Readable for Cndtr7Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr7::W`](W) writer structure"]
impl crate::Writable for Cndtr7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR7 to value 0"]
impl crate::Resettable for Cndtr7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar7`]
module"]
#[doc(alias = "CPAR7")]
pub type Cpar7 = crate::Reg<cpar7::Cpar7Spec>;
#[doc = ""]
pub mod cpar7 {
#[doc = "Register `CPAR7` reader"]
pub type R = crate::R<Cpar7Spec>;
#[doc = "Register `CPAR7` writer"]
pub type W = crate::W<Cpar7Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar7Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar7Spec;
impl crate::RegisterSpec for Cpar7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar7::R`](R) reader structure"]
impl crate::Readable for Cpar7Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar7::W`](W) writer structure"]
impl crate::Writable for Cpar7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR7 to value 0"]
impl crate::Resettable for Cpar7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar7`]
module"]
#[doc(alias = "CM0AR7")]
pub type Cm0ar7 = crate::Reg<cm0ar7::Cm0ar7Spec>;
#[doc = ""]
pub mod cm0ar7 {
#[doc = "Register `CM0AR7` reader"]
pub type R = crate::R<Cm0ar7Spec>;
#[doc = "Register `CM0AR7` writer"]
pub type W = crate::W<Cm0ar7Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar7Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar7Spec;
impl crate::RegisterSpec for Cm0ar7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar7::R`](R) reader structure"]
impl crate::Readable for Cm0ar7Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar7::W`](W) writer structure"]
impl crate::Writable for Cm0ar7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR7 to value 0"]
impl crate::Resettable for Cm0ar7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr7`]
module"]
#[doc(alias = "CBSR7")]
pub type Cbsr7 = crate::Reg<cbsr7::Cbsr7Spec>;
#[doc = ""]
pub mod cbsr7 {
#[doc = "Register `CBSR7` reader"]
pub type R = crate::R<Cbsr7Spec>;
#[doc = "Register `CBSR7` writer"]
pub type W = crate::W<Cbsr7Spec>;
#[doc = "Field `BS` reader - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr7Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr7Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr7Spec;
impl crate::RegisterSpec for Cbsr7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr7::R`](R) reader structure"]
impl crate::Readable for Cbsr7Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr7::W`](W) writer structure"]
impl crate::Writable for Cbsr7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR7 to value 0"]
impl crate::Resettable for Cbsr7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr8`]
module"]
#[doc(alias = "CCR8")]
pub type Ccr8 = crate::Reg<ccr8::Ccr8Spec>;
#[doc = ""]
pub mod ccr8 {
#[doc = "Register `CCR8` reader"]
pub type R = crate::R<Ccr8Spec>;
#[doc = "Register `CCR8` writer"]
pub type W = crate::W<Ccr8Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr8Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr8Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr8Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr8Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr8Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr8Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr8Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr8Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr8Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr8Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr8Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr8Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr8Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr8Spec;
impl crate::RegisterSpec for Ccr8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr8::R`](R) reader structure"]
impl crate::Readable for Ccr8Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr8::W`](W) writer structure"]
impl crate::Writable for Ccr8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR8 to value 0"]
impl crate::Resettable for Ccr8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr8`]
module"]
#[doc(alias = "CNDTR8")]
pub type Cndtr8 = crate::Reg<cndtr8::Cndtr8Spec>;
#[doc = ""]
pub mod cndtr8 {
#[doc = "Register `CNDTR8` reader"]
pub type R = crate::R<Cndtr8Spec>;
#[doc = "Register `CNDTR8` writer"]
pub type W = crate::W<Cndtr8Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr8Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr8Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr8Spec;
impl crate::RegisterSpec for Cndtr8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr8::R`](R) reader structure"]
impl crate::Readable for Cndtr8Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr8::W`](W) writer structure"]
impl crate::Writable for Cndtr8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR8 to value 0"]
impl crate::Resettable for Cndtr8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar8`]
module"]
#[doc(alias = "CPAR8")]
pub type Cpar8 = crate::Reg<cpar8::Cpar8Spec>;
#[doc = ""]
pub mod cpar8 {
#[doc = "Register `CPAR8` reader"]
pub type R = crate::R<Cpar8Spec>;
#[doc = "Register `CPAR8` writer"]
pub type W = crate::W<Cpar8Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar8Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar8Spec;
impl crate::RegisterSpec for Cpar8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar8::R`](R) reader structure"]
impl crate::Readable for Cpar8Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar8::W`](W) writer structure"]
impl crate::Writable for Cpar8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR8 to value 0"]
impl crate::Resettable for Cpar8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar8`]
module"]
#[doc(alias = "CM0AR8")]
pub type Cm0ar8 = crate::Reg<cm0ar8::Cm0ar8Spec>;
#[doc = ""]
pub mod cm0ar8 {
#[doc = "Register `CM0AR8` reader"]
pub type R = crate::R<Cm0ar8Spec>;
#[doc = "Register `CM0AR8` writer"]
pub type W = crate::W<Cm0ar8Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar8Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar8Spec;
impl crate::RegisterSpec for Cm0ar8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar8::R`](R) reader structure"]
impl crate::Readable for Cm0ar8Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar8::W`](W) writer structure"]
impl crate::Writable for Cm0ar8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR8 to value 0"]
impl crate::Resettable for Cm0ar8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr8`]
module"]
#[doc(alias = "CBSR8")]
pub type Cbsr8 = crate::Reg<cbsr8::Cbsr8Spec>;
#[doc = ""]
pub mod cbsr8 {
#[doc = "Register `CBSR8` reader"]
pub type R = crate::R<Cbsr8Spec>;
#[doc = "Register `CBSR8` writer"]
pub type W = crate::W<Cbsr8Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr8Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr8Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr8Spec;
impl crate::RegisterSpec for Cbsr8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr8::R`](R) reader structure"]
impl crate::Readable for Cbsr8Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr8::W`](W) writer structure"]
impl crate::Writable for Cbsr8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR8 to value 0"]
impl crate::Resettable for Cbsr8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CSELR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cselr1`]
module"]
#[doc(alias = "CSELR1")]
pub type Cselr1 = crate::Reg<cselr1::Cselr1Spec>;
#[doc = ""]
pub mod cselr1 {
#[doc = "Register `CSELR1` reader"]
pub type R = crate::R<Cselr1Spec>;
#[doc = "Register `CSELR1` writer"]
pub type W = crate::W<Cselr1Spec>;
#[doc = "Field `C1S` reader - DMA channel 1 selection"]
pub type C1sR = crate::FieldReader;
#[doc = "Field `C1S` writer - DMA channel 1 selection"]
pub type C1sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C2S` reader - DMA channel 2 selection"]
pub type C2sR = crate::FieldReader;
#[doc = "Field `C2S` writer - DMA channel 2 selection"]
pub type C2sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C3S` reader - DMA channel 3 selection"]
pub type C3sR = crate::FieldReader;
#[doc = "Field `C3S` writer - DMA channel 3 selection"]
pub type C3sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C4S` reader - DMA channel 4 selection"]
pub type C4sR = crate::FieldReader;
#[doc = "Field `C4S` writer - DMA channel 4 selection"]
pub type C4sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5 - DMA channel 1 selection"]
#[inline(always)]
pub fn c1s(&self) -> C1sR {
C1sR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13 - DMA channel 2 selection"]
#[inline(always)]
pub fn c2s(&self) -> C2sR {
C2sR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21 - DMA channel 3 selection"]
#[inline(always)]
pub fn c3s(&self) -> C3sR {
C3sR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29 - DMA channel 4 selection"]
#[inline(always)]
pub fn c4s(&self) -> C4sR {
C4sR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - DMA channel 1 selection"]
#[inline(always)]
#[must_use]
pub fn c1s(&mut self) -> C1sW<Cselr1Spec> {
C1sW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cselr1Spec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13 - DMA channel 2 selection"]
#[inline(always)]
#[must_use]
pub fn c2s(&mut self) -> C2sW<Cselr1Spec> {
C2sW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cselr1Spec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21 - DMA channel 3 selection"]
#[inline(always)]
#[must_use]
pub fn c3s(&mut self) -> C3sW<Cselr1Spec> {
C3sW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cselr1Spec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29 - DMA channel 4 selection"]
#[inline(always)]
#[must_use]
pub fn c4s(&mut self) -> C4sW<Cselr1Spec> {
C4sW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cselr1Spec> {
RsvdW::new(self, 30)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cselr1Spec;
impl crate::RegisterSpec for Cselr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cselr1::R`](R) reader structure"]
impl crate::Readable for Cselr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cselr1::W`](W) writer structure"]
impl crate::Writable for Cselr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CSELR1 to value 0"]
impl crate::Resettable for Cselr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CSELR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cselr2`]
module"]
#[doc(alias = "CSELR2")]
pub type Cselr2 = crate::Reg<cselr2::Cselr2Spec>;
#[doc = ""]
pub mod cselr2 {
#[doc = "Register `CSELR2` reader"]
pub type R = crate::R<Cselr2Spec>;
#[doc = "Register `CSELR2` writer"]
pub type W = crate::W<Cselr2Spec>;
#[doc = "Field `C5S` reader - DMA channel 5 selection"]
pub type C5sR = crate::FieldReader;
#[doc = "Field `C5S` writer - DMA channel 5 selection"]
pub type C5sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C6S` reader - DMA channel 6 selection"]
pub type C6sR = crate::FieldReader;
#[doc = "Field `C6S` writer - DMA channel 6 selection"]
pub type C6sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C7S` reader - DMA channel 7 selection"]
pub type C7sR = crate::FieldReader;
#[doc = "Field `C7S` writer - DMA channel 7 selection"]
pub type C7sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C8S` reader - DMA channel 8 selection"]
pub type C8sR = crate::FieldReader;
#[doc = "Field `C8S` writer - DMA channel 8 selection"]
pub type C8sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5 - DMA channel 5 selection"]
#[inline(always)]
pub fn c5s(&self) -> C5sR {
C5sR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13 - DMA channel 6 selection"]
#[inline(always)]
pub fn c6s(&self) -> C6sR {
C6sR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21 - DMA channel 7 selection"]
#[inline(always)]
pub fn c7s(&self) -> C7sR {
C7sR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29 - DMA channel 8 selection"]
#[inline(always)]
pub fn c8s(&self) -> C8sR {
C8sR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - DMA channel 5 selection"]
#[inline(always)]
#[must_use]
pub fn c5s(&mut self) -> C5sW<Cselr2Spec> {
C5sW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cselr2Spec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13 - DMA channel 6 selection"]
#[inline(always)]
#[must_use]
pub fn c6s(&mut self) -> C6sW<Cselr2Spec> {
C6sW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cselr2Spec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21 - DMA channel 7 selection"]
#[inline(always)]
#[must_use]
pub fn c7s(&mut self) -> C7sW<Cselr2Spec> {
C7sW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cselr2Spec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29 - DMA channel 8 selection"]
#[inline(always)]
#[must_use]
pub fn c8s(&mut self) -> C8sW<Cselr2Spec> {
C8sW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cselr2Spec> {
RsvdW::new(self, 30)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cselr2Spec;
impl crate::RegisterSpec for Cselr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cselr2::R`](R) reader structure"]
impl crate::Readable for Cselr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cselr2::W`](W) writer structure"]
impl crate::Writable for Cselr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CSELR2 to value 0"]
impl crate::Resettable for Cselr2Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "USART1"]
pub struct Usart1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Usart1 {}
impl Usart1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const usart1::RegisterBlock = 0x5008_4000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const usart1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Usart1 {
type Target = usart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Usart1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart1").finish()
}
}
#[doc = "USART1"]
pub mod usart1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
cr3: Cr3,
brr: Brr,
gtpr: Gtpr,
rtor: Rtor,
rqr: Rqr,
isr: Isr,
icr: Icr,
rdr: Rdr,
tdr: Tdr,
miscr: Miscr,
drdr: Drdr,
dtdr: Dtdr,
exr: Exr,
}
impl RegisterBlock {
#[doc = "0x00 - Control Register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - Control Register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - Control Register 3"]
#[inline(always)]
pub const fn cr3(&self) -> &Cr3 {
&self.cr3
}
#[doc = "0x0c - Baud Rate Register"]
#[inline(always)]
pub const fn brr(&self) -> &Brr {
&self.brr
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn gtpr(&self) -> &Gtpr {
&self.gtpr
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn rtor(&self) -> &Rtor {
&self.rtor
}
#[doc = "0x18 - Request Register"]
#[inline(always)]
pub const fn rqr(&self) -> &Rqr {
&self.rqr
}
#[doc = "0x1c - Interrupt and Status Register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x20 - Interrupt flag Clear Register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x24 - Receive Data Register"]
#[inline(always)]
pub const fn rdr(&self) -> &Rdr {
&self.rdr
}
#[doc = "0x28 - Transmit Data Register"]
#[inline(always)]
pub const fn tdr(&self) -> &Tdr {
&self.tdr
}
#[doc = "0x2c - Miscellaneous Register"]
#[inline(always)]
pub const fn miscr(&self) -> &Miscr {
&self.miscr
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn drdr(&self) -> &Drdr {
&self.drdr
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn dtdr(&self) -> &Dtdr {
&self.dtdr
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn exr(&self) -> &Exr {
&self.exr
}
}
#[doc = "CR1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `UE` reader - "]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - "]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RE` reader - "]
pub type ReR = crate::BitReader;
#[doc = "Field `RE` writer - "]
pub type ReW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - "]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - "]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLEIE` reader - "]
pub type IdleieR = crate::BitReader;
#[doc = "Field `IDLEIE` writer - "]
pub type IdleieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNEIE` reader - "]
pub type RxneieR = crate::BitReader;
#[doc = "Field `RXNEIE` writer - "]
pub type RxneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - "]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - "]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXEIE` reader - "]
pub type TxeieR = crate::BitReader;
#[doc = "Field `TXEIE` writer - "]
pub type TxeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PEIE` reader - "]
pub type PeieR = crate::BitReader;
#[doc = "Field `PEIE` writer - "]
pub type PeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCE` reader - "]
pub type PceR = crate::BitReader;
#[doc = "Field `PCE` writer - "]
pub type PceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `OVER8` reader - "]
pub type Over8R = crate::BitReader;
#[doc = "Field `OVER8` writer - "]
pub type Over8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `M` reader - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MR = crate::FieldReader;
#[doc = "Field `M` writer - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn re(&self) -> ReR {
ReR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idleie(&self) -> IdleieR {
IdleieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxneie(&self) -> RxneieR {
RxneieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txeie(&self) -> TxeieR {
TxeieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn peie(&self) -> PeieR {
PeieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn pce(&self) -> PceR {
PceR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:13"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn over8(&self) -> Over8R {
Over8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:26"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 0x0fff) as u16)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
pub fn m(&self) -> MR {
MR::new(((self.bits >> 27) & 3) as u8)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<Cr1Spec> {
UeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cr1Spec> {
Rsvd4W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn re(&mut self) -> ReW<Cr1Spec> {
ReW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<Cr1Spec> {
TeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idleie(&mut self) -> IdleieW<Cr1Spec> {
IdleieW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxneie(&mut self) -> RxneieW<Cr1Spec> {
RxneieW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Cr1Spec> {
TcieW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txeie(&mut self) -> TxeieW<Cr1Spec> {
TxeieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn peie(&mut self) -> PeieW<Cr1Spec> {
PeieW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Cr1Spec> {
PsW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn pce(&mut self) -> PceW<Cr1Spec> {
PceW::new(self, 10)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cr1Spec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn over8(&mut self) -> Over8W<Cr1Spec> {
Over8W::new(self, 14)
}
#[doc = "Bits 15:26"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
#[must_use]
pub fn m(&mut self) -> MW<Cr1Spec> {
MW::new(self, 27)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 29)
}
}
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `STOP` reader - "]
pub type StopR = crate::FieldReader;
#[doc = "Field `STOP` writer - "]
pub type StopW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<Cr2Spec> {
StopW::new(self, 12)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 14)
}
}
#[doc = "Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR3 (rw) register accessor: Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr3`]
module"]
#[doc(alias = "CR3")]
pub type Cr3 = crate::Reg<cr3::Cr3Spec>;
#[doc = "Control Register 3"]
pub mod cr3 {
#[doc = "Register `CR3` reader"]
pub type R = crate::R<Cr3Spec>;
#[doc = "Register `CR3` writer"]
pub type W = crate::W<Cr3Spec>;
#[doc = "Field `EIE` reader - "]
pub type EieR = crate::BitReader;
#[doc = "Field `EIE` writer - "]
pub type EieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMAR` reader - "]
pub type DmarR = crate::BitReader;
#[doc = "Field `DMAR` writer - "]
pub type DmarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAT` reader - "]
pub type DmatR = crate::BitReader;
#[doc = "Field `DMAT` writer - "]
pub type DmatW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTSE` reader - "]
pub type RtseR = crate::BitReader;
#[doc = "Field `RTSE` writer - "]
pub type RtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSE` reader - "]
pub type CtseR = crate::BitReader;
#[doc = "Field `CTSE` writer - "]
pub type CtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIE` reader - "]
pub type CtsieR = crate::BitReader;
#[doc = "Field `CTSIE` writer - "]
pub type CtsieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ONEBIT` reader - "]
pub type OnebitR = crate::BitReader;
#[doc = "Field `ONEBIT` writer - "]
pub type OnebitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVRDIS` reader - "]
pub type OvrdisR = crate::BitReader;
#[doc = "Field `OVRDIS` writer - "]
pub type OvrdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn eie(&self) -> EieR {
EieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x1f) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn dmar(&self) -> DmarR {
DmarR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dmat(&self) -> DmatR {
DmatR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rtse(&self) -> RtseR {
RtseR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctse(&self) -> CtseR {
CtseR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ctsie(&self) -> CtsieR {
CtsieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn onebit(&self) -> OnebitR {
OnebitR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn ovrdis(&self) -> OvrdisR {
OvrdisR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn eie(&mut self) -> EieW<Cr3Spec> {
EieW::new(self, 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr3Spec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn dmar(&mut self) -> DmarW<Cr3Spec> {
DmarW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dmat(&mut self) -> DmatW<Cr3Spec> {
DmatW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rtse(&mut self) -> RtseW<Cr3Spec> {
RtseW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctse(&mut self) -> CtseW<Cr3Spec> {
CtseW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ctsie(&mut self) -> CtsieW<Cr3Spec> {
CtsieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn onebit(&mut self) -> OnebitW<Cr3Spec> {
OnebitW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn ovrdis(&mut self) -> OvrdisW<Cr3Spec> {
OvrdisW::new(self, 12)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr3Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr3Spec;
impl crate::RegisterSpec for Cr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr3::R`](R) reader structure"]
impl crate::Readable for Cr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cr3::W`](W) writer structure"]
impl crate::Writable for Cr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR3 to value 0"]
impl crate::Resettable for Cr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BRR (rw) register accessor: Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@brr`]
module"]
#[doc(alias = "BRR")]
pub type Brr = crate::Reg<brr::BrrSpec>;
#[doc = "Baud Rate Register"]
pub mod brr {
#[doc = "Register `BRR` reader"]
pub type R = crate::R<BrrSpec>;
#[doc = "Register `BRR` writer"]
pub type W = crate::W<BrrSpec>;
#[doc = "Field `FRAC` reader - "]
pub type FracR = crate::FieldReader;
#[doc = "Field `FRAC` writer - "]
pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `INT` reader - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntR = crate::FieldReader<u16>;
#[doc = "Field `INT` writer - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn frac(&self) -> FracR {
FracR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
pub fn int(&self) -> IntR {
IntR::new(((self.bits >> 4) & 0x0fff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn frac(&mut self) -> FracW<BrrSpec> {
FracW::new(self, 0)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
#[must_use]
pub fn int(&mut self) -> IntW<BrrSpec> {
IntW::new(self, 4)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BrrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BrrSpec;
impl crate::RegisterSpec for BrrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`brr::R`](R) reader structure"]
impl crate::Readable for BrrSpec {}
#[doc = "`write(|w| ..)` method takes [`brr::W`](W) writer structure"]
impl crate::Writable for BrrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BRR to value 0"]
impl crate::Resettable for BrrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GTPR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gtpr`]
module"]
#[doc(alias = "GTPR")]
pub type Gtpr = crate::Reg<gtpr::GtprSpec>;
#[doc = ""]
pub mod gtpr {
#[doc = "Register `GTPR` reader"]
pub type R = crate::R<GtprSpec>;
#[doc = "Register `GTPR` writer"]
pub type W = crate::W<GtprSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<GtprSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GtprSpec;
impl crate::RegisterSpec for GtprSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gtpr::R`](R) reader structure"]
impl crate::Readable for GtprSpec {}
#[doc = "`write(|w| ..)` method takes [`gtpr::W`](W) writer structure"]
impl crate::Writable for GtprSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GTPR to value 0"]
impl crate::Resettable for GtprSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RTOR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtor`]
module"]
#[doc(alias = "RTOR")]
pub type Rtor = crate::Reg<rtor::RtorSpec>;
#[doc = ""]
pub mod rtor {
#[doc = "Register `RTOR` reader"]
pub type R = crate::R<RtorSpec>;
#[doc = "Register `RTOR` writer"]
pub type W = crate::W<RtorSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RtorSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtorSpec;
impl crate::RegisterSpec for RtorSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtor::R`](R) reader structure"]
impl crate::Readable for RtorSpec {}
#[doc = "`write(|w| ..)` method takes [`rtor::W`](W) writer structure"]
impl crate::Writable for RtorSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTOR to value 0"]
impl crate::Resettable for RtorSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RQR (rw) register accessor: Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rqr`]
module"]
#[doc(alias = "RQR")]
pub type Rqr = crate::Reg<rqr::RqrSpec>;
#[doc = "Request Register"]
pub mod rqr {
#[doc = "Register `RQR` reader"]
pub type R = crate::R<RqrSpec>;
#[doc = "Register `RQR` writer"]
pub type W = crate::W<RqrSpec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RXFRQ` reader - "]
pub type RxfrqR = crate::BitReader;
#[doc = "Field `RXFRQ` writer - "]
pub type RxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXFRQ` reader - "]
pub type TxfrqR = crate::BitReader;
#[doc = "Field `TXFRQ` writer - "]
pub type TxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxfrq(&self) -> RxfrqR {
RxfrqR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn txfrq(&self) -> TxfrqR {
TxfrqR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<RqrSpec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxfrq(&mut self) -> RxfrqW<RqrSpec> {
RxfrqW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn txfrq(&mut self) -> TxfrqW<RqrSpec> {
TxfrqW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RqrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RqrSpec;
impl crate::RegisterSpec for RqrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rqr::R`](R) reader structure"]
impl crate::Readable for RqrSpec {}
#[doc = "`write(|w| ..)` method takes [`rqr::W`](W) writer structure"]
impl crate::Writable for RqrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RQR to value 0"]
impl crate::Resettable for RqrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR (rw) register accessor: Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "Interrupt and Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - "]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - "]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NF` reader - "]
pub type NfR = crate::BitReader;
#[doc = "Field `NF` writer - "]
pub type NfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORE` reader - "]
pub type OreR = crate::BitReader;
#[doc = "Field `ORE` writer - "]
pub type OreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLE` reader - "]
pub type IdleR = crate::BitReader;
#[doc = "Field `IDLE` writer - "]
pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNE` reader - "]
pub type RxneR = crate::BitReader;
#[doc = "Field `RXNE` writer - "]
pub type RxneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TC` reader - "]
pub type TcR = crate::BitReader;
#[doc = "Field `TC` writer - "]
pub type TcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - "]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - "]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIF` reader - "]
pub type CtsifR = crate::BitReader;
#[doc = "Field `CTSIF` writer - "]
pub type CtsifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTS` reader - "]
pub type CtsR = crate::BitReader;
#[doc = "Field `CTS` writer - "]
pub type CtsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn nf(&self) -> NfR {
NfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ore(&self) -> OreR {
OreR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idle(&self) -> IdleR {
IdleR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxne(&self) -> RxneR {
RxneR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tc(&self) -> TcR {
TcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctsif(&self) -> CtsifR {
CtsifR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cts(&self) -> CtsR {
CtsR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<IsrSpec> {
PeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fe(&mut self) -> FeW<IsrSpec> {
FeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn nf(&mut self) -> NfW<IsrSpec> {
NfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ore(&mut self) -> OreW<IsrSpec> {
OreW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idle(&mut self) -> IdleW<IsrSpec> {
IdleW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxne(&mut self) -> RxneW<IsrSpec> {
RxneW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tc(&mut self) -> TcW<IsrSpec> {
TcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txe(&mut self) -> TxeW<IsrSpec> {
TxeW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctsif(&mut self) -> CtsifW<IsrSpec> {
CtsifW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cts(&mut self) -> CtsW<IsrSpec> {
CtsW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "Interrupt flag Clear Register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `PECF` reader - "]
pub type PecfR = crate::BitReader;
#[doc = "Field `PECF` writer - "]
pub type PecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FECF` reader - "]
pub type FecfR = crate::BitReader;
#[doc = "Field `FECF` writer - "]
pub type FecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NCF` reader - "]
pub type NcfR = crate::BitReader;
#[doc = "Field `NCF` writer - "]
pub type NcfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORECF` reader - "]
pub type OrecfR = crate::BitReader;
#[doc = "Field `ORECF` writer - "]
pub type OrecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLECF` reader - "]
pub type IdlecfR = crate::BitReader;
#[doc = "Field `IDLECF` writer - "]
pub type IdlecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCCF` reader - "]
pub type TccfR = crate::BitReader;
#[doc = "Field `TCCF` writer - "]
pub type TccfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTSCF` reader - "]
pub type CtscfR = crate::BitReader;
#[doc = "Field `CTSCF` writer - "]
pub type CtscfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pecf(&self) -> PecfR {
PecfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fecf(&self) -> FecfR {
FecfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ncf(&self) -> NcfR {
NcfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn orecf(&self) -> OrecfR {
OrecfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idlecf(&self) -> IdlecfR {
IdlecfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tccf(&self) -> TccfR {
TccfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 7) & 3) as u8)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctscf(&self) -> CtscfR {
CtscfR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pecf(&mut self) -> PecfW<IcrSpec> {
PecfW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fecf(&mut self) -> FecfW<IcrSpec> {
FecfW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ncf(&mut self) -> NcfW<IcrSpec> {
NcfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn orecf(&mut self) -> OrecfW<IcrSpec> {
OrecfW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idlecf(&mut self) -> IdlecfW<IcrSpec> {
IdlecfW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IcrSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tccf(&mut self) -> TccfW<IcrSpec> {
TccfW::new(self, 6)
}
#[doc = "Bits 7:8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 7)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctscf(&mut self) -> CtscfW<IcrSpec> {
CtscfW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RDR (rw) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdr`]
module"]
#[doc(alias = "RDR")]
pub type Rdr = crate::Reg<rdr::RdrSpec>;
#[doc = "Receive Data Register"]
pub mod rdr {
#[doc = "Register `RDR` reader"]
pub type R = crate::R<RdrSpec>;
#[doc = "Register `RDR` writer"]
pub type W = crate::W<RdrSpec>;
#[doc = "Field `RDR` reader - "]
pub type RdrR = crate::FieldReader<u16>;
#[doc = "Field `RDR` writer - "]
pub type RdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn rdr(&self) -> RdrR {
RdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn rdr(&mut self) -> RdrW<RdrSpec> {
RdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrSpec;
impl crate::RegisterSpec for RdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rdr::R`](R) reader structure"]
impl crate::Readable for RdrSpec {}
#[doc = "`write(|w| ..)` method takes [`rdr::W`](W) writer structure"]
impl crate::Writable for RdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RDR to value 0"]
impl crate::Resettable for RdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TDR (rw) register accessor: Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`]
module"]
#[doc(alias = "TDR")]
pub type Tdr = crate::Reg<tdr::TdrSpec>;
#[doc = "Transmit Data Register"]
pub mod tdr {
#[doc = "Register `TDR` reader"]
pub type R = crate::R<TdrSpec>;
#[doc = "Register `TDR` writer"]
pub type W = crate::W<TdrSpec>;
#[doc = "Field `TDR` reader - "]
pub type TdrR = crate::FieldReader<u16>;
#[doc = "Field `TDR` writer - "]
pub type TdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn tdr(&self) -> TdrR {
TdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn tdr(&mut self) -> TdrW<TdrSpec> {
TdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TdrSpec;
impl crate::RegisterSpec for TdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tdr::R`](R) reader structure"]
impl crate::Readable for TdrSpec {}
#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"]
impl crate::Writable for TdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TDR to value 0"]
impl crate::Resettable for TdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "MISCR (rw) register accessor: Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscr`]
module"]
#[doc(alias = "MISCR")]
pub type Miscr = crate::Reg<miscr::MiscrSpec>;
#[doc = "Miscellaneous Register"]
pub mod miscr {
#[doc = "Register `MISCR` reader"]
pub type R = crate::R<MiscrSpec>;
#[doc = "Register `MISCR` writer"]
pub type W = crate::W<MiscrSpec>;
#[doc = "Field `SMPLINI` reader - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniR = crate::FieldReader;
#[doc = "Field `SMPLINI` writer - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RTSBIT` reader - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitR = crate::FieldReader;
#[doc = "Field `RTSBIT` writer - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
#[doc = "Field `AUTOCAL` reader - "]
pub type AutocalR = crate::BitReader;
#[doc = "Field `AUTOCAL` writer - "]
pub type AutocalW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
pub fn smplini(&self) -> SmpliniR {
SmpliniR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
pub fn rtsbit(&self) -> RtsbitR {
RtsbitR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x007f_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn autocal(&self) -> AutocalR {
AutocalR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
#[must_use]
pub fn smplini(&mut self) -> SmpliniW<MiscrSpec> {
SmpliniW::new(self, 0)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
#[must_use]
pub fn rtsbit(&mut self) -> RtsbitW<MiscrSpec> {
RtsbitW::new(self, 4)
}
#[doc = "Bits 8:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<MiscrSpec> {
RsvdW::new(self, 8)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn autocal(&mut self) -> AutocalW<MiscrSpec> {
AutocalW::new(self, 31)
}
}
#[doc = "Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscrSpec;
impl crate::RegisterSpec for MiscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miscr::R`](R) reader structure"]
impl crate::Readable for MiscrSpec {}
#[doc = "`write(|w| ..)` method takes [`miscr::W`](W) writer structure"]
impl crate::Writable for MiscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISCR to value 0"]
impl crate::Resettable for MiscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DRDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@drdr`]
module"]
#[doc(alias = "DRDR")]
pub type Drdr = crate::Reg<drdr::DrdrSpec>;
#[doc = ""]
pub mod drdr {
#[doc = "Register `DRDR` reader"]
pub type R = crate::R<DrdrSpec>;
#[doc = "Register `DRDR` writer"]
pub type W = crate::W<DrdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DrdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrdrSpec;
impl crate::RegisterSpec for DrdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`drdr::R`](R) reader structure"]
impl crate::Readable for DrdrSpec {}
#[doc = "`write(|w| ..)` method takes [`drdr::W`](W) writer structure"]
impl crate::Writable for DrdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DRDR to value 0"]
impl crate::Resettable for DrdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtdr`]
module"]
#[doc(alias = "DTDR")]
pub type Dtdr = crate::Reg<dtdr::DtdrSpec>;
#[doc = ""]
pub mod dtdr {
#[doc = "Register `DTDR` reader"]
pub type R = crate::R<DtdrSpec>;
#[doc = "Register `DTDR` writer"]
pub type W = crate::W<DtdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DtdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DtdrSpec;
impl crate::RegisterSpec for DtdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtdr::R`](R) reader structure"]
impl crate::Readable for DtdrSpec {}
#[doc = "`write(|w| ..)` method takes [`dtdr::W`](W) writer structure"]
impl crate::Writable for DtdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTDR to value 0"]
impl crate::Resettable for DtdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EXR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exr`]
module"]
#[doc(alias = "EXR")]
pub type Exr = crate::Reg<exr::ExrSpec>;
#[doc = ""]
pub mod exr {
#[doc = "Register `EXR` reader"]
pub type R = crate::R<ExrSpec>;
#[doc = "Register `EXR` writer"]
pub type W = crate::W<ExrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ExrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExrSpec;
impl crate::RegisterSpec for ExrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`exr::R`](R) reader structure"]
impl crate::Readable for ExrSpec {}
#[doc = "`write(|w| ..)` method takes [`exr::W`](W) writer structure"]
impl crate::Writable for ExrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EXR to value 0"]
impl crate::Resettable for ExrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "USART2"]
pub struct Usart2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Usart2 {}
impl Usart2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const usart2::RegisterBlock = 0x5008_5000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const usart2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Usart2 {
type Target = usart2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Usart2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart2").finish()
}
}
#[doc = "USART2"]
pub mod usart2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
cr3: Cr3,
brr: Brr,
gtpr: Gtpr,
rtor: Rtor,
rqr: Rqr,
isr: Isr,
icr: Icr,
rdr: Rdr,
tdr: Tdr,
miscr: Miscr,
drdr: Drdr,
dtdr: Dtdr,
exr: Exr,
}
impl RegisterBlock {
#[doc = "0x00 - Control Register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - Control Register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - Control Register 3"]
#[inline(always)]
pub const fn cr3(&self) -> &Cr3 {
&self.cr3
}
#[doc = "0x0c - Baud Rate Register"]
#[inline(always)]
pub const fn brr(&self) -> &Brr {
&self.brr
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn gtpr(&self) -> &Gtpr {
&self.gtpr
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn rtor(&self) -> &Rtor {
&self.rtor
}
#[doc = "0x18 - Request Register"]
#[inline(always)]
pub const fn rqr(&self) -> &Rqr {
&self.rqr
}
#[doc = "0x1c - Interrupt and Status Register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x20 - Interrupt flag Clear Register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x24 - Receive Data Register"]
#[inline(always)]
pub const fn rdr(&self) -> &Rdr {
&self.rdr
}
#[doc = "0x28 - Transmit Data Register"]
#[inline(always)]
pub const fn tdr(&self) -> &Tdr {
&self.tdr
}
#[doc = "0x2c - Miscellaneous Register"]
#[inline(always)]
pub const fn miscr(&self) -> &Miscr {
&self.miscr
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn drdr(&self) -> &Drdr {
&self.drdr
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn dtdr(&self) -> &Dtdr {
&self.dtdr
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn exr(&self) -> &Exr {
&self.exr
}
}
#[doc = "CR1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `UE` reader - "]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - "]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RE` reader - "]
pub type ReR = crate::BitReader;
#[doc = "Field `RE` writer - "]
pub type ReW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - "]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - "]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLEIE` reader - "]
pub type IdleieR = crate::BitReader;
#[doc = "Field `IDLEIE` writer - "]
pub type IdleieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNEIE` reader - "]
pub type RxneieR = crate::BitReader;
#[doc = "Field `RXNEIE` writer - "]
pub type RxneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - "]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - "]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXEIE` reader - "]
pub type TxeieR = crate::BitReader;
#[doc = "Field `TXEIE` writer - "]
pub type TxeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PEIE` reader - "]
pub type PeieR = crate::BitReader;
#[doc = "Field `PEIE` writer - "]
pub type PeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCE` reader - "]
pub type PceR = crate::BitReader;
#[doc = "Field `PCE` writer - "]
pub type PceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `OVER8` reader - "]
pub type Over8R = crate::BitReader;
#[doc = "Field `OVER8` writer - "]
pub type Over8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `M` reader - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MR = crate::FieldReader;
#[doc = "Field `M` writer - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn re(&self) -> ReR {
ReR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idleie(&self) -> IdleieR {
IdleieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxneie(&self) -> RxneieR {
RxneieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txeie(&self) -> TxeieR {
TxeieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn peie(&self) -> PeieR {
PeieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn pce(&self) -> PceR {
PceR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:13"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn over8(&self) -> Over8R {
Over8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:26"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 0x0fff) as u16)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
pub fn m(&self) -> MR {
MR::new(((self.bits >> 27) & 3) as u8)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<Cr1Spec> {
UeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cr1Spec> {
Rsvd4W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn re(&mut self) -> ReW<Cr1Spec> {
ReW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<Cr1Spec> {
TeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idleie(&mut self) -> IdleieW<Cr1Spec> {
IdleieW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxneie(&mut self) -> RxneieW<Cr1Spec> {
RxneieW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Cr1Spec> {
TcieW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txeie(&mut self) -> TxeieW<Cr1Spec> {
TxeieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn peie(&mut self) -> PeieW<Cr1Spec> {
PeieW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Cr1Spec> {
PsW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn pce(&mut self) -> PceW<Cr1Spec> {
PceW::new(self, 10)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cr1Spec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn over8(&mut self) -> Over8W<Cr1Spec> {
Over8W::new(self, 14)
}
#[doc = "Bits 15:26"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
#[must_use]
pub fn m(&mut self) -> MW<Cr1Spec> {
MW::new(self, 27)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 29)
}
}
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `STOP` reader - "]
pub type StopR = crate::FieldReader;
#[doc = "Field `STOP` writer - "]
pub type StopW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<Cr2Spec> {
StopW::new(self, 12)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 14)
}
}
#[doc = "Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR3 (rw) register accessor: Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr3`]
module"]
#[doc(alias = "CR3")]
pub type Cr3 = crate::Reg<cr3::Cr3Spec>;
#[doc = "Control Register 3"]
pub mod cr3 {
#[doc = "Register `CR3` reader"]
pub type R = crate::R<Cr3Spec>;
#[doc = "Register `CR3` writer"]
pub type W = crate::W<Cr3Spec>;
#[doc = "Field `EIE` reader - "]
pub type EieR = crate::BitReader;
#[doc = "Field `EIE` writer - "]
pub type EieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMAR` reader - "]
pub type DmarR = crate::BitReader;
#[doc = "Field `DMAR` writer - "]
pub type DmarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAT` reader - "]
pub type DmatR = crate::BitReader;
#[doc = "Field `DMAT` writer - "]
pub type DmatW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTSE` reader - "]
pub type RtseR = crate::BitReader;
#[doc = "Field `RTSE` writer - "]
pub type RtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSE` reader - "]
pub type CtseR = crate::BitReader;
#[doc = "Field `CTSE` writer - "]
pub type CtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIE` reader - "]
pub type CtsieR = crate::BitReader;
#[doc = "Field `CTSIE` writer - "]
pub type CtsieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ONEBIT` reader - "]
pub type OnebitR = crate::BitReader;
#[doc = "Field `ONEBIT` writer - "]
pub type OnebitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVRDIS` reader - "]
pub type OvrdisR = crate::BitReader;
#[doc = "Field `OVRDIS` writer - "]
pub type OvrdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn eie(&self) -> EieR {
EieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x1f) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn dmar(&self) -> DmarR {
DmarR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dmat(&self) -> DmatR {
DmatR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rtse(&self) -> RtseR {
RtseR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctse(&self) -> CtseR {
CtseR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ctsie(&self) -> CtsieR {
CtsieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn onebit(&self) -> OnebitR {
OnebitR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn ovrdis(&self) -> OvrdisR {
OvrdisR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn eie(&mut self) -> EieW<Cr3Spec> {
EieW::new(self, 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr3Spec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn dmar(&mut self) -> DmarW<Cr3Spec> {
DmarW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dmat(&mut self) -> DmatW<Cr3Spec> {
DmatW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rtse(&mut self) -> RtseW<Cr3Spec> {
RtseW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctse(&mut self) -> CtseW<Cr3Spec> {
CtseW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ctsie(&mut self) -> CtsieW<Cr3Spec> {
CtsieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn onebit(&mut self) -> OnebitW<Cr3Spec> {
OnebitW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn ovrdis(&mut self) -> OvrdisW<Cr3Spec> {
OvrdisW::new(self, 12)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr3Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr3Spec;
impl crate::RegisterSpec for Cr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr3::R`](R) reader structure"]
impl crate::Readable for Cr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cr3::W`](W) writer structure"]
impl crate::Writable for Cr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR3 to value 0"]
impl crate::Resettable for Cr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BRR (rw) register accessor: Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@brr`]
module"]
#[doc(alias = "BRR")]
pub type Brr = crate::Reg<brr::BrrSpec>;
#[doc = "Baud Rate Register"]
pub mod brr {
#[doc = "Register `BRR` reader"]
pub type R = crate::R<BrrSpec>;
#[doc = "Register `BRR` writer"]
pub type W = crate::W<BrrSpec>;
#[doc = "Field `FRAC` reader - "]
pub type FracR = crate::FieldReader;
#[doc = "Field `FRAC` writer - "]
pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `INT` reader - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntR = crate::FieldReader<u16>;
#[doc = "Field `INT` writer - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn frac(&self) -> FracR {
FracR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
pub fn int(&self) -> IntR {
IntR::new(((self.bits >> 4) & 0x0fff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn frac(&mut self) -> FracW<BrrSpec> {
FracW::new(self, 0)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
#[must_use]
pub fn int(&mut self) -> IntW<BrrSpec> {
IntW::new(self, 4)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BrrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BrrSpec;
impl crate::RegisterSpec for BrrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`brr::R`](R) reader structure"]
impl crate::Readable for BrrSpec {}
#[doc = "`write(|w| ..)` method takes [`brr::W`](W) writer structure"]
impl crate::Writable for BrrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BRR to value 0"]
impl crate::Resettable for BrrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GTPR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gtpr`]
module"]
#[doc(alias = "GTPR")]
pub type Gtpr = crate::Reg<gtpr::GtprSpec>;
#[doc = ""]
pub mod gtpr {
#[doc = "Register `GTPR` reader"]
pub type R = crate::R<GtprSpec>;
#[doc = "Register `GTPR` writer"]
pub type W = crate::W<GtprSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<GtprSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GtprSpec;
impl crate::RegisterSpec for GtprSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gtpr::R`](R) reader structure"]
impl crate::Readable for GtprSpec {}
#[doc = "`write(|w| ..)` method takes [`gtpr::W`](W) writer structure"]
impl crate::Writable for GtprSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GTPR to value 0"]
impl crate::Resettable for GtprSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RTOR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtor`]
module"]
#[doc(alias = "RTOR")]
pub type Rtor = crate::Reg<rtor::RtorSpec>;
#[doc = ""]
pub mod rtor {
#[doc = "Register `RTOR` reader"]
pub type R = crate::R<RtorSpec>;
#[doc = "Register `RTOR` writer"]
pub type W = crate::W<RtorSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RtorSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtorSpec;
impl crate::RegisterSpec for RtorSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtor::R`](R) reader structure"]
impl crate::Readable for RtorSpec {}
#[doc = "`write(|w| ..)` method takes [`rtor::W`](W) writer structure"]
impl crate::Writable for RtorSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTOR to value 0"]
impl crate::Resettable for RtorSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RQR (rw) register accessor: Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rqr`]
module"]
#[doc(alias = "RQR")]
pub type Rqr = crate::Reg<rqr::RqrSpec>;
#[doc = "Request Register"]
pub mod rqr {
#[doc = "Register `RQR` reader"]
pub type R = crate::R<RqrSpec>;
#[doc = "Register `RQR` writer"]
pub type W = crate::W<RqrSpec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RXFRQ` reader - "]
pub type RxfrqR = crate::BitReader;
#[doc = "Field `RXFRQ` writer - "]
pub type RxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXFRQ` reader - "]
pub type TxfrqR = crate::BitReader;
#[doc = "Field `TXFRQ` writer - "]
pub type TxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxfrq(&self) -> RxfrqR {
RxfrqR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn txfrq(&self) -> TxfrqR {
TxfrqR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<RqrSpec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxfrq(&mut self) -> RxfrqW<RqrSpec> {
RxfrqW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn txfrq(&mut self) -> TxfrqW<RqrSpec> {
TxfrqW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RqrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RqrSpec;
impl crate::RegisterSpec for RqrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rqr::R`](R) reader structure"]
impl crate::Readable for RqrSpec {}
#[doc = "`write(|w| ..)` method takes [`rqr::W`](W) writer structure"]
impl crate::Writable for RqrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RQR to value 0"]
impl crate::Resettable for RqrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR (rw) register accessor: Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "Interrupt and Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - "]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - "]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NF` reader - "]
pub type NfR = crate::BitReader;
#[doc = "Field `NF` writer - "]
pub type NfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORE` reader - "]
pub type OreR = crate::BitReader;
#[doc = "Field `ORE` writer - "]
pub type OreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLE` reader - "]
pub type IdleR = crate::BitReader;
#[doc = "Field `IDLE` writer - "]
pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNE` reader - "]
pub type RxneR = crate::BitReader;
#[doc = "Field `RXNE` writer - "]
pub type RxneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TC` reader - "]
pub type TcR = crate::BitReader;
#[doc = "Field `TC` writer - "]
pub type TcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - "]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - "]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIF` reader - "]
pub type CtsifR = crate::BitReader;
#[doc = "Field `CTSIF` writer - "]
pub type CtsifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTS` reader - "]
pub type CtsR = crate::BitReader;
#[doc = "Field `CTS` writer - "]
pub type CtsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn nf(&self) -> NfR {
NfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ore(&self) -> OreR {
OreR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idle(&self) -> IdleR {
IdleR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxne(&self) -> RxneR {
RxneR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tc(&self) -> TcR {
TcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctsif(&self) -> CtsifR {
CtsifR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cts(&self) -> CtsR {
CtsR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<IsrSpec> {
PeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fe(&mut self) -> FeW<IsrSpec> {
FeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn nf(&mut self) -> NfW<IsrSpec> {
NfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ore(&mut self) -> OreW<IsrSpec> {
OreW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idle(&mut self) -> IdleW<IsrSpec> {
IdleW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxne(&mut self) -> RxneW<IsrSpec> {
RxneW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tc(&mut self) -> TcW<IsrSpec> {
TcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txe(&mut self) -> TxeW<IsrSpec> {
TxeW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctsif(&mut self) -> CtsifW<IsrSpec> {
CtsifW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cts(&mut self) -> CtsW<IsrSpec> {
CtsW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "Interrupt flag Clear Register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `PECF` reader - "]
pub type PecfR = crate::BitReader;
#[doc = "Field `PECF` writer - "]
pub type PecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FECF` reader - "]
pub type FecfR = crate::BitReader;
#[doc = "Field `FECF` writer - "]
pub type FecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NCF` reader - "]
pub type NcfR = crate::BitReader;
#[doc = "Field `NCF` writer - "]
pub type NcfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORECF` reader - "]
pub type OrecfR = crate::BitReader;
#[doc = "Field `ORECF` writer - "]
pub type OrecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLECF` reader - "]
pub type IdlecfR = crate::BitReader;
#[doc = "Field `IDLECF` writer - "]
pub type IdlecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCCF` reader - "]
pub type TccfR = crate::BitReader;
#[doc = "Field `TCCF` writer - "]
pub type TccfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTSCF` reader - "]
pub type CtscfR = crate::BitReader;
#[doc = "Field `CTSCF` writer - "]
pub type CtscfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pecf(&self) -> PecfR {
PecfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fecf(&self) -> FecfR {
FecfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ncf(&self) -> NcfR {
NcfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn orecf(&self) -> OrecfR {
OrecfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idlecf(&self) -> IdlecfR {
IdlecfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tccf(&self) -> TccfR {
TccfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 7) & 3) as u8)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctscf(&self) -> CtscfR {
CtscfR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pecf(&mut self) -> PecfW<IcrSpec> {
PecfW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fecf(&mut self) -> FecfW<IcrSpec> {
FecfW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ncf(&mut self) -> NcfW<IcrSpec> {
NcfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn orecf(&mut self) -> OrecfW<IcrSpec> {
OrecfW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idlecf(&mut self) -> IdlecfW<IcrSpec> {
IdlecfW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IcrSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tccf(&mut self) -> TccfW<IcrSpec> {
TccfW::new(self, 6)
}
#[doc = "Bits 7:8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 7)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctscf(&mut self) -> CtscfW<IcrSpec> {
CtscfW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RDR (rw) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdr`]
module"]
#[doc(alias = "RDR")]
pub type Rdr = crate::Reg<rdr::RdrSpec>;
#[doc = "Receive Data Register"]
pub mod rdr {
#[doc = "Register `RDR` reader"]
pub type R = crate::R<RdrSpec>;
#[doc = "Register `RDR` writer"]
pub type W = crate::W<RdrSpec>;
#[doc = "Field `RDR` reader - "]
pub type RdrR = crate::FieldReader<u16>;
#[doc = "Field `RDR` writer - "]
pub type RdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn rdr(&self) -> RdrR {
RdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn rdr(&mut self) -> RdrW<RdrSpec> {
RdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrSpec;
impl crate::RegisterSpec for RdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rdr::R`](R) reader structure"]
impl crate::Readable for RdrSpec {}
#[doc = "`write(|w| ..)` method takes [`rdr::W`](W) writer structure"]
impl crate::Writable for RdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RDR to value 0"]
impl crate::Resettable for RdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TDR (rw) register accessor: Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`]
module"]
#[doc(alias = "TDR")]
pub type Tdr = crate::Reg<tdr::TdrSpec>;
#[doc = "Transmit Data Register"]
pub mod tdr {
#[doc = "Register `TDR` reader"]
pub type R = crate::R<TdrSpec>;
#[doc = "Register `TDR` writer"]
pub type W = crate::W<TdrSpec>;
#[doc = "Field `TDR` reader - "]
pub type TdrR = crate::FieldReader<u16>;
#[doc = "Field `TDR` writer - "]
pub type TdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn tdr(&self) -> TdrR {
TdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn tdr(&mut self) -> TdrW<TdrSpec> {
TdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TdrSpec;
impl crate::RegisterSpec for TdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tdr::R`](R) reader structure"]
impl crate::Readable for TdrSpec {}
#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"]
impl crate::Writable for TdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TDR to value 0"]
impl crate::Resettable for TdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "MISCR (rw) register accessor: Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscr`]
module"]
#[doc(alias = "MISCR")]
pub type Miscr = crate::Reg<miscr::MiscrSpec>;
#[doc = "Miscellaneous Register"]
pub mod miscr {
#[doc = "Register `MISCR` reader"]
pub type R = crate::R<MiscrSpec>;
#[doc = "Register `MISCR` writer"]
pub type W = crate::W<MiscrSpec>;
#[doc = "Field `SMPLINI` reader - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniR = crate::FieldReader;
#[doc = "Field `SMPLINI` writer - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RTSBIT` reader - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitR = crate::FieldReader;
#[doc = "Field `RTSBIT` writer - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
#[doc = "Field `AUTOCAL` reader - "]
pub type AutocalR = crate::BitReader;
#[doc = "Field `AUTOCAL` writer - "]
pub type AutocalW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
pub fn smplini(&self) -> SmpliniR {
SmpliniR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
pub fn rtsbit(&self) -> RtsbitR {
RtsbitR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x007f_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn autocal(&self) -> AutocalR {
AutocalR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
#[must_use]
pub fn smplini(&mut self) -> SmpliniW<MiscrSpec> {
SmpliniW::new(self, 0)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
#[must_use]
pub fn rtsbit(&mut self) -> RtsbitW<MiscrSpec> {
RtsbitW::new(self, 4)
}
#[doc = "Bits 8:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<MiscrSpec> {
RsvdW::new(self, 8)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn autocal(&mut self) -> AutocalW<MiscrSpec> {
AutocalW::new(self, 31)
}
}
#[doc = "Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscrSpec;
impl crate::RegisterSpec for MiscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miscr::R`](R) reader structure"]
impl crate::Readable for MiscrSpec {}
#[doc = "`write(|w| ..)` method takes [`miscr::W`](W) writer structure"]
impl crate::Writable for MiscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISCR to value 0"]
impl crate::Resettable for MiscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DRDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@drdr`]
module"]
#[doc(alias = "DRDR")]
pub type Drdr = crate::Reg<drdr::DrdrSpec>;
#[doc = ""]
pub mod drdr {
#[doc = "Register `DRDR` reader"]
pub type R = crate::R<DrdrSpec>;
#[doc = "Register `DRDR` writer"]
pub type W = crate::W<DrdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DrdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrdrSpec;
impl crate::RegisterSpec for DrdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`drdr::R`](R) reader structure"]
impl crate::Readable for DrdrSpec {}
#[doc = "`write(|w| ..)` method takes [`drdr::W`](W) writer structure"]
impl crate::Writable for DrdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DRDR to value 0"]
impl crate::Resettable for DrdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtdr`]
module"]
#[doc(alias = "DTDR")]
pub type Dtdr = crate::Reg<dtdr::DtdrSpec>;
#[doc = ""]
pub mod dtdr {
#[doc = "Register `DTDR` reader"]
pub type R = crate::R<DtdrSpec>;
#[doc = "Register `DTDR` writer"]
pub type W = crate::W<DtdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DtdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DtdrSpec;
impl crate::RegisterSpec for DtdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtdr::R`](R) reader structure"]
impl crate::Readable for DtdrSpec {}
#[doc = "`write(|w| ..)` method takes [`dtdr::W`](W) writer structure"]
impl crate::Writable for DtdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTDR to value 0"]
impl crate::Resettable for DtdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EXR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exr`]
module"]
#[doc(alias = "EXR")]
pub type Exr = crate::Reg<exr::ExrSpec>;
#[doc = ""]
pub mod exr {
#[doc = "Register `EXR` reader"]
pub type R = crate::R<ExrSpec>;
#[doc = "Register `EXR` writer"]
pub type W = crate::W<ExrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ExrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExrSpec;
impl crate::RegisterSpec for ExrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`exr::R`](R) reader structure"]
impl crate::Readable for ExrSpec {}
#[doc = "`write(|w| ..)` method takes [`exr::W`](W) writer structure"]
impl crate::Writable for ExrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EXR to value 0"]
impl crate::Resettable for ExrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "USART3"]
pub struct Usart3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Usart3 {}
impl Usart3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const usart3::RegisterBlock = 0x5008_6000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const usart3::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Usart3 {
type Target = usart3::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Usart3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart3").finish()
}
}
#[doc = "USART3"]
pub mod usart3 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
cr3: Cr3,
brr: Brr,
gtpr: Gtpr,
rtor: Rtor,
rqr: Rqr,
isr: Isr,
icr: Icr,
rdr: Rdr,
tdr: Tdr,
miscr: Miscr,
drdr: Drdr,
dtdr: Dtdr,
exr: Exr,
}
impl RegisterBlock {
#[doc = "0x00 - Control Register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - Control Register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - Control Register 3"]
#[inline(always)]
pub const fn cr3(&self) -> &Cr3 {
&self.cr3
}
#[doc = "0x0c - Baud Rate Register"]
#[inline(always)]
pub const fn brr(&self) -> &Brr {
&self.brr
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn gtpr(&self) -> &Gtpr {
&self.gtpr
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn rtor(&self) -> &Rtor {
&self.rtor
}
#[doc = "0x18 - Request Register"]
#[inline(always)]
pub const fn rqr(&self) -> &Rqr {
&self.rqr
}
#[doc = "0x1c - Interrupt and Status Register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x20 - Interrupt flag Clear Register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x24 - Receive Data Register"]
#[inline(always)]
pub const fn rdr(&self) -> &Rdr {
&self.rdr
}
#[doc = "0x28 - Transmit Data Register"]
#[inline(always)]
pub const fn tdr(&self) -> &Tdr {
&self.tdr
}
#[doc = "0x2c - Miscellaneous Register"]
#[inline(always)]
pub const fn miscr(&self) -> &Miscr {
&self.miscr
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn drdr(&self) -> &Drdr {
&self.drdr
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn dtdr(&self) -> &Dtdr {
&self.dtdr
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn exr(&self) -> &Exr {
&self.exr
}
}
#[doc = "CR1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `UE` reader - "]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - "]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RE` reader - "]
pub type ReR = crate::BitReader;
#[doc = "Field `RE` writer - "]
pub type ReW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - "]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - "]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLEIE` reader - "]
pub type IdleieR = crate::BitReader;
#[doc = "Field `IDLEIE` writer - "]
pub type IdleieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNEIE` reader - "]
pub type RxneieR = crate::BitReader;
#[doc = "Field `RXNEIE` writer - "]
pub type RxneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - "]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - "]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXEIE` reader - "]
pub type TxeieR = crate::BitReader;
#[doc = "Field `TXEIE` writer - "]
pub type TxeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PEIE` reader - "]
pub type PeieR = crate::BitReader;
#[doc = "Field `PEIE` writer - "]
pub type PeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCE` reader - "]
pub type PceR = crate::BitReader;
#[doc = "Field `PCE` writer - "]
pub type PceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `OVER8` reader - "]
pub type Over8R = crate::BitReader;
#[doc = "Field `OVER8` writer - "]
pub type Over8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `M` reader - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MR = crate::FieldReader;
#[doc = "Field `M` writer - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn re(&self) -> ReR {
ReR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idleie(&self) -> IdleieR {
IdleieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxneie(&self) -> RxneieR {
RxneieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txeie(&self) -> TxeieR {
TxeieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn peie(&self) -> PeieR {
PeieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn pce(&self) -> PceR {
PceR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:13"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn over8(&self) -> Over8R {
Over8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:26"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 0x0fff) as u16)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
pub fn m(&self) -> MR {
MR::new(((self.bits >> 27) & 3) as u8)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<Cr1Spec> {
UeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cr1Spec> {
Rsvd4W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn re(&mut self) -> ReW<Cr1Spec> {
ReW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<Cr1Spec> {
TeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idleie(&mut self) -> IdleieW<Cr1Spec> {
IdleieW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxneie(&mut self) -> RxneieW<Cr1Spec> {
RxneieW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Cr1Spec> {
TcieW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txeie(&mut self) -> TxeieW<Cr1Spec> {
TxeieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn peie(&mut self) -> PeieW<Cr1Spec> {
PeieW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Cr1Spec> {
PsW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn pce(&mut self) -> PceW<Cr1Spec> {
PceW::new(self, 10)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cr1Spec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn over8(&mut self) -> Over8W<Cr1Spec> {
Over8W::new(self, 14)
}
#[doc = "Bits 15:26"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
#[must_use]
pub fn m(&mut self) -> MW<Cr1Spec> {
MW::new(self, 27)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 29)
}
}
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `STOP` reader - "]
pub type StopR = crate::FieldReader;
#[doc = "Field `STOP` writer - "]
pub type StopW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<Cr2Spec> {
StopW::new(self, 12)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 14)
}
}
#[doc = "Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR3 (rw) register accessor: Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr3`]
module"]
#[doc(alias = "CR3")]
pub type Cr3 = crate::Reg<cr3::Cr3Spec>;
#[doc = "Control Register 3"]
pub mod cr3 {
#[doc = "Register `CR3` reader"]
pub type R = crate::R<Cr3Spec>;
#[doc = "Register `CR3` writer"]
pub type W = crate::W<Cr3Spec>;
#[doc = "Field `EIE` reader - "]
pub type EieR = crate::BitReader;
#[doc = "Field `EIE` writer - "]
pub type EieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMAR` reader - "]
pub type DmarR = crate::BitReader;
#[doc = "Field `DMAR` writer - "]
pub type DmarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAT` reader - "]
pub type DmatR = crate::BitReader;
#[doc = "Field `DMAT` writer - "]
pub type DmatW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTSE` reader - "]
pub type RtseR = crate::BitReader;
#[doc = "Field `RTSE` writer - "]
pub type RtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSE` reader - "]
pub type CtseR = crate::BitReader;
#[doc = "Field `CTSE` writer - "]
pub type CtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIE` reader - "]
pub type CtsieR = crate::BitReader;
#[doc = "Field `CTSIE` writer - "]
pub type CtsieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ONEBIT` reader - "]
pub type OnebitR = crate::BitReader;
#[doc = "Field `ONEBIT` writer - "]
pub type OnebitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVRDIS` reader - "]
pub type OvrdisR = crate::BitReader;
#[doc = "Field `OVRDIS` writer - "]
pub type OvrdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn eie(&self) -> EieR {
EieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x1f) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn dmar(&self) -> DmarR {
DmarR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dmat(&self) -> DmatR {
DmatR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rtse(&self) -> RtseR {
RtseR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctse(&self) -> CtseR {
CtseR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ctsie(&self) -> CtsieR {
CtsieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn onebit(&self) -> OnebitR {
OnebitR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn ovrdis(&self) -> OvrdisR {
OvrdisR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn eie(&mut self) -> EieW<Cr3Spec> {
EieW::new(self, 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr3Spec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn dmar(&mut self) -> DmarW<Cr3Spec> {
DmarW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dmat(&mut self) -> DmatW<Cr3Spec> {
DmatW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rtse(&mut self) -> RtseW<Cr3Spec> {
RtseW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctse(&mut self) -> CtseW<Cr3Spec> {
CtseW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ctsie(&mut self) -> CtsieW<Cr3Spec> {
CtsieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn onebit(&mut self) -> OnebitW<Cr3Spec> {
OnebitW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn ovrdis(&mut self) -> OvrdisW<Cr3Spec> {
OvrdisW::new(self, 12)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr3Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr3Spec;
impl crate::RegisterSpec for Cr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr3::R`](R) reader structure"]
impl crate::Readable for Cr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cr3::W`](W) writer structure"]
impl crate::Writable for Cr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR3 to value 0"]
impl crate::Resettable for Cr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BRR (rw) register accessor: Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@brr`]
module"]
#[doc(alias = "BRR")]
pub type Brr = crate::Reg<brr::BrrSpec>;
#[doc = "Baud Rate Register"]
pub mod brr {
#[doc = "Register `BRR` reader"]
pub type R = crate::R<BrrSpec>;
#[doc = "Register `BRR` writer"]
pub type W = crate::W<BrrSpec>;
#[doc = "Field `FRAC` reader - "]
pub type FracR = crate::FieldReader;
#[doc = "Field `FRAC` writer - "]
pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `INT` reader - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntR = crate::FieldReader<u16>;
#[doc = "Field `INT` writer - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn frac(&self) -> FracR {
FracR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
pub fn int(&self) -> IntR {
IntR::new(((self.bits >> 4) & 0x0fff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn frac(&mut self) -> FracW<BrrSpec> {
FracW::new(self, 0)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
#[must_use]
pub fn int(&mut self) -> IntW<BrrSpec> {
IntW::new(self, 4)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BrrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BrrSpec;
impl crate::RegisterSpec for BrrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`brr::R`](R) reader structure"]
impl crate::Readable for BrrSpec {}
#[doc = "`write(|w| ..)` method takes [`brr::W`](W) writer structure"]
impl crate::Writable for BrrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BRR to value 0"]
impl crate::Resettable for BrrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GTPR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gtpr`]
module"]
#[doc(alias = "GTPR")]
pub type Gtpr = crate::Reg<gtpr::GtprSpec>;
#[doc = ""]
pub mod gtpr {
#[doc = "Register `GTPR` reader"]
pub type R = crate::R<GtprSpec>;
#[doc = "Register `GTPR` writer"]
pub type W = crate::W<GtprSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<GtprSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GtprSpec;
impl crate::RegisterSpec for GtprSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gtpr::R`](R) reader structure"]
impl crate::Readable for GtprSpec {}
#[doc = "`write(|w| ..)` method takes [`gtpr::W`](W) writer structure"]
impl crate::Writable for GtprSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GTPR to value 0"]
impl crate::Resettable for GtprSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RTOR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtor`]
module"]
#[doc(alias = "RTOR")]
pub type Rtor = crate::Reg<rtor::RtorSpec>;
#[doc = ""]
pub mod rtor {
#[doc = "Register `RTOR` reader"]
pub type R = crate::R<RtorSpec>;
#[doc = "Register `RTOR` writer"]
pub type W = crate::W<RtorSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RtorSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtorSpec;
impl crate::RegisterSpec for RtorSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtor::R`](R) reader structure"]
impl crate::Readable for RtorSpec {}
#[doc = "`write(|w| ..)` method takes [`rtor::W`](W) writer structure"]
impl crate::Writable for RtorSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTOR to value 0"]
impl crate::Resettable for RtorSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RQR (rw) register accessor: Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rqr`]
module"]
#[doc(alias = "RQR")]
pub type Rqr = crate::Reg<rqr::RqrSpec>;
#[doc = "Request Register"]
pub mod rqr {
#[doc = "Register `RQR` reader"]
pub type R = crate::R<RqrSpec>;
#[doc = "Register `RQR` writer"]
pub type W = crate::W<RqrSpec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RXFRQ` reader - "]
pub type RxfrqR = crate::BitReader;
#[doc = "Field `RXFRQ` writer - "]
pub type RxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXFRQ` reader - "]
pub type TxfrqR = crate::BitReader;
#[doc = "Field `TXFRQ` writer - "]
pub type TxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxfrq(&self) -> RxfrqR {
RxfrqR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn txfrq(&self) -> TxfrqR {
TxfrqR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<RqrSpec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxfrq(&mut self) -> RxfrqW<RqrSpec> {
RxfrqW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn txfrq(&mut self) -> TxfrqW<RqrSpec> {
TxfrqW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RqrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RqrSpec;
impl crate::RegisterSpec for RqrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rqr::R`](R) reader structure"]
impl crate::Readable for RqrSpec {}
#[doc = "`write(|w| ..)` method takes [`rqr::W`](W) writer structure"]
impl crate::Writable for RqrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RQR to value 0"]
impl crate::Resettable for RqrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR (rw) register accessor: Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "Interrupt and Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - "]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - "]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NF` reader - "]
pub type NfR = crate::BitReader;
#[doc = "Field `NF` writer - "]
pub type NfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORE` reader - "]
pub type OreR = crate::BitReader;
#[doc = "Field `ORE` writer - "]
pub type OreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLE` reader - "]
pub type IdleR = crate::BitReader;
#[doc = "Field `IDLE` writer - "]
pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNE` reader - "]
pub type RxneR = crate::BitReader;
#[doc = "Field `RXNE` writer - "]
pub type RxneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TC` reader - "]
pub type TcR = crate::BitReader;
#[doc = "Field `TC` writer - "]
pub type TcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - "]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - "]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIF` reader - "]
pub type CtsifR = crate::BitReader;
#[doc = "Field `CTSIF` writer - "]
pub type CtsifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTS` reader - "]
pub type CtsR = crate::BitReader;
#[doc = "Field `CTS` writer - "]
pub type CtsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn nf(&self) -> NfR {
NfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ore(&self) -> OreR {
OreR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idle(&self) -> IdleR {
IdleR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxne(&self) -> RxneR {
RxneR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tc(&self) -> TcR {
TcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctsif(&self) -> CtsifR {
CtsifR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cts(&self) -> CtsR {
CtsR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<IsrSpec> {
PeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fe(&mut self) -> FeW<IsrSpec> {
FeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn nf(&mut self) -> NfW<IsrSpec> {
NfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ore(&mut self) -> OreW<IsrSpec> {
OreW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idle(&mut self) -> IdleW<IsrSpec> {
IdleW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxne(&mut self) -> RxneW<IsrSpec> {
RxneW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tc(&mut self) -> TcW<IsrSpec> {
TcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txe(&mut self) -> TxeW<IsrSpec> {
TxeW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctsif(&mut self) -> CtsifW<IsrSpec> {
CtsifW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cts(&mut self) -> CtsW<IsrSpec> {
CtsW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "Interrupt flag Clear Register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `PECF` reader - "]
pub type PecfR = crate::BitReader;
#[doc = "Field `PECF` writer - "]
pub type PecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FECF` reader - "]
pub type FecfR = crate::BitReader;
#[doc = "Field `FECF` writer - "]
pub type FecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NCF` reader - "]
pub type NcfR = crate::BitReader;
#[doc = "Field `NCF` writer - "]
pub type NcfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORECF` reader - "]
pub type OrecfR = crate::BitReader;
#[doc = "Field `ORECF` writer - "]
pub type OrecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLECF` reader - "]
pub type IdlecfR = crate::BitReader;
#[doc = "Field `IDLECF` writer - "]
pub type IdlecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCCF` reader - "]
pub type TccfR = crate::BitReader;
#[doc = "Field `TCCF` writer - "]
pub type TccfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTSCF` reader - "]
pub type CtscfR = crate::BitReader;
#[doc = "Field `CTSCF` writer - "]
pub type CtscfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pecf(&self) -> PecfR {
PecfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fecf(&self) -> FecfR {
FecfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ncf(&self) -> NcfR {
NcfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn orecf(&self) -> OrecfR {
OrecfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idlecf(&self) -> IdlecfR {
IdlecfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tccf(&self) -> TccfR {
TccfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 7) & 3) as u8)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctscf(&self) -> CtscfR {
CtscfR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pecf(&mut self) -> PecfW<IcrSpec> {
PecfW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fecf(&mut self) -> FecfW<IcrSpec> {
FecfW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ncf(&mut self) -> NcfW<IcrSpec> {
NcfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn orecf(&mut self) -> OrecfW<IcrSpec> {
OrecfW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idlecf(&mut self) -> IdlecfW<IcrSpec> {
IdlecfW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IcrSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tccf(&mut self) -> TccfW<IcrSpec> {
TccfW::new(self, 6)
}
#[doc = "Bits 7:8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 7)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctscf(&mut self) -> CtscfW<IcrSpec> {
CtscfW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RDR (rw) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdr`]
module"]
#[doc(alias = "RDR")]
pub type Rdr = crate::Reg<rdr::RdrSpec>;
#[doc = "Receive Data Register"]
pub mod rdr {
#[doc = "Register `RDR` reader"]
pub type R = crate::R<RdrSpec>;
#[doc = "Register `RDR` writer"]
pub type W = crate::W<RdrSpec>;
#[doc = "Field `RDR` reader - "]
pub type RdrR = crate::FieldReader<u16>;
#[doc = "Field `RDR` writer - "]
pub type RdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn rdr(&self) -> RdrR {
RdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn rdr(&mut self) -> RdrW<RdrSpec> {
RdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrSpec;
impl crate::RegisterSpec for RdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rdr::R`](R) reader structure"]
impl crate::Readable for RdrSpec {}
#[doc = "`write(|w| ..)` method takes [`rdr::W`](W) writer structure"]
impl crate::Writable for RdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RDR to value 0"]
impl crate::Resettable for RdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TDR (rw) register accessor: Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`]
module"]
#[doc(alias = "TDR")]
pub type Tdr = crate::Reg<tdr::TdrSpec>;
#[doc = "Transmit Data Register"]
pub mod tdr {
#[doc = "Register `TDR` reader"]
pub type R = crate::R<TdrSpec>;
#[doc = "Register `TDR` writer"]
pub type W = crate::W<TdrSpec>;
#[doc = "Field `TDR` reader - "]
pub type TdrR = crate::FieldReader<u16>;
#[doc = "Field `TDR` writer - "]
pub type TdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn tdr(&self) -> TdrR {
TdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn tdr(&mut self) -> TdrW<TdrSpec> {
TdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TdrSpec;
impl crate::RegisterSpec for TdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tdr::R`](R) reader structure"]
impl crate::Readable for TdrSpec {}
#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"]
impl crate::Writable for TdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TDR to value 0"]
impl crate::Resettable for TdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "MISCR (rw) register accessor: Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscr`]
module"]
#[doc(alias = "MISCR")]
pub type Miscr = crate::Reg<miscr::MiscrSpec>;
#[doc = "Miscellaneous Register"]
pub mod miscr {
#[doc = "Register `MISCR` reader"]
pub type R = crate::R<MiscrSpec>;
#[doc = "Register `MISCR` writer"]
pub type W = crate::W<MiscrSpec>;
#[doc = "Field `SMPLINI` reader - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniR = crate::FieldReader;
#[doc = "Field `SMPLINI` writer - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RTSBIT` reader - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitR = crate::FieldReader;
#[doc = "Field `RTSBIT` writer - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
#[doc = "Field `AUTOCAL` reader - "]
pub type AutocalR = crate::BitReader;
#[doc = "Field `AUTOCAL` writer - "]
pub type AutocalW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
pub fn smplini(&self) -> SmpliniR {
SmpliniR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
pub fn rtsbit(&self) -> RtsbitR {
RtsbitR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x007f_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn autocal(&self) -> AutocalR {
AutocalR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
#[must_use]
pub fn smplini(&mut self) -> SmpliniW<MiscrSpec> {
SmpliniW::new(self, 0)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
#[must_use]
pub fn rtsbit(&mut self) -> RtsbitW<MiscrSpec> {
RtsbitW::new(self, 4)
}
#[doc = "Bits 8:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<MiscrSpec> {
RsvdW::new(self, 8)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn autocal(&mut self) -> AutocalW<MiscrSpec> {
AutocalW::new(self, 31)
}
}
#[doc = "Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscrSpec;
impl crate::RegisterSpec for MiscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miscr::R`](R) reader structure"]
impl crate::Readable for MiscrSpec {}
#[doc = "`write(|w| ..)` method takes [`miscr::W`](W) writer structure"]
impl crate::Writable for MiscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISCR to value 0"]
impl crate::Resettable for MiscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DRDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@drdr`]
module"]
#[doc(alias = "DRDR")]
pub type Drdr = crate::Reg<drdr::DrdrSpec>;
#[doc = ""]
pub mod drdr {
#[doc = "Register `DRDR` reader"]
pub type R = crate::R<DrdrSpec>;
#[doc = "Register `DRDR` writer"]
pub type W = crate::W<DrdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DrdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrdrSpec;
impl crate::RegisterSpec for DrdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`drdr::R`](R) reader structure"]
impl crate::Readable for DrdrSpec {}
#[doc = "`write(|w| ..)` method takes [`drdr::W`](W) writer structure"]
impl crate::Writable for DrdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DRDR to value 0"]
impl crate::Resettable for DrdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtdr`]
module"]
#[doc(alias = "DTDR")]
pub type Dtdr = crate::Reg<dtdr::DtdrSpec>;
#[doc = ""]
pub mod dtdr {
#[doc = "Register `DTDR` reader"]
pub type R = crate::R<DtdrSpec>;
#[doc = "Register `DTDR` writer"]
pub type W = crate::W<DtdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DtdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DtdrSpec;
impl crate::RegisterSpec for DtdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtdr::R`](R) reader structure"]
impl crate::Readable for DtdrSpec {}
#[doc = "`write(|w| ..)` method takes [`dtdr::W`](W) writer structure"]
impl crate::Writable for DtdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTDR to value 0"]
impl crate::Resettable for DtdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EXR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exr`]
module"]
#[doc(alias = "EXR")]
pub type Exr = crate::Reg<exr::ExrSpec>;
#[doc = ""]
pub mod exr {
#[doc = "Register `EXR` reader"]
pub type R = crate::R<ExrSpec>;
#[doc = "Register `EXR` writer"]
pub type W = crate::W<ExrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ExrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExrSpec;
impl crate::RegisterSpec for ExrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`exr::R`](R) reader structure"]
impl crate::Readable for ExrSpec {}
#[doc = "`write(|w| ..)` method takes [`exr::W`](W) writer structure"]
impl crate::Writable for ExrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EXR to value 0"]
impl crate::Resettable for ExrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "BTIM1"]
pub struct Btim1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Btim1 {}
impl Btim1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const btim1::RegisterBlock = 0x5009_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const btim1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Btim1 {
type Target = btim1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Btim1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Btim1").finish()
}
}
#[doc = "BTIM1"]
pub mod btim1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
smcr: Smcr,
dier: Dier,
sr: Sr,
egr: Egr,
rsvd1: Rsvd1,
_reserved7: [u8; 0x08],
cnt: Cnt,
psc: Psc,
arr: Arr,
}
impl RegisterBlock {
#[doc = "0x00 - TIM control register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - TIM control register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - TIM slave mode control register"]
#[inline(always)]
pub const fn smcr(&self) -> &Smcr {
&self.smcr
}
#[doc = "0x0c - TIM DMA/Interrupt enable register"]
#[inline(always)]
pub const fn dier(&self) -> &Dier {
&self.dier
}
#[doc = "0x10 - TIM status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Event generation register"]
#[inline(always)]
pub const fn egr(&self) -> &Egr {
&self.egr
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x24 - Counter"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x28 - Prescaler"]
#[inline(always)]
pub const fn psc(&self) -> &Psc {
&self.psc
}
#[doc = "0x2c - Auto-reload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
}
#[doc = "CR1 (rw) register accessor: TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "TIM control register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `CEN` reader - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UDIS` reader - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisR = crate::BitReader;
#[doc = "Field `UDIS` writer - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `URS` reader - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsR = crate::BitReader;
#[doc = "Field `URS` writer - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OPM` reader - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmR = crate::BitReader;
#[doc = "Field `OPM` writer - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ARPE` reader - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeR = crate::BitReader;
#[doc = "Field `ARPE` writer - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
pub fn udis(&self) -> UdisR {
UdisR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
pub fn urs(&self) -> UrsR {
UrsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
pub fn opm(&self) -> OpmR {
OpmR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
pub fn arpe(&self) -> ArpeR {
ArpeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CenW<Cr1Spec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UdisW<Cr1Spec> {
UdisW::new(self, 1)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> UrsW<Cr1Spec> {
UrsW::new(self, 2)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OpmW<Cr1Spec> {
OpmW::new(self, 3)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ArpeW<Cr1Spec> {
ArpeW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "TIM control register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MMS` reader - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsR = crate::FieldReader;
#[doc = "Field `MMS` writer - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
pub fn mms(&self) -> MmsR {
MmsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MmsW<Cr2Spec> {
MmsW::new(self, 4)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 6)
}
}
#[doc = "TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMCR (rw) register accessor: TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcr`]
module"]
#[doc(alias = "SMCR")]
pub type Smcr = crate::Reg<smcr::SmcrSpec>;
#[doc = "TIM slave mode control register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub type R = crate::R<SmcrSpec>;
#[doc = "Register `SMCR` writer"]
pub type W = crate::W<SmcrSpec>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::FieldReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TS` reader - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsR = crate::FieldReader;
#[doc = "Field `TS` writer - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSM` reader - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmR = crate::BitReader;
#[doc = "Field `MSM` writer - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SMS` reader - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsR = crate::FieldReader;
#[doc = "Field `SMS` writer - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GTS` reader - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsR = crate::FieldReader;
#[doc = "Field `GTS` writer - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `GTP` reader - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpR = crate::BitReader;
#[doc = "Field `GTP` writer - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GM` reader - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmR = crate::BitReader;
#[doc = "Field `GM` writer - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn ts(&self) -> TsR {
TsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
pub fn msm(&self) -> MsmR {
MsmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
pub fn sms(&self) -> SmsR {
SmsR::new(((self.bits >> 16) & 7) as u8)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn gts(&self) -> GtsR {
GtsR::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
pub fn gtp(&self) -> GtpR {
GtpR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
pub fn gm(&self) -> GmR {
GmR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<SmcrSpec> {
Rsvd5W::new(self, 0)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TsW<SmcrSpec> {
TsW::new(self, 4)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<SmcrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MsmW<SmcrSpec> {
MsmW::new(self, 7)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<SmcrSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SmsW<SmcrSpec> {
SmsW::new(self, 16)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SmcrSpec> {
Rsvd2W::new(self, 19)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn gts(&mut self) -> GtsW<SmcrSpec> {
GtsW::new(self, 20)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
#[must_use]
pub fn gtp(&mut self) -> GtpW<SmcrSpec> {
GtpW::new(self, 22)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
#[must_use]
pub fn gm(&mut self) -> GmW<SmcrSpec> {
GmW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SmcrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmcrSpec;
impl crate::RegisterSpec for SmcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smcr::R`](R) reader structure"]
impl crate::Readable for SmcrSpec {}
#[doc = "`write(|w| ..)` method takes [`smcr::W`](W) writer structure"]
impl crate::Writable for SmcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SmcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DIER (rw) register accessor: TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dier`]
module"]
#[doc(alias = "DIER")]
pub type Dier = crate::Reg<dier::DierSpec>;
#[doc = "TIM DMA/Interrupt enable register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub type R = crate::R<DierSpec>;
#[doc = "Register `DIER` writer"]
pub type W = crate::W<DierSpec>;
#[doc = "Field `UIE` reader - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieR = crate::BitReader;
#[doc = "Field `UIE` writer - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `UDE` reader - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeR = crate::BitReader;
#[doc = "Field `UDE` writer - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
pub fn uie(&self) -> UieR {
UieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x7f) as u8)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
pub fn ude(&self) -> UdeR {
UdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UieW<DierSpec> {
UieW::new(self, 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DierSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UdeW<DierSpec> {
UdeW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DierSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DierSpec;
impl crate::RegisterSpec for DierSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dier::R`](R) reader structure"]
impl crate::Readable for DierSpec {}
#[doc = "`write(|w| ..)` method takes [`dier::W`](W) writer structure"]
impl crate::Writable for DierSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DierSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "TIM status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `UIF` reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifR = crate::BitReader;
#[doc = "Field `UIF` writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
pub fn uif(&self) -> UifR {
UifR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UifW<SrSpec> {
UifW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EGR (rw) register accessor: Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@egr`]
module"]
#[doc(alias = "EGR")]
pub type Egr = crate::Reg<egr::EgrSpec>;
#[doc = "Event generation register"]
pub mod egr {
#[doc = "Register `EGR` reader"]
pub type R = crate::R<EgrSpec>;
#[doc = "Register `EGR` writer"]
pub type W = crate::W<EgrSpec>;
#[doc = "Field `UG` reader - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgR = crate::BitReader;
#[doc = "Field `UG` writer - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
pub fn ug(&self) -> UgR {
UgR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UgW<EgrSpec> {
UgW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<EgrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EgrSpec;
impl crate::RegisterSpec for EgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`egr::R`](R) reader structure"]
impl crate::Readable for EgrSpec {}
#[doc = "`write(|w| ..)` method takes [`egr::W`](W) writer structure"]
impl crate::Writable for EgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "Counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - counter value"]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - counter value"]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
}
#[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSC (rw) register accessor: Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`]
module"]
#[doc(alias = "PSC")]
pub type Psc = crate::Reg<psc::PscSpec>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub type R = crate::R<PscSpec>;
#[doc = "Register `PSC` writer"]
pub type W = crate::W<PscSpec>;
#[doc = "Field `PSC` reader - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscR = crate::FieldReader<u16>;
#[doc = "Field `PSC` writer - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
pub fn psc(&self) -> PscR {
PscR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PscW<PscSpec> {
PscW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PscSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PscSpec;
impl crate::RegisterSpec for PscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate::Readable for PscSpec {}
#[doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate::Writable for PscSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PscSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "Auto-reload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
}
#[doc = "Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "WDT1"]
pub struct Wdt1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Wdt1 {}
impl Wdt1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const wdt1::RegisterBlock = 0x5009_4000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const wdt1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Wdt1 {
type Target = wdt1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Wdt1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wdt1").finish()
}
}
#[doc = "WDT1"]
pub mod wdt1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
wdt_cvr0: WdtCvr0,
wdt_cvr1: WdtCvr1,
wdt_cr: WdtCr,
wdt_ccr: WdtCcr,
wdt_icr: WdtIcr,
wdt_sr: WdtSr,
wdt_wp: WdtWp,
wdt_fg: WdtFg,
}
impl RegisterBlock {
#[doc = "0x00 - WatchDog Counter Value 0"]
#[inline(always)]
pub const fn wdt_cvr0(&self) -> &WdtCvr0 {
&self.wdt_cvr0
}
#[doc = "0x04 - WatchDog Counter Value 1"]
#[inline(always)]
pub const fn wdt_cvr1(&self) -> &WdtCvr1 {
&self.wdt_cvr1
}
#[doc = "0x08 - WatchDog Control Register"]
#[inline(always)]
pub const fn wdt_cr(&self) -> &WdtCr {
&self.wdt_cr
}
#[doc = "0x0c - WatchDog Counter Control Register"]
#[inline(always)]
pub const fn wdt_ccr(&self) -> &WdtCcr {
&self.wdt_ccr
}
#[doc = "0x10 - WatchDog Interrupt Clear Register"]
#[inline(always)]
pub const fn wdt_icr(&self) -> &WdtIcr {
&self.wdt_icr
}
#[doc = "0x14 - WatchDog Status Register"]
#[inline(always)]
pub const fn wdt_sr(&self) -> &WdtSr {
&self.wdt_sr
}
#[doc = "0x18 - WatchDog Write Protect Register"]
#[inline(always)]
pub const fn wdt_wp(&self) -> &WdtWp {
&self.wdt_wp
}
#[doc = "0x1c - WatchDog Flag Register"]
#[inline(always)]
pub const fn wdt_fg(&self) -> &WdtFg {
&self.wdt_fg
}
}
#[doc = "WDT_CVR0 (rw) register accessor: WatchDog Counter Value 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cvr0`]
module"]
#[doc(alias = "WDT_CVR0")]
pub type WdtCvr0 = crate::Reg<wdt_cvr0::WdtCvr0Spec>;
#[doc = "WatchDog Counter Value 0"]
pub mod wdt_cvr0 {
#[doc = "Register `WDT_CVR0` reader"]
pub type R = crate::R<WdtCvr0Spec>;
#[doc = "Register `WDT_CVR0` writer"]
pub type W = crate::W<WdtCvr0Spec>;
#[doc = "Field `COUNT_VALUE_0` reader - Count Value for 1st TimeOut"]
pub type CountValue0R = crate::FieldReader<u32>;
#[doc = "Field `COUNT_VALUE_0` writer - Count Value for 1st TimeOut"]
pub type CountValue0W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Count Value for 1st TimeOut"]
#[inline(always)]
pub fn count_value_0(&self) -> CountValue0R {
CountValue0R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Count Value for 1st TimeOut"]
#[inline(always)]
#[must_use]
pub fn count_value_0(&mut self) -> CountValue0W<WdtCvr0Spec> {
CountValue0W::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCvr0Spec> {
RsvdW::new(self, 24)
}
}
#[doc = "WatchDog Counter Value 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCvr0Spec;
impl crate::RegisterSpec for WdtCvr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cvr0::R`](R) reader structure"]
impl crate::Readable for WdtCvr0Spec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cvr0::W`](W) writer structure"]
impl crate::Writable for WdtCvr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CVR0 to value 0"]
impl crate::Resettable for WdtCvr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CVR1 (rw) register accessor: WatchDog Counter Value 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cvr1`]
module"]
#[doc(alias = "WDT_CVR1")]
pub type WdtCvr1 = crate::Reg<wdt_cvr1::WdtCvr1Spec>;
#[doc = "WatchDog Counter Value 1"]
pub mod wdt_cvr1 {
#[doc = "Register `WDT_CVR1` reader"]
pub type R = crate::R<WdtCvr1Spec>;
#[doc = "Register `WDT_CVR1` writer"]
pub type W = crate::W<WdtCvr1Spec>;
#[doc = "Field `COUNT_VALUE_1` reader - Count Value for 2nd TimeOut"]
pub type CountValue1R = crate::FieldReader<u32>;
#[doc = "Field `COUNT_VALUE_1` writer - Count Value for 2nd TimeOut"]
pub type CountValue1W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Count Value for 2nd TimeOut"]
#[inline(always)]
pub fn count_value_1(&self) -> CountValue1R {
CountValue1R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Count Value for 2nd TimeOut"]
#[inline(always)]
#[must_use]
pub fn count_value_1(&mut self) -> CountValue1W<WdtCvr1Spec> {
CountValue1W::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCvr1Spec> {
RsvdW::new(self, 24)
}
}
#[doc = "WatchDog Counter Value 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCvr1Spec;
impl crate::RegisterSpec for WdtCvr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cvr1::R`](R) reader structure"]
impl crate::Readable for WdtCvr1Spec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cvr1::W`](W) writer structure"]
impl crate::Writable for WdtCvr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CVR1 to value 0"]
impl crate::Resettable for WdtCvr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CR (rw) register accessor: WatchDog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cr`]
module"]
#[doc(alias = "WDT_CR")]
pub type WdtCr = crate::Reg<wdt_cr::WdtCrSpec>;
#[doc = "WatchDog Control Register"]
pub mod wdt_cr {
#[doc = "Register `WDT_CR` reader"]
pub type R = crate::R<WdtCrSpec>;
#[doc = "Register `WDT_CR` writer"]
pub type W = crate::W<WdtCrSpec>;
#[doc = "Field `RESET_LENGTH` reader - reset pulse length in number of wdt clock cycles"]
pub type ResetLengthR = crate::FieldReader;
#[doc = "Field `RESET_LENGTH` writer - reset pulse length in number of wdt clock cycles"]
pub type ResetLengthW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RESPONSE_MODE` reader - 0:reset only, 1:interrupt and reset"]
pub type ResponseModeR = crate::BitReader;
#[doc = "Field `RESPONSE_MODE` writer - 0:reset only, 1:interrupt and reset"]
pub type ResponseModeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2 - reset pulse length in number of wdt clock cycles"]
#[inline(always)]
pub fn reset_length(&self) -> ResetLengthR {
ResetLengthR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 0:reset only, 1:interrupt and reset"]
#[inline(always)]
pub fn response_mode(&self) -> ResponseModeR {
ResponseModeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2 - reset pulse length in number of wdt clock cycles"]
#[inline(always)]
#[must_use]
pub fn reset_length(&mut self) -> ResetLengthW<WdtCrSpec> {
ResetLengthW::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<WdtCrSpec> {
Rsvd2W::new(self, 3)
}
#[doc = "Bit 4 - 0:reset only, 1:interrupt and reset"]
#[inline(always)]
#[must_use]
pub fn response_mode(&mut self) -> ResponseModeW<WdtCrSpec> {
ResponseModeW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "WatchDog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCrSpec;
impl crate::RegisterSpec for WdtCrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cr::R`](R) reader structure"]
impl crate::Readable for WdtCrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cr::W`](W) writer structure"]
impl crate::Writable for WdtCrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CR to value 0"]
impl crate::Resettable for WdtCrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CCR (rw) register accessor: WatchDog Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ccr`]
module"]
#[doc(alias = "WDT_CCR")]
pub type WdtCcr = crate::Reg<wdt_ccr::WdtCcrSpec>;
#[doc = "WatchDog Counter Control Register"]
pub mod wdt_ccr {
#[doc = "Register `WDT_CCR` reader"]
pub type R = crate::R<WdtCcrSpec>;
#[doc = "Register `WDT_CCR` writer"]
pub type W = crate::W<WdtCcrSpec>;
#[doc = "Field `COUNTER_CONTROL` reader - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
pub type CounterControlR = crate::FieldReader;
#[doc = "Field `COUNTER_CONTROL` writer - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
pub type CounterControlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
#[inline(always)]
pub fn counter_control(&self) -> CounterControlR {
CounterControlR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
#[inline(always)]
#[must_use]
pub fn counter_control(&mut self) -> CounterControlW<WdtCcrSpec> {
CounterControlW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "WatchDog Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCcrSpec;
impl crate::RegisterSpec for WdtCcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_ccr::R`](R) reader structure"]
impl crate::Readable for WdtCcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_ccr::W`](W) writer structure"]
impl crate::Writable for WdtCcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CCR to value 0"]
impl crate::Resettable for WdtCcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_ICR (rw) register accessor: WatchDog Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_icr`]
module"]
#[doc(alias = "WDT_ICR")]
pub type WdtIcr = crate::Reg<wdt_icr::WdtIcrSpec>;
#[doc = "WatchDog Interrupt Clear Register"]
pub mod wdt_icr {
#[doc = "Register `WDT_ICR` reader"]
pub type R = crate::R<WdtIcrSpec>;
#[doc = "Register `WDT_ICR` writer"]
pub type W = crate::W<WdtIcrSpec>;
#[doc = "Field `INT_CLR` reader - SinglePulse /A pulse to clear interrupt"]
pub type IntClrR = crate::BitReader;
#[doc = "Field `INT_CLR` writer - SinglePulse /A pulse to clear interrupt"]
pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - SinglePulse /A pulse to clear interrupt"]
#[inline(always)]
pub fn int_clr(&self) -> IntClrR {
IntClrR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SinglePulse /A pulse to clear interrupt"]
#[inline(always)]
#[must_use]
pub fn int_clr(&mut self) -> IntClrW<WdtIcrSpec> {
IntClrW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtIcrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "WatchDog Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtIcrSpec;
impl crate::RegisterSpec for WdtIcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_icr::R`](R) reader structure"]
impl crate::Readable for WdtIcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_icr::W`](W) writer structure"]
impl crate::Writable for WdtIcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_ICR to value 0"]
impl crate::Resettable for WdtIcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_SR (rw) register accessor: WatchDog Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_sr`]
module"]
#[doc(alias = "WDT_SR")]
pub type WdtSr = crate::Reg<wdt_sr::WdtSrSpec>;
#[doc = "WatchDog Status Register"]
pub mod wdt_sr {
#[doc = "Register `WDT_SR` reader"]
pub type R = crate::R<WdtSrSpec>;
#[doc = "Register `WDT_SR` writer"]
pub type W = crate::W<WdtSrSpec>;
#[doc = "Field `INT_ASSERT` reader - Interrupt assert when 1"]
pub type IntAssertR = crate::BitReader;
#[doc = "Field `INT_ASSERT` writer - Interrupt assert when 1"]
pub type IntAssertW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WDT_ACTIVE` reader - Watchdog runs when 1, else 0"]
pub type WdtActiveR = crate::BitReader;
#[doc = "Field `WDT_ACTIVE` writer - Watchdog runs when 1, else 0"]
pub type WdtActiveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - Interrupt assert when 1"]
#[inline(always)]
pub fn int_assert(&self) -> IntAssertR {
IntAssertR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Watchdog runs when 1, else 0"]
#[inline(always)]
pub fn wdt_active(&self) -> WdtActiveR {
WdtActiveR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Interrupt assert when 1"]
#[inline(always)]
#[must_use]
pub fn int_assert(&mut self) -> IntAssertW<WdtSrSpec> {
IntAssertW::new(self, 0)
}
#[doc = "Bit 1 - Watchdog runs when 1, else 0"]
#[inline(always)]
#[must_use]
pub fn wdt_active(&mut self) -> WdtActiveW<WdtSrSpec> {
WdtActiveW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtSrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "WatchDog Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtSrSpec;
impl crate::RegisterSpec for WdtSrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_sr::R`](R) reader structure"]
impl crate::Readable for WdtSrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_sr::W`](W) writer structure"]
impl crate::Writable for WdtSrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_SR to value 0"]
impl crate::Resettable for WdtSrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_WP (rw) register accessor: WatchDog Write Protect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_wp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_wp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_wp`]
module"]
#[doc(alias = "WDT_WP")]
pub type WdtWp = crate::Reg<wdt_wp::WdtWpSpec>;
#[doc = "WatchDog Write Protect Register"]
pub mod wdt_wp {
#[doc = "Register `WDT_WP` reader"]
pub type R = crate::R<WdtWpSpec>;
#[doc = "Register `WDT_WP` writer"]
pub type W = crate::W<WdtWpSpec>;
#[doc = "Field `WRPT` reader - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
pub type WrptR = crate::FieldReader<u32>;
#[doc = "Field `WRPT` writer - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
pub type WrptW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
#[doc = "Field `WRPT_ST` reader - 1 indicates write protect is active"]
pub type WrptStR = crate::BitReader;
#[doc = "Field `WRPT_ST` writer - 1 indicates write protect is active"]
pub type WrptStW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:30 - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
#[inline(always)]
pub fn wrpt(&self) -> WrptR {
WrptR::new(self.bits & 0x7fff_ffff)
}
#[doc = "Bit 31 - 1 indicates write protect is active"]
#[inline(always)]
pub fn wrpt_st(&self) -> WrptStR {
WrptStR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:30 - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
#[inline(always)]
#[must_use]
pub fn wrpt(&mut self) -> WrptW<WdtWpSpec> {
WrptW::new(self, 0)
}
#[doc = "Bit 31 - 1 indicates write protect is active"]
#[inline(always)]
#[must_use]
pub fn wrpt_st(&mut self) -> WrptStW<WdtWpSpec> {
WrptStW::new(self, 31)
}
}
#[doc = "WatchDog Write Protect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_wp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_wp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtWpSpec;
impl crate::RegisterSpec for WdtWpSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_wp::R`](R) reader structure"]
impl crate::Readable for WdtWpSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_wp::W`](W) writer structure"]
impl crate::Writable for WdtWpSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_WP to value 0"]
impl crate::Resettable for WdtWpSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_FG (rw) register accessor: WatchDog Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_fg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_fg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_fg`]
module"]
#[doc(alias = "WDT_FG")]
pub type WdtFg = crate::Reg<wdt_fg::WdtFgSpec>;
#[doc = "WatchDog Flag Register"]
pub mod wdt_fg {
#[doc = "Register `WDT_FG` reader"]
pub type R = crate::R<WdtFgSpec>;
#[doc = "Register `WDT_FG` writer"]
pub type W = crate::W<WdtFgSpec>;
#[doc = "Field `RST_FG_CLR` reader - SinglePulse/A pulse to clear reset flag"]
pub type RstFgClrR = crate::BitReader;
#[doc = "Field `RST_FG_CLR` writer - SinglePulse/A pulse to clear reset flag"]
pub type RstFgClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RST_FG` reader - 1 indicates wdt has already reset system"]
pub type RstFgR = crate::BitReader;
#[doc = "Field `RST_FG` writer - 1 indicates wdt has already reset system"]
pub type RstFgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYNC_FG_CLR` reader - SinglePulse/A pulse to clear sync flag"]
pub type SyncFgClrR = crate::BitReader;
#[doc = "Field `SYNC_FG_CLR` writer - SinglePulse/A pulse to clear sync flag"]
pub type SyncFgClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYNC_FG` reader - 1 indicates one transition from system clk to wdt clk has complicated"]
pub type SyncFgR = crate::BitReader;
#[doc = "Field `SYNC_FG` writer - 1 indicates one transition from system clk to wdt clk has complicated"]
pub type SyncFgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - SinglePulse/A pulse to clear reset flag"]
#[inline(always)]
pub fn rst_fg_clr(&self) -> RstFgClrR {
RstFgClrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1 indicates wdt has already reset system"]
#[inline(always)]
pub fn rst_fg(&self) -> RstFgR {
RstFgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SinglePulse/A pulse to clear sync flag"]
#[inline(always)]
pub fn sync_fg_clr(&self) -> SyncFgClrR {
SyncFgClrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 1 indicates one transition from system clk to wdt clk has complicated"]
#[inline(always)]
pub fn sync_fg(&self) -> SyncFgR {
SyncFgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SinglePulse/A pulse to clear reset flag"]
#[inline(always)]
#[must_use]
pub fn rst_fg_clr(&mut self) -> RstFgClrW<WdtFgSpec> {
RstFgClrW::new(self, 0)
}
#[doc = "Bit 1 - 1 indicates wdt has already reset system"]
#[inline(always)]
#[must_use]
pub fn rst_fg(&mut self) -> RstFgW<WdtFgSpec> {
RstFgW::new(self, 1)
}
#[doc = "Bit 2 - SinglePulse/A pulse to clear sync flag"]
#[inline(always)]
#[must_use]
pub fn sync_fg_clr(&mut self) -> SyncFgClrW<WdtFgSpec> {
SyncFgClrW::new(self, 2)
}
#[doc = "Bit 3 - 1 indicates one transition from system clk to wdt clk has complicated"]
#[inline(always)]
#[must_use]
pub fn sync_fg(&mut self) -> SyncFgW<WdtFgSpec> {
SyncFgW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtFgSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "WatchDog Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_fg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_fg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtFgSpec;
impl crate::RegisterSpec for WdtFgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_fg::R`](R) reader structure"]
impl crate::Readable for WdtFgSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_fg::W`](W) writer structure"]
impl crate::Writable for WdtFgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_FG to value 0"]
impl crate::Resettable for WdtFgSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "SPI1"]
pub struct Spi1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Spi1 {}
impl Spi1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const spi1::RegisterBlock = 0x5009_5000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const spi1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Spi1 {
type Target = spi1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Spi1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi1").finish()
}
}
#[doc = "SPI1"]
pub mod spi1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
top_ctrl: TopCtrl,
fifo_ctrl: FifoCtrl,
inte: Inte,
to: To,
data: Data,
status: Status,
rsvd3: Rsvd3,
_reserved7: [u8; 0x08],
rwot_ctrl: RwotCtrl,
rwot_ccm: RwotCcm,
rwot_cvwrn: RwotCvwrn,
rsvd2: Rsvd2,
_reserved11: [u8; 0x08],
clk_ctrl: ClkCtrl,
rsvd1: Rsvd1,
_reserved13: [u8; 0x10],
triwire_ctrl: TriwireCtrl,
}
impl RegisterBlock {
#[doc = "0x00 - Top Control Register"]
#[inline(always)]
pub const fn top_ctrl(&self) -> &TopCtrl {
&self.top_ctrl
}
#[doc = "0x04 - FIFO Control Register"]
#[inline(always)]
pub const fn fifo_ctrl(&self) -> &FifoCtrl {
&self.fifo_ctrl
}
#[doc = "0x08 - Interrupt Enable Register"]
#[inline(always)]
pub const fn inte(&self) -> &Inte {
&self.inte
}
#[doc = "0x0c - SPI Time Out Register"]
#[inline(always)]
pub const fn to(&self) -> &To {
&self.to
}
#[doc = "0x10 - SPI DATA Register"]
#[inline(always)]
pub const fn data(&self) -> &Data {
&self.data
}
#[doc = "0x14 - Status Register"]
#[inline(always)]
pub const fn status(&self) -> &Status {
&self.status
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn rsvd3(&self) -> &Rsvd3 {
&self.rsvd3
}
#[doc = "0x24 - SSP RWOT Control Register"]
#[inline(always)]
pub const fn rwot_ctrl(&self) -> &RwotCtrl {
&self.rwot_ctrl
}
#[doc = "0x28 - SSP RWOT Counter Cycles Match Register"]
#[inline(always)]
pub const fn rwot_ccm(&self) -> &RwotCcm {
&self.rwot_ccm
}
#[doc = "0x2c - SSP RWOT Counter Value Write for Red Request Register"]
#[inline(always)]
pub const fn rwot_cvwrn(&self) -> &RwotCvwrn {
&self.rwot_cvwrn
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn rsvd2(&self) -> &Rsvd2 {
&self.rsvd2
}
#[doc = "0x3c - SSP CLK Control Register"]
#[inline(always)]
pub const fn clk_ctrl(&self) -> &ClkCtrl {
&self.clk_ctrl
}
#[doc = "0x40 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x54 - SSP Three Wire Mode Control Register"]
#[inline(always)]
pub const fn triwire_ctrl(&self) -> &TriwireCtrl {
&self.triwire_ctrl
}
}
#[doc = "TOP_CTRL (rw) register accessor: Top Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`top_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@top_ctrl`]
module"]
#[doc(alias = "TOP_CTRL")]
pub type TopCtrl = crate::Reg<top_ctrl::TopCtrlSpec>;
#[doc = "Top Control Register"]
pub mod top_ctrl {
#[doc = "Register `TOP_CTRL` reader"]
pub type R = crate::R<TopCtrlSpec>;
#[doc = "Register `TOP_CTRL` writer"]
pub type W = crate::W<TopCtrlSpec>;
#[doc = "Field `SSE` reader - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
pub type SseR = crate::BitReader;
#[doc = "Field `SSE` writer - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
pub type SseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FRF` reader - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
pub type FrfR = crate::FieldReader;
#[doc = "Field `FRF` writer - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
pub type FrfW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SCLKDIR` reader - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
pub type SclkdirR = crate::BitReader;
#[doc = "Field `SCLKDIR` writer - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
pub type SclkdirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SFRMDIR` reader - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
pub type SfrmdirR = crate::BitReader;
#[doc = "Field `SFRMDIR` writer - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
pub type SfrmdirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DSS` reader - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
pub type DssR = crate::FieldReader;
#[doc = "Field `DSS` writer - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
pub type DssW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `SPO` reader - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
pub type SpoR = crate::BitReader;
#[doc = "Field `SPO` writer - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
pub type SpoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPH` reader - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
pub type SphR = crate::BitReader;
#[doc = "Field `SPH` writer - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
pub type SphW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRAIL` reader - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
pub type TrailR = crate::BitReader;
#[doc = "Field `TRAIL` writer - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
pub type TrailW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOLD_FRAME_LOW` reader - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
pub type HoldFrameLowR = crate::BitReader;
#[doc = "Field `HOLD_FRAME_LOW` writer - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
pub type HoldFrameLowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IFS` reader - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
pub type IfsR = crate::BitReader;
#[doc = "Field `IFS` writer - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
pub type IfsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCFR` reader - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
pub type ScfrR = crate::BitReader;
#[doc = "Field `SCFR` writer - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
pub type ScfrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TTE` reader - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
pub type TteR = crate::BitReader;
#[doc = "Field `TTE` writer - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
pub type TteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TTELP` reader - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
pub type TtelpR = crate::BitReader;
#[doc = "Field `TTELP` writer - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
pub type TtelpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
impl R {
#[doc = "Bit 0 - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
#[inline(always)]
pub fn sse(&self) -> SseR {
SseR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
#[inline(always)]
pub fn frf(&self) -> FrfR {
FrfR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3 - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
#[inline(always)]
pub fn sclkdir(&self) -> SclkdirR {
SclkdirR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
#[inline(always)]
pub fn sfrmdir(&self) -> SfrmdirR {
SfrmdirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:9 - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
#[inline(always)]
pub fn dss(&self) -> DssR {
DssR::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bit 10 - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
#[inline(always)]
pub fn spo(&self) -> SpoR {
SpoR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
#[inline(always)]
pub fn sph(&self) -> SphR {
SphR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
#[inline(always)]
pub fn trail(&self) -> TrailR {
TrailR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
#[inline(always)]
pub fn hold_frame_low(&self) -> HoldFrameLowR {
HoldFrameLowR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
#[inline(always)]
pub fn ifs(&self) -> IfsR {
IfsR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
#[inline(always)]
pub fn scfr(&self) -> ScfrR {
ScfrR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
#[inline(always)]
pub fn tte(&self) -> TteR {
TteR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
#[inline(always)]
pub fn ttelp(&self) -> TtelpR {
TtelpR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bits 19:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 19) & 0x1fff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
#[inline(always)]
#[must_use]
pub fn sse(&mut self) -> SseW<TopCtrlSpec> {
SseW::new(self, 0)
}
#[doc = "Bits 1:2 - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
#[inline(always)]
#[must_use]
pub fn frf(&mut self) -> FrfW<TopCtrlSpec> {
FrfW::new(self, 1)
}
#[doc = "Bit 3 - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
#[inline(always)]
#[must_use]
pub fn sclkdir(&mut self) -> SclkdirW<TopCtrlSpec> {
SclkdirW::new(self, 3)
}
#[doc = "Bit 4 - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
#[inline(always)]
#[must_use]
pub fn sfrmdir(&mut self) -> SfrmdirW<TopCtrlSpec> {
SfrmdirW::new(self, 4)
}
#[doc = "Bits 5:9 - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
#[inline(always)]
#[must_use]
pub fn dss(&mut self) -> DssW<TopCtrlSpec> {
DssW::new(self, 5)
}
#[doc = "Bit 10 - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
#[inline(always)]
#[must_use]
pub fn spo(&mut self) -> SpoW<TopCtrlSpec> {
SpoW::new(self, 10)
}
#[doc = "Bit 11 - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
#[inline(always)]
#[must_use]
pub fn sph(&mut self) -> SphW<TopCtrlSpec> {
SphW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<TopCtrlSpec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bit 13 - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
#[inline(always)]
#[must_use]
pub fn trail(&mut self) -> TrailW<TopCtrlSpec> {
TrailW::new(self, 13)
}
#[doc = "Bit 14 - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
#[inline(always)]
#[must_use]
pub fn hold_frame_low(&mut self) -> HoldFrameLowW<TopCtrlSpec> {
HoldFrameLowW::new(self, 14)
}
#[doc = "Bit 15 - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
#[inline(always)]
#[must_use]
pub fn ifs(&mut self) -> IfsW<TopCtrlSpec> {
IfsW::new(self, 15)
}
#[doc = "Bit 16 - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
#[inline(always)]
#[must_use]
pub fn scfr(&mut self) -> ScfrW<TopCtrlSpec> {
ScfrW::new(self, 16)
}
#[doc = "Bit 17 - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
#[inline(always)]
#[must_use]
pub fn tte(&mut self) -> TteW<TopCtrlSpec> {
TteW::new(self, 17)
}
#[doc = "Bit 18 - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
#[inline(always)]
#[must_use]
pub fn ttelp(&mut self) -> TtelpW<TopCtrlSpec> {
TtelpW::new(self, 18)
}
#[doc = "Bits 19:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TopCtrlSpec> {
RsvdW::new(self, 19)
}
}
#[doc = "Top Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`top_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TopCtrlSpec;
impl crate::RegisterSpec for TopCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`top_ctrl::R`](R) reader structure"]
impl crate::Readable for TopCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`top_ctrl::W`](W) writer structure"]
impl crate::Writable for TopCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TOP_CTRL to value 0"]
impl crate::Resettable for TopCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO_CTRL (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_ctrl`]
module"]
#[doc(alias = "FIFO_CTRL")]
pub type FifoCtrl = crate::Reg<fifo_ctrl::FifoCtrlSpec>;
#[doc = "FIFO Control Register"]
pub mod fifo_ctrl {
#[doc = "Register `FIFO_CTRL` reader"]
pub type R = crate::R<FifoCtrlSpec>;
#[doc = "Register `FIFO_CTRL` writer"]
pub type W = crate::W<FifoCtrlSpec>;
#[doc = "Field `TFT` reader - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type TftR = crate::FieldReader;
#[doc = "Field `TFT` writer - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type TftW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RFT` reader - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type RftR = crate::FieldReader;
#[doc = "Field `RFT` writer - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type RftW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `TSRE` reader - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type TsreR = crate::BitReader;
#[doc = "Field `TSRE` writer - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type TsreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSRE` reader - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type RsreR = crate::BitReader;
#[doc = "Field `RSRE` writer - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type RsreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXFIFO_RD_ENDIAN` reader - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
pub type RxfifoRdEndianR = crate::FieldReader;
#[doc = "Field `RXFIFO_RD_ENDIAN` writer - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
pub type RxfifoRdEndianW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `TXFIFO_WR_ENDIAN` reader - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
pub type TxfifoWrEndianR = crate::FieldReader;
#[doc = "Field `TXFIFO_WR_ENDIAN` writer - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
pub type TxfifoWrEndianW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `FPCKE` reader - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
pub type FpckeR = crate::BitReader;
#[doc = "Field `FPCKE` writer - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
pub type FpckeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXFIFO_AUTO_FULL_CTRL` reader - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
pub type RxfifoAutoFullCtrlR = crate::BitReader;
#[doc = "Field `RXFIFO_AUTO_FULL_CTRL` writer - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
pub type RxfifoAutoFullCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EFWR` reader - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
pub type EfwrR = crate::BitReader;
#[doc = "Field `EFWR` writer - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
pub type EfwrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STRF` reader - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
pub type StrfR = crate::BitReader;
#[doc = "Field `STRF` writer - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
pub type StrfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:4 - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
pub fn tft(&self) -> TftR {
TftR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9 - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
pub fn rft(&self) -> RftR {
RftR::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bit 10 - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
pub fn tsre(&self) -> TsreR {
TsreR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
pub fn rsre(&self) -> RsreR {
RsreR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
#[inline(always)]
pub fn rxfifo_rd_endian(&self) -> RxfifoRdEndianR {
RxfifoRdEndianR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
#[inline(always)]
pub fn txfifo_wr_endian(&self) -> TxfifoWrEndianR {
TxfifoWrEndianR::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bit 16 - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
#[inline(always)]
pub fn fpcke(&self) -> FpckeR {
FpckeR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
#[inline(always)]
pub fn rxfifo_auto_full_ctrl(&self) -> RxfifoAutoFullCtrlR {
RxfifoAutoFullCtrlR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
#[inline(always)]
pub fn efwr(&self) -> EfwrR {
EfwrR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
#[inline(always)]
pub fn strf(&self) -> StrfR {
StrfR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:4 - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
#[must_use]
pub fn tft(&mut self) -> TftW<FifoCtrlSpec> {
TftW::new(self, 0)
}
#[doc = "Bits 5:9 - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
#[must_use]
pub fn rft(&mut self) -> RftW<FifoCtrlSpec> {
RftW::new(self, 5)
}
#[doc = "Bit 10 - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
#[must_use]
pub fn tsre(&mut self) -> TsreW<FifoCtrlSpec> {
TsreW::new(self, 10)
}
#[doc = "Bit 11 - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
#[must_use]
pub fn rsre(&mut self) -> RsreW<FifoCtrlSpec> {
RsreW::new(self, 11)
}
#[doc = "Bits 12:13 - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
#[inline(always)]
#[must_use]
pub fn rxfifo_rd_endian(&mut self) -> RxfifoRdEndianW<FifoCtrlSpec> {
RxfifoRdEndianW::new(self, 12)
}
#[doc = "Bits 14:15 - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
#[inline(always)]
#[must_use]
pub fn txfifo_wr_endian(&mut self) -> TxfifoWrEndianW<FifoCtrlSpec> {
TxfifoWrEndianW::new(self, 14)
}
#[doc = "Bit 16 - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
#[inline(always)]
#[must_use]
pub fn fpcke(&mut self) -> FpckeW<FifoCtrlSpec> {
FpckeW::new(self, 16)
}
#[doc = "Bit 17 - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
#[inline(always)]
#[must_use]
pub fn rxfifo_auto_full_ctrl(&mut self) -> RxfifoAutoFullCtrlW<FifoCtrlSpec> {
RxfifoAutoFullCtrlW::new(self, 17)
}
#[doc = "Bit 18 - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
#[inline(always)]
#[must_use]
pub fn efwr(&mut self) -> EfwrW<FifoCtrlSpec> {
EfwrW::new(self, 18)
}
#[doc = "Bit 19 - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
#[inline(always)]
#[must_use]
pub fn strf(&mut self) -> StrfW<FifoCtrlSpec> {
StrfW::new(self, 19)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoCtrlSpec> {
RsvdW::new(self, 20)
}
}
#[doc = "FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoCtrlSpec;
impl crate::RegisterSpec for FifoCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo_ctrl::R`](R) reader structure"]
impl crate::Readable for FifoCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo_ctrl::W`](W) writer structure"]
impl crate::Writable for FifoCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO_CTRL to value 0"]
impl crate::Resettable for FifoCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTE (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inte`]
module"]
#[doc(alias = "INTE")]
pub type Inte = crate::Reg<inte::InteSpec>;
#[doc = "Interrupt Enable Register"]
pub mod inte {
#[doc = "Register `INTE` reader"]
pub type R = crate::R<InteSpec>;
#[doc = "Register `INTE` writer"]
pub type W = crate::W<InteSpec>;
#[doc = "Field `PINTE` reader - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
pub type PinteR = crate::BitReader;
#[doc = "Field `PINTE` writer - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
pub type PinteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TINTE` reader - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
pub type TinteR = crate::BitReader;
#[doc = "Field `TINTE` writer - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
pub type TinteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIE` reader - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
pub type RieR = crate::BitReader;
#[doc = "Field `RIE` writer - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
pub type RieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIE` reader - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
pub type TieR = crate::BitReader;
#[doc = "Field `TIE` writer - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
pub type TieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIM` reader - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
pub type RimR = crate::BitReader;
#[doc = "Field `RIM` writer - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
pub type RimW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIM` reader - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
pub type TimR = crate::BitReader;
#[doc = "Field `TIM` writer - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
pub type TimW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EBCEI` reader - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
pub type EbceiR = crate::BitReader;
#[doc = "Field `EBCEI` writer - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
pub type EbceiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>;
impl R {
#[doc = "Bit 0 - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
#[inline(always)]
pub fn pinte(&self) -> PinteR {
PinteR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
#[inline(always)]
pub fn tinte(&self) -> TinteR {
TinteR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
pub fn rie(&self) -> RieR {
RieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
pub fn tie(&self) -> TieR {
TieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
#[inline(always)]
pub fn rim(&self) -> RimR {
RimR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
#[inline(always)]
pub fn tim(&self) -> TimR {
TimR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
#[inline(always)]
pub fn ebcei(&self) -> EbceiR {
EbceiR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 7) & 0x01ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn pinte(&mut self) -> PinteW<InteSpec> {
PinteW::new(self, 0)
}
#[doc = "Bit 1 - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn tinte(&mut self) -> TinteW<InteSpec> {
TinteW::new(self, 1)
}
#[doc = "Bit 2 - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn rie(&mut self) -> RieW<InteSpec> {
RieW::new(self, 2)
}
#[doc = "Bit 3 - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn tie(&mut self) -> TieW<InteSpec> {
TieW::new(self, 3)
}
#[doc = "Bit 4 - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
#[inline(always)]
#[must_use]
pub fn rim(&mut self) -> RimW<InteSpec> {
RimW::new(self, 4)
}
#[doc = "Bit 5 - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
#[inline(always)]
#[must_use]
pub fn tim(&mut self) -> TimW<InteSpec> {
TimW::new(self, 5)
}
#[doc = "Bit 6 - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
#[inline(always)]
#[must_use]
pub fn ebcei(&mut self) -> EbceiW<InteSpec> {
EbceiW::new(self, 6)
}
#[doc = "Bits 7:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<InteSpec> {
RsvdW::new(self, 7)
}
}
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct InteSpec;
impl crate::RegisterSpec for InteSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`inte::R`](R) reader structure"]
impl crate::Readable for InteSpec {}
#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"]
impl crate::Writable for InteSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTE to value 0"]
impl crate::Resettable for InteSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TO (rw) register accessor: SPI Time Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@to`]
module"]
#[doc(alias = "TO")]
pub type To = crate::Reg<to::ToSpec>;
#[doc = "SPI Time Out Register"]
pub mod to {
#[doc = "Register `TO` reader"]
pub type R = crate::R<ToSpec>;
#[doc = "Register `TO` writer"]
pub type W = crate::W<ToSpec>;
#[doc = "Field `TIMEOUT` reader - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
pub type TimeoutR = crate::FieldReader<u32>;
#[doc = "Field `TIMEOUT` writer - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
pub type TimeoutW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
#[inline(always)]
pub fn timeout(&self) -> TimeoutR {
TimeoutR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
#[inline(always)]
#[must_use]
pub fn timeout(&mut self) -> TimeoutW<ToSpec> {
TimeoutW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ToSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "SPI Time Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ToSpec;
impl crate::RegisterSpec for ToSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`to::R`](R) reader structure"]
impl crate::Readable for ToSpec {}
#[doc = "`write(|w| ..)` method takes [`to::W`](W) writer structure"]
impl crate::Writable for ToSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TO to value 0"]
impl crate::Resettable for ToSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DATA (rw) register accessor: SPI DATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "SPI DATA Register"]
pub mod data {
#[doc = "Register `DATA` reader"]
pub type R = crate::R<DataSpec>;
#[doc = "Register `DATA` writer"]
pub type W = crate::W<DataSpec>;
#[doc = "Field `DATA` reader - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
pub type DataR = crate::FieldReader<u32>;
#[doc = "Field `DATA` writer - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DataSpec> {
DataW::new(self, 0)
}
}
#[doc = "SPI DATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data::R`](R) reader structure"]
impl crate::Readable for DataSpec {}
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
impl crate::Writable for DataSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DATA to value 0"]
impl crate::Resettable for DataSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "STATUS (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
#[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "Status Register"]
pub mod status {
#[doc = "Register `STATUS` reader"]
pub type R = crate::R<StatusSpec>;
#[doc = "Register `STATUS` writer"]
pub type W = crate::W<StatusSpec>;
#[doc = "Field `BSY` reader - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
pub type BsyR = crate::BitReader;
#[doc = "Field `BSY` writer - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
pub type BsyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CSS` reader - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
pub type CssR = crate::BitReader;
#[doc = "Field `CSS` writer - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
pub type CssW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINT` reader - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
pub type PintR = crate::BitReader;
#[doc = "Field `PINT` writer - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
pub type PintW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TINT` reader - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
pub type TintR = crate::BitReader;
#[doc = "Field `TINT` writer - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
pub type TintW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EOC` reader - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
pub type EocR = crate::BitReader;
#[doc = "Field `EOC` writer - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
pub type EocW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TFS` reader - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
pub type TfsR = crate::BitReader;
#[doc = "Field `TFS` writer - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
pub type TfsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TNF` reader - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
pub type TnfR = crate::BitReader;
#[doc = "Field `TNF` writer - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
pub type TnfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TFL` reader - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
pub type TflR = crate::FieldReader;
#[doc = "Field `TFL` writer - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
pub type TflW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TUR` reader - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
pub type TurR = crate::BitReader;
#[doc = "Field `TUR` writer - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
pub type TurW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFS` reader - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
pub type RfsR = crate::BitReader;
#[doc = "Field `RFS` writer - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
pub type RfsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RNE` reader - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
pub type RneR = crate::BitReader;
#[doc = "Field `RNE` writer - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
pub type RneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFL` reader - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
pub type RflR = crate::FieldReader;
#[doc = "Field `RFL` writer - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
pub type RflW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ROR` reader - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
pub type RorR = crate::BitReader;
#[doc = "Field `ROR` writer - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
pub type RorW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BCE` reader - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
pub type BceR = crate::BitReader;
#[doc = "Field `BCE` writer - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
pub type BceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX_OSS` reader - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
pub type TxOssR = crate::BitReader;
#[doc = "Field `TX_OSS` writer - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
pub type TxOssW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OSS` reader - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
pub type OssR = crate::BitReader;
#[doc = "Field `OSS` writer - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
pub type OssW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bit 0 - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
#[inline(always)]
pub fn bsy(&self) -> BsyR {
BsyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
#[inline(always)]
pub fn css(&self) -> CssR {
CssR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
#[inline(always)]
pub fn pint(&self) -> PintR {
PintR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
#[inline(always)]
pub fn tint(&self) -> TintR {
TintR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
#[inline(always)]
pub fn eoc(&self) -> EocR {
EocR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
#[inline(always)]
pub fn tfs(&self) -> TfsR {
TfsR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
#[inline(always)]
pub fn tnf(&self) -> TnfR {
TnfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:10 - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
#[inline(always)]
pub fn tfl(&self) -> TflR {
TflR::new(((self.bits >> 7) & 0x0f) as u8)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
#[inline(always)]
pub fn tur(&self) -> TurR {
TurR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
#[inline(always)]
pub fn rfs(&self) -> RfsR {
RfsR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
#[inline(always)]
pub fn rne(&self) -> RneR {
RneR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:18 - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
#[inline(always)]
pub fn rfl(&self) -> RflR {
RflR::new(((self.bits >> 15) & 0x0f) as u8)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
#[inline(always)]
pub fn ror(&self) -> RorR {
RorR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
#[inline(always)]
pub fn bce(&self) -> BceR {
BceR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
#[inline(always)]
pub fn tx_oss(&self) -> TxOssR {
TxOssR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
#[inline(always)]
pub fn oss(&self) -> OssR {
OssR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0 - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
#[inline(always)]
#[must_use]
pub fn bsy(&mut self) -> BsyW<StatusSpec> {
BsyW::new(self, 0)
}
#[doc = "Bit 1 - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
#[inline(always)]
#[must_use]
pub fn css(&mut self) -> CssW<StatusSpec> {
CssW::new(self, 1)
}
#[doc = "Bit 2 - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
#[inline(always)]
#[must_use]
pub fn pint(&mut self) -> PintW<StatusSpec> {
PintW::new(self, 2)
}
#[doc = "Bit 3 - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn tint(&mut self) -> TintW<StatusSpec> {
TintW::new(self, 3)
}
#[doc = "Bit 4 - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
#[inline(always)]
#[must_use]
pub fn eoc(&mut self) -> EocW<StatusSpec> {
EocW::new(self, 4)
}
#[doc = "Bit 5 - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn tfs(&mut self) -> TfsW<StatusSpec> {
TfsW::new(self, 5)
}
#[doc = "Bit 6 - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
#[inline(always)]
#[must_use]
pub fn tnf(&mut self) -> TnfW<StatusSpec> {
TnfW::new(self, 6)
}
#[doc = "Bits 7:10 - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
#[inline(always)]
#[must_use]
pub fn tfl(&mut self) -> TflW<StatusSpec> {
TflW::new(self, 7)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<StatusSpec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bit 12 - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
#[inline(always)]
#[must_use]
pub fn tur(&mut self) -> TurW<StatusSpec> {
TurW::new(self, 12)
}
#[doc = "Bit 13 - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn rfs(&mut self) -> RfsW<StatusSpec> {
RfsW::new(self, 13)
}
#[doc = "Bit 14 - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
#[inline(always)]
#[must_use]
pub fn rne(&mut self) -> RneW<StatusSpec> {
RneW::new(self, 14)
}
#[doc = "Bits 15:18 - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
#[inline(always)]
#[must_use]
pub fn rfl(&mut self) -> RflW<StatusSpec> {
RflW::new(self, 15)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<StatusSpec> {
Rsvd2W::new(self, 19)
}
#[doc = "Bit 20 - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn ror(&mut self) -> RorW<StatusSpec> {
RorW::new(self, 20)
}
#[doc = "Bit 21 - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
#[inline(always)]
#[must_use]
pub fn bce(&mut self) -> BceW<StatusSpec> {
BceW::new(self, 21)
}
#[doc = "Bit 22 - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
#[inline(always)]
#[must_use]
pub fn tx_oss(&mut self) -> TxOssW<StatusSpec> {
TxOssW::new(self, 22)
}
#[doc = "Bit 23 - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
#[inline(always)]
#[must_use]
pub fn oss(&mut self) -> OssW<StatusSpec> {
OssW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<StatusSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`status::R`](R) reader structure"]
impl crate::Readable for StatusSpec {}
#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
impl crate::Writable for StatusSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets STATUS to value 0"]
impl crate::Resettable for StatusSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd3`]
module"]
#[doc(alias = "RSVD3")]
pub type Rsvd3 = crate::Reg<rsvd3::Rsvd3Spec>;
#[doc = ""]
pub mod rsvd3 {
#[doc = "Register `RSVD3` reader"]
pub type R = crate::R<Rsvd3Spec>;
#[doc = "Register `RSVD3` writer"]
pub type W = crate::W<Rsvd3Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd3Spec;
impl crate::RegisterSpec for Rsvd3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd3::R`](R) reader structure"]
impl crate::Readable for Rsvd3Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd3::W`](W) writer structure"]
impl crate::Writable for Rsvd3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD3 to value 0"]
impl crate::Resettable for Rsvd3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RWOT_CTRL (rw) register accessor: SSP RWOT Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwot_ctrl`]
module"]
#[doc(alias = "RWOT_CTRL")]
pub type RwotCtrl = crate::Reg<rwot_ctrl::RwotCtrlSpec>;
#[doc = "SSP RWOT Control Register"]
pub mod rwot_ctrl {
#[doc = "Register `RWOT_CTRL` reader"]
pub type R = crate::R<RwotCtrlSpec>;
#[doc = "Register `RWOT_CTRL` writer"]
pub type W = crate::W<RwotCtrlSpec>;
#[doc = "Field `RWOT` reader - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
pub type RwotR = crate::BitReader;
#[doc = "Field `RWOT` writer - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
pub type RwotW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CYCLE_RWOT_EN` reader - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
pub type CycleRwotEnR = crate::BitReader;
#[doc = "Field `CYCLE_RWOT_EN` writer - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
pub type CycleRwotEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SET_RWOT_CYCLE` reader - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
pub type SetRwotCycleR = crate::BitReader;
#[doc = "Field `SET_RWOT_CYCLE` writer - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
pub type SetRwotCycleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR_RWOT_CYCLE` reader - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
pub type ClrRwotCycleR = crate::BitReader;
#[doc = "Field `CLR_RWOT_CYCLE` writer - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
pub type ClrRwotCycleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK_RWOT_LAST_SAMPLE` reader - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
pub type MaskRwotLastSampleR = crate::BitReader;
#[doc = "Field `MASK_RWOT_LAST_SAMPLE` writer - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
pub type MaskRwotLastSampleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bit 0 - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
#[inline(always)]
pub fn rwot(&self) -> RwotR {
RwotR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
#[inline(always)]
pub fn cycle_rwot_en(&self) -> CycleRwotEnR {
CycleRwotEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
#[inline(always)]
pub fn set_rwot_cycle(&self) -> SetRwotCycleR {
SetRwotCycleR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
#[inline(always)]
pub fn clr_rwot_cycle(&self) -> ClrRwotCycleR {
ClrRwotCycleR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
#[inline(always)]
pub fn mask_rwot_last_sample(&self) -> MaskRwotLastSampleR {
MaskRwotLastSampleR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
#[inline(always)]
#[must_use]
pub fn rwot(&mut self) -> RwotW<RwotCtrlSpec> {
RwotW::new(self, 0)
}
#[doc = "Bit 1 - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
#[inline(always)]
#[must_use]
pub fn cycle_rwot_en(&mut self) -> CycleRwotEnW<RwotCtrlSpec> {
CycleRwotEnW::new(self, 1)
}
#[doc = "Bit 2 - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
#[inline(always)]
#[must_use]
pub fn set_rwot_cycle(&mut self) -> SetRwotCycleW<RwotCtrlSpec> {
SetRwotCycleW::new(self, 2)
}
#[doc = "Bit 3 - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
#[inline(always)]
#[must_use]
pub fn clr_rwot_cycle(&mut self) -> ClrRwotCycleW<RwotCtrlSpec> {
ClrRwotCycleW::new(self, 3)
}
#[doc = "Bit 4 - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
#[inline(always)]
#[must_use]
pub fn mask_rwot_last_sample(&mut self) -> MaskRwotLastSampleW<RwotCtrlSpec> {
MaskRwotLastSampleW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RwotCtrlSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "SSP RWOT Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RwotCtrlSpec;
impl crate::RegisterSpec for RwotCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rwot_ctrl::R`](R) reader structure"]
impl crate::Readable for RwotCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`rwot_ctrl::W`](W) writer structure"]
impl crate::Writable for RwotCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RWOT_CTRL to value 0"]
impl crate::Resettable for RwotCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RWOT_CCM (rw) register accessor: SSP RWOT Counter Cycles Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ccm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ccm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwot_ccm`]
module"]
#[doc(alias = "RWOT_CCM")]
pub type RwotCcm = crate::Reg<rwot_ccm::RwotCcmSpec>;
#[doc = "SSP RWOT Counter Cycles Match Register"]
pub mod rwot_ccm {
#[doc = "Register `RWOT_CCM` reader"]
pub type R = crate::R<RwotCcmSpec>;
#[doc = "Register `RWOT_CCM` writer"]
pub type W = crate::W<RwotCcmSpec>;
#[doc = "Field `SSPRWOTCCM` reader - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
pub type SsprwotccmR = crate::FieldReader<u32>;
#[doc = "Field `SSPRWOTCCM` writer - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
pub type SsprwotccmW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
#[inline(always)]
pub fn ssprwotccm(&self) -> SsprwotccmR {
SsprwotccmR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
#[inline(always)]
#[must_use]
pub fn ssprwotccm(&mut self) -> SsprwotccmW<RwotCcmSpec> {
SsprwotccmW::new(self, 0)
}
}
#[doc = "SSP RWOT Counter Cycles Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ccm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ccm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RwotCcmSpec;
impl crate::RegisterSpec for RwotCcmSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rwot_ccm::R`](R) reader structure"]
impl crate::Readable for RwotCcmSpec {}
#[doc = "`write(|w| ..)` method takes [`rwot_ccm::W`](W) writer structure"]
impl crate::Writable for RwotCcmSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RWOT_CCM to value 0"]
impl crate::Resettable for RwotCcmSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RWOT_CVWRN (rw) register accessor: SSP RWOT Counter Value Write for Red Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_cvwrn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_cvwrn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwot_cvwrn`]
module"]
#[doc(alias = "RWOT_CVWRN")]
pub type RwotCvwrn = crate::Reg<rwot_cvwrn::RwotCvwrnSpec>;
#[doc = "SSP RWOT Counter Value Write for Red Request Register"]
pub mod rwot_cvwrn {
#[doc = "Register `RWOT_CVWRN` reader"]
pub type R = crate::R<RwotCvwrnSpec>;
#[doc = "Register `RWOT_CVWRN` writer"]
pub type W = crate::W<RwotCvwrnSpec>;
#[doc = "Field `SSPRWOTCVWR` reader - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
pub type SsprwotcvwrR = crate::FieldReader<u32>;
#[doc = "Field `SSPRWOTCVWR` writer - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
pub type SsprwotcvwrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
#[inline(always)]
pub fn ssprwotcvwr(&self) -> SsprwotcvwrR {
SsprwotcvwrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
#[inline(always)]
#[must_use]
pub fn ssprwotcvwr(&mut self) -> SsprwotcvwrW<RwotCvwrnSpec> {
SsprwotcvwrW::new(self, 0)
}
}
#[doc = "SSP RWOT Counter Value Write for Red Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_cvwrn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_cvwrn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RwotCvwrnSpec;
impl crate::RegisterSpec for RwotCvwrnSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rwot_cvwrn::R`](R) reader structure"]
impl crate::Readable for RwotCvwrnSpec {}
#[doc = "`write(|w| ..)` method takes [`rwot_cvwrn::W`](W) writer structure"]
impl crate::Writable for RwotCvwrnSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RWOT_CVWRN to value 0"]
impl crate::Resettable for RwotCvwrnSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd2`]
module"]
#[doc(alias = "RSVD2")]
pub type Rsvd2 = crate::Reg<rsvd2::Rsvd2Spec>;
#[doc = ""]
pub mod rsvd2 {
#[doc = "Register `RSVD2` reader"]
pub type R = crate::R<Rsvd2Spec>;
#[doc = "Register `RSVD2` writer"]
pub type W = crate::W<Rsvd2Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd2Spec;
impl crate::RegisterSpec for Rsvd2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd2::R`](R) reader structure"]
impl crate::Readable for Rsvd2Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd2::W`](W) writer structure"]
impl crate::Writable for Rsvd2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD2 to value 0"]
impl crate::Resettable for Rsvd2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CLK_CTRL (rw) register accessor: SSP CLK Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ctrl`]
module"]
#[doc(alias = "CLK_CTRL")]
pub type ClkCtrl = crate::Reg<clk_ctrl::ClkCtrlSpec>;
#[doc = "SSP CLK Control Register"]
pub mod clk_ctrl {
#[doc = "Register `CLK_CTRL` reader"]
pub type R = crate::R<ClkCtrlSpec>;
#[doc = "Register `CLK_CTRL` writer"]
pub type W = crate::W<ClkCtrlSpec>;
#[doc = "Field `CLK_DIV` reader - div ratio from clk_sys"]
pub type ClkDivR = crate::FieldReader;
#[doc = "Field `CLK_DIV` writer - div ratio from clk_sys"]
pub type ClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `CLK_SEL` reader - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
pub type ClkSelR = crate::BitReader;
#[doc = "Field `CLK_SEL` writer - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
pub type ClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_SSP_EN` reader - "]
pub type ClkSspEnR = crate::BitReader;
#[doc = "Field `CLK_SSP_EN` writer - "]
pub type ClkSspEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_DI_SEL` reader - Select spi_di source. 0: from port DI. 1: from port DIO."]
pub type SpiDiSelR = crate::BitReader;
#[doc = "Field `SPI_DI_SEL` writer - Select spi_di source. 0: from port DI. 1: from port DIO."]
pub type SpiDiSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bits 0:6 - div ratio from clk_sys"]
#[inline(always)]
pub fn clk_div(&self) -> ClkDivR {
ClkDivR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bit 7 - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
#[inline(always)]
pub fn clk_sel(&self) -> ClkSelR {
ClkSelR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn clk_ssp_en(&self) -> ClkSspEnR {
ClkSspEnR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Select spi_di source. 0: from port DI. 1: from port DIO."]
#[inline(always)]
pub fn spi_di_sel(&self) -> SpiDiSelR {
SpiDiSelR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bits 0:6 - div ratio from clk_sys"]
#[inline(always)]
#[must_use]
pub fn clk_div(&mut self) -> ClkDivW<ClkCtrlSpec> {
ClkDivW::new(self, 0)
}
#[doc = "Bit 7 - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
#[inline(always)]
#[must_use]
pub fn clk_sel(&mut self) -> ClkSelW<ClkCtrlSpec> {
ClkSelW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn clk_ssp_en(&mut self) -> ClkSspEnW<ClkCtrlSpec> {
ClkSspEnW::new(self, 8)
}
#[doc = "Bit 9 - Select spi_di source. 0: from port DI. 1: from port DIO."]
#[inline(always)]
#[must_use]
pub fn spi_di_sel(&mut self) -> SpiDiSelW<ClkCtrlSpec> {
SpiDiSelW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ClkCtrlSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "SSP CLK Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkCtrlSpec;
impl crate::RegisterSpec for ClkCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`clk_ctrl::R`](R) reader structure"]
impl crate::Readable for ClkCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`clk_ctrl::W`](W) writer structure"]
impl crate::Writable for ClkCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CLK_CTRL to value 0"]
impl crate::Resettable for ClkCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TRIWIRE_CTRL (rw) register accessor: SSP Three Wire Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`triwire_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`triwire_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@triwire_ctrl`]
module"]
#[doc(alias = "TRIWIRE_CTRL")]
pub type TriwireCtrl = crate::Reg<triwire_ctrl::TriwireCtrlSpec>;
#[doc = "SSP Three Wire Mode Control Register"]
pub mod triwire_ctrl {
#[doc = "Register `TRIWIRE_CTRL` reader"]
pub type R = crate::R<TriwireCtrlSpec>;
#[doc = "Register `TRIWIRE_CTRL` writer"]
pub type W = crate::W<TriwireCtrlSpec>;
#[doc = "Field `SPI_TRI_WIRE_EN` reader - SPI_THREE_WIRE_MODE_EN 1=enable"]
pub type SpiTriWireEnR = crate::BitReader;
#[doc = "Field `SPI_TRI_WIRE_EN` writer - SPI_THREE_WIRE_MODE_EN 1=enable"]
pub type SpiTriWireEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXD_OEN` reader - TXD_OEN 1=TXD is input 0=TXD is output"]
pub type TxdOenR = crate::BitReader;
#[doc = "Field `TXD_OEN` writer - TXD_OEN 1=TXD is input 0=TXD is output"]
pub type TxdOenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SSP_WORK_WIDTH_DYN_CHANGE` reader - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
pub type SspWorkWidthDynChangeR = crate::BitReader;
#[doc = "Field `SSP_WORK_WIDTH_DYN_CHANGE` writer - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
pub type SspWorkWidthDynChangeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bit 0 - SPI_THREE_WIRE_MODE_EN 1=enable"]
#[inline(always)]
pub fn spi_tri_wire_en(&self) -> SpiTriWireEnR {
SpiTriWireEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TXD_OEN 1=TXD is input 0=TXD is output"]
#[inline(always)]
pub fn txd_oen(&self) -> TxdOenR {
TxdOenR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
#[inline(always)]
pub fn ssp_work_width_dyn_change(&self) -> SspWorkWidthDynChangeR {
SspWorkWidthDynChangeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SPI_THREE_WIRE_MODE_EN 1=enable"]
#[inline(always)]
#[must_use]
pub fn spi_tri_wire_en(&mut self) -> SpiTriWireEnW<TriwireCtrlSpec> {
SpiTriWireEnW::new(self, 0)
}
#[doc = "Bit 1 - TXD_OEN 1=TXD is input 0=TXD is output"]
#[inline(always)]
#[must_use]
pub fn txd_oen(&mut self) -> TxdOenW<TriwireCtrlSpec> {
TxdOenW::new(self, 1)
}
#[doc = "Bit 2 - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
#[inline(always)]
#[must_use]
pub fn ssp_work_width_dyn_change(&mut self) -> SspWorkWidthDynChangeW<TriwireCtrlSpec> {
SspWorkWidthDynChangeW::new(self, 2)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TriwireCtrlSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "SSP Three Wire Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`triwire_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`triwire_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TriwireCtrlSpec;
impl crate::RegisterSpec for TriwireCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`triwire_ctrl::R`](R) reader structure"]
impl crate::Readable for TriwireCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`triwire_ctrl::W`](W) writer structure"]
impl crate::Writable for TriwireCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TRIWIRE_CTRL to value 0"]
impl crate::Resettable for TriwireCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "SPI2"]
pub struct Spi2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Spi2 {}
impl Spi2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const spi2::RegisterBlock = 0x5009_6000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const spi2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Spi2 {
type Target = spi2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Spi2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi2").finish()
}
}
#[doc = "SPI2"]
pub mod spi2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
top_ctrl: TopCtrl,
fifo_ctrl: FifoCtrl,
inte: Inte,
to: To,
data: Data,
status: Status,
rsvd3: Rsvd3,
_reserved7: [u8; 0x08],
rwot_ctrl: RwotCtrl,
rwot_ccm: RwotCcm,
rwot_cvwrn: RwotCvwrn,
rsvd2: Rsvd2,
_reserved11: [u8; 0x08],
clk_ctrl: ClkCtrl,
rsvd1: Rsvd1,
_reserved13: [u8; 0x10],
triwire_ctrl: TriwireCtrl,
}
impl RegisterBlock {
#[doc = "0x00 - Top Control Register"]
#[inline(always)]
pub const fn top_ctrl(&self) -> &TopCtrl {
&self.top_ctrl
}
#[doc = "0x04 - FIFO Control Register"]
#[inline(always)]
pub const fn fifo_ctrl(&self) -> &FifoCtrl {
&self.fifo_ctrl
}
#[doc = "0x08 - Interrupt Enable Register"]
#[inline(always)]
pub const fn inte(&self) -> &Inte {
&self.inte
}
#[doc = "0x0c - SPI Time Out Register"]
#[inline(always)]
pub const fn to(&self) -> &To {
&self.to
}
#[doc = "0x10 - SPI DATA Register"]
#[inline(always)]
pub const fn data(&self) -> &Data {
&self.data
}
#[doc = "0x14 - Status Register"]
#[inline(always)]
pub const fn status(&self) -> &Status {
&self.status
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn rsvd3(&self) -> &Rsvd3 {
&self.rsvd3
}
#[doc = "0x24 - SSP RWOT Control Register"]
#[inline(always)]
pub const fn rwot_ctrl(&self) -> &RwotCtrl {
&self.rwot_ctrl
}
#[doc = "0x28 - SSP RWOT Counter Cycles Match Register"]
#[inline(always)]
pub const fn rwot_ccm(&self) -> &RwotCcm {
&self.rwot_ccm
}
#[doc = "0x2c - SSP RWOT Counter Value Write for Red Request Register"]
#[inline(always)]
pub const fn rwot_cvwrn(&self) -> &RwotCvwrn {
&self.rwot_cvwrn
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn rsvd2(&self) -> &Rsvd2 {
&self.rsvd2
}
#[doc = "0x3c - SSP CLK Control Register"]
#[inline(always)]
pub const fn clk_ctrl(&self) -> &ClkCtrl {
&self.clk_ctrl
}
#[doc = "0x40 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x54 - SSP Three Wire Mode Control Register"]
#[inline(always)]
pub const fn triwire_ctrl(&self) -> &TriwireCtrl {
&self.triwire_ctrl
}
}
#[doc = "TOP_CTRL (rw) register accessor: Top Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`top_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@top_ctrl`]
module"]
#[doc(alias = "TOP_CTRL")]
pub type TopCtrl = crate::Reg<top_ctrl::TopCtrlSpec>;
#[doc = "Top Control Register"]
pub mod top_ctrl {
#[doc = "Register `TOP_CTRL` reader"]
pub type R = crate::R<TopCtrlSpec>;
#[doc = "Register `TOP_CTRL` writer"]
pub type W = crate::W<TopCtrlSpec>;
#[doc = "Field `SSE` reader - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
pub type SseR = crate::BitReader;
#[doc = "Field `SSE` writer - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
pub type SseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FRF` reader - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
pub type FrfR = crate::FieldReader;
#[doc = "Field `FRF` writer - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
pub type FrfW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SCLKDIR` reader - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
pub type SclkdirR = crate::BitReader;
#[doc = "Field `SCLKDIR` writer - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
pub type SclkdirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SFRMDIR` reader - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
pub type SfrmdirR = crate::BitReader;
#[doc = "Field `SFRMDIR` writer - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
pub type SfrmdirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DSS` reader - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
pub type DssR = crate::FieldReader;
#[doc = "Field `DSS` writer - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
pub type DssW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `SPO` reader - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
pub type SpoR = crate::BitReader;
#[doc = "Field `SPO` writer - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
pub type SpoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPH` reader - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
pub type SphR = crate::BitReader;
#[doc = "Field `SPH` writer - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
pub type SphW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRAIL` reader - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
pub type TrailR = crate::BitReader;
#[doc = "Field `TRAIL` writer - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
pub type TrailW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOLD_FRAME_LOW` reader - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
pub type HoldFrameLowR = crate::BitReader;
#[doc = "Field `HOLD_FRAME_LOW` writer - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
pub type HoldFrameLowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IFS` reader - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
pub type IfsR = crate::BitReader;
#[doc = "Field `IFS` writer - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
pub type IfsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCFR` reader - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
pub type ScfrR = crate::BitReader;
#[doc = "Field `SCFR` writer - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
pub type ScfrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TTE` reader - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
pub type TteR = crate::BitReader;
#[doc = "Field `TTE` writer - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
pub type TteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TTELP` reader - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
pub type TtelpR = crate::BitReader;
#[doc = "Field `TTELP` writer - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
pub type TtelpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
impl R {
#[doc = "Bit 0 - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
#[inline(always)]
pub fn sse(&self) -> SseR {
SseR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
#[inline(always)]
pub fn frf(&self) -> FrfR {
FrfR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3 - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
#[inline(always)]
pub fn sclkdir(&self) -> SclkdirR {
SclkdirR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
#[inline(always)]
pub fn sfrmdir(&self) -> SfrmdirR {
SfrmdirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:9 - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
#[inline(always)]
pub fn dss(&self) -> DssR {
DssR::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bit 10 - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
#[inline(always)]
pub fn spo(&self) -> SpoR {
SpoR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
#[inline(always)]
pub fn sph(&self) -> SphR {
SphR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
#[inline(always)]
pub fn trail(&self) -> TrailR {
TrailR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
#[inline(always)]
pub fn hold_frame_low(&self) -> HoldFrameLowR {
HoldFrameLowR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
#[inline(always)]
pub fn ifs(&self) -> IfsR {
IfsR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
#[inline(always)]
pub fn scfr(&self) -> ScfrR {
ScfrR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
#[inline(always)]
pub fn tte(&self) -> TteR {
TteR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
#[inline(always)]
pub fn ttelp(&self) -> TtelpR {
TtelpR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bits 19:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 19) & 0x1fff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled"]
#[inline(always)]
#[must_use]
pub fn sse(&mut self) -> SseW<TopCtrlSpec> {
SseW::new(self, 0)
}
#[doc = "Bits 1:2 - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)"]
#[inline(always)]
#[must_use]
pub fn frf(&mut self) -> FrfW<TopCtrlSpec> {
FrfW::new(self, 1)
}
#[doc = "Bit 3 - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx"]
#[inline(always)]
#[must_use]
pub fn sclkdir(&mut self) -> SclkdirW<TopCtrlSpec> {
SclkdirW::new(self, 3)
}
#[doc = "Bit 4 - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx"]
#[inline(always)]
#[must_use]
pub fn sfrmdir(&mut self) -> SfrmdirW<TopCtrlSpec> {
SfrmdirW::new(self, 4)
}
#[doc = "Bits 5:9 - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits"]
#[inline(always)]
#[must_use]
pub fn dss(&mut self) -> DssW<TopCtrlSpec> {
DssW::new(self, 5)
}
#[doc = "Bit 10 - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high"]
#[inline(always)]
#[must_use]
pub fn spo(&mut self) -> SpoW<TopCtrlSpec> {
SpoW::new(self, 10)
}
#[doc = "Bit 11 - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame"]
#[inline(always)]
#[must_use]
pub fn sph(&mut self) -> SphW<TopCtrlSpec> {
SphW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<TopCtrlSpec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bit 13 - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts"]
#[inline(always)]
#[must_use]
pub fn trail(&mut self) -> TrailW<TopCtrlSpec> {
TrailW::new(self, 13)
}
#[doc = "Bit 14 - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there's no bit clock, or the data transfers before the stop clock will be discarded."]
#[inline(always)]
#[must_use]
pub fn hold_frame_low(&mut self) -> HoldFrameLowW<TopCtrlSpec> {
HoldFrameLowW::new(self, 14)
}
#[doc = "Bit 15 - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)"]
#[inline(always)]
#[must_use]
pub fn ifs(&mut self) -> IfsW<TopCtrlSpec> {
IfsW::new(self, 15)
}
#[doc = "Bit 16 - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers."]
#[inline(always)]
#[must_use]
pub fn scfr(&mut self) -> ScfrW<TopCtrlSpec> {
ScfrW::new(self, 16)
}
#[doc = "Bit 17 - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data"]
#[inline(always)]
#[must_use]
pub fn tte(&mut self) -> TteW<TopCtrlSpec> {
TteW::new(self, 17)
}
#[doc = "Bit 18 - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB"]
#[inline(always)]
#[must_use]
pub fn ttelp(&mut self) -> TtelpW<TopCtrlSpec> {
TtelpW::new(self, 18)
}
#[doc = "Bits 19:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TopCtrlSpec> {
RsvdW::new(self, 19)
}
}
#[doc = "Top Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`top_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TopCtrlSpec;
impl crate::RegisterSpec for TopCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`top_ctrl::R`](R) reader structure"]
impl crate::Readable for TopCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`top_ctrl::W`](W) writer structure"]
impl crate::Writable for TopCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TOP_CTRL to value 0"]
impl crate::Resettable for TopCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO_CTRL (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_ctrl`]
module"]
#[doc(alias = "FIFO_CTRL")]
pub type FifoCtrl = crate::Reg<fifo_ctrl::FifoCtrlSpec>;
#[doc = "FIFO Control Register"]
pub mod fifo_ctrl {
#[doc = "Register `FIFO_CTRL` reader"]
pub type R = crate::R<FifoCtrlSpec>;
#[doc = "Register `FIFO_CTRL` writer"]
pub type W = crate::W<FifoCtrlSpec>;
#[doc = "Field `TFT` reader - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type TftR = crate::FieldReader;
#[doc = "Field `TFT` writer - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type TftW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `RFT` reader - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type RftR = crate::FieldReader;
#[doc = "Field `RFT` writer - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
pub type RftW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `TSRE` reader - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type TsreR = crate::BitReader;
#[doc = "Field `TSRE` writer - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type TsreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSRE` reader - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type RsreR = crate::BitReader;
#[doc = "Field `RSRE` writer - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
pub type RsreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXFIFO_RD_ENDIAN` reader - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
pub type RxfifoRdEndianR = crate::FieldReader;
#[doc = "Field `RXFIFO_RD_ENDIAN` writer - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
pub type RxfifoRdEndianW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `TXFIFO_WR_ENDIAN` reader - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
pub type TxfifoWrEndianR = crate::FieldReader;
#[doc = "Field `TXFIFO_WR_ENDIAN` writer - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
pub type TxfifoWrEndianW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `FPCKE` reader - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
pub type FpckeR = crate::BitReader;
#[doc = "Field `FPCKE` writer - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
pub type FpckeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXFIFO_AUTO_FULL_CTRL` reader - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
pub type RxfifoAutoFullCtrlR = crate::BitReader;
#[doc = "Field `RXFIFO_AUTO_FULL_CTRL` writer - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
pub type RxfifoAutoFullCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EFWR` reader - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
pub type EfwrR = crate::BitReader;
#[doc = "Field `EFWR` writer - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
pub type EfwrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STRF` reader - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
pub type StrfR = crate::BitReader;
#[doc = "Field `STRF` writer - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
pub type StrfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:4 - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
pub fn tft(&self) -> TftR {
TftR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9 - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
pub fn rft(&self) -> RftR {
RftR::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bit 10 - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
pub fn tsre(&self) -> TsreR {
TsreR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
pub fn rsre(&self) -> RsreR {
RsreR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
#[inline(always)]
pub fn rxfifo_rd_endian(&self) -> RxfifoRdEndianR {
RxfifoRdEndianR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
#[inline(always)]
pub fn txfifo_wr_endian(&self) -> TxfifoWrEndianR {
TxfifoWrEndianR::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bit 16 - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
#[inline(always)]
pub fn fpcke(&self) -> FpckeR {
FpckeR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
#[inline(always)]
pub fn rxfifo_auto_full_ctrl(&self) -> RxfifoAutoFullCtrlR {
RxfifoAutoFullCtrlR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
#[inline(always)]
pub fn efwr(&self) -> EfwrR {
EfwrR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
#[inline(always)]
pub fn strf(&self) -> StrfR {
StrfR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:4 - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
#[must_use]
pub fn tft(&mut self) -> TftW<FifoCtrlSpec> {
TftW::new(self, 0)
}
#[doc = "Bits 5:9 - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1."]
#[inline(always)]
#[must_use]
pub fn rft(&mut self) -> RftW<FifoCtrlSpec> {
RftW::new(self, 5)
}
#[doc = "Bit 10 - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
#[must_use]
pub fn tsre(&mut self) -> TsreW<FifoCtrlSpec> {
TsreW::new(self, 10)
}
#[doc = "Bit 11 - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled"]
#[inline(always)]
#[must_use]
pub fn rsre(&mut self) -> RsreW<FifoCtrlSpec> {
RsreW::new(self, 11)
}
#[doc = "Bits 12:13 - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata\\[31:0\\]
= rxfifo_wdata\\[31:0\\]
0x1 = apb_prdata\\[31:0\\]
= {rxfifo_wdata\\[15:0\\], rxfifo_wdata\\[31:16\\]} 0x2 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\], rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\]} 0x3 = apb_prdata\\[31:0\\]= {rxfifo_wdata\\[23:16\\], rxfifo_wdata\\[31:24\\], rxfifo_wdata\\[7:0\\], rxfifo_wdata\\[15:8\\]}"]
#[inline(always)]
#[must_use]
pub fn rxfifo_rd_endian(&mut self) -> RxfifoRdEndianW<FifoCtrlSpec> {
RxfifoRdEndianW::new(self, 12)
}
#[doc = "Bits 14:15 - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata\\[31:0\\]
= apb_pwdata\\[31:0\\]
0x1 = fifo_wdata\\[31:0\\]
= {apb_pwdata\\[15:0\\], apb_pwdata\\[31:16\\]} 0x2 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\], apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\]} 0x3 = txfifo_wdata\\[31:0\\]
= {apb_pwdata\\[23:16\\], apb_pwdata\\[31:24\\], apb_pwdata\\[7:0\\], apb_pwdata\\[15:8\\]}"]
#[inline(always)]
#[must_use]
pub fn txfifo_wr_endian(&mut self) -> TxfifoWrEndianW<FifoCtrlSpec> {
TxfifoWrEndianW::new(self, 14)
}
#[doc = "Bit 16 - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled"]
#[inline(always)]
#[must_use]
pub fn fpcke(&mut self) -> FpckeW<FifoCtrlSpec> {
FpckeW::new(self, 16)
}
#[doc = "Bit 17 - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control"]
#[inline(always)]
#[must_use]
pub fn rxfifo_auto_full_ctrl(&mut self) -> RxfifoAutoFullCtrlW<FifoCtrlSpec> {
RxfifoAutoFullCtrlW::new(self, 17)
}
#[doc = "Bit 18 - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled"]
#[inline(always)]
#[must_use]
pub fn efwr(&mut self) -> EfwrW<FifoCtrlSpec> {
EfwrW::new(self, 18)
}
#[doc = "Bit 19 - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register"]
#[inline(always)]
#[must_use]
pub fn strf(&mut self) -> StrfW<FifoCtrlSpec> {
StrfW::new(self, 19)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoCtrlSpec> {
RsvdW::new(self, 20)
}
}
#[doc = "FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoCtrlSpec;
impl crate::RegisterSpec for FifoCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo_ctrl::R`](R) reader structure"]
impl crate::Readable for FifoCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo_ctrl::W`](W) writer structure"]
impl crate::Writable for FifoCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO_CTRL to value 0"]
impl crate::Resettable for FifoCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTE (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inte`]
module"]
#[doc(alias = "INTE")]
pub type Inte = crate::Reg<inte::InteSpec>;
#[doc = "Interrupt Enable Register"]
pub mod inte {
#[doc = "Register `INTE` reader"]
pub type R = crate::R<InteSpec>;
#[doc = "Register `INTE` writer"]
pub type W = crate::W<InteSpec>;
#[doc = "Field `PINTE` reader - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
pub type PinteR = crate::BitReader;
#[doc = "Field `PINTE` writer - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
pub type PinteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TINTE` reader - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
pub type TinteR = crate::BitReader;
#[doc = "Field `TINTE` writer - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
pub type TinteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIE` reader - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
pub type RieR = crate::BitReader;
#[doc = "Field `RIE` writer - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
pub type RieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIE` reader - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
pub type TieR = crate::BitReader;
#[doc = "Field `TIE` writer - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
pub type TieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIM` reader - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
pub type RimR = crate::BitReader;
#[doc = "Field `RIM` writer - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
pub type RimW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIM` reader - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
pub type TimR = crate::BitReader;
#[doc = "Field `TIM` writer - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
pub type TimW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EBCEI` reader - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
pub type EbceiR = crate::BitReader;
#[doc = "Field `EBCEI` writer - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
pub type EbceiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>;
impl R {
#[doc = "Bit 0 - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
#[inline(always)]
pub fn pinte(&self) -> PinteR {
PinteR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
#[inline(always)]
pub fn tinte(&self) -> TinteR {
TinteR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
pub fn rie(&self) -> RieR {
RieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
pub fn tie(&self) -> TieR {
TieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
#[inline(always)]
pub fn rim(&self) -> RimR {
RimR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
#[inline(always)]
pub fn tim(&self) -> TimR {
TimR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
#[inline(always)]
pub fn ebcei(&self) -> EbceiR {
EbceiR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 7) & 0x01ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Peripheral Trailing Byte Interrupt Enable 0 = Peripheral trailing byte interrupt is disabled 1 = Peripheral trailing byte interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn pinte(&mut self) -> PinteW<InteSpec> {
PinteW::new(self, 0)
}
#[doc = "Bit 1 - Receiver Time-out Interrupt Enable 0 = Receiver time-out interrupt is disabled 1 = Receiver time-out interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn tinte(&mut self) -> TinteW<InteSpec> {
TinteW::new(self, 1)
}
#[doc = "Bit 2 - Receive FIFO Interrupt Enable 0 = RXFIFO threshold-level-reached interrupt is disabled 1 = RXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn rie(&mut self) -> RieW<InteSpec> {
RieW::new(self, 2)
}
#[doc = "Bit 3 - Transmit FIFO Interrupt Enable 0 = TXFIFO threshold-level-reached interrupt is disabled 1 = TXFIFO threshold-level-reached interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn tie(&mut self) -> TieW<InteSpec> {
TieW::new(self, 3)
}
#[doc = "Bit 4 - Receive FIFO Overrun Interrupt Mask 0 = ROR events generate an SSP interrupt 1 = ROR events do NOT generate an SSP interrupt"]
#[inline(always)]
#[must_use]
pub fn rim(&mut self) -> RimW<InteSpec> {
RimW::new(self, 4)
}
#[doc = "Bit 5 - Transmit FIFO Underrun Interrupt Mask 0 = TUR events generate an SSP interrupt 1 = TUR events do NOT generate an SSP interrupt"]
#[inline(always)]
#[must_use]
pub fn tim(&mut self) -> TimW<InteSpec> {
TimW::new(self, 5)
}
#[doc = "Bit 6 - Enable Bit Count Error Interrupt 0 = Interrupt due to a bit count error is disabled 1 = Interrupt due to a bit count error is enabled"]
#[inline(always)]
#[must_use]
pub fn ebcei(&mut self) -> EbceiW<InteSpec> {
EbceiW::new(self, 6)
}
#[doc = "Bits 7:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<InteSpec> {
RsvdW::new(self, 7)
}
}
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct InteSpec;
impl crate::RegisterSpec for InteSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`inte::R`](R) reader structure"]
impl crate::Readable for InteSpec {}
#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"]
impl crate::Writable for InteSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTE to value 0"]
impl crate::Resettable for InteSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TO (rw) register accessor: SPI Time Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@to`]
module"]
#[doc(alias = "TO")]
pub type To = crate::Reg<to::ToSpec>;
#[doc = "SPI Time Out Register"]
pub mod to {
#[doc = "Register `TO` reader"]
pub type R = crate::R<ToSpec>;
#[doc = "Register `TO` writer"]
pub type W = crate::W<ToSpec>;
#[doc = "Field `TIMEOUT` reader - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
pub type TimeoutR = crate::FieldReader<u32>;
#[doc = "Field `TIMEOUT` writer - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
pub type TimeoutW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
#[inline(always)]
pub fn timeout(&self) -> TimeoutR {
TimeoutR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Timeout Value TIMEOUT value is the value (0 to 2<super 24>-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation."]
#[inline(always)]
#[must_use]
pub fn timeout(&mut self) -> TimeoutW<ToSpec> {
TimeoutW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ToSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "SPI Time Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ToSpec;
impl crate::RegisterSpec for ToSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`to::R`](R) reader structure"]
impl crate::Readable for ToSpec {}
#[doc = "`write(|w| ..)` method takes [`to::W`](W) writer structure"]
impl crate::Writable for ToSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TO to value 0"]
impl crate::Resettable for ToSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DATA (rw) register accessor: SPI DATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "SPI DATA Register"]
pub mod data {
#[doc = "Register `DATA` reader"]
pub type R = crate::R<DataSpec>;
#[doc = "Register `DATA` writer"]
pub type W = crate::W<DataSpec>;
#[doc = "Field `DATA` reader - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
pub type DataR = crate::FieldReader<u32>;
#[doc = "Field `DATA` writer - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - DATA This field is used for data to be written to the TXFIFO read from the RXFIFO."]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DataSpec> {
DataW::new(self, 0)
}
}
#[doc = "SPI DATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data::R`](R) reader structure"]
impl crate::Readable for DataSpec {}
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
impl crate::Writable for DataSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DATA to value 0"]
impl crate::Resettable for DataSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "STATUS (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
#[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "Status Register"]
pub mod status {
#[doc = "Register `STATUS` reader"]
pub type R = crate::R<StatusSpec>;
#[doc = "Register `STATUS` writer"]
pub type W = crate::W<StatusSpec>;
#[doc = "Field `BSY` reader - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
pub type BsyR = crate::BitReader;
#[doc = "Field `BSY` writer - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
pub type BsyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CSS` reader - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
pub type CssR = crate::BitReader;
#[doc = "Field `CSS` writer - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
pub type CssW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINT` reader - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
pub type PintR = crate::BitReader;
#[doc = "Field `PINT` writer - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
pub type PintW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TINT` reader - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
pub type TintR = crate::BitReader;
#[doc = "Field `TINT` writer - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
pub type TintW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EOC` reader - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
pub type EocR = crate::BitReader;
#[doc = "Field `EOC` writer - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
pub type EocW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TFS` reader - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
pub type TfsR = crate::BitReader;
#[doc = "Field `TFS` writer - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
pub type TfsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TNF` reader - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
pub type TnfR = crate::BitReader;
#[doc = "Field `TNF` writer - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
pub type TnfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TFL` reader - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
pub type TflR = crate::FieldReader;
#[doc = "Field `TFL` writer - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
pub type TflW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TUR` reader - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
pub type TurR = crate::BitReader;
#[doc = "Field `TUR` writer - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
pub type TurW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFS` reader - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
pub type RfsR = crate::BitReader;
#[doc = "Field `RFS` writer - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
pub type RfsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RNE` reader - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
pub type RneR = crate::BitReader;
#[doc = "Field `RNE` writer - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
pub type RneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFL` reader - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
pub type RflR = crate::FieldReader;
#[doc = "Field `RFL` writer - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
pub type RflW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ROR` reader - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
pub type RorR = crate::BitReader;
#[doc = "Field `ROR` writer - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
pub type RorW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BCE` reader - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
pub type BceR = crate::BitReader;
#[doc = "Field `BCE` writer - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
pub type BceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX_OSS` reader - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
pub type TxOssR = crate::BitReader;
#[doc = "Field `TX_OSS` writer - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
pub type TxOssW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OSS` reader - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
pub type OssR = crate::BitReader;
#[doc = "Field `OSS` writer - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
pub type OssW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bit 0 - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
#[inline(always)]
pub fn bsy(&self) -> BsyR {
BsyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
#[inline(always)]
pub fn css(&self) -> CssR {
CssR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
#[inline(always)]
pub fn pint(&self) -> PintR {
PintR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
#[inline(always)]
pub fn tint(&self) -> TintR {
TintR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
#[inline(always)]
pub fn eoc(&self) -> EocR {
EocR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
#[inline(always)]
pub fn tfs(&self) -> TfsR {
TfsR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
#[inline(always)]
pub fn tnf(&self) -> TnfR {
TnfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:10 - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
#[inline(always)]
pub fn tfl(&self) -> TflR {
TflR::new(((self.bits >> 7) & 0x0f) as u8)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
#[inline(always)]
pub fn tur(&self) -> TurR {
TurR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
#[inline(always)]
pub fn rfs(&self) -> RfsR {
RfsR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
#[inline(always)]
pub fn rne(&self) -> RneR {
RneR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:18 - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
#[inline(always)]
pub fn rfl(&self) -> RflR {
RflR::new(((self.bits >> 15) & 0x0f) as u8)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
#[inline(always)]
pub fn ror(&self) -> RorR {
RorR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
#[inline(always)]
pub fn bce(&self) -> BceR {
BceR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
#[inline(always)]
pub fn tx_oss(&self) -> TxOssR {
TxOssR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
#[inline(always)]
pub fn oss(&self) -> OssR {
OssR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0 - SSP Busy 0 = SSPx port is idle or disabled 1 = SSPx port is currently transmitting or receiving framed data"]
#[inline(always)]
#[must_use]
pub fn bsy(&mut self) -> BsyW<StatusSpec> {
BsyW::new(self, 0)
}
#[doc = "Bit 1 - Clock Synchronization Status 0 = The SSPx port is ready for slave clock operations 1 = The SSPx port is currently busy synchronizing slave mode signals"]
#[inline(always)]
#[must_use]
pub fn css(&mut self) -> CssW<StatusSpec> {
CssW::new(self, 1)
}
#[doc = "Bit 2 - Peripheral Trailing Byte Interrupt 0 = No peripheral trailing byte interrupt is pending 1 = Peripheral trailing byte interrupt is pending"]
#[inline(always)]
#[must_use]
pub fn pint(&mut self) -> PintW<StatusSpec> {
PintW::new(self, 2)
}
#[doc = "Bit 3 - Receiver Time-out Interrupt 0 = No receiver time-out is pending 1 = Receiver time-out pending, causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn tint(&mut self) -> TintW<StatusSpec> {
TintW::new(self, 3)
}
#[doc = "Bit 4 - End Of Chain 0 = DMA has not signaled an end of chain condition 1 = DMA has signaled an end of chain condition"]
#[inline(always)]
#[must_use]
pub fn eoc(&mut self) -> EocW<StatusSpec> {
EocW::new(self, 4)
}
#[doc = "Bit 5 - Transmit FIFO Service Request 0 = TX FIFO level exceeds the TFT threshold (TFT + 1) or SSPx port disabled 1 = TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn tfs(&mut self) -> TfsW<StatusSpec> {
TfsW::new(self, 5)
}
#[doc = "Bit 6 - Transmit FIFO Not Full 0 = TXFIFO is full 1 = TXFIFO is not full"]
#[inline(always)]
#[must_use]
pub fn tnf(&mut self) -> TnfW<StatusSpec> {
TnfW::new(self, 6)
}
#[doc = "Bits 7:10 - Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the <Transmit FIFO Not Full> field."]
#[inline(always)]
#[must_use]
pub fn tfl(&mut self) -> TflW<StatusSpec> {
TflW::new(self, 7)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<StatusSpec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bit 12 - Transmit FIFO Underrun 0 = The TXFIFO has not experienced an underrun 1 = A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled (<Transmit FIFO Underrun Interrupt Mask> in the SSP INT EN Register is 0)"]
#[inline(always)]
#[must_use]
pub fn tur(&mut self) -> TurW<StatusSpec> {
TurW::new(self, 12)
}
#[doc = "Bit 13 - Receive FIFO Service Request 0 = RXFIFO level is at or below RFT threshold (RFT) or SSPx port is disabled 1 = RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn rfs(&mut self) -> RfsW<StatusSpec> {
RfsW::new(self, 13)
}
#[doc = "Bit 14 - Receive FIFO Not Empty 0 = RXFIFO is empty 1 = RXFIFO is not empty"]
#[inline(always)]
#[must_use]
pub fn rne(&mut self) -> RneW<StatusSpec> {
RneW::new(self, 14)
}
#[doc = "Bits 15:18 - Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0x1F is read, the RXFIFO is either empty or full, and software should read the <Receive FIFO Not Empty> field."]
#[inline(always)]
#[must_use]
pub fn rfl(&mut self) -> RflW<StatusSpec> {
RflW::new(self, 15)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<StatusSpec> {
Rsvd2W::new(self, 19)
}
#[doc = "Bit 20 - Receive FIFO Overrun 0 = RXFIFO has not experienced an overrun 1 = Attempted data write to full RXFIFO, causes an interrupt request"]
#[inline(always)]
#[must_use]
pub fn ror(&mut self) -> RorW<StatusSpec> {
RorW::new(self, 20)
}
#[doc = "Bit 21 - Bit Count Error 0 = The SSPx port has not experienced a bit count error 1 = The SSPSFRMx signal was asserted when the bit counter was not zero"]
#[inline(always)]
#[must_use]
pub fn bce(&mut self) -> BceW<StatusSpec> {
BceW::new(self, 21)
}
#[doc = "Bit 22 - TX FIFO Odd Sample Status When SSPx port is in packed mode, the number of samples in the TX FIFO is: (<Transmit FIFO Level>*2 + this field), when <Transmit FIFO Not Full> = 1 32, when <Transmit FIFO Not Full> = 0. The TX FIFO cannot accept new data when <Transmit FIFO Not Full> = 1 and <Transmit FIFO Level> = 15 and this field = 1. (The TX FIFO has 31 samples). 0 = TxFIFO entry has an even number of samples 1 = TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled (<FIFO Packing Enable> in the SSP FIFO Control Register is set). Otherwise, this bit is zero."]
#[inline(always)]
#[must_use]
pub fn tx_oss(&mut self) -> TxOssW<StatusSpec> {
TxOssW::new(self, 22)
}
#[doc = "Bit 23 - Odd Sample Status 0 = RxFIFO entry has two samples 1 = RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (<FIFO Packing Enable> field in SSP FIFO Control Register is set). Otherwise, this bit is zero. When SSPx port is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that <Receive FIFO Not Empty> = 1 AND this field = 0 before it attempts to read the RxFIFO."]
#[inline(always)]
#[must_use]
pub fn oss(&mut self) -> OssW<StatusSpec> {
OssW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<StatusSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`status::R`](R) reader structure"]
impl crate::Readable for StatusSpec {}
#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
impl crate::Writable for StatusSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets STATUS to value 0"]
impl crate::Resettable for StatusSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd3`]
module"]
#[doc(alias = "RSVD3")]
pub type Rsvd3 = crate::Reg<rsvd3::Rsvd3Spec>;
#[doc = ""]
pub mod rsvd3 {
#[doc = "Register `RSVD3` reader"]
pub type R = crate::R<Rsvd3Spec>;
#[doc = "Register `RSVD3` writer"]
pub type W = crate::W<Rsvd3Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd3Spec;
impl crate::RegisterSpec for Rsvd3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd3::R`](R) reader structure"]
impl crate::Readable for Rsvd3Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd3::W`](W) writer structure"]
impl crate::Writable for Rsvd3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD3 to value 0"]
impl crate::Resettable for Rsvd3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RWOT_CTRL (rw) register accessor: SSP RWOT Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwot_ctrl`]
module"]
#[doc(alias = "RWOT_CTRL")]
pub type RwotCtrl = crate::Reg<rwot_ctrl::RwotCtrlSpec>;
#[doc = "SSP RWOT Control Register"]
pub mod rwot_ctrl {
#[doc = "Register `RWOT_CTRL` reader"]
pub type R = crate::R<RwotCtrlSpec>;
#[doc = "Register `RWOT_CTRL` writer"]
pub type W = crate::W<RwotCtrlSpec>;
#[doc = "Field `RWOT` reader - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
pub type RwotR = crate::BitReader;
#[doc = "Field `RWOT` writer - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
pub type RwotW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CYCLE_RWOT_EN` reader - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
pub type CycleRwotEnR = crate::BitReader;
#[doc = "Field `CYCLE_RWOT_EN` writer - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
pub type CycleRwotEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SET_RWOT_CYCLE` reader - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
pub type SetRwotCycleR = crate::BitReader;
#[doc = "Field `SET_RWOT_CYCLE` writer - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
pub type SetRwotCycleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR_RWOT_CYCLE` reader - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
pub type ClrRwotCycleR = crate::BitReader;
#[doc = "Field `CLR_RWOT_CYCLE` writer - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
pub type ClrRwotCycleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK_RWOT_LAST_SAMPLE` reader - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
pub type MaskRwotLastSampleR = crate::BitReader;
#[doc = "Field `MASK_RWOT_LAST_SAMPLE` writer - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
pub type MaskRwotLastSampleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bit 0 - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
#[inline(always)]
pub fn rwot(&self) -> RwotR {
RwotR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
#[inline(always)]
pub fn cycle_rwot_en(&self) -> CycleRwotEnR {
CycleRwotEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
#[inline(always)]
pub fn set_rwot_cycle(&self) -> SetRwotCycleR {
SetRwotCycleR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
#[inline(always)]
pub fn clr_rwot_cycle(&self) -> ClrRwotCycleR {
ClrRwotCycleR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
#[inline(always)]
pub fn mask_rwot_last_sample(&self) -> MaskRwotLastSampleR {
MaskRwotLastSampleR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Receive Without Transmit 0 = Transmit/receive mode 1 = Receive without transmit mode"]
#[inline(always)]
#[must_use]
pub fn rwot(&mut self) -> RwotW<RwotCtrlSpec> {
RwotW::new(self, 0)
}
#[doc = "Bit 1 - Enable SSP RWOT Cycle Counter Mode 1 = Enable"]
#[inline(always)]
#[must_use]
pub fn cycle_rwot_en(&mut self) -> CycleRwotEnW<RwotCtrlSpec> {
CycleRwotEnW::new(self, 1)
}
#[doc = "Bit 2 - Set RWOT Cycle This field is used to set the value of the SSP_RWOT_CCM register to the SSP internal rwot_counter. This field is self-cleared by SSP after SSE = 1. 1 = Set rwot_counter"]
#[inline(always)]
#[must_use]
pub fn set_rwot_cycle(&mut self) -> SetRwotCycleW<RwotCtrlSpec> {
SetRwotCycleW::new(self, 2)
}
#[doc = "Bit 3 - Clear SSP Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared by SSP after SSE = 1. 1 = Clear rwot_counter"]
#[inline(always)]
#[must_use]
pub fn clr_rwot_cycle(&mut self) -> ClrRwotCycleW<RwotCtrlSpec> {
ClrRwotCycleW::new(self, 3)
}
#[doc = "Bit 4 - Mask last_sample_flag in RWOT Mode 1= Mask 0 = Unmask"]
#[inline(always)]
#[must_use]
pub fn mask_rwot_last_sample(&mut self) -> MaskRwotLastSampleW<RwotCtrlSpec> {
MaskRwotLastSampleW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RwotCtrlSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "SSP RWOT Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RwotCtrlSpec;
impl crate::RegisterSpec for RwotCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rwot_ctrl::R`](R) reader structure"]
impl crate::Readable for RwotCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`rwot_ctrl::W`](W) writer structure"]
impl crate::Writable for RwotCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RWOT_CTRL to value 0"]
impl crate::Resettable for RwotCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RWOT_CCM (rw) register accessor: SSP RWOT Counter Cycles Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ccm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ccm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwot_ccm`]
module"]
#[doc(alias = "RWOT_CCM")]
pub type RwotCcm = crate::Reg<rwot_ccm::RwotCcmSpec>;
#[doc = "SSP RWOT Counter Cycles Match Register"]
pub mod rwot_ccm {
#[doc = "Register `RWOT_CCM` reader"]
pub type R = crate::R<RwotCcmSpec>;
#[doc = "Register `RWOT_CCM` writer"]
pub type W = crate::W<RwotCcmSpec>;
#[doc = "Field `SSPRWOTCCM` reader - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
pub type SsprwotccmR = crate::FieldReader<u32>;
#[doc = "Field `SSPRWOTCCM` writer - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
pub type SsprwotccmW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
#[inline(always)]
pub fn ssprwotccm(&self) -> SsprwotccmR {
SsprwotccmR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - It's just total ssp_sclk_gpio Cycles The value of this register defines the total number of ssp_sclk_gpio cycles when SSP works in master and RWOT mode. When the rwot_counter matches this value, SSP returns to IDLE state and does not output ssp_sclk_gpio anymore."]
#[inline(always)]
#[must_use]
pub fn ssprwotccm(&mut self) -> SsprwotccmW<RwotCcmSpec> {
SsprwotccmW::new(self, 0)
}
}
#[doc = "SSP RWOT Counter Cycles Match Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_ccm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_ccm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RwotCcmSpec;
impl crate::RegisterSpec for RwotCcmSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rwot_ccm::R`](R) reader structure"]
impl crate::Readable for RwotCcmSpec {}
#[doc = "`write(|w| ..)` method takes [`rwot_ccm::W`](W) writer structure"]
impl crate::Writable for RwotCcmSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RWOT_CCM to value 0"]
impl crate::Resettable for RwotCcmSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RWOT_CVWRN (rw) register accessor: SSP RWOT Counter Value Write for Red Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_cvwrn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_cvwrn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwot_cvwrn`]
module"]
#[doc(alias = "RWOT_CVWRN")]
pub type RwotCvwrn = crate::Reg<rwot_cvwrn::RwotCvwrnSpec>;
#[doc = "SSP RWOT Counter Value Write for Red Request Register"]
pub mod rwot_cvwrn {
#[doc = "Register `RWOT_CVWRN` reader"]
pub type R = crate::R<RwotCvwrnSpec>;
#[doc = "Register `RWOT_CVWRN` writer"]
pub type W = crate::W<RwotCvwrnSpec>;
#[doc = "Field `SSPRWOTCVWR` reader - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
pub type SsprwotcvwrR = crate::FieldReader<u32>;
#[doc = "Field `SSPRWOTCVWR` writer - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
pub type SsprwotcvwrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
#[inline(always)]
pub fn ssprwotcvwr(&self) -> SsprwotcvwrR {
SsprwotcvwrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - SSPRWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SSP has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter"]
#[inline(always)]
#[must_use]
pub fn ssprwotcvwr(&mut self) -> SsprwotcvwrW<RwotCvwrnSpec> {
SsprwotcvwrW::new(self, 0)
}
}
#[doc = "SSP RWOT Counter Value Write for Red Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwot_cvwrn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwot_cvwrn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RwotCvwrnSpec;
impl crate::RegisterSpec for RwotCvwrnSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rwot_cvwrn::R`](R) reader structure"]
impl crate::Readable for RwotCvwrnSpec {}
#[doc = "`write(|w| ..)` method takes [`rwot_cvwrn::W`](W) writer structure"]
impl crate::Writable for RwotCvwrnSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RWOT_CVWRN to value 0"]
impl crate::Resettable for RwotCvwrnSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd2`]
module"]
#[doc(alias = "RSVD2")]
pub type Rsvd2 = crate::Reg<rsvd2::Rsvd2Spec>;
#[doc = ""]
pub mod rsvd2 {
#[doc = "Register `RSVD2` reader"]
pub type R = crate::R<Rsvd2Spec>;
#[doc = "Register `RSVD2` writer"]
pub type W = crate::W<Rsvd2Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd2Spec;
impl crate::RegisterSpec for Rsvd2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd2::R`](R) reader structure"]
impl crate::Readable for Rsvd2Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd2::W`](W) writer structure"]
impl crate::Writable for Rsvd2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD2 to value 0"]
impl crate::Resettable for Rsvd2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CLK_CTRL (rw) register accessor: SSP CLK Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_ctrl`]
module"]
#[doc(alias = "CLK_CTRL")]
pub type ClkCtrl = crate::Reg<clk_ctrl::ClkCtrlSpec>;
#[doc = "SSP CLK Control Register"]
pub mod clk_ctrl {
#[doc = "Register `CLK_CTRL` reader"]
pub type R = crate::R<ClkCtrlSpec>;
#[doc = "Register `CLK_CTRL` writer"]
pub type W = crate::W<ClkCtrlSpec>;
#[doc = "Field `CLK_DIV` reader - div ratio from clk_sys"]
pub type ClkDivR = crate::FieldReader;
#[doc = "Field `CLK_DIV` writer - div ratio from clk_sys"]
pub type ClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `CLK_SEL` reader - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
pub type ClkSelR = crate::BitReader;
#[doc = "Field `CLK_SEL` writer - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
pub type ClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_SSP_EN` reader - "]
pub type ClkSspEnR = crate::BitReader;
#[doc = "Field `CLK_SSP_EN` writer - "]
pub type ClkSspEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_DI_SEL` reader - Select spi_di source. 0: from port DI. 1: from port DIO."]
pub type SpiDiSelR = crate::BitReader;
#[doc = "Field `SPI_DI_SEL` writer - Select spi_di source. 0: from port DI. 1: from port DIO."]
pub type SpiDiSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bits 0:6 - div ratio from clk_sys"]
#[inline(always)]
pub fn clk_div(&self) -> ClkDivR {
ClkDivR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bit 7 - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
#[inline(always)]
pub fn clk_sel(&self) -> ClkSelR {
ClkSelR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn clk_ssp_en(&self) -> ClkSspEnR {
ClkSspEnR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Select spi_di source. 0: from port DI. 1: from port DIO."]
#[inline(always)]
pub fn spi_di_sel(&self) -> SpiDiSelR {
SpiDiSelR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bits 0:6 - div ratio from clk_sys"]
#[inline(always)]
#[must_use]
pub fn clk_div(&mut self) -> ClkDivW<ClkCtrlSpec> {
ClkDivW::new(self, 0)
}
#[doc = "Bit 7 - 0: select clk_div as clk_ssp 1: select clk_sys as clk_ssp"]
#[inline(always)]
#[must_use]
pub fn clk_sel(&mut self) -> ClkSelW<ClkCtrlSpec> {
ClkSelW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn clk_ssp_en(&mut self) -> ClkSspEnW<ClkCtrlSpec> {
ClkSspEnW::new(self, 8)
}
#[doc = "Bit 9 - Select spi_di source. 0: from port DI. 1: from port DIO."]
#[inline(always)]
#[must_use]
pub fn spi_di_sel(&mut self) -> SpiDiSelW<ClkCtrlSpec> {
SpiDiSelW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ClkCtrlSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "SSP CLK Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkCtrlSpec;
impl crate::RegisterSpec for ClkCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`clk_ctrl::R`](R) reader structure"]
impl crate::Readable for ClkCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`clk_ctrl::W`](W) writer structure"]
impl crate::Writable for ClkCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CLK_CTRL to value 0"]
impl crate::Resettable for ClkCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TRIWIRE_CTRL (rw) register accessor: SSP Three Wire Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`triwire_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`triwire_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@triwire_ctrl`]
module"]
#[doc(alias = "TRIWIRE_CTRL")]
pub type TriwireCtrl = crate::Reg<triwire_ctrl::TriwireCtrlSpec>;
#[doc = "SSP Three Wire Mode Control Register"]
pub mod triwire_ctrl {
#[doc = "Register `TRIWIRE_CTRL` reader"]
pub type R = crate::R<TriwireCtrlSpec>;
#[doc = "Register `TRIWIRE_CTRL` writer"]
pub type W = crate::W<TriwireCtrlSpec>;
#[doc = "Field `SPI_TRI_WIRE_EN` reader - SPI_THREE_WIRE_MODE_EN 1=enable"]
pub type SpiTriWireEnR = crate::BitReader;
#[doc = "Field `SPI_TRI_WIRE_EN` writer - SPI_THREE_WIRE_MODE_EN 1=enable"]
pub type SpiTriWireEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXD_OEN` reader - TXD_OEN 1=TXD is input 0=TXD is output"]
pub type TxdOenR = crate::BitReader;
#[doc = "Field `TXD_OEN` writer - TXD_OEN 1=TXD is input 0=TXD is output"]
pub type TxdOenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SSP_WORK_WIDTH_DYN_CHANGE` reader - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
pub type SspWorkWidthDynChangeR = crate::BitReader;
#[doc = "Field `SSP_WORK_WIDTH_DYN_CHANGE` writer - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
pub type SspWorkWidthDynChangeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bit 0 - SPI_THREE_WIRE_MODE_EN 1=enable"]
#[inline(always)]
pub fn spi_tri_wire_en(&self) -> SpiTriWireEnR {
SpiTriWireEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TXD_OEN 1=TXD is input 0=TXD is output"]
#[inline(always)]
pub fn txd_oen(&self) -> TxdOenR {
TxdOenR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
#[inline(always)]
pub fn ssp_work_width_dyn_change(&self) -> SspWorkWidthDynChangeR {
SspWorkWidthDynChangeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SPI_THREE_WIRE_MODE_EN 1=enable"]
#[inline(always)]
#[must_use]
pub fn spi_tri_wire_en(&mut self) -> SpiTriWireEnW<TriwireCtrlSpec> {
SpiTriWireEnW::new(self, 0)
}
#[doc = "Bit 1 - TXD_OEN 1=TXD is input 0=TXD is output"]
#[inline(always)]
#[must_use]
pub fn txd_oen(&mut self) -> TxdOenW<TriwireCtrlSpec> {
TxdOenW::new(self, 1)
}
#[doc = "Bit 2 - SSP_WORK_WIDTH_DYN_CHNAGE 1=SP can dynamicly change SSP_TOP_CTRL\\[9:5\\]
without disabling SSP_TOP_CTRL\\[0\\]
and re-enabling SSP_TOP_CTRL\\[0\\]"]
#[inline(always)]
#[must_use]
pub fn ssp_work_width_dyn_change(&mut self) -> SspWorkWidthDynChangeW<TriwireCtrlSpec> {
SspWorkWidthDynChangeW::new(self, 2)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TriwireCtrlSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "SSP Three Wire Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`triwire_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`triwire_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TriwireCtrlSpec;
impl crate::RegisterSpec for TriwireCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`triwire_ctrl::R`](R) reader structure"]
impl crate::Readable for TriwireCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`triwire_ctrl::W`](W) writer structure"]
impl crate::Writable for TriwireCtrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TRIWIRE_CTRL to value 0"]
impl crate::Resettable for TriwireCtrlSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "PDM1"]
pub struct Pdm1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Pdm1 {}
impl Pdm1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const pdm1::RegisterBlock = 0x5009_a000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const pdm1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Pdm1 {
type Target = pdm1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Pdm1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pdm1").finish()
}
}
#[doc = "PDM1"]
pub mod pdm1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cfg0: Cfg0,
cfg1: Cfg1,
sinc_cfg: SincCfg,
rsvd3: Rsvd3,
_reserved4: [u8; 0x04],
hpf_cfg: HpfCfg,
pga_cfg: PgaCfg,
rsvd2: Rsvd2,
_reserved7: [u8; 0x14],
lpf_cfg6: LpfCfg6,
fifo_cfg: FifoCfg,
rsvd1: Rsvd1,
_reserved10: [u8; 0x04],
fifo_st: FifoSt,
int_st: IntSt,
int_msk: IntMsk,
int_clr: IntClr,
}
impl RegisterBlock {
#[doc = "0x00 - "]
#[inline(always)]
pub const fn cfg0(&self) -> &Cfg0 {
&self.cfg0
}
#[doc = "0x04 - "]
#[inline(always)]
pub const fn cfg1(&self) -> &Cfg1 {
&self.cfg1
}
#[doc = "0x08 - "]
#[inline(always)]
pub const fn sinc_cfg(&self) -> &SincCfg {
&self.sinc_cfg
}
#[doc = "0x0c - "]
#[inline(always)]
pub const fn rsvd3(&self) -> &Rsvd3 {
&self.rsvd3
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn hpf_cfg(&self) -> &HpfCfg {
&self.hpf_cfg
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn pga_cfg(&self) -> &PgaCfg {
&self.pga_cfg
}
#[doc = "0x1c - "]
#[inline(always)]
pub const fn rsvd2(&self) -> &Rsvd2 {
&self.rsvd2
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn lpf_cfg6(&self) -> &LpfCfg6 {
&self.lpf_cfg6
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn fifo_cfg(&self) -> &FifoCfg {
&self.fifo_cfg
}
#[doc = "0x3c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x44 - "]
#[inline(always)]
pub const fn fifo_st(&self) -> &FifoSt {
&self.fifo_st
}
#[doc = "0x48 - "]
#[inline(always)]
pub const fn int_st(&self) -> &IntSt {
&self.int_st
}
#[doc = "0x4c - "]
#[inline(always)]
pub const fn int_msk(&self) -> &IntMsk {
&self.int_msk
}
#[doc = "0x50 - "]
#[inline(always)]
pub const fn int_clr(&self) -> &IntClr {
&self.int_clr
}
}
#[doc = "CFG0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg0`]
module"]
#[doc(alias = "CFG0")]
pub type Cfg0 = crate::Reg<cfg0::Cfg0Spec>;
#[doc = ""]
pub mod cfg0 {
#[doc = "Register `CFG0` reader"]
pub type R = crate::R<Cfg0Spec>;
#[doc = "Register `CFG0` writer"]
pub type W = crate::W<Cfg0Spec>;
#[doc = "Field `PDMCOREEN` reader - 1:Enable pdm module; 0: Disable pdm module"]
pub type PdmcoreenR = crate::BitReader;
#[doc = "Field `PDMCOREEN` writer - 1:Enable pdm module; 0: Disable pdm module"]
pub type PdmcoreenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_SEL` reader - 1:Clk select dll 3.072MHz; 0: Clk selct xtal 9.6MHz"]
pub type ClkSelR = crate::BitReader;
#[doc = "Field `CLK_SEL` writer - 1:Clk select dll 3.072MHz; 0: Clk selct xtal 9.6MHz"]
pub type ClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_DIV` reader - Clock frequency division ratio of 3.072MHz or 9.6MHz according to register clk_sel"]
pub type ClkDivR = crate::FieldReader;
#[doc = "Field `CLK_DIV` writer - Clock frequency division ratio of 3.072MHz or 9.6MHz according to register clk_sel"]
pub type ClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `LEFT_EN` reader - 1: Enable left channel pdm data sampling; 0: Disable left channel pdm data sampling"]
pub type LeftEnR = crate::BitReader;
#[doc = "Field `LEFT_EN` writer - 1: Enable left channel pdm data sampling; 0: Disable left channel pdm data sampling"]
pub type LeftEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIGHT_EN` reader - 1: Enable right channel pdm data sampling; 0: Disable right channel pdm data sampling"]
pub type RightEnR = crate::BitReader;
#[doc = "Field `RIGHT_EN` writer - 1: Enable right channel pdm data sampling; 0: Disable right channel pdm data sampling"]
pub type RightEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STEREO_EN` reader - 1:Enable double channels pdm data sampling; 0: Disable double channels pdm data sampling"]
pub type StereoEnR = crate::BitReader;
#[doc = "Field `STEREO_EN` writer - 1:Enable double channels pdm data sampling; 0: Disable double channels pdm data sampling"]
pub type StereoEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SWAP_EN` reader - 1: Swap right channel and left channel pdm data; 0: Not swap right channel and left channel pdm data"]
pub type SwapEnR = crate::BitReader;
#[doc = "Field `SWAP_EN` writer - 1: Swap right channel and left channel pdm data; 0: Not swap right channel and left channel pdm data"]
pub type SwapEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bit 0 - 1:Enable pdm module; 0: Disable pdm module"]
#[inline(always)]
pub fn pdmcoreen(&self) -> PdmcoreenR {
PdmcoreenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:Clk select dll 3.072MHz; 0: Clk selct xtal 9.6MHz"]
#[inline(always)]
pub fn clk_sel(&self) -> ClkSelR {
ClkSelR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:5 - Clock frequency division ratio of 3.072MHz or 9.6MHz according to register clk_sel"]
#[inline(always)]
pub fn clk_div(&self) -> ClkDivR {
ClkDivR::new(((self.bits >> 2) & 0x0f) as u8)
}
#[doc = "Bit 6 - 1: Enable left channel pdm data sampling; 0: Disable left channel pdm data sampling"]
#[inline(always)]
pub fn left_en(&self) -> LeftEnR {
LeftEnR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 1: Enable right channel pdm data sampling; 0: Disable right channel pdm data sampling"]
#[inline(always)]
pub fn right_en(&self) -> RightEnR {
RightEnR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - 1:Enable double channels pdm data sampling; 0: Disable double channels pdm data sampling"]
#[inline(always)]
pub fn stereo_en(&self) -> StereoEnR {
StereoEnR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 1: Swap right channel and left channel pdm data; 0: Not swap right channel and left channel pdm data"]
#[inline(always)]
pub fn swap_en(&self) -> SwapEnR {
SwapEnR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bit 0 - 1:Enable pdm module; 0: Disable pdm module"]
#[inline(always)]
#[must_use]
pub fn pdmcoreen(&mut self) -> PdmcoreenW<Cfg0Spec> {
PdmcoreenW::new(self, 0)
}
#[doc = "Bit 1 - 1:Clk select dll 3.072MHz; 0: Clk selct xtal 9.6MHz"]
#[inline(always)]
#[must_use]
pub fn clk_sel(&mut self) -> ClkSelW<Cfg0Spec> {
ClkSelW::new(self, 1)
}
#[doc = "Bits 2:5 - Clock frequency division ratio of 3.072MHz or 9.6MHz according to register clk_sel"]
#[inline(always)]
#[must_use]
pub fn clk_div(&mut self) -> ClkDivW<Cfg0Spec> {
ClkDivW::new(self, 2)
}
#[doc = "Bit 6 - 1: Enable left channel pdm data sampling; 0: Disable left channel pdm data sampling"]
#[inline(always)]
#[must_use]
pub fn left_en(&mut self) -> LeftEnW<Cfg0Spec> {
LeftEnW::new(self, 6)
}
#[doc = "Bit 7 - 1: Enable right channel pdm data sampling; 0: Disable right channel pdm data sampling"]
#[inline(always)]
#[must_use]
pub fn right_en(&mut self) -> RightEnW<Cfg0Spec> {
RightEnW::new(self, 7)
}
#[doc = "Bit 8 - 1:Enable double channels pdm data sampling; 0: Disable double channels pdm data sampling"]
#[inline(always)]
#[must_use]
pub fn stereo_en(&mut self) -> StereoEnW<Cfg0Spec> {
StereoEnW::new(self, 8)
}
#[doc = "Bit 9 - 1: Swap right channel and left channel pdm data; 0: Not swap right channel and left channel pdm data"]
#[inline(always)]
#[must_use]
pub fn swap_en(&mut self) -> SwapEnW<Cfg0Spec> {
SwapEnW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cfg0Spec> {
RsvdW::new(self, 10)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cfg0Spec;
impl crate::RegisterSpec for Cfg0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cfg0::R`](R) reader structure"]
impl crate::Readable for Cfg0Spec {}
#[doc = "`write(|w| ..)` method takes [`cfg0::W`](W) writer structure"]
impl crate::Writable for Cfg0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CFG0 to value 0"]
impl crate::Resettable for Cfg0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CFG1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg1`]
module"]
#[doc(alias = "CFG1")]
pub type Cfg1 = crate::Reg<cfg1::Cfg1Spec>;
#[doc = ""]
pub mod cfg1 {
#[doc = "Register `CFG1` reader"]
pub type R = crate::R<Cfg1Spec>;
#[doc = "Register `CFG1` writer"]
pub type W = crate::W<Cfg1Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `SAMPLE_DLY_L` reader - The number of delay dff before the left data stream in processing"]
pub type SampleDlyLR = crate::FieldReader;
#[doc = "Field `SAMPLE_DLY_L` writer - The number of delay dff before the left data stream in processing"]
pub type SampleDlyLW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SAMPLE_DLY_R` reader - The number of delay dff before the right data stream in processing"]
pub type SampleDlyRR = crate::FieldReader;
#[doc = "Field `SAMPLE_DLY_R` writer - The number of delay dff before the right data stream in processing"]
pub type SampleDlyRW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:7 - The number of delay dff before the left data stream in processing"]
#[inline(always)]
pub fn sample_dly_l(&self) -> SampleDlyLR {
SampleDlyLR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bits 8:10 - The number of delay dff before the right data stream in processing"]
#[inline(always)]
pub fn sample_dly_r(&self) -> SampleDlyRR {
SampleDlyRR::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cfg1Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 5:7 - The number of delay dff before the left data stream in processing"]
#[inline(always)]
#[must_use]
pub fn sample_dly_l(&mut self) -> SampleDlyLW<Cfg1Spec> {
SampleDlyLW::new(self, 5)
}
#[doc = "Bits 8:10 - The number of delay dff before the right data stream in processing"]
#[inline(always)]
#[must_use]
pub fn sample_dly_r(&mut self) -> SampleDlyRW<Cfg1Spec> {
SampleDlyRW::new(self, 8)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cfg1Spec> {
RsvdW::new(self, 11)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cfg1Spec;
impl crate::RegisterSpec for Cfg1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cfg1::R`](R) reader structure"]
impl crate::Readable for Cfg1Spec {}
#[doc = "`write(|w| ..)` method takes [`cfg1::W`](W) writer structure"]
impl crate::Writable for Cfg1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CFG1 to value 0"]
impl crate::Resettable for Cfg1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SINC_CFG (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sinc_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sinc_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sinc_cfg`]
module"]
#[doc(alias = "SINC_CFG")]
pub type SincCfg = crate::Reg<sinc_cfg::SincCfgSpec>;
#[doc = ""]
pub mod sinc_cfg {
#[doc = "Register `SINC_CFG` reader"]
pub type R = crate::R<SincCfgSpec>;
#[doc = "Register `SINC_CFG` writer"]
pub type W = crate::W<SincCfgSpec>;
#[doc = "Field `SINC_RATE` reader - dowmsampling rate of sinc filter"]
pub type SincRateR = crate::FieldReader;
#[doc = "Field `SINC_RATE` writer - dowmsampling rate of sinc filter"]
pub type SincRateW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SINC_ORDER_SEL` reader - 1:select four differentiators in sinc filter; 0:select three differentiators in sinc filter"]
pub type SincOrderSelR = crate::BitReader;
#[doc = "Field `SINC_ORDER_SEL` writer - 1:select four differentiators in sinc filter; 0:select three differentiators in sinc filter"]
pub type SincOrderSelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:7 - dowmsampling rate of sinc filter"]
#[inline(always)]
pub fn sinc_rate(&self) -> SincRateR {
SincRateR::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - 1:select four differentiators in sinc filter; 0:select three differentiators in sinc filter"]
#[inline(always)]
pub fn sinc_order_sel(&self) -> SincOrderSelR {
SincOrderSelR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - dowmsampling rate of sinc filter"]
#[inline(always)]
#[must_use]
pub fn sinc_rate(&mut self) -> SincRateW<SincCfgSpec> {
SincRateW::new(self, 0)
}
#[doc = "Bit 8 - 1:select four differentiators in sinc filter; 0:select three differentiators in sinc filter"]
#[inline(always)]
#[must_use]
pub fn sinc_order_sel(&mut self) -> SincOrderSelW<SincCfgSpec> {
SincOrderSelW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SincCfgSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sinc_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sinc_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SincCfgSpec;
impl crate::RegisterSpec for SincCfgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sinc_cfg::R`](R) reader structure"]
impl crate::Readable for SincCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`sinc_cfg::W`](W) writer structure"]
impl crate::Writable for SincCfgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SINC_CFG to value 0"]
impl crate::Resettable for SincCfgSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd3`]
module"]
#[doc(alias = "RSVD3")]
pub type Rsvd3 = crate::Reg<rsvd3::Rsvd3Spec>;
#[doc = ""]
pub mod rsvd3 {
#[doc = "Register `RSVD3` reader"]
pub type R = crate::R<Rsvd3Spec>;
#[doc = "Register `RSVD3` writer"]
pub type W = crate::W<Rsvd3Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd3Spec;
impl crate::RegisterSpec for Rsvd3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd3::R`](R) reader structure"]
impl crate::Readable for Rsvd3Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd3::W`](W) writer structure"]
impl crate::Writable for Rsvd3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD3 to value 0"]
impl crate::Resettable for Rsvd3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "HPF_CFG (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpf_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpf_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hpf_cfg`]
module"]
#[doc(alias = "HPF_CFG")]
pub type HpfCfg = crate::Reg<hpf_cfg::HpfCfgSpec>;
#[doc = ""]
pub mod hpf_cfg {
#[doc = "Register `HPF_CFG` reader"]
pub type R = crate::R<HpfCfgSpec>;
#[doc = "Register `HPF_CFG` writer"]
pub type W = crate::W<HpfCfgSpec>;
#[doc = "Field `HPF_COEFF` reader - coefficient of high-pass filter"]
pub type HpfCoeffR = crate::FieldReader;
#[doc = "Field `HPF_COEFF` writer - coefficient of high-pass filter"]
pub type HpfCoeffW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `HPF_BYPASS` reader - 1:bypass-high pass filter ; 0: enable high-pass filter"]
pub type HpfBypassR = crate::BitReader;
#[doc = "Field `HPF_BYPASS` writer - 1:bypass-high pass filter ; 0: enable high-pass filter"]
pub type HpfBypassW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HPF_RST` reader - 1:high-pass filter normal operation ; 0:reset high-pass filter"]
pub type HpfRstR = crate::BitReader;
#[doc = "Field `HPF_RST` writer - 1:high-pass filter normal operation ; 0:reset high-pass filter"]
pub type HpfRstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:3 - coefficient of high-pass filter"]
#[inline(always)]
pub fn hpf_coeff(&self) -> HpfCoeffR {
HpfCoeffR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4 - 1:bypass-high pass filter ; 0: enable high-pass filter"]
#[inline(always)]
pub fn hpf_bypass(&self) -> HpfBypassR {
HpfBypassR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 1:high-pass filter normal operation ; 0:reset high-pass filter"]
#[inline(always)]
pub fn hpf_rst(&self) -> HpfRstR {
HpfRstR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3 - coefficient of high-pass filter"]
#[inline(always)]
#[must_use]
pub fn hpf_coeff(&mut self) -> HpfCoeffW<HpfCfgSpec> {
HpfCoeffW::new(self, 0)
}
#[doc = "Bit 4 - 1:bypass-high pass filter ; 0: enable high-pass filter"]
#[inline(always)]
#[must_use]
pub fn hpf_bypass(&mut self) -> HpfBypassW<HpfCfgSpec> {
HpfBypassW::new(self, 4)
}
#[doc = "Bit 5 - 1:high-pass filter normal operation ; 0:reset high-pass filter"]
#[inline(always)]
#[must_use]
pub fn hpf_rst(&mut self) -> HpfRstW<HpfCfgSpec> {
HpfRstW::new(self, 5)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<HpfCfgSpec> {
RsvdW::new(self, 6)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpf_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpf_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HpfCfgSpec;
impl crate::RegisterSpec for HpfCfgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hpf_cfg::R`](R) reader structure"]
impl crate::Readable for HpfCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`hpf_cfg::W`](W) writer structure"]
impl crate::Writable for HpfCfgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HPF_CFG to value 0"]
impl crate::Resettable for HpfCfgSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PGA_CFG (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pga_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pga_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pga_cfg`]
module"]
#[doc(alias = "PGA_CFG")]
pub type PgaCfg = crate::Reg<pga_cfg::PgaCfgSpec>;
#[doc = ""]
pub mod pga_cfg {
#[doc = "Register `PGA_CFG` reader"]
pub type R = crate::R<PgaCfgSpec>;
#[doc = "Register `PGA_CFG` writer"]
pub type W = crate::W<PgaCfgSpec>;
#[doc = "Field `PGA_GAIN_L` reader - left channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
pub type PgaGainLR = crate::FieldReader;
#[doc = "Field `PGA_GAIN_L` writer - left channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
pub type PgaGainLW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `PGA_GAIN_R` reader - right channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
pub type PgaGainRR = crate::FieldReader;
#[doc = "Field `PGA_GAIN_R` writer - right channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
pub type PgaGainRW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:6 - left channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
#[inline(always)]
pub fn pga_gain_l(&self) -> PgaGainLR {
PgaGainLR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:13 - right channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
#[inline(always)]
pub fn pga_gain_r(&self) -> PgaGainRR {
PgaGainRR::new(((self.bits >> 7) & 0x7f) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:6 - left channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
#[inline(always)]
#[must_use]
pub fn pga_gain_l(&mut self) -> PgaGainLW<PgaCfgSpec> {
PgaGainLW::new(self, 0)
}
#[doc = "Bits 7:13 - right channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB"]
#[inline(always)]
#[must_use]
pub fn pga_gain_r(&mut self) -> PgaGainRW<PgaCfgSpec> {
PgaGainRW::new(self, 7)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PgaCfgSpec> {
RsvdW::new(self, 14)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pga_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pga_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PgaCfgSpec;
impl crate::RegisterSpec for PgaCfgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pga_cfg::R`](R) reader structure"]
impl crate::Readable for PgaCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`pga_cfg::W`](W) writer structure"]
impl crate::Writable for PgaCfgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PGA_CFG to value 0"]
impl crate::Resettable for PgaCfgSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd2`]
module"]
#[doc(alias = "RSVD2")]
pub type Rsvd2 = crate::Reg<rsvd2::Rsvd2Spec>;
#[doc = ""]
pub mod rsvd2 {
#[doc = "Register `RSVD2` reader"]
pub type R = crate::R<Rsvd2Spec>;
#[doc = "Register `RSVD2` writer"]
pub type W = crate::W<Rsvd2Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd2Spec;
impl crate::RegisterSpec for Rsvd2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd2::R`](R) reader structure"]
impl crate::Readable for Rsvd2Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd2::W`](W) writer structure"]
impl crate::Writable for Rsvd2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD2 to value 0"]
impl crate::Resettable for Rsvd2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "LPF_CFG6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpf_cfg6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpf_cfg6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpf_cfg6`]
module"]
#[doc(alias = "LPF_CFG6")]
pub type LpfCfg6 = crate::Reg<lpf_cfg6::LpfCfg6Spec>;
#[doc = ""]
pub mod lpf_cfg6 {
#[doc = "Register `LPF_CFG6` reader"]
pub type R = crate::R<LpfCfg6Spec>;
#[doc = "Register `LPF_CFG6` writer"]
pub type W = crate::W<LpfCfg6Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `LPF_DS` reader - 1:downsampling rate of low pass filter is two;0:No downsampling of low pass filter"]
pub type LpfDsR = crate::BitReader;
#[doc = "Field `LPF_DS` writer - 1:downsampling rate of low pass filter is two;0:No downsampling of low pass filter"]
pub type LpfDsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LPF_BYPASS` reader - 1:bypass low-pass filter ; 0: enable low-pass filter"]
pub type LpfBypassR = crate::BitReader;
#[doc = "Field `LPF_BYPASS` writer - 1:bypass low-pass filter ; 0: enable low-pass filter"]
pub type LpfBypassW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bit 12 - 1:downsampling rate of low pass filter is two;0:No downsampling of low pass filter"]
#[inline(always)]
pub fn lpf_ds(&self) -> LpfDsR {
LpfDsR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - 1:bypass low-pass filter ; 0: enable low-pass filter"]
#[inline(always)]
pub fn lpf_bypass(&self) -> LpfBypassR {
LpfBypassR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<LpfCfg6Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bit 12 - 1:downsampling rate of low pass filter is two;0:No downsampling of low pass filter"]
#[inline(always)]
#[must_use]
pub fn lpf_ds(&mut self) -> LpfDsW<LpfCfg6Spec> {
LpfDsW::new(self, 12)
}
#[doc = "Bit 13 - 1:bypass low-pass filter ; 0: enable low-pass filter"]
#[inline(always)]
#[must_use]
pub fn lpf_bypass(&mut self) -> LpfBypassW<LpfCfg6Spec> {
LpfBypassW::new(self, 13)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<LpfCfg6Spec> {
RsvdW::new(self, 14)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpf_cfg6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpf_cfg6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LpfCfg6Spec;
impl crate::RegisterSpec for LpfCfg6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lpf_cfg6::R`](R) reader structure"]
impl crate::Readable for LpfCfg6Spec {}
#[doc = "`write(|w| ..)` method takes [`lpf_cfg6::W`](W) writer structure"]
impl crate::Writable for LpfCfg6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LPF_CFG6 to value 0"]
impl crate::Resettable for LpfCfg6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO_CFG (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_cfg`]
module"]
#[doc(alias = "FIFO_CFG")]
pub type FifoCfg = crate::Reg<fifo_cfg::FifoCfgSpec>;
#[doc = ""]
pub mod fifo_cfg {
#[doc = "Register `FIFO_CFG` reader"]
pub type R = crate::R<FifoCfgSpec>;
#[doc = "Register `FIFO_CFG` writer"]
pub type W = crate::W<FifoCfgSpec>;
#[doc = "Field `BYTE_CON` reader - 1: combine left channel and right channel; 0: not combine left channel and right channel"]
pub type ByteConR = crate::BitReader;
#[doc = "Field `BYTE_CON` writer - 1: combine left channel and right channel; 0: not combine left channel and right channel"]
pub type ByteConW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BYTE_TRUNC` reader - 1: 16bits output ; 0: 24bits output ;2: 8bits output ; 3: 32bits output"]
pub type ByteTruncR = crate::FieldReader;
#[doc = "Field `BYTE_TRUNC` writer - 1: 16bits output ; 0: 24bits output ;2: 8bits output ; 3: 32bits output"]
pub type ByteTruncW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PDM_SHIFT` reader - the number of data left shift for higher data accuracy"]
pub type PdmShiftR = crate::FieldReader;
#[doc = "Field `PDM_SHIFT` writer - the number of data left shift for higher data accuracy"]
pub type PdmShiftW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RX_DMA_MSK_R` reader - 1:disable right channel dma request; 0: enable right channel dma request"]
pub type RxDmaMskRR = crate::BitReader;
#[doc = "Field `RX_DMA_MSK_R` writer - 1:disable right channel dma request; 0: enable right channel dma request"]
pub type RxDmaMskRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RX_DMA_MSK_L` reader - 1:disable left channel dma request; 0: enable left channel dma request"]
pub type RxDmaMskLR = crate::BitReader;
#[doc = "Field `RX_DMA_MSK_L` writer - 1:disable left channel dma request; 0: enable left channel dma request"]
pub type RxDmaMskLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LR_CHG` reader - 1:exchange storage location of left and right channel; 0: don't exchange storage location of left and right channel"]
pub type LrChgR = crate::BitReader;
#[doc = "Field `LR_CHG` writer - 1:exchange storage location of left and right channel; 0: don't exchange storage location of left and right channel"]
pub type LrChgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - 1: combine left channel and right channel; 0: not combine left channel and right channel"]
#[inline(always)]
pub fn byte_con(&self) -> ByteConR {
ByteConR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - 1: 16bits output ; 0: 24bits output ;2: 8bits output ; 3: 32bits output"]
#[inline(always)]
pub fn byte_trunc(&self) -> ByteTruncR {
ByteTruncR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:5 - the number of data left shift for higher data accuracy"]
#[inline(always)]
pub fn pdm_shift(&self) -> PdmShiftR {
PdmShiftR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bit 6 - 1:disable right channel dma request; 0: enable right channel dma request"]
#[inline(always)]
pub fn rx_dma_msk_r(&self) -> RxDmaMskRR {
RxDmaMskRR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 1:disable left channel dma request; 0: enable left channel dma request"]
#[inline(always)]
pub fn rx_dma_msk_l(&self) -> RxDmaMskLR {
RxDmaMskLR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - 1:exchange storage location of left and right channel; 0: don't exchange storage location of left and right channel"]
#[inline(always)]
pub fn lr_chg(&self) -> LrChgR {
LrChgR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - 1: combine left channel and right channel; 0: not combine left channel and right channel"]
#[inline(always)]
#[must_use]
pub fn byte_con(&mut self) -> ByteConW<FifoCfgSpec> {
ByteConW::new(self, 0)
}
#[doc = "Bits 1:2 - 1: 16bits output ; 0: 24bits output ;2: 8bits output ; 3: 32bits output"]
#[inline(always)]
#[must_use]
pub fn byte_trunc(&mut self) -> ByteTruncW<FifoCfgSpec> {
ByteTruncW::new(self, 1)
}
#[doc = "Bits 3:5 - the number of data left shift for higher data accuracy"]
#[inline(always)]
#[must_use]
pub fn pdm_shift(&mut self) -> PdmShiftW<FifoCfgSpec> {
PdmShiftW::new(self, 3)
}
#[doc = "Bit 6 - 1:disable right channel dma request; 0: enable right channel dma request"]
#[inline(always)]
#[must_use]
pub fn rx_dma_msk_r(&mut self) -> RxDmaMskRW<FifoCfgSpec> {
RxDmaMskRW::new(self, 6)
}
#[doc = "Bit 7 - 1:disable left channel dma request; 0: enable left channel dma request"]
#[inline(always)]
#[must_use]
pub fn rx_dma_msk_l(&mut self) -> RxDmaMskLW<FifoCfgSpec> {
RxDmaMskLW::new(self, 7)
}
#[doc = "Bit 8 - 1:exchange storage location of left and right channel; 0: don't exchange storage location of left and right channel"]
#[inline(always)]
#[must_use]
pub fn lr_chg(&mut self) -> LrChgW<FifoCfgSpec> {
LrChgW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoCfgSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoCfgSpec;
impl crate::RegisterSpec for FifoCfgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo_cfg::R`](R) reader structure"]
impl crate::Readable for FifoCfgSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo_cfg::W`](W) writer structure"]
impl crate::Writable for FifoCfgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO_CFG to value 0"]
impl crate::Resettable for FifoCfgSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO_ST (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_st`]
module"]
#[doc(alias = "FIFO_ST")]
pub type FifoSt = crate::Reg<fifo_st::FifoStSpec>;
#[doc = ""]
pub mod fifo_st {
#[doc = "Register `FIFO_ST` reader"]
pub type R = crate::R<FifoStSpec>;
#[doc = "Register `FIFO_ST` writer"]
pub type W = crate::W<FifoStSpec>;
#[doc = "Field `ALMOST_EMPTY_R` reader - 1 indicates right channel fifo is less than two datas left"]
pub type AlmostEmptyRR = crate::BitReader;
#[doc = "Field `ALMOST_EMPTY_R` writer - 1 indicates right channel fifo is less than two datas left"]
pub type AlmostEmptyRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALMOST_FULL_R` reader - 1 indicates right channel fifo is less than two full"]
pub type AlmostFullRR = crate::BitReader;
#[doc = "Field `ALMOST_FULL_R` writer - 1 indicates right channel fifo is less than two full"]
pub type AlmostFullRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EMPTY_R` reader - 1 indicates right channel fifo is empty"]
pub type EmptyRR = crate::BitReader;
#[doc = "Field `EMPTY_R` writer - 1 indicates right channel fifo is empty"]
pub type EmptyRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FULL_R` reader - 1 indicates right channel fifo is full"]
pub type FullRR = crate::BitReader;
#[doc = "Field `FULL_R` writer - 1 indicates right channel fifo is full"]
pub type FullRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALMOST_EMPTY_L` reader - 1 indicates left channel fifo is less than two datas left"]
pub type AlmostEmptyLR = crate::BitReader;
#[doc = "Field `ALMOST_EMPTY_L` writer - 1 indicates left channel fifo is less than two datas left"]
pub type AlmostEmptyLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALMOST_FULL_L` reader - 1 indicates left channel fifo is less than two full"]
pub type AlmostFullLR = crate::BitReader;
#[doc = "Field `ALMOST_FULL_L` writer - 1 indicates left channel fifo is less than two full"]
pub type AlmostFullLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EMPTY_L` reader - 1 indicates left channel fifo is empty"]
pub type EmptyLR = crate::BitReader;
#[doc = "Field `EMPTY_L` writer - 1 indicates left channel fifo is empty"]
pub type EmptyLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FULL_L` reader - 1 indicates left channel fifo is full"]
pub type FullLR = crate::BitReader;
#[doc = "Field `FULL_L` writer - 1 indicates left channel fifo is full"]
pub type FullLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - 1 indicates right channel fifo is less than two datas left"]
#[inline(always)]
pub fn almost_empty_r(&self) -> AlmostEmptyRR {
AlmostEmptyRR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1 indicates right channel fifo is less than two full"]
#[inline(always)]
pub fn almost_full_r(&self) -> AlmostFullRR {
AlmostFullRR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 1 indicates right channel fifo is empty"]
#[inline(always)]
pub fn empty_r(&self) -> EmptyRR {
EmptyRR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 1 indicates right channel fifo is full"]
#[inline(always)]
pub fn full_r(&self) -> FullRR {
FullRR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 1 indicates left channel fifo is less than two datas left"]
#[inline(always)]
pub fn almost_empty_l(&self) -> AlmostEmptyLR {
AlmostEmptyLR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 1 indicates left channel fifo is less than two full"]
#[inline(always)]
pub fn almost_full_l(&self) -> AlmostFullLR {
AlmostFullLR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - 1 indicates left channel fifo is empty"]
#[inline(always)]
pub fn empty_l(&self) -> EmptyLR {
EmptyLR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 1 indicates left channel fifo is full"]
#[inline(always)]
pub fn full_l(&self) -> FullLR {
FullLR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 1 indicates right channel fifo is less than two datas left"]
#[inline(always)]
#[must_use]
pub fn almost_empty_r(&mut self) -> AlmostEmptyRW<FifoStSpec> {
AlmostEmptyRW::new(self, 0)
}
#[doc = "Bit 1 - 1 indicates right channel fifo is less than two full"]
#[inline(always)]
#[must_use]
pub fn almost_full_r(&mut self) -> AlmostFullRW<FifoStSpec> {
AlmostFullRW::new(self, 1)
}
#[doc = "Bit 2 - 1 indicates right channel fifo is empty"]
#[inline(always)]
#[must_use]
pub fn empty_r(&mut self) -> EmptyRW<FifoStSpec> {
EmptyRW::new(self, 2)
}
#[doc = "Bit 3 - 1 indicates right channel fifo is full"]
#[inline(always)]
#[must_use]
pub fn full_r(&mut self) -> FullRW<FifoStSpec> {
FullRW::new(self, 3)
}
#[doc = "Bit 4 - 1 indicates left channel fifo is less than two datas left"]
#[inline(always)]
#[must_use]
pub fn almost_empty_l(&mut self) -> AlmostEmptyLW<FifoStSpec> {
AlmostEmptyLW::new(self, 4)
}
#[doc = "Bit 5 - 1 indicates left channel fifo is less than two full"]
#[inline(always)]
#[must_use]
pub fn almost_full_l(&mut self) -> AlmostFullLW<FifoStSpec> {
AlmostFullLW::new(self, 5)
}
#[doc = "Bit 6 - 1 indicates left channel fifo is empty"]
#[inline(always)]
#[must_use]
pub fn empty_l(&mut self) -> EmptyLW<FifoStSpec> {
EmptyLW::new(self, 6)
}
#[doc = "Bit 7 - 1 indicates left channel fifo is full"]
#[inline(always)]
#[must_use]
pub fn full_l(&mut self) -> FullLW<FifoStSpec> {
FullLW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoStSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoStSpec;
impl crate::RegisterSpec for FifoStSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo_st::R`](R) reader structure"]
impl crate::Readable for FifoStSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo_st::W`](W) writer structure"]
impl crate::Writable for FifoStSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO_ST to value 0"]
impl crate::Resettable for FifoStSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INT_ST (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`]
module"]
#[doc(alias = "INT_ST")]
pub type IntSt = crate::Reg<int_st::IntStSpec>;
#[doc = ""]
pub mod int_st {
#[doc = "Register `INT_ST` reader"]
pub type R = crate::R<IntStSpec>;
#[doc = "Register `INT_ST` writer"]
pub type W = crate::W<IntStSpec>;
#[doc = "Field `OVERFLOW_R` reader - 1 indicates right channel fifo has already overflowed and as irq at same time"]
pub type OverflowRR = crate::BitReader;
#[doc = "Field `OVERFLOW_R` writer - 1 indicates right channel fifo has already overflowed and as irq at same time"]
pub type OverflowRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVERFLOW_L` reader - 1 indicates left channel fifo has already overflowed and as irq at same time"]
pub type OverflowLR = crate::BitReader;
#[doc = "Field `OVERFLOW_L` writer - 1 indicates left channel fifo has already overflowed and as irq at same time"]
pub type OverflowLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - 1 indicates right channel fifo has already overflowed and as irq at same time"]
#[inline(always)]
pub fn overflow_r(&self) -> OverflowRR {
OverflowRR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1 indicates left channel fifo has already overflowed and as irq at same time"]
#[inline(always)]
pub fn overflow_l(&self) -> OverflowLR {
OverflowLR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 1 indicates right channel fifo has already overflowed and as irq at same time"]
#[inline(always)]
#[must_use]
pub fn overflow_r(&mut self) -> OverflowRW<IntStSpec> {
OverflowRW::new(self, 0)
}
#[doc = "Bit 1 - 1 indicates left channel fifo has already overflowed and as irq at same time"]
#[inline(always)]
#[must_use]
pub fn overflow_l(&mut self) -> OverflowLW<IntStSpec> {
OverflowLW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IntStSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntStSpec;
impl crate::RegisterSpec for IntStSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
impl crate::Readable for IntStSpec {}
#[doc = "`write(|w| ..)` method takes [`int_st::W`](W) writer structure"]
impl crate::Writable for IntStSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_ST to value 0"]
impl crate::Resettable for IntStSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INT_MSK (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk`]
module"]
#[doc(alias = "INT_MSK")]
pub type IntMsk = crate::Reg<int_msk::IntMskSpec>;
#[doc = ""]
pub mod int_msk {
#[doc = "Register `INT_MSK` reader"]
pub type R = crate::R<IntMskSpec>;
#[doc = "Register `INT_MSK` writer"]
pub type W = crate::W<IntMskSpec>;
#[doc = "Field `INT_MASK_R` reader - 1:disable right channel irq to system; 0: enable right channel irq to system"]
pub type IntMaskRR = crate::BitReader;
#[doc = "Field `INT_MASK_R` writer - 1:disable right channel irq to system; 0: enable right channel irq to system"]
pub type IntMaskRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_MASK_L` reader - 1:disable left channel irq to system; 0: enable left channel irq to system"]
pub type IntMaskLR = crate::BitReader;
#[doc = "Field `INT_MASK_L` writer - 1:disable left channel irq to system; 0: enable left channel irq to system"]
pub type IntMaskLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - 1:disable right channel irq to system; 0: enable right channel irq to system"]
#[inline(always)]
pub fn int_mask_r(&self) -> IntMaskRR {
IntMaskRR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:disable left channel irq to system; 0: enable left channel irq to system"]
#[inline(always)]
pub fn int_mask_l(&self) -> IntMaskLR {
IntMaskLR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - 1:disable right channel irq to system; 0: enable right channel irq to system"]
#[inline(always)]
#[must_use]
pub fn int_mask_r(&mut self) -> IntMaskRW<IntMskSpec> {
IntMaskRW::new(self, 0)
}
#[doc = "Bit 1 - 1:disable left channel irq to system; 0: enable left channel irq to system"]
#[inline(always)]
#[must_use]
pub fn int_mask_l(&mut self) -> IntMaskLW<IntMskSpec> {
IntMaskLW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IntMskSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntMskSpec;
impl crate::RegisterSpec for IntMskSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_msk::R`](R) reader structure"]
impl crate::Readable for IntMskSpec {}
#[doc = "`write(|w| ..)` method takes [`int_msk::W`](W) writer structure"]
impl crate::Writable for IntMskSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_MSK to value 0"]
impl crate::Resettable for IntMskSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INT_CLR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`]
module"]
#[doc(alias = "INT_CLR")]
pub type IntClr = crate::Reg<int_clr::IntClrSpec>;
#[doc = ""]
pub mod int_clr {
#[doc = "Register `INT_CLR` reader"]
pub type R = crate::R<IntClrSpec>;
#[doc = "Register `INT_CLR` writer"]
pub type W = crate::W<IntClrSpec>;
#[doc = "Field `INT_CLR_R` reader - clear right channel irq"]
pub type IntClrRR = crate::BitReader;
#[doc = "Field `INT_CLR_R` writer - clear right channel irq"]
pub type IntClrRW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_CLR_L` reader - clear left channel irq"]
pub type IntClrLR = crate::BitReader;
#[doc = "Field `INT_CLR_L` writer - clear left channel irq"]
pub type IntClrLW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - clear right channel irq"]
#[inline(always)]
pub fn int_clr_r(&self) -> IntClrRR {
IntClrRR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - clear left channel irq"]
#[inline(always)]
pub fn int_clr_l(&self) -> IntClrLR {
IntClrLR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - clear right channel irq"]
#[inline(always)]
#[must_use]
pub fn int_clr_r(&mut self) -> IntClrRW<IntClrSpec> {
IntClrRW::new(self, 0)
}
#[doc = "Bit 1 - clear left channel irq"]
#[inline(always)]
#[must_use]
pub fn int_clr_l(&mut self) -> IntClrLW<IntClrSpec> {
IntClrLW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IntClrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntClrSpec;
impl crate::RegisterSpec for IntClrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
impl crate::Readable for IntClrSpec {}
#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
impl crate::Writable for IntClrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_CLR to value 0"]
impl crate::Resettable for IntClrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "I2C1"]
pub struct I2c1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2c1 {}
impl I2c1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2c1::RegisterBlock = 0x5009_c000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2c1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2c1 {
type Target = i2c1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2c1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c1").finish()
}
}
#[doc = "I2C1"]
pub mod i2c1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr: Cr,
tcr: Tcr,
ier: Ier,
sr: Sr,
dbr: Dbr,
sar: Sar,
lcr: Lcr,
wcr: Wcr,
rccr: Rccr,
bmr: Bmr,
dnr: Dnr,
rsvd1: Rsvd1,
fifo: Fifo,
}
impl RegisterBlock {
#[doc = "0x00 - Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x04 - Transfer Control register"]
#[inline(always)]
pub const fn tcr(&self) -> &Tcr {
&self.tcr
}
#[doc = "0x08 - Interrupt Enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x0c - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x10 - Data Buffer register"]
#[inline(always)]
pub const fn dbr(&self) -> &Dbr {
&self.dbr
}
#[doc = "0x14 - Slave Address Register"]
#[inline(always)]
pub const fn sar(&self) -> &Sar {
&self.sar
}
#[doc = "0x18 - Load Count Register"]
#[inline(always)]
pub const fn lcr(&self) -> &Lcr {
&self.lcr
}
#[doc = "0x1c - Wait Count Register"]
#[inline(always)]
pub const fn wcr(&self) -> &Wcr {
&self.wcr
}
#[doc = "0x20 - Bus Reset Cycle Counter Register"]
#[inline(always)]
pub const fn rccr(&self) -> &Rccr {
&self.rccr
}
#[doc = "0x24 - Bus Monitor Register"]
#[inline(always)]
pub const fn bmr(&self) -> &Bmr {
&self.bmr
}
#[doc = "0x28 - DMA number register"]
#[inline(always)]
pub const fn dnr(&self) -> &Dnr {
&self.dnr
}
#[doc = "0x2c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x30 - FIFO Register"]
#[inline(always)]
pub const fn fifo(&self) -> &Fifo {
&self.fifo
}
}
#[doc = "CR (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `MODE` reader - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeR = crate::FieldReader;
#[doc = "Field `MODE` writer - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IUE` reader - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueR = crate::BitReader;
#[doc = "Field `IUE` writer - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLE` reader - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleR = crate::BitReader;
#[doc = "Field `SCLE` writer - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAEN` reader - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenR = crate::BitReader;
#[doc = "Field `DMAEN` writer - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTNACK` reader - Generate NACK for last DMA Read transfer"]
pub type LastnackR = crate::BitReader;
#[doc = "Field `LASTNACK` writer - Generate NACK for last DMA Read transfer"]
pub type LastnackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTSTOP` reader - Generate STOP for last DMA transfer"]
pub type LaststopR = crate::BitReader;
#[doc = "Field `LASTSTOP` writer - Generate STOP for last DMA transfer"]
pub type LaststopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDE` reader - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeR = crate::BitReader;
#[doc = "Field `MSDE` writer - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLPP` reader - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppR = crate::BitReader;
#[doc = "Field `SCLPP` writer - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLVEN` reader - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenR = crate::BitReader;
#[doc = "Field `SLVEN` writer - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DNF` reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfR = crate::FieldReader;
#[doc = "Field `DNF` writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `BRGRST` reader - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstR = crate::BitReader;
#[doc = "Field `BRGRST` writer - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSTREQ` reader - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqR = crate::BitReader;
#[doc = "Field `RSTREQ` writer - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UR` reader - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrR = crate::BitReader;
#[doc = "Field `UR` writer - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
pub fn iue(&self) -> IueR {
IueR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
pub fn scle(&self) -> ScleR {
ScleR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
pub fn dmaen(&self) -> DmaenR {
DmaenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
pub fn lastnack(&self) -> LastnackR {
LastnackR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
pub fn laststop(&self) -> LaststopR {
LaststopR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
pub fn msde(&self) -> MsdeR {
MsdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
pub fn sclpp(&self) -> SclppR {
SclppR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
pub fn slven(&self) -> SlvenR {
SlvenR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
pub fn dnf(&self) -> DnfR {
DnfR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:28"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 15) & 0x3fff) as u16)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
pub fn brgrst(&self) -> BrgrstR {
BrgrstR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
pub fn rstreq(&self) -> RstreqR {
RstreqR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
pub fn ur(&self) -> UrR {
UrR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<CrSpec> {
ModeW::new(self, 0)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
#[must_use]
pub fn iue(&mut self) -> IueW<CrSpec> {
IueW::new(self, 2)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
#[must_use]
pub fn scle(&mut self) -> ScleW<CrSpec> {
ScleW::new(self, 3)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
#[must_use]
pub fn dmaen(&mut self) -> DmaenW<CrSpec> {
DmaenW::new(self, 4)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
#[must_use]
pub fn lastnack(&mut self) -> LastnackW<CrSpec> {
LastnackW::new(self, 5)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
#[must_use]
pub fn laststop(&mut self) -> LaststopW<CrSpec> {
LaststopW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CrSpec> {
Rsvd3W::new(self, 7)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
#[must_use]
pub fn msde(&mut self) -> MsdeW<CrSpec> {
MsdeW::new(self, 8)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
#[must_use]
pub fn sclpp(&mut self) -> SclppW<CrSpec> {
SclppW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CrSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
#[must_use]
pub fn slven(&mut self) -> SlvenW<CrSpec> {
SlvenW::new(self, 11)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
#[must_use]
pub fn dnf(&mut self) -> DnfW<CrSpec> {
DnfW::new(self, 12)
}
#[doc = "Bits 15:28"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 15)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
#[must_use]
pub fn brgrst(&mut self) -> BrgrstW<CrSpec> {
BrgrstW::new(self, 29)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
#[must_use]
pub fn rstreq(&mut self) -> RstreqW<CrSpec> {
RstreqW::new(self, 30)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
#[must_use]
pub fn ur(&mut self) -> UrW<CrSpec> {
UrW::new(self, 31)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TCR (rw) register accessor: Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
module"]
#[doc(alias = "TCR")]
pub type Tcr = crate::Reg<tcr::TcrSpec>;
#[doc = "Transfer Control register"]
pub mod tcr {
#[doc = "Register `TCR` reader"]
pub type R = crate::R<TcrSpec>;
#[doc = "Register `TCR` writer"]
pub type W = crate::W<TcrSpec>;
#[doc = "Field `TB` reader - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbR = crate::BitReader;
#[doc = "Field `TB` writer - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `START` reader - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartR = crate::BitReader;
#[doc = "Field `START` writer - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STOP` reader - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopR = crate::BitReader;
#[doc = "Field `STOP` writer - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MA` reader - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaR = crate::BitReader;
#[doc = "Field `MA` writer - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXREQ` reader - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqR = crate::BitReader;
#[doc = "Field `TXREQ` writer - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXREQ` reader - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqR = crate::BitReader;
#[doc = "Field `RXREQ` writer - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ABORTDMA` reader - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaR = crate::BitReader;
#[doc = "Field `ABORTDMA` writer - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
pub fn tb(&self) -> TbR {
TbR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
pub fn start(&self) -> StartR {
StartR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn txreq(&self) -> TxreqR {
TxreqR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn rxreq(&self) -> RxreqR {
RxreqR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
pub fn abortdma(&self) -> AbortdmaR {
AbortdmaR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
#[must_use]
pub fn tb(&mut self) -> TbW<TcrSpec> {
TbW::new(self, 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> StartW<TcrSpec> {
StartW::new(self, 1)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<TcrSpec> {
StopW::new(self, 2)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<TcrSpec> {
NackW::new(self, 3)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<TcrSpec> {
MaW::new(self, 4)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn txreq(&mut self) -> TxreqW<TcrSpec> {
TxreqW::new(self, 5)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn rxreq(&mut self) -> RxreqW<TcrSpec> {
RxreqW::new(self, 6)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn abortdma(&mut self) -> AbortdmaW<TcrSpec> {
AbortdmaW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcrSpec;
impl crate::RegisterSpec for TcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
impl crate::Readable for TcrSpec {}
#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
impl crate::Writable for TcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TCR to value 0"]
impl crate::Resettable for TcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "Interrupt Enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `SSDIE` reader - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieR = crate::BitReader;
#[doc = "Field `SSDIE` writer - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALDIE` reader - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieR = crate::BitReader;
#[doc = "Field `ALDIE` writer - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFIE` reader - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieR = crate::BitReader;
#[doc = "Field `RFIE` writer - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SADIE` reader - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieR = crate::BitReader;
#[doc = "Field `SADIE` writer - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BEDIE` reader - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieR = crate::BitReader;
#[doc = "Field `BEDIE` writer - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDIE` reader - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieR = crate::BitReader;
#[doc = "Field `MSDIE` writer - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONEIE` reader - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieR = crate::BitReader;
#[doc = "Field `DMADONEIE` writer - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UFIE` reader - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieR = crate::BitReader;
#[doc = "Field `UFIE` writer - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
pub fn ssdie(&self) -> SsdieR {
SsdieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
pub fn aldie(&self) -> AldieR {
AldieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
pub fn rfie(&self) -> RfieR {
RfieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
pub fn sadie(&self) -> SadieR {
SadieR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
pub fn bedie(&self) -> BedieR {
BedieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
pub fn msdie(&self) -> MsdieR {
MsdieR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
pub fn dmadoneie(&self) -> DmadoneieR {
DmadoneieR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
pub fn ufie(&self) -> UfieR {
UfieR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<IerSpec> {
Rsvd4W::new(self, 0)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
#[must_use]
pub fn ssdie(&mut self) -> SsdieW<IerSpec> {
SsdieW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
#[must_use]
pub fn aldie(&mut self) -> AldieW<IerSpec> {
AldieW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<IerSpec> {
TeieW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
#[must_use]
pub fn rfie(&mut self) -> RfieW<IerSpec> {
RfieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IerSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
#[must_use]
pub fn sadie(&mut self) -> SadieW<IerSpec> {
SadieW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
#[must_use]
pub fn bedie(&mut self) -> BedieW<IerSpec> {
BedieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IerSpec> {
Rsvd2W::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
#[must_use]
pub fn msdie(&mut self) -> MsdieW<IerSpec> {
MsdieW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
#[must_use]
pub fn dmadoneie(&mut self) -> DmadoneieW<IerSpec> {
DmadoneieW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ofie(&mut self) -> OfieW<IerSpec> {
OfieW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ufie(&mut self) -> UfieW<IerSpec> {
UfieW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IerSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `RWM` reader - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmR = crate::BitReader;
#[doc = "Field `RWM` writer - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UB` reader - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbR = crate::BitReader;
#[doc = "Field `UB` writer - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBB` reader - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbR = crate::BitReader;
#[doc = "Field `IBB` writer - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SSD` reader - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdR = crate::BitReader;
#[doc = "Field `SSD` writer - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALD` reader - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldR = crate::BitReader;
#[doc = "Field `ALD` writer - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RF` reader - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfR = crate::BitReader;
#[doc = "Field `RF` writer - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAD` reader - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadR = crate::BitReader;
#[doc = "Field `SAD` writer - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BED` reader - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedR = crate::BitReader;
#[doc = "Field `BED` writer - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EBB` reader - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbR = crate::BitReader;
#[doc = "Field `EBB` writer - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSD` reader - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdR = crate::BitReader;
#[doc = "Field `MSD` writer - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONE` reader - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneR = crate::BitReader;
#[doc = "Field `DMADONE` writer - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OF` reader - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfR = crate::BitReader;
#[doc = "Field `OF` writer - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UF` reader - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfR = crate::BitReader;
#[doc = "Field `UF` writer - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
pub fn rwm(&self) -> RwmR {
RwmR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
pub fn ub(&self) -> UbR {
UbR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
pub fn ibb(&self) -> IbbR {
IbbR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
pub fn ssd(&self) -> SsdR {
SsdR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
pub fn ald(&self) -> AldR {
AldR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn rf(&self) -> RfR {
RfR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn sad(&self) -> SadR {
SadR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
pub fn bed(&self) -> BedR {
BedR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
pub fn ebb(&self) -> EbbR {
EbbR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
pub fn msd(&self) -> MsdR {
MsdR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
pub fn dmadone(&self) -> DmadoneR {
DmadoneR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
pub fn of(&self) -> OfR {
OfR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
pub fn uf(&self) -> UfR {
UfR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
#[must_use]
pub fn rwm(&mut self) -> RwmW<SrSpec> {
RwmW::new(self, 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<SrSpec> {
NackW::new(self, 1)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
#[must_use]
pub fn ub(&mut self) -> UbW<SrSpec> {
UbW::new(self, 2)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
#[must_use]
pub fn ibb(&mut self) -> IbbW<SrSpec> {
IbbW::new(self, 3)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ssd(&mut self) -> SsdW<SrSpec> {
SsdW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ald(&mut self) -> AldW<SrSpec> {
AldW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<SrSpec> {
TeW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn rf(&mut self) -> RfW<SrSpec> {
RfW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn sad(&mut self) -> SadW<SrSpec> {
SadW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn bed(&mut self) -> BedW<SrSpec> {
BedW::new(self, 10)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
#[must_use]
pub fn ebb(&mut self) -> EbbW<SrSpec> {
EbbW::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
#[must_use]
pub fn msd(&mut self) -> MsdW<SrSpec> {
MsdW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn dmadone(&mut self) -> DmadoneW<SrSpec> {
DmadoneW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn of(&mut self) -> OfW<SrSpec> {
OfW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn uf(&mut self) -> UfW<SrSpec> {
UfW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DBR (rw) register accessor: Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbr`]
module"]
#[doc(alias = "DBR")]
pub type Dbr = crate::Reg<dbr::DbrSpec>;
#[doc = "Data Buffer register"]
pub mod dbr {
#[doc = "Register `DBR` reader"]
pub type R = crate::R<DbrSpec>;
#[doc = "Register `DBR` writer"]
pub type W = crate::W<DbrSpec>;
#[doc = "Field `DATA` reader - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DbrSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DbrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DbrSpec;
impl crate::RegisterSpec for DbrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dbr::R`](R) reader structure"]
impl crate::Readable for DbrSpec {}
#[doc = "`write(|w| ..)` method takes [`dbr::W`](W) writer structure"]
impl crate::Writable for DbrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DBR to value 0"]
impl crate::Resettable for DbrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SAR (rw) register accessor: Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`]
module"]
#[doc(alias = "SAR")]
pub type Sar = crate::Reg<sar::SarSpec>;
#[doc = "Slave Address Register"]
pub mod sar {
#[doc = "Register `SAR` reader"]
pub type R = crate::R<SarSpec>;
#[doc = "Register `SAR` writer"]
pub type W = crate::W<SarSpec>;
#[doc = "Field `ADDR` reader - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrR = crate::FieldReader;
#[doc = "Field `ADDR` writer - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>;
impl R {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 7) & 0x01ff_ffff)
}
}
impl W {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<SarSpec> {
AddrW::new(self, 0)
}
#[doc = "Bits 7:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SarSpec> {
RsvdW::new(self, 7)
}
}
#[doc = "Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SarSpec;
impl crate::RegisterSpec for SarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar::R`](R) reader structure"]
impl crate::Readable for SarSpec {}
#[doc = "`write(|w| ..)` method takes [`sar::W`](W) writer structure"]
impl crate::Writable for SarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR to value 0x47"]
impl crate::Resettable for SarSpec {
const RESET_VALUE: u32 = 0x47;
}
}
#[doc = "LCR (rw) register accessor: Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`]
module"]
#[doc(alias = "LCR")]
pub type Lcr = crate::Reg<lcr::LcrSpec>;
#[doc = "Load Count Register"]
pub mod lcr {
#[doc = "Register `LCR` reader"]
pub type R = crate::R<LcrSpec>;
#[doc = "Register `LCR` writer"]
pub type W = crate::W<LcrSpec>;
#[doc = "Field `SLV` reader - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvR = crate::FieldReader<u16>;
#[doc = "Field `SLV` writer - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `FLV` reader - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvR = crate::FieldReader<u16>;
#[doc = "Field `FLV` writer - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVL` reader - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlR = crate::FieldReader<u16>;
#[doc = "Field `HLVL` writer - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVH` reader - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhR = crate::FieldReader;
#[doc = "Field `HLVH` writer - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
pub fn slv(&self) -> SlvR {
SlvR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
pub fn flv(&self) -> FlvR {
FlvR::new(((self.bits >> 9) & 0x01ff) as u16)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
pub fn hlvl(&self) -> HlvlR {
HlvlR::new(((self.bits >> 18) & 0x01ff) as u16)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
pub fn hlvh(&self) -> HlvhR {
HlvhR::new(((self.bits >> 27) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
#[must_use]
pub fn slv(&mut self) -> SlvW<LcrSpec> {
SlvW::new(self, 0)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
#[must_use]
pub fn flv(&mut self) -> FlvW<LcrSpec> {
FlvW::new(self, 9)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
#[must_use]
pub fn hlvl(&mut self) -> HlvlW<LcrSpec> {
HlvlW::new(self, 18)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
#[must_use]
pub fn hlvh(&mut self) -> HlvhW<LcrSpec> {
HlvhW::new(self, 27)
}
}
#[doc = "Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LcrSpec;
impl crate::RegisterSpec for LcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lcr::R`](R) reader structure"]
impl crate::Readable for LcrSpec {}
#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"]
impl crate::Writable for LcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LCR to value 0x081c_72ed"]
impl crate::Resettable for LcrSpec {
const RESET_VALUE: u32 = 0x081c_72ed;
}
}
#[doc = "WCR (rw) register accessor: Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wcr`]
module"]
#[doc(alias = "WCR")]
pub type Wcr = crate::Reg<wcr::WcrSpec>;
#[doc = "Wait Count Register"]
pub mod wcr {
#[doc = "Register `WCR` reader"]
pub type R = crate::R<WcrSpec>;
#[doc = "Register `WCR` writer"]
pub type W = crate::W<WcrSpec>;
#[doc = "Field `CNT` reader - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntR = crate::FieldReader;
#[doc = "Field `CNT` writer - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<WcrSpec> {
CntW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WcrSpec;
impl crate::RegisterSpec for WcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wcr::R`](R) reader structure"]
impl crate::Readable for WcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wcr::W`](W) writer structure"]
impl crate::Writable for WcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WCR to value 0x0a"]
impl crate::Resettable for WcrSpec {
const RESET_VALUE: u32 = 0x0a;
}
}
#[doc = "RCCR (rw) register accessor: Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rccr`]
module"]
#[doc(alias = "RCCR")]
pub type Rccr = crate::Reg<rccr::RccrSpec>;
#[doc = "Bus Reset Cycle Counter Register"]
pub mod rccr {
#[doc = "Register `RCCR` reader"]
pub type R = crate::R<RccrSpec>;
#[doc = "Register `RCCR` writer"]
pub type W = crate::W<RccrSpec>;
#[doc = "Field `RSTCYC` reader - The cycles of SCL during bus reset"]
pub type RstcycR = crate::FieldReader;
#[doc = "Field `RSTCYC` writer - The cycles of SCL during bus reset"]
pub type RstcycW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
pub fn rstcyc(&self) -> RstcycR {
RstcycR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
#[must_use]
pub fn rstcyc(&mut self) -> RstcycW<RccrSpec> {
RstcycW::new(self, 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RccrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RccrSpec;
impl crate::RegisterSpec for RccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rccr::R`](R) reader structure"]
impl crate::Readable for RccrSpec {}
#[doc = "`write(|w| ..)` method takes [`rccr::W`](W) writer structure"]
impl crate::Writable for RccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCCR to value 0x09"]
impl crate::Resettable for RccrSpec {
const RESET_VALUE: u32 = 0x09;
}
}
#[doc = "BMR (rw) register accessor: Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmr`]
module"]
#[doc(alias = "BMR")]
pub type Bmr = crate::Reg<bmr::BmrSpec>;
#[doc = "Bus Monitor Register"]
pub mod bmr {
#[doc = "Register `BMR` reader"]
pub type R = crate::R<BmrSpec>;
#[doc = "Register `BMR` writer"]
pub type W = crate::W<BmrSpec>;
#[doc = "Field `SDA` reader - value of the SDA pin."]
pub type SdaR = crate::BitReader;
#[doc = "Field `SDA` writer - value of the SDA pin."]
pub type SdaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCL` reader - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclR = crate::BitReader;
#[doc = "Field `SCL` writer - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
pub fn sda(&self) -> SdaR {
SdaR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
pub fn scl(&self) -> SclR {
SclR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
#[must_use]
pub fn sda(&mut self) -> SdaW<BmrSpec> {
SdaW::new(self, 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
#[must_use]
pub fn scl(&mut self) -> SclW<BmrSpec> {
SclW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BmrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BmrSpec;
impl crate::RegisterSpec for BmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bmr::R`](R) reader structure"]
impl crate::Readable for BmrSpec {}
#[doc = "`write(|w| ..)` method takes [`bmr::W`](W) writer structure"]
impl crate::Writable for BmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BMR to value 0x03"]
impl crate::Resettable for BmrSpec {
const RESET_VALUE: u32 = 0x03;
}
}
#[doc = "DNR (rw) register accessor: DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dnr`]
module"]
#[doc(alias = "DNR")]
pub type Dnr = crate::Reg<dnr::DnrSpec>;
#[doc = "DMA number register"]
pub mod dnr {
#[doc = "Register `DNR` reader"]
pub type R = crate::R<DnrSpec>;
#[doc = "Register `DNR` writer"]
pub type W = crate::W<DnrSpec>;
#[doc = "Field `NDT` reader - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<DnrSpec> {
NdtW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DnrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DnrSpec;
impl crate::RegisterSpec for DnrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dnr::R`](R) reader structure"]
impl crate::Readable for DnrSpec {}
#[doc = "`write(|w| ..)` method takes [`dnr::W`](W) writer structure"]
impl crate::Writable for DnrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DNR to value 0"]
impl crate::Resettable for DnrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO (rw) register accessor: FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`]
module"]
#[doc(alias = "FIFO")]
pub type Fifo = crate::Reg<fifo::FifoSpec>;
#[doc = "FIFO Register"]
pub mod fifo {
#[doc = "Register `FIFO` reader"]
pub type R = crate::R<FifoSpec>;
#[doc = "Register `FIFO` writer"]
pub type W = crate::W<FifoSpec>;
#[doc = "Field `DATA` reader - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<FifoSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoSpec;
impl crate::RegisterSpec for FifoSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo::R`](R) reader structure"]
impl crate::Readable for FifoSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"]
impl crate::Writable for FifoSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO to value 0"]
impl crate::Resettable for FifoSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "I2C2"]
pub struct I2c2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2c2 {}
impl I2c2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2c2::RegisterBlock = 0x5009_d000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2c2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2c2 {
type Target = i2c2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2c2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c2").finish()
}
}
#[doc = "I2C2"]
pub mod i2c2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr: Cr,
tcr: Tcr,
ier: Ier,
sr: Sr,
dbr: Dbr,
sar: Sar,
lcr: Lcr,
wcr: Wcr,
rccr: Rccr,
bmr: Bmr,
dnr: Dnr,
rsvd1: Rsvd1,
fifo: Fifo,
}
impl RegisterBlock {
#[doc = "0x00 - Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x04 - Transfer Control register"]
#[inline(always)]
pub const fn tcr(&self) -> &Tcr {
&self.tcr
}
#[doc = "0x08 - Interrupt Enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x0c - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x10 - Data Buffer register"]
#[inline(always)]
pub const fn dbr(&self) -> &Dbr {
&self.dbr
}
#[doc = "0x14 - Slave Address Register"]
#[inline(always)]
pub const fn sar(&self) -> &Sar {
&self.sar
}
#[doc = "0x18 - Load Count Register"]
#[inline(always)]
pub const fn lcr(&self) -> &Lcr {
&self.lcr
}
#[doc = "0x1c - Wait Count Register"]
#[inline(always)]
pub const fn wcr(&self) -> &Wcr {
&self.wcr
}
#[doc = "0x20 - Bus Reset Cycle Counter Register"]
#[inline(always)]
pub const fn rccr(&self) -> &Rccr {
&self.rccr
}
#[doc = "0x24 - Bus Monitor Register"]
#[inline(always)]
pub const fn bmr(&self) -> &Bmr {
&self.bmr
}
#[doc = "0x28 - DMA number register"]
#[inline(always)]
pub const fn dnr(&self) -> &Dnr {
&self.dnr
}
#[doc = "0x2c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x30 - FIFO Register"]
#[inline(always)]
pub const fn fifo(&self) -> &Fifo {
&self.fifo
}
}
#[doc = "CR (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `MODE` reader - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeR = crate::FieldReader;
#[doc = "Field `MODE` writer - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IUE` reader - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueR = crate::BitReader;
#[doc = "Field `IUE` writer - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLE` reader - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleR = crate::BitReader;
#[doc = "Field `SCLE` writer - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAEN` reader - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenR = crate::BitReader;
#[doc = "Field `DMAEN` writer - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTNACK` reader - Generate NACK for last DMA Read transfer"]
pub type LastnackR = crate::BitReader;
#[doc = "Field `LASTNACK` writer - Generate NACK for last DMA Read transfer"]
pub type LastnackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTSTOP` reader - Generate STOP for last DMA transfer"]
pub type LaststopR = crate::BitReader;
#[doc = "Field `LASTSTOP` writer - Generate STOP for last DMA transfer"]
pub type LaststopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDE` reader - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeR = crate::BitReader;
#[doc = "Field `MSDE` writer - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLPP` reader - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppR = crate::BitReader;
#[doc = "Field `SCLPP` writer - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLVEN` reader - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenR = crate::BitReader;
#[doc = "Field `SLVEN` writer - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DNF` reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfR = crate::FieldReader;
#[doc = "Field `DNF` writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `BRGRST` reader - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstR = crate::BitReader;
#[doc = "Field `BRGRST` writer - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSTREQ` reader - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqR = crate::BitReader;
#[doc = "Field `RSTREQ` writer - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UR` reader - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrR = crate::BitReader;
#[doc = "Field `UR` writer - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
pub fn iue(&self) -> IueR {
IueR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
pub fn scle(&self) -> ScleR {
ScleR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
pub fn dmaen(&self) -> DmaenR {
DmaenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
pub fn lastnack(&self) -> LastnackR {
LastnackR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
pub fn laststop(&self) -> LaststopR {
LaststopR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
pub fn msde(&self) -> MsdeR {
MsdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
pub fn sclpp(&self) -> SclppR {
SclppR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
pub fn slven(&self) -> SlvenR {
SlvenR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
pub fn dnf(&self) -> DnfR {
DnfR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:28"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 15) & 0x3fff) as u16)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
pub fn brgrst(&self) -> BrgrstR {
BrgrstR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
pub fn rstreq(&self) -> RstreqR {
RstreqR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
pub fn ur(&self) -> UrR {
UrR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<CrSpec> {
ModeW::new(self, 0)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
#[must_use]
pub fn iue(&mut self) -> IueW<CrSpec> {
IueW::new(self, 2)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
#[must_use]
pub fn scle(&mut self) -> ScleW<CrSpec> {
ScleW::new(self, 3)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
#[must_use]
pub fn dmaen(&mut self) -> DmaenW<CrSpec> {
DmaenW::new(self, 4)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
#[must_use]
pub fn lastnack(&mut self) -> LastnackW<CrSpec> {
LastnackW::new(self, 5)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
#[must_use]
pub fn laststop(&mut self) -> LaststopW<CrSpec> {
LaststopW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CrSpec> {
Rsvd3W::new(self, 7)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
#[must_use]
pub fn msde(&mut self) -> MsdeW<CrSpec> {
MsdeW::new(self, 8)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
#[must_use]
pub fn sclpp(&mut self) -> SclppW<CrSpec> {
SclppW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CrSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
#[must_use]
pub fn slven(&mut self) -> SlvenW<CrSpec> {
SlvenW::new(self, 11)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
#[must_use]
pub fn dnf(&mut self) -> DnfW<CrSpec> {
DnfW::new(self, 12)
}
#[doc = "Bits 15:28"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 15)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
#[must_use]
pub fn brgrst(&mut self) -> BrgrstW<CrSpec> {
BrgrstW::new(self, 29)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
#[must_use]
pub fn rstreq(&mut self) -> RstreqW<CrSpec> {
RstreqW::new(self, 30)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
#[must_use]
pub fn ur(&mut self) -> UrW<CrSpec> {
UrW::new(self, 31)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TCR (rw) register accessor: Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
module"]
#[doc(alias = "TCR")]
pub type Tcr = crate::Reg<tcr::TcrSpec>;
#[doc = "Transfer Control register"]
pub mod tcr {
#[doc = "Register `TCR` reader"]
pub type R = crate::R<TcrSpec>;
#[doc = "Register `TCR` writer"]
pub type W = crate::W<TcrSpec>;
#[doc = "Field `TB` reader - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbR = crate::BitReader;
#[doc = "Field `TB` writer - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `START` reader - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartR = crate::BitReader;
#[doc = "Field `START` writer - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STOP` reader - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopR = crate::BitReader;
#[doc = "Field `STOP` writer - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MA` reader - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaR = crate::BitReader;
#[doc = "Field `MA` writer - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXREQ` reader - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqR = crate::BitReader;
#[doc = "Field `TXREQ` writer - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXREQ` reader - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqR = crate::BitReader;
#[doc = "Field `RXREQ` writer - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ABORTDMA` reader - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaR = crate::BitReader;
#[doc = "Field `ABORTDMA` writer - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
pub fn tb(&self) -> TbR {
TbR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
pub fn start(&self) -> StartR {
StartR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn txreq(&self) -> TxreqR {
TxreqR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn rxreq(&self) -> RxreqR {
RxreqR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
pub fn abortdma(&self) -> AbortdmaR {
AbortdmaR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
#[must_use]
pub fn tb(&mut self) -> TbW<TcrSpec> {
TbW::new(self, 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> StartW<TcrSpec> {
StartW::new(self, 1)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<TcrSpec> {
StopW::new(self, 2)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<TcrSpec> {
NackW::new(self, 3)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<TcrSpec> {
MaW::new(self, 4)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn txreq(&mut self) -> TxreqW<TcrSpec> {
TxreqW::new(self, 5)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn rxreq(&mut self) -> RxreqW<TcrSpec> {
RxreqW::new(self, 6)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn abortdma(&mut self) -> AbortdmaW<TcrSpec> {
AbortdmaW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcrSpec;
impl crate::RegisterSpec for TcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
impl crate::Readable for TcrSpec {}
#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
impl crate::Writable for TcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TCR to value 0"]
impl crate::Resettable for TcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "Interrupt Enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `SSDIE` reader - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieR = crate::BitReader;
#[doc = "Field `SSDIE` writer - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALDIE` reader - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieR = crate::BitReader;
#[doc = "Field `ALDIE` writer - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFIE` reader - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieR = crate::BitReader;
#[doc = "Field `RFIE` writer - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SADIE` reader - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieR = crate::BitReader;
#[doc = "Field `SADIE` writer - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BEDIE` reader - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieR = crate::BitReader;
#[doc = "Field `BEDIE` writer - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDIE` reader - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieR = crate::BitReader;
#[doc = "Field `MSDIE` writer - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONEIE` reader - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieR = crate::BitReader;
#[doc = "Field `DMADONEIE` writer - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UFIE` reader - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieR = crate::BitReader;
#[doc = "Field `UFIE` writer - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
pub fn ssdie(&self) -> SsdieR {
SsdieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
pub fn aldie(&self) -> AldieR {
AldieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
pub fn rfie(&self) -> RfieR {
RfieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
pub fn sadie(&self) -> SadieR {
SadieR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
pub fn bedie(&self) -> BedieR {
BedieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
pub fn msdie(&self) -> MsdieR {
MsdieR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
pub fn dmadoneie(&self) -> DmadoneieR {
DmadoneieR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
pub fn ufie(&self) -> UfieR {
UfieR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<IerSpec> {
Rsvd4W::new(self, 0)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
#[must_use]
pub fn ssdie(&mut self) -> SsdieW<IerSpec> {
SsdieW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
#[must_use]
pub fn aldie(&mut self) -> AldieW<IerSpec> {
AldieW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<IerSpec> {
TeieW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
#[must_use]
pub fn rfie(&mut self) -> RfieW<IerSpec> {
RfieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IerSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
#[must_use]
pub fn sadie(&mut self) -> SadieW<IerSpec> {
SadieW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
#[must_use]
pub fn bedie(&mut self) -> BedieW<IerSpec> {
BedieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IerSpec> {
Rsvd2W::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
#[must_use]
pub fn msdie(&mut self) -> MsdieW<IerSpec> {
MsdieW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
#[must_use]
pub fn dmadoneie(&mut self) -> DmadoneieW<IerSpec> {
DmadoneieW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ofie(&mut self) -> OfieW<IerSpec> {
OfieW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ufie(&mut self) -> UfieW<IerSpec> {
UfieW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IerSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `RWM` reader - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmR = crate::BitReader;
#[doc = "Field `RWM` writer - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UB` reader - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbR = crate::BitReader;
#[doc = "Field `UB` writer - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBB` reader - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbR = crate::BitReader;
#[doc = "Field `IBB` writer - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SSD` reader - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdR = crate::BitReader;
#[doc = "Field `SSD` writer - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALD` reader - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldR = crate::BitReader;
#[doc = "Field `ALD` writer - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RF` reader - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfR = crate::BitReader;
#[doc = "Field `RF` writer - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAD` reader - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadR = crate::BitReader;
#[doc = "Field `SAD` writer - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BED` reader - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedR = crate::BitReader;
#[doc = "Field `BED` writer - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EBB` reader - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbR = crate::BitReader;
#[doc = "Field `EBB` writer - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSD` reader - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdR = crate::BitReader;
#[doc = "Field `MSD` writer - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONE` reader - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneR = crate::BitReader;
#[doc = "Field `DMADONE` writer - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OF` reader - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfR = crate::BitReader;
#[doc = "Field `OF` writer - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UF` reader - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfR = crate::BitReader;
#[doc = "Field `UF` writer - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
pub fn rwm(&self) -> RwmR {
RwmR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
pub fn ub(&self) -> UbR {
UbR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
pub fn ibb(&self) -> IbbR {
IbbR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
pub fn ssd(&self) -> SsdR {
SsdR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
pub fn ald(&self) -> AldR {
AldR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn rf(&self) -> RfR {
RfR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn sad(&self) -> SadR {
SadR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
pub fn bed(&self) -> BedR {
BedR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
pub fn ebb(&self) -> EbbR {
EbbR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
pub fn msd(&self) -> MsdR {
MsdR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
pub fn dmadone(&self) -> DmadoneR {
DmadoneR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
pub fn of(&self) -> OfR {
OfR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
pub fn uf(&self) -> UfR {
UfR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
#[must_use]
pub fn rwm(&mut self) -> RwmW<SrSpec> {
RwmW::new(self, 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<SrSpec> {
NackW::new(self, 1)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
#[must_use]
pub fn ub(&mut self) -> UbW<SrSpec> {
UbW::new(self, 2)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
#[must_use]
pub fn ibb(&mut self) -> IbbW<SrSpec> {
IbbW::new(self, 3)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ssd(&mut self) -> SsdW<SrSpec> {
SsdW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ald(&mut self) -> AldW<SrSpec> {
AldW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<SrSpec> {
TeW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn rf(&mut self) -> RfW<SrSpec> {
RfW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn sad(&mut self) -> SadW<SrSpec> {
SadW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn bed(&mut self) -> BedW<SrSpec> {
BedW::new(self, 10)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
#[must_use]
pub fn ebb(&mut self) -> EbbW<SrSpec> {
EbbW::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
#[must_use]
pub fn msd(&mut self) -> MsdW<SrSpec> {
MsdW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn dmadone(&mut self) -> DmadoneW<SrSpec> {
DmadoneW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn of(&mut self) -> OfW<SrSpec> {
OfW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn uf(&mut self) -> UfW<SrSpec> {
UfW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DBR (rw) register accessor: Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbr`]
module"]
#[doc(alias = "DBR")]
pub type Dbr = crate::Reg<dbr::DbrSpec>;
#[doc = "Data Buffer register"]
pub mod dbr {
#[doc = "Register `DBR` reader"]
pub type R = crate::R<DbrSpec>;
#[doc = "Register `DBR` writer"]
pub type W = crate::W<DbrSpec>;
#[doc = "Field `DATA` reader - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DbrSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DbrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DbrSpec;
impl crate::RegisterSpec for DbrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dbr::R`](R) reader structure"]
impl crate::Readable for DbrSpec {}
#[doc = "`write(|w| ..)` method takes [`dbr::W`](W) writer structure"]
impl crate::Writable for DbrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DBR to value 0"]
impl crate::Resettable for DbrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SAR (rw) register accessor: Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`]
module"]
#[doc(alias = "SAR")]
pub type Sar = crate::Reg<sar::SarSpec>;
#[doc = "Slave Address Register"]
pub mod sar {
#[doc = "Register `SAR` reader"]
pub type R = crate::R<SarSpec>;
#[doc = "Register `SAR` writer"]
pub type W = crate::W<SarSpec>;
#[doc = "Field `ADDR` reader - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrR = crate::FieldReader;
#[doc = "Field `ADDR` writer - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>;
impl R {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 7) & 0x01ff_ffff)
}
}
impl W {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<SarSpec> {
AddrW::new(self, 0)
}
#[doc = "Bits 7:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SarSpec> {
RsvdW::new(self, 7)
}
}
#[doc = "Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SarSpec;
impl crate::RegisterSpec for SarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar::R`](R) reader structure"]
impl crate::Readable for SarSpec {}
#[doc = "`write(|w| ..)` method takes [`sar::W`](W) writer structure"]
impl crate::Writable for SarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR to value 0x47"]
impl crate::Resettable for SarSpec {
const RESET_VALUE: u32 = 0x47;
}
}
#[doc = "LCR (rw) register accessor: Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`]
module"]
#[doc(alias = "LCR")]
pub type Lcr = crate::Reg<lcr::LcrSpec>;
#[doc = "Load Count Register"]
pub mod lcr {
#[doc = "Register `LCR` reader"]
pub type R = crate::R<LcrSpec>;
#[doc = "Register `LCR` writer"]
pub type W = crate::W<LcrSpec>;
#[doc = "Field `SLV` reader - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvR = crate::FieldReader<u16>;
#[doc = "Field `SLV` writer - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `FLV` reader - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvR = crate::FieldReader<u16>;
#[doc = "Field `FLV` writer - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVL` reader - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlR = crate::FieldReader<u16>;
#[doc = "Field `HLVL` writer - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVH` reader - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhR = crate::FieldReader;
#[doc = "Field `HLVH` writer - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
pub fn slv(&self) -> SlvR {
SlvR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
pub fn flv(&self) -> FlvR {
FlvR::new(((self.bits >> 9) & 0x01ff) as u16)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
pub fn hlvl(&self) -> HlvlR {
HlvlR::new(((self.bits >> 18) & 0x01ff) as u16)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
pub fn hlvh(&self) -> HlvhR {
HlvhR::new(((self.bits >> 27) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
#[must_use]
pub fn slv(&mut self) -> SlvW<LcrSpec> {
SlvW::new(self, 0)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
#[must_use]
pub fn flv(&mut self) -> FlvW<LcrSpec> {
FlvW::new(self, 9)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
#[must_use]
pub fn hlvl(&mut self) -> HlvlW<LcrSpec> {
HlvlW::new(self, 18)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
#[must_use]
pub fn hlvh(&mut self) -> HlvhW<LcrSpec> {
HlvhW::new(self, 27)
}
}
#[doc = "Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LcrSpec;
impl crate::RegisterSpec for LcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lcr::R`](R) reader structure"]
impl crate::Readable for LcrSpec {}
#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"]
impl crate::Writable for LcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LCR to value 0x081c_72ed"]
impl crate::Resettable for LcrSpec {
const RESET_VALUE: u32 = 0x081c_72ed;
}
}
#[doc = "WCR (rw) register accessor: Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wcr`]
module"]
#[doc(alias = "WCR")]
pub type Wcr = crate::Reg<wcr::WcrSpec>;
#[doc = "Wait Count Register"]
pub mod wcr {
#[doc = "Register `WCR` reader"]
pub type R = crate::R<WcrSpec>;
#[doc = "Register `WCR` writer"]
pub type W = crate::W<WcrSpec>;
#[doc = "Field `CNT` reader - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntR = crate::FieldReader;
#[doc = "Field `CNT` writer - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<WcrSpec> {
CntW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WcrSpec;
impl crate::RegisterSpec for WcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wcr::R`](R) reader structure"]
impl crate::Readable for WcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wcr::W`](W) writer structure"]
impl crate::Writable for WcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WCR to value 0x0a"]
impl crate::Resettable for WcrSpec {
const RESET_VALUE: u32 = 0x0a;
}
}
#[doc = "RCCR (rw) register accessor: Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rccr`]
module"]
#[doc(alias = "RCCR")]
pub type Rccr = crate::Reg<rccr::RccrSpec>;
#[doc = "Bus Reset Cycle Counter Register"]
pub mod rccr {
#[doc = "Register `RCCR` reader"]
pub type R = crate::R<RccrSpec>;
#[doc = "Register `RCCR` writer"]
pub type W = crate::W<RccrSpec>;
#[doc = "Field `RSTCYC` reader - The cycles of SCL during bus reset"]
pub type RstcycR = crate::FieldReader;
#[doc = "Field `RSTCYC` writer - The cycles of SCL during bus reset"]
pub type RstcycW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
pub fn rstcyc(&self) -> RstcycR {
RstcycR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
#[must_use]
pub fn rstcyc(&mut self) -> RstcycW<RccrSpec> {
RstcycW::new(self, 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RccrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RccrSpec;
impl crate::RegisterSpec for RccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rccr::R`](R) reader structure"]
impl crate::Readable for RccrSpec {}
#[doc = "`write(|w| ..)` method takes [`rccr::W`](W) writer structure"]
impl crate::Writable for RccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCCR to value 0x09"]
impl crate::Resettable for RccrSpec {
const RESET_VALUE: u32 = 0x09;
}
}
#[doc = "BMR (rw) register accessor: Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmr`]
module"]
#[doc(alias = "BMR")]
pub type Bmr = crate::Reg<bmr::BmrSpec>;
#[doc = "Bus Monitor Register"]
pub mod bmr {
#[doc = "Register `BMR` reader"]
pub type R = crate::R<BmrSpec>;
#[doc = "Register `BMR` writer"]
pub type W = crate::W<BmrSpec>;
#[doc = "Field `SDA` reader - value of the SDA pin."]
pub type SdaR = crate::BitReader;
#[doc = "Field `SDA` writer - value of the SDA pin."]
pub type SdaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCL` reader - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclR = crate::BitReader;
#[doc = "Field `SCL` writer - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
pub fn sda(&self) -> SdaR {
SdaR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
pub fn scl(&self) -> SclR {
SclR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
#[must_use]
pub fn sda(&mut self) -> SdaW<BmrSpec> {
SdaW::new(self, 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
#[must_use]
pub fn scl(&mut self) -> SclW<BmrSpec> {
SclW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BmrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BmrSpec;
impl crate::RegisterSpec for BmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bmr::R`](R) reader structure"]
impl crate::Readable for BmrSpec {}
#[doc = "`write(|w| ..)` method takes [`bmr::W`](W) writer structure"]
impl crate::Writable for BmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BMR to value 0x03"]
impl crate::Resettable for BmrSpec {
const RESET_VALUE: u32 = 0x03;
}
}
#[doc = "DNR (rw) register accessor: DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dnr`]
module"]
#[doc(alias = "DNR")]
pub type Dnr = crate::Reg<dnr::DnrSpec>;
#[doc = "DMA number register"]
pub mod dnr {
#[doc = "Register `DNR` reader"]
pub type R = crate::R<DnrSpec>;
#[doc = "Register `DNR` writer"]
pub type W = crate::W<DnrSpec>;
#[doc = "Field `NDT` reader - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<DnrSpec> {
NdtW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DnrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DnrSpec;
impl crate::RegisterSpec for DnrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dnr::R`](R) reader structure"]
impl crate::Readable for DnrSpec {}
#[doc = "`write(|w| ..)` method takes [`dnr::W`](W) writer structure"]
impl crate::Writable for DnrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DNR to value 0"]
impl crate::Resettable for DnrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO (rw) register accessor: FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`]
module"]
#[doc(alias = "FIFO")]
pub type Fifo = crate::Reg<fifo::FifoSpec>;
#[doc = "FIFO Register"]
pub mod fifo {
#[doc = "Register `FIFO` reader"]
pub type R = crate::R<FifoSpec>;
#[doc = "Register `FIFO` writer"]
pub type W = crate::W<FifoSpec>;
#[doc = "Field `DATA` reader - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<FifoSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoSpec;
impl crate::RegisterSpec for FifoSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo::R`](R) reader structure"]
impl crate::Readable for FifoSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"]
impl crate::Writable for FifoSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO to value 0"]
impl crate::Resettable for FifoSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "I2C3"]
pub struct I2c3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2c3 {}
impl I2c3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2c3::RegisterBlock = 0x5009_e000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2c3::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2c3 {
type Target = i2c3::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2c3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c3").finish()
}
}
#[doc = "I2C3"]
pub mod i2c3 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr: Cr,
tcr: Tcr,
ier: Ier,
sr: Sr,
dbr: Dbr,
sar: Sar,
lcr: Lcr,
wcr: Wcr,
rccr: Rccr,
bmr: Bmr,
dnr: Dnr,
rsvd1: Rsvd1,
fifo: Fifo,
}
impl RegisterBlock {
#[doc = "0x00 - Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x04 - Transfer Control register"]
#[inline(always)]
pub const fn tcr(&self) -> &Tcr {
&self.tcr
}
#[doc = "0x08 - Interrupt Enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x0c - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x10 - Data Buffer register"]
#[inline(always)]
pub const fn dbr(&self) -> &Dbr {
&self.dbr
}
#[doc = "0x14 - Slave Address Register"]
#[inline(always)]
pub const fn sar(&self) -> &Sar {
&self.sar
}
#[doc = "0x18 - Load Count Register"]
#[inline(always)]
pub const fn lcr(&self) -> &Lcr {
&self.lcr
}
#[doc = "0x1c - Wait Count Register"]
#[inline(always)]
pub const fn wcr(&self) -> &Wcr {
&self.wcr
}
#[doc = "0x20 - Bus Reset Cycle Counter Register"]
#[inline(always)]
pub const fn rccr(&self) -> &Rccr {
&self.rccr
}
#[doc = "0x24 - Bus Monitor Register"]
#[inline(always)]
pub const fn bmr(&self) -> &Bmr {
&self.bmr
}
#[doc = "0x28 - DMA number register"]
#[inline(always)]
pub const fn dnr(&self) -> &Dnr {
&self.dnr
}
#[doc = "0x2c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x30 - FIFO Register"]
#[inline(always)]
pub const fn fifo(&self) -> &Fifo {
&self.fifo
}
}
#[doc = "CR (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `MODE` reader - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeR = crate::FieldReader;
#[doc = "Field `MODE` writer - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IUE` reader - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueR = crate::BitReader;
#[doc = "Field `IUE` writer - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLE` reader - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleR = crate::BitReader;
#[doc = "Field `SCLE` writer - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAEN` reader - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenR = crate::BitReader;
#[doc = "Field `DMAEN` writer - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTNACK` reader - Generate NACK for last DMA Read transfer"]
pub type LastnackR = crate::BitReader;
#[doc = "Field `LASTNACK` writer - Generate NACK for last DMA Read transfer"]
pub type LastnackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTSTOP` reader - Generate STOP for last DMA transfer"]
pub type LaststopR = crate::BitReader;
#[doc = "Field `LASTSTOP` writer - Generate STOP for last DMA transfer"]
pub type LaststopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDE` reader - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeR = crate::BitReader;
#[doc = "Field `MSDE` writer - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLPP` reader - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppR = crate::BitReader;
#[doc = "Field `SCLPP` writer - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLVEN` reader - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenR = crate::BitReader;
#[doc = "Field `SLVEN` writer - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DNF` reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfR = crate::FieldReader;
#[doc = "Field `DNF` writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `BRGRST` reader - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstR = crate::BitReader;
#[doc = "Field `BRGRST` writer - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSTREQ` reader - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqR = crate::BitReader;
#[doc = "Field `RSTREQ` writer - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UR` reader - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrR = crate::BitReader;
#[doc = "Field `UR` writer - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
pub fn iue(&self) -> IueR {
IueR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
pub fn scle(&self) -> ScleR {
ScleR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
pub fn dmaen(&self) -> DmaenR {
DmaenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
pub fn lastnack(&self) -> LastnackR {
LastnackR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
pub fn laststop(&self) -> LaststopR {
LaststopR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
pub fn msde(&self) -> MsdeR {
MsdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
pub fn sclpp(&self) -> SclppR {
SclppR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
pub fn slven(&self) -> SlvenR {
SlvenR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
pub fn dnf(&self) -> DnfR {
DnfR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:28"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 15) & 0x3fff) as u16)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
pub fn brgrst(&self) -> BrgrstR {
BrgrstR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
pub fn rstreq(&self) -> RstreqR {
RstreqR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
pub fn ur(&self) -> UrR {
UrR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<CrSpec> {
ModeW::new(self, 0)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
#[must_use]
pub fn iue(&mut self) -> IueW<CrSpec> {
IueW::new(self, 2)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
#[must_use]
pub fn scle(&mut self) -> ScleW<CrSpec> {
ScleW::new(self, 3)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
#[must_use]
pub fn dmaen(&mut self) -> DmaenW<CrSpec> {
DmaenW::new(self, 4)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
#[must_use]
pub fn lastnack(&mut self) -> LastnackW<CrSpec> {
LastnackW::new(self, 5)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
#[must_use]
pub fn laststop(&mut self) -> LaststopW<CrSpec> {
LaststopW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CrSpec> {
Rsvd3W::new(self, 7)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
#[must_use]
pub fn msde(&mut self) -> MsdeW<CrSpec> {
MsdeW::new(self, 8)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
#[must_use]
pub fn sclpp(&mut self) -> SclppW<CrSpec> {
SclppW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CrSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
#[must_use]
pub fn slven(&mut self) -> SlvenW<CrSpec> {
SlvenW::new(self, 11)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
#[must_use]
pub fn dnf(&mut self) -> DnfW<CrSpec> {
DnfW::new(self, 12)
}
#[doc = "Bits 15:28"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 15)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
#[must_use]
pub fn brgrst(&mut self) -> BrgrstW<CrSpec> {
BrgrstW::new(self, 29)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
#[must_use]
pub fn rstreq(&mut self) -> RstreqW<CrSpec> {
RstreqW::new(self, 30)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
#[must_use]
pub fn ur(&mut self) -> UrW<CrSpec> {
UrW::new(self, 31)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TCR (rw) register accessor: Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
module"]
#[doc(alias = "TCR")]
pub type Tcr = crate::Reg<tcr::TcrSpec>;
#[doc = "Transfer Control register"]
pub mod tcr {
#[doc = "Register `TCR` reader"]
pub type R = crate::R<TcrSpec>;
#[doc = "Register `TCR` writer"]
pub type W = crate::W<TcrSpec>;
#[doc = "Field `TB` reader - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbR = crate::BitReader;
#[doc = "Field `TB` writer - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `START` reader - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartR = crate::BitReader;
#[doc = "Field `START` writer - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STOP` reader - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopR = crate::BitReader;
#[doc = "Field `STOP` writer - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MA` reader - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaR = crate::BitReader;
#[doc = "Field `MA` writer - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXREQ` reader - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqR = crate::BitReader;
#[doc = "Field `TXREQ` writer - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXREQ` reader - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqR = crate::BitReader;
#[doc = "Field `RXREQ` writer - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ABORTDMA` reader - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaR = crate::BitReader;
#[doc = "Field `ABORTDMA` writer - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
pub fn tb(&self) -> TbR {
TbR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
pub fn start(&self) -> StartR {
StartR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn txreq(&self) -> TxreqR {
TxreqR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn rxreq(&self) -> RxreqR {
RxreqR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
pub fn abortdma(&self) -> AbortdmaR {
AbortdmaR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
#[must_use]
pub fn tb(&mut self) -> TbW<TcrSpec> {
TbW::new(self, 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> StartW<TcrSpec> {
StartW::new(self, 1)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<TcrSpec> {
StopW::new(self, 2)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<TcrSpec> {
NackW::new(self, 3)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<TcrSpec> {
MaW::new(self, 4)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn txreq(&mut self) -> TxreqW<TcrSpec> {
TxreqW::new(self, 5)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn rxreq(&mut self) -> RxreqW<TcrSpec> {
RxreqW::new(self, 6)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn abortdma(&mut self) -> AbortdmaW<TcrSpec> {
AbortdmaW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcrSpec;
impl crate::RegisterSpec for TcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
impl crate::Readable for TcrSpec {}
#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
impl crate::Writable for TcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TCR to value 0"]
impl crate::Resettable for TcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "Interrupt Enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `SSDIE` reader - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieR = crate::BitReader;
#[doc = "Field `SSDIE` writer - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALDIE` reader - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieR = crate::BitReader;
#[doc = "Field `ALDIE` writer - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFIE` reader - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieR = crate::BitReader;
#[doc = "Field `RFIE` writer - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SADIE` reader - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieR = crate::BitReader;
#[doc = "Field `SADIE` writer - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BEDIE` reader - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieR = crate::BitReader;
#[doc = "Field `BEDIE` writer - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDIE` reader - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieR = crate::BitReader;
#[doc = "Field `MSDIE` writer - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONEIE` reader - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieR = crate::BitReader;
#[doc = "Field `DMADONEIE` writer - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UFIE` reader - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieR = crate::BitReader;
#[doc = "Field `UFIE` writer - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
pub fn ssdie(&self) -> SsdieR {
SsdieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
pub fn aldie(&self) -> AldieR {
AldieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
pub fn rfie(&self) -> RfieR {
RfieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
pub fn sadie(&self) -> SadieR {
SadieR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
pub fn bedie(&self) -> BedieR {
BedieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
pub fn msdie(&self) -> MsdieR {
MsdieR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
pub fn dmadoneie(&self) -> DmadoneieR {
DmadoneieR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
pub fn ufie(&self) -> UfieR {
UfieR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<IerSpec> {
Rsvd4W::new(self, 0)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
#[must_use]
pub fn ssdie(&mut self) -> SsdieW<IerSpec> {
SsdieW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
#[must_use]
pub fn aldie(&mut self) -> AldieW<IerSpec> {
AldieW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<IerSpec> {
TeieW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
#[must_use]
pub fn rfie(&mut self) -> RfieW<IerSpec> {
RfieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IerSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
#[must_use]
pub fn sadie(&mut self) -> SadieW<IerSpec> {
SadieW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
#[must_use]
pub fn bedie(&mut self) -> BedieW<IerSpec> {
BedieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IerSpec> {
Rsvd2W::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
#[must_use]
pub fn msdie(&mut self) -> MsdieW<IerSpec> {
MsdieW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
#[must_use]
pub fn dmadoneie(&mut self) -> DmadoneieW<IerSpec> {
DmadoneieW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ofie(&mut self) -> OfieW<IerSpec> {
OfieW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ufie(&mut self) -> UfieW<IerSpec> {
UfieW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IerSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `RWM` reader - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmR = crate::BitReader;
#[doc = "Field `RWM` writer - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UB` reader - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbR = crate::BitReader;
#[doc = "Field `UB` writer - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBB` reader - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbR = crate::BitReader;
#[doc = "Field `IBB` writer - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SSD` reader - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdR = crate::BitReader;
#[doc = "Field `SSD` writer - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALD` reader - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldR = crate::BitReader;
#[doc = "Field `ALD` writer - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RF` reader - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfR = crate::BitReader;
#[doc = "Field `RF` writer - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAD` reader - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadR = crate::BitReader;
#[doc = "Field `SAD` writer - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BED` reader - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedR = crate::BitReader;
#[doc = "Field `BED` writer - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EBB` reader - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbR = crate::BitReader;
#[doc = "Field `EBB` writer - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSD` reader - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdR = crate::BitReader;
#[doc = "Field `MSD` writer - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONE` reader - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneR = crate::BitReader;
#[doc = "Field `DMADONE` writer - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OF` reader - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfR = crate::BitReader;
#[doc = "Field `OF` writer - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UF` reader - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfR = crate::BitReader;
#[doc = "Field `UF` writer - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
pub fn rwm(&self) -> RwmR {
RwmR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
pub fn ub(&self) -> UbR {
UbR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
pub fn ibb(&self) -> IbbR {
IbbR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
pub fn ssd(&self) -> SsdR {
SsdR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
pub fn ald(&self) -> AldR {
AldR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn rf(&self) -> RfR {
RfR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn sad(&self) -> SadR {
SadR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
pub fn bed(&self) -> BedR {
BedR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
pub fn ebb(&self) -> EbbR {
EbbR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
pub fn msd(&self) -> MsdR {
MsdR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
pub fn dmadone(&self) -> DmadoneR {
DmadoneR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
pub fn of(&self) -> OfR {
OfR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
pub fn uf(&self) -> UfR {
UfR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
#[must_use]
pub fn rwm(&mut self) -> RwmW<SrSpec> {
RwmW::new(self, 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<SrSpec> {
NackW::new(self, 1)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
#[must_use]
pub fn ub(&mut self) -> UbW<SrSpec> {
UbW::new(self, 2)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
#[must_use]
pub fn ibb(&mut self) -> IbbW<SrSpec> {
IbbW::new(self, 3)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ssd(&mut self) -> SsdW<SrSpec> {
SsdW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ald(&mut self) -> AldW<SrSpec> {
AldW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<SrSpec> {
TeW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn rf(&mut self) -> RfW<SrSpec> {
RfW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn sad(&mut self) -> SadW<SrSpec> {
SadW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn bed(&mut self) -> BedW<SrSpec> {
BedW::new(self, 10)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
#[must_use]
pub fn ebb(&mut self) -> EbbW<SrSpec> {
EbbW::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
#[must_use]
pub fn msd(&mut self) -> MsdW<SrSpec> {
MsdW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn dmadone(&mut self) -> DmadoneW<SrSpec> {
DmadoneW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn of(&mut self) -> OfW<SrSpec> {
OfW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn uf(&mut self) -> UfW<SrSpec> {
UfW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DBR (rw) register accessor: Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbr`]
module"]
#[doc(alias = "DBR")]
pub type Dbr = crate::Reg<dbr::DbrSpec>;
#[doc = "Data Buffer register"]
pub mod dbr {
#[doc = "Register `DBR` reader"]
pub type R = crate::R<DbrSpec>;
#[doc = "Register `DBR` writer"]
pub type W = crate::W<DbrSpec>;
#[doc = "Field `DATA` reader - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DbrSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DbrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DbrSpec;
impl crate::RegisterSpec for DbrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dbr::R`](R) reader structure"]
impl crate::Readable for DbrSpec {}
#[doc = "`write(|w| ..)` method takes [`dbr::W`](W) writer structure"]
impl crate::Writable for DbrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DBR to value 0"]
impl crate::Resettable for DbrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SAR (rw) register accessor: Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`]
module"]
#[doc(alias = "SAR")]
pub type Sar = crate::Reg<sar::SarSpec>;
#[doc = "Slave Address Register"]
pub mod sar {
#[doc = "Register `SAR` reader"]
pub type R = crate::R<SarSpec>;
#[doc = "Register `SAR` writer"]
pub type W = crate::W<SarSpec>;
#[doc = "Field `ADDR` reader - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrR = crate::FieldReader;
#[doc = "Field `ADDR` writer - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>;
impl R {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 7) & 0x01ff_ffff)
}
}
impl W {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<SarSpec> {
AddrW::new(self, 0)
}
#[doc = "Bits 7:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SarSpec> {
RsvdW::new(self, 7)
}
}
#[doc = "Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SarSpec;
impl crate::RegisterSpec for SarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar::R`](R) reader structure"]
impl crate::Readable for SarSpec {}
#[doc = "`write(|w| ..)` method takes [`sar::W`](W) writer structure"]
impl crate::Writable for SarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR to value 0x47"]
impl crate::Resettable for SarSpec {
const RESET_VALUE: u32 = 0x47;
}
}
#[doc = "LCR (rw) register accessor: Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`]
module"]
#[doc(alias = "LCR")]
pub type Lcr = crate::Reg<lcr::LcrSpec>;
#[doc = "Load Count Register"]
pub mod lcr {
#[doc = "Register `LCR` reader"]
pub type R = crate::R<LcrSpec>;
#[doc = "Register `LCR` writer"]
pub type W = crate::W<LcrSpec>;
#[doc = "Field `SLV` reader - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvR = crate::FieldReader<u16>;
#[doc = "Field `SLV` writer - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `FLV` reader - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvR = crate::FieldReader<u16>;
#[doc = "Field `FLV` writer - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVL` reader - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlR = crate::FieldReader<u16>;
#[doc = "Field `HLVL` writer - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVH` reader - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhR = crate::FieldReader;
#[doc = "Field `HLVH` writer - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
pub fn slv(&self) -> SlvR {
SlvR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
pub fn flv(&self) -> FlvR {
FlvR::new(((self.bits >> 9) & 0x01ff) as u16)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
pub fn hlvl(&self) -> HlvlR {
HlvlR::new(((self.bits >> 18) & 0x01ff) as u16)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
pub fn hlvh(&self) -> HlvhR {
HlvhR::new(((self.bits >> 27) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
#[must_use]
pub fn slv(&mut self) -> SlvW<LcrSpec> {
SlvW::new(self, 0)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
#[must_use]
pub fn flv(&mut self) -> FlvW<LcrSpec> {
FlvW::new(self, 9)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
#[must_use]
pub fn hlvl(&mut self) -> HlvlW<LcrSpec> {
HlvlW::new(self, 18)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
#[must_use]
pub fn hlvh(&mut self) -> HlvhW<LcrSpec> {
HlvhW::new(self, 27)
}
}
#[doc = "Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LcrSpec;
impl crate::RegisterSpec for LcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lcr::R`](R) reader structure"]
impl crate::Readable for LcrSpec {}
#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"]
impl crate::Writable for LcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LCR to value 0x081c_72ed"]
impl crate::Resettable for LcrSpec {
const RESET_VALUE: u32 = 0x081c_72ed;
}
}
#[doc = "WCR (rw) register accessor: Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wcr`]
module"]
#[doc(alias = "WCR")]
pub type Wcr = crate::Reg<wcr::WcrSpec>;
#[doc = "Wait Count Register"]
pub mod wcr {
#[doc = "Register `WCR` reader"]
pub type R = crate::R<WcrSpec>;
#[doc = "Register `WCR` writer"]
pub type W = crate::W<WcrSpec>;
#[doc = "Field `CNT` reader - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntR = crate::FieldReader;
#[doc = "Field `CNT` writer - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<WcrSpec> {
CntW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WcrSpec;
impl crate::RegisterSpec for WcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wcr::R`](R) reader structure"]
impl crate::Readable for WcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wcr::W`](W) writer structure"]
impl crate::Writable for WcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WCR to value 0x0a"]
impl crate::Resettable for WcrSpec {
const RESET_VALUE: u32 = 0x0a;
}
}
#[doc = "RCCR (rw) register accessor: Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rccr`]
module"]
#[doc(alias = "RCCR")]
pub type Rccr = crate::Reg<rccr::RccrSpec>;
#[doc = "Bus Reset Cycle Counter Register"]
pub mod rccr {
#[doc = "Register `RCCR` reader"]
pub type R = crate::R<RccrSpec>;
#[doc = "Register `RCCR` writer"]
pub type W = crate::W<RccrSpec>;
#[doc = "Field `RSTCYC` reader - The cycles of SCL during bus reset"]
pub type RstcycR = crate::FieldReader;
#[doc = "Field `RSTCYC` writer - The cycles of SCL during bus reset"]
pub type RstcycW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
pub fn rstcyc(&self) -> RstcycR {
RstcycR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
#[must_use]
pub fn rstcyc(&mut self) -> RstcycW<RccrSpec> {
RstcycW::new(self, 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RccrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RccrSpec;
impl crate::RegisterSpec for RccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rccr::R`](R) reader structure"]
impl crate::Readable for RccrSpec {}
#[doc = "`write(|w| ..)` method takes [`rccr::W`](W) writer structure"]
impl crate::Writable for RccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCCR to value 0x09"]
impl crate::Resettable for RccrSpec {
const RESET_VALUE: u32 = 0x09;
}
}
#[doc = "BMR (rw) register accessor: Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmr`]
module"]
#[doc(alias = "BMR")]
pub type Bmr = crate::Reg<bmr::BmrSpec>;
#[doc = "Bus Monitor Register"]
pub mod bmr {
#[doc = "Register `BMR` reader"]
pub type R = crate::R<BmrSpec>;
#[doc = "Register `BMR` writer"]
pub type W = crate::W<BmrSpec>;
#[doc = "Field `SDA` reader - value of the SDA pin."]
pub type SdaR = crate::BitReader;
#[doc = "Field `SDA` writer - value of the SDA pin."]
pub type SdaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCL` reader - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclR = crate::BitReader;
#[doc = "Field `SCL` writer - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
pub fn sda(&self) -> SdaR {
SdaR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
pub fn scl(&self) -> SclR {
SclR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
#[must_use]
pub fn sda(&mut self) -> SdaW<BmrSpec> {
SdaW::new(self, 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
#[must_use]
pub fn scl(&mut self) -> SclW<BmrSpec> {
SclW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BmrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BmrSpec;
impl crate::RegisterSpec for BmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bmr::R`](R) reader structure"]
impl crate::Readable for BmrSpec {}
#[doc = "`write(|w| ..)` method takes [`bmr::W`](W) writer structure"]
impl crate::Writable for BmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BMR to value 0x03"]
impl crate::Resettable for BmrSpec {
const RESET_VALUE: u32 = 0x03;
}
}
#[doc = "DNR (rw) register accessor: DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dnr`]
module"]
#[doc(alias = "DNR")]
pub type Dnr = crate::Reg<dnr::DnrSpec>;
#[doc = "DMA number register"]
pub mod dnr {
#[doc = "Register `DNR` reader"]
pub type R = crate::R<DnrSpec>;
#[doc = "Register `DNR` writer"]
pub type W = crate::W<DnrSpec>;
#[doc = "Field `NDT` reader - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<DnrSpec> {
NdtW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DnrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DnrSpec;
impl crate::RegisterSpec for DnrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dnr::R`](R) reader structure"]
impl crate::Readable for DnrSpec {}
#[doc = "`write(|w| ..)` method takes [`dnr::W`](W) writer structure"]
impl crate::Writable for DnrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DNR to value 0"]
impl crate::Resettable for DnrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO (rw) register accessor: FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`]
module"]
#[doc(alias = "FIFO")]
pub type Fifo = crate::Reg<fifo::FifoSpec>;
#[doc = "FIFO Register"]
pub mod fifo {
#[doc = "Register `FIFO` reader"]
pub type R = crate::R<FifoSpec>;
#[doc = "Register `FIFO` writer"]
pub type W = crate::W<FifoSpec>;
#[doc = "Field `DATA` reader - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<FifoSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoSpec;
impl crate::RegisterSpec for FifoSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo::R`](R) reader structure"]
impl crate::Readable for FifoSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"]
impl crate::Writable for FifoSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO to value 0"]
impl crate::Resettable for FifoSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "I2C4"]
pub struct I2c4 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2c4 {}
impl I2c4 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2c4::RegisterBlock = 0x5009_f000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2c4::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2c4 {
type Target = i2c4::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2c4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c4").finish()
}
}
#[doc = "I2C4"]
pub mod i2c4 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr: Cr,
tcr: Tcr,
ier: Ier,
sr: Sr,
dbr: Dbr,
sar: Sar,
lcr: Lcr,
wcr: Wcr,
rccr: Rccr,
bmr: Bmr,
dnr: Dnr,
rsvd1: Rsvd1,
fifo: Fifo,
}
impl RegisterBlock {
#[doc = "0x00 - Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x04 - Transfer Control register"]
#[inline(always)]
pub const fn tcr(&self) -> &Tcr {
&self.tcr
}
#[doc = "0x08 - Interrupt Enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x0c - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x10 - Data Buffer register"]
#[inline(always)]
pub const fn dbr(&self) -> &Dbr {
&self.dbr
}
#[doc = "0x14 - Slave Address Register"]
#[inline(always)]
pub const fn sar(&self) -> &Sar {
&self.sar
}
#[doc = "0x18 - Load Count Register"]
#[inline(always)]
pub const fn lcr(&self) -> &Lcr {
&self.lcr
}
#[doc = "0x1c - Wait Count Register"]
#[inline(always)]
pub const fn wcr(&self) -> &Wcr {
&self.wcr
}
#[doc = "0x20 - Bus Reset Cycle Counter Register"]
#[inline(always)]
pub const fn rccr(&self) -> &Rccr {
&self.rccr
}
#[doc = "0x24 - Bus Monitor Register"]
#[inline(always)]
pub const fn bmr(&self) -> &Bmr {
&self.bmr
}
#[doc = "0x28 - DMA number register"]
#[inline(always)]
pub const fn dnr(&self) -> &Dnr {
&self.dnr
}
#[doc = "0x2c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x30 - FIFO Register"]
#[inline(always)]
pub const fn fifo(&self) -> &Fifo {
&self.fifo
}
}
#[doc = "CR (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `MODE` reader - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeR = crate::FieldReader;
#[doc = "Field `MODE` writer - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `IUE` reader - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueR = crate::BitReader;
#[doc = "Field `IUE` writer - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
pub type IueW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLE` reader - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleR = crate::BitReader;
#[doc = "Field `SCLE` writer - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
pub type ScleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAEN` reader - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenR = crate::BitReader;
#[doc = "Field `DMAEN` writer - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTNACK` reader - Generate NACK for last DMA Read transfer"]
pub type LastnackR = crate::BitReader;
#[doc = "Field `LASTNACK` writer - Generate NACK for last DMA Read transfer"]
pub type LastnackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LASTSTOP` reader - Generate STOP for last DMA transfer"]
pub type LaststopR = crate::BitReader;
#[doc = "Field `LASTSTOP` writer - Generate STOP for last DMA transfer"]
pub type LaststopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDE` reader - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeR = crate::BitReader;
#[doc = "Field `MSDE` writer - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
pub type MsdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCLPP` reader - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppR = crate::BitReader;
#[doc = "Field `SCLPP` writer - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
pub type SclppW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLVEN` reader - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenR = crate::BitReader;
#[doc = "Field `SLVEN` writer - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
pub type SlvenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DNF` reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfR = crate::FieldReader;
#[doc = "Field `DNF` writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
pub type DnfW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `BRGRST` reader - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstR = crate::BitReader;
#[doc = "Field `BRGRST` writer - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
pub type BrgrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSTREQ` reader - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqR = crate::BitReader;
#[doc = "Field `RSTREQ` writer - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
pub type RstreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UR` reader - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrR = crate::BitReader;
#[doc = "Field `UR` writer - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
pub type UrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
pub fn iue(&self) -> IueR {
IueR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
pub fn scle(&self) -> ScleR {
ScleR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
pub fn dmaen(&self) -> DmaenR {
DmaenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
pub fn lastnack(&self) -> LastnackR {
LastnackR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
pub fn laststop(&self) -> LaststopR {
LaststopR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
pub fn msde(&self) -> MsdeR {
MsdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
pub fn sclpp(&self) -> SclppR {
SclppR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
pub fn slven(&self) -> SlvenR {
SlvenR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
pub fn dnf(&self) -> DnfR {
DnfR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:28"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 15) & 0x3fff) as u16)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
pub fn brgrst(&self) -> BrgrstR {
BrgrstR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
pub fn rstreq(&self) -> RstreqR {
RstreqR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
pub fn ur(&self) -> UrR {
UrR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<CrSpec> {
ModeW::new(self, 0)
}
#[doc = "Bit 2 - I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit."]
#[inline(always)]
#[must_use]
pub fn iue(&mut self) -> IueW<CrSpec> {
IueW::new(self, 2)
}
#[doc = "Bit 3 - SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation."]
#[inline(always)]
#[must_use]
pub fn scle(&mut self) -> ScleW<CrSpec> {
ScleW::new(self, 3)
}
#[doc = "Bit 4 - DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled"]
#[inline(always)]
#[must_use]
pub fn dmaen(&mut self) -> DmaenW<CrSpec> {
DmaenW::new(self, 4)
}
#[doc = "Bit 5 - Generate NACK for last DMA Read transfer"]
#[inline(always)]
#[must_use]
pub fn lastnack(&mut self) -> LastnackW<CrSpec> {
LastnackW::new(self, 5)
}
#[doc = "Bit 6 - Generate STOP for last DMA transfer"]
#[inline(always)]
#[must_use]
pub fn laststop(&mut self) -> LaststopW<CrSpec> {
LaststopW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CrSpec> {
Rsvd3W::new(self, 7)
}
#[doc = "Bit 8 - Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled."]
#[inline(always)]
#[must_use]
pub fn msde(&mut self) -> MsdeW<CrSpec> {
MsdeW::new(self, 8)
}
#[doc = "Bit 9 - Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL"]
#[inline(always)]
#[must_use]
pub fn sclpp(&mut self) -> SclppW<CrSpec> {
SclppW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CrSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bit 11 - Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus."]
#[inline(always)]
#[must_use]
pub fn slven(&mut self) -> SlvenW<CrSpec> {
SlvenW::new(self, 11)
}
#[doc = "Bits 12:14 - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode."]
#[inline(always)]
#[must_use]
pub fn dnf(&mut self) -> DnfW<CrSpec> {
DnfW::new(self, 12)
}
#[doc = "Bits 15:28"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 15)
}
#[doc = "Bit 29 - Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished"]
#[inline(always)]
#[must_use]
pub fn brgrst(&mut self) -> BrgrstW<CrSpec> {
BrgrstW::new(self, 29)
}
#[doc = "Bit 30 - I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished"]
#[inline(always)]
#[must_use]
pub fn rstreq(&mut self) -> RstreqW<CrSpec> {
RstreqW::new(self, 30)
}
#[doc = "Bit 31 - Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module."]
#[inline(always)]
#[must_use]
pub fn ur(&mut self) -> UrW<CrSpec> {
UrW::new(self, 31)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TCR (rw) register accessor: Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
module"]
#[doc(alias = "TCR")]
pub type Tcr = crate::Reg<tcr::TcrSpec>;
#[doc = "Transfer Control register"]
pub mod tcr {
#[doc = "Register `TCR` reader"]
pub type R = crate::R<TcrSpec>;
#[doc = "Register `TCR` writer"]
pub type W = crate::W<TcrSpec>;
#[doc = "Field `TB` reader - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbR = crate::BitReader;
#[doc = "Field `TB` writer - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
pub type TbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `START` reader - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartR = crate::BitReader;
#[doc = "Field `START` writer - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STOP` reader - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopR = crate::BitReader;
#[doc = "Field `STOP` writer - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MA` reader - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaR = crate::BitReader;
#[doc = "Field `MA` writer - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
pub type MaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXREQ` reader - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqR = crate::BitReader;
#[doc = "Field `TXREQ` writer - Request DMA TX. Will be cleared by HW automatically"]
pub type TxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXREQ` reader - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqR = crate::BitReader;
#[doc = "Field `RXREQ` writer - Request DMA RX. Will be cleared by HW automatically"]
pub type RxreqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ABORTDMA` reader - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaR = crate::BitReader;
#[doc = "Field `ABORTDMA` writer - Abort DMA operation. Will be cleared by HW automatically"]
pub type AbortdmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
pub fn tb(&self) -> TbR {
TbR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
pub fn start(&self) -> StartR {
StartR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn txreq(&self) -> TxreqR {
TxreqR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
pub fn rxreq(&self) -> RxreqR {
RxreqR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
pub fn abortdma(&self) -> AbortdmaR {
AbortdmaR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set."]
#[inline(always)]
#[must_use]
pub fn tb(&mut self) -> TbW<TcrSpec> {
TbW::new(self, 0)
}
#[doc = "Bit 1 - Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse."]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> StartW<TcrSpec> {
StartW::new(self, 1)
}
#[doc = "Bit 2 - Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop."]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<TcrSpec> {
StopW::new(self, 2)
}
#[doc = "Bit 3 - The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<TcrSpec> {
NackW::new(self, 3)
}
#[doc = "Bit 4 - Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR\\[STOP\\]
is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR\\[TB\\]
bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR\\[TB\\]
bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR\\[STOP\\]
bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR\\[TB\\]
bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only)."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<TcrSpec> {
MaW::new(self, 4)
}
#[doc = "Bit 5 - Request DMA TX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn txreq(&mut self) -> TxreqW<TcrSpec> {
TxreqW::new(self, 5)
}
#[doc = "Bit 6 - Request DMA RX. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn rxreq(&mut self) -> RxreqW<TcrSpec> {
RxreqW::new(self, 6)
}
#[doc = "Bit 7 - Abort DMA operation. Will be cleared by HW automatically"]
#[inline(always)]
#[must_use]
pub fn abortdma(&mut self) -> AbortdmaW<TcrSpec> {
AbortdmaW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Transfer Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcrSpec;
impl crate::RegisterSpec for TcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
impl crate::Readable for TcrSpec {}
#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
impl crate::Writable for TcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TCR to value 0"]
impl crate::Resettable for TcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER (rw) register accessor: Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "Interrupt Enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `SSDIE` reader - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieR = crate::BitReader;
#[doc = "Field `SSDIE` writer - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
pub type SsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALDIE` reader - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieR = crate::BitReader;
#[doc = "Field `ALDIE` writer - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
pub type AldieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RFIE` reader - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieR = crate::BitReader;
#[doc = "Field `RFIE` writer - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
pub type RfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SADIE` reader - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieR = crate::BitReader;
#[doc = "Field `SADIE` writer - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
pub type SadieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BEDIE` reader - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieR = crate::BitReader;
#[doc = "Field `BEDIE` writer - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
pub type BedieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSDIE` reader - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieR = crate::BitReader;
#[doc = "Field `MSDIE` writer - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
pub type MsdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONEIE` reader - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieR = crate::BitReader;
#[doc = "Field `DMADONEIE` writer - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
pub type DmadoneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UFIE` reader - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieR = crate::BitReader;
#[doc = "Field `UFIE` writer - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
pub type UfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
pub fn ssdie(&self) -> SsdieR {
SsdieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
pub fn aldie(&self) -> AldieR {
AldieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
pub fn rfie(&self) -> RfieR {
RfieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
pub fn sadie(&self) -> SadieR {
SadieR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
pub fn bedie(&self) -> BedieR {
BedieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
pub fn msdie(&self) -> MsdieR {
MsdieR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
pub fn dmadoneie(&self) -> DmadoneieR {
DmadoneieR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
pub fn ufie(&self) -> UfieR {
UfieR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<IerSpec> {
Rsvd4W::new(self, 0)
}
#[doc = "Bit 4 - Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode."]
#[inline(always)]
#[must_use]
pub fn ssdie(&mut self) -> SsdieW<IerSpec> {
SsdieW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode."]
#[inline(always)]
#[must_use]
pub fn aldie(&mut self) -> AldieW<IerSpec> {
AldieW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus."]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<IerSpec> {
TeieW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus."]
#[inline(always)]
#[must_use]
pub fn rfie(&mut self) -> RfieW<IerSpec> {
RfieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IerSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address."]
#[inline(always)]
#[must_use]
pub fn sadie(&mut self) -> SadieW<IerSpec> {
SadieW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur."]
#[inline(always)]
#[must_use]
pub fn bedie(&mut self) -> BedieW<IerSpec> {
BedieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IerSpec> {
Rsvd2W::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit."]
#[inline(always)]
#[must_use]
pub fn msdie(&mut self) -> MsdieW<IerSpec> {
MsdieW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled."]
#[inline(always)]
#[must_use]
pub fn dmadoneie(&mut self) -> DmadoneieW<IerSpec> {
DmadoneieW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ofie(&mut self) -> OfieW<IerSpec> {
OfieW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled"]
#[inline(always)]
#[must_use]
pub fn ufie(&mut self) -> UfieW<IerSpec> {
UfieW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IerSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Interrupt Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `RWM` reader - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmR = crate::BitReader;
#[doc = "Field `RWM` writer - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
pub type RwmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` reader - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackR = crate::BitReader;
#[doc = "Field `NACK` writer - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UB` reader - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbR = crate::BitReader;
#[doc = "Field `UB` writer - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
pub type UbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBB` reader - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbR = crate::BitReader;
#[doc = "Field `IBB` writer - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
pub type IbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SSD` reader - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdR = crate::BitReader;
#[doc = "Field `SSD` writer - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
pub type SsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALD` reader - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldR = crate::BitReader;
#[doc = "Field `ALD` writer - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
pub type AldW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RF` reader - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfR = crate::BitReader;
#[doc = "Field `RF` writer - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type RfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SAD` reader - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadR = crate::BitReader;
#[doc = "Field `SAD` writer - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
pub type SadW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BED` reader - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedR = crate::BitReader;
#[doc = "Field `BED` writer - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
pub type BedW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EBB` reader - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbR = crate::BitReader;
#[doc = "Field `EBB` writer - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
pub type EbbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSD` reader - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdR = crate::BitReader;
#[doc = "Field `MSD` writer - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
pub type MsdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADONE` reader - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneR = crate::BitReader;
#[doc = "Field `DMADONE` writer - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
pub type DmadoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OF` reader - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfR = crate::BitReader;
#[doc = "Field `OF` writer - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UF` reader - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfR = crate::BitReader;
#[doc = "Field `UF` writer - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
pub type UfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
pub fn rwm(&self) -> RwmR {
RwmR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
pub fn nack(&self) -> NackR {
NackR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
pub fn ub(&self) -> UbR {
UbR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
pub fn ibb(&self) -> IbbR {
IbbR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
pub fn ssd(&self) -> SsdR {
SsdR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
pub fn ald(&self) -> AldR {
AldR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn rf(&self) -> RfR {
RfR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
pub fn sad(&self) -> SadR {
SadR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
pub fn bed(&self) -> BedR {
BedR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
pub fn ebb(&self) -> EbbR {
EbbR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
pub fn msd(&self) -> MsdR {
MsdR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
pub fn dmadone(&self) -> DmadoneR {
DmadoneR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
pub fn of(&self) -> OfR {
OfR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
pub fn uf(&self) -> UfR {
UfR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bit 0 - Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state."]
#[inline(always)]
#[must_use]
pub fn rwm(&mut self) -> RwmW<SrSpec> {
RwmW::new(self, 0)
}
#[doc = "Bit 1 - ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received."]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NackW<SrSpec> {
NackW::new(self, 1)
}
#[doc = "Bit 2 - Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop."]
#[inline(always)]
#[must_use]
pub fn ub(&mut self) -> UbW<SrSpec> {
UbW::new(self, 2)
}
#[doc = "Bit 3 - I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction."]
#[inline(always)]
#[must_use]
pub fn ibb(&mut self) -> IbbW<SrSpec> {
IbbW::new(self, 3)
}
#[doc = "Bit 4 - Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ssd(&mut self) -> SsdW<SrSpec> {
SsdW::new(self, 4)
}
#[doc = "Bit 5 - Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn ald(&mut self) -> AldW<SrSpec> {
AldW::new(self, 5)
}
#[doc = "Bit 6 - DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<SrSpec> {
TeW::new(self, 6)
}
#[doc = "Bit 7 - DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn rf(&mut self) -> RfW<SrSpec> {
RfW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9 - Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn sad(&mut self) -> SadW<SrSpec> {
SadW::new(self, 9)
}
#[doc = "Bit 10 - Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn bed(&mut self) -> BedW<SrSpec> {
BedW::new(self, 10)
}
#[doc = "Bit 11 - Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set."]
#[inline(always)]
#[must_use]
pub fn ebb(&mut self) -> EbbW<SrSpec> {
EbbW::new(self, 11)
}
#[doc = "Bit 12 - Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR\\[MSDE\\]
= 1); I2C unit is configured as a master; I2C transmits a STOP signal"]
#[inline(always)]
#[must_use]
pub fn msd(&mut self) -> MsdW<SrSpec> {
MsdW::new(self, 12)
}
#[doc = "Bit 13 - DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn dmadone(&mut self) -> DmadoneW<SrSpec> {
DmadoneW::new(self, 13)
}
#[doc = "Bit 14 - FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn of(&mut self) -> OfW<SrSpec> {
OfW::new(self, 14)
}
#[doc = "Bit 15 - FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1"]
#[inline(always)]
#[must_use]
pub fn uf(&mut self) -> UfW<SrSpec> {
UfW::new(self, 15)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DBR (rw) register accessor: Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbr`]
module"]
#[doc(alias = "DBR")]
pub type Dbr = crate::Reg<dbr::DbrSpec>;
#[doc = "Data Buffer register"]
pub mod dbr {
#[doc = "Register `DBR` reader"]
pub type R = crate::R<DbrSpec>;
#[doc = "Register `DBR` writer"]
pub type W = crate::W<DbrSpec>;
#[doc = "Field `DATA` reader - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR\\[NACK\\]
are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted."]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DbrSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DbrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Data Buffer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DbrSpec;
impl crate::RegisterSpec for DbrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dbr::R`](R) reader structure"]
impl crate::Readable for DbrSpec {}
#[doc = "`write(|w| ..)` method takes [`dbr::W`](W) writer structure"]
impl crate::Writable for DbrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DBR to value 0"]
impl crate::Resettable for DbrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SAR (rw) register accessor: Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar`]
module"]
#[doc(alias = "SAR")]
pub type Sar = crate::Reg<sar::SarSpec>;
#[doc = "Slave Address Register"]
pub mod sar {
#[doc = "Register `SAR` reader"]
pub type R = crate::R<SarSpec>;
#[doc = "Register `SAR` writer"]
pub type W = crate::W<SarSpec>;
#[doc = "Field `ADDR` reader - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrR = crate::FieldReader;
#[doc = "Field `ADDR` writer - The seven-bit address to which the I2C responds when in slave-receive mode"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>;
impl R {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 7) & 0x01ff_ffff)
}
}
impl W {
#[doc = "Bits 0:6 - The seven-bit address to which the I2C responds when in slave-receive mode"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> AddrW<SarSpec> {
AddrW::new(self, 0)
}
#[doc = "Bits 7:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SarSpec> {
RsvdW::new(self, 7)
}
}
#[doc = "Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SarSpec;
impl crate::RegisterSpec for SarSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sar::R`](R) reader structure"]
impl crate::Readable for SarSpec {}
#[doc = "`write(|w| ..)` method takes [`sar::W`](W) writer structure"]
impl crate::Writable for SarSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SAR to value 0x47"]
impl crate::Resettable for SarSpec {
const RESET_VALUE: u32 = 0x47;
}
}
#[doc = "LCR (rw) register accessor: Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`]
module"]
#[doc(alias = "LCR")]
pub type Lcr = crate::Reg<lcr::LcrSpec>;
#[doc = "Load Count Register"]
pub mod lcr {
#[doc = "Register `LCR` reader"]
pub type R = crate::R<LcrSpec>;
#[doc = "Register `LCR` writer"]
pub type W = crate::W<LcrSpec>;
#[doc = "Field `SLV` reader - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvR = crate::FieldReader<u16>;
#[doc = "Field `SLV` writer - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
pub type SlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `FLV` reader - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvR = crate::FieldReader<u16>;
#[doc = "Field `FLV` writer - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
pub type FlvW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVL` reader - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlR = crate::FieldReader<u16>;
#[doc = "Field `HLVL` writer - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
pub type HlvlW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `HLVH` reader - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhR = crate::FieldReader;
#[doc = "Field `HLVH` writer - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
pub type HlvhW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
pub fn slv(&self) -> SlvR {
SlvR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
pub fn flv(&self) -> FlvR {
FlvR::new(((self.bits >> 9) & 0x01ff) as u16)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
pub fn hlvl(&self) -> HlvlR {
HlvlR::new(((self.bits >> 18) & 0x01ff) as u16)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
pub fn hlvh(&self) -> HlvhR {
HlvhR::new(((self.bits >> 27) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:8 - Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV"]
#[inline(always)]
#[must_use]
pub fn slv(&mut self) -> SlvW<LcrSpec> {
SlvW::new(self, 0)
}
#[doc = "Bits 9:17 - Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV"]
#[inline(always)]
#[must_use]
pub fn flv(&mut self) -> FlvW<LcrSpec> {
FlvW::new(self, 9)
}
#[doc = "Bits 18:26 - Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1)"]
#[inline(always)]
#[must_use]
pub fn hlvl(&mut self) -> HlvlW<LcrSpec> {
HlvlW::new(self, 18)
}
#[doc = "Bits 27:31 - Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF)"]
#[inline(always)]
#[must_use]
pub fn hlvh(&mut self) -> HlvhW<LcrSpec> {
HlvhW::new(self, 27)
}
}
#[doc = "Load Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LcrSpec;
impl crate::RegisterSpec for LcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lcr::R`](R) reader structure"]
impl crate::Readable for LcrSpec {}
#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"]
impl crate::Writable for LcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LCR to value 0x081c_72ed"]
impl crate::Resettable for LcrSpec {
const RESET_VALUE: u32 = 0x081c_72ed;
}
}
#[doc = "WCR (rw) register accessor: Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wcr`]
module"]
#[doc(alias = "WCR")]
pub type Wcr = crate::Reg<wcr::WcrSpec>;
#[doc = "Wait Count Register"]
pub mod wcr {
#[doc = "Register `WCR` reader"]
pub type R = crate::R<WcrSpec>;
#[doc = "Register `WCR` writer"]
pub type W = crate::W<WcrSpec>;
#[doc = "Field `CNT` reader - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntR = crate::FieldReader;
#[doc = "Field `CNT` writer - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times."]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<WcrSpec> {
CntW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Wait Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WcrSpec;
impl crate::RegisterSpec for WcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wcr::R`](R) reader structure"]
impl crate::Readable for WcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wcr::W`](W) writer structure"]
impl crate::Writable for WcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WCR to value 0x0a"]
impl crate::Resettable for WcrSpec {
const RESET_VALUE: u32 = 0x0a;
}
}
#[doc = "RCCR (rw) register accessor: Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rccr`]
module"]
#[doc(alias = "RCCR")]
pub type Rccr = crate::Reg<rccr::RccrSpec>;
#[doc = "Bus Reset Cycle Counter Register"]
pub mod rccr {
#[doc = "Register `RCCR` reader"]
pub type R = crate::R<RccrSpec>;
#[doc = "Register `RCCR` writer"]
pub type W = crate::W<RccrSpec>;
#[doc = "Field `RSTCYC` reader - The cycles of SCL during bus reset"]
pub type RstcycR = crate::FieldReader;
#[doc = "Field `RSTCYC` writer - The cycles of SCL during bus reset"]
pub type RstcycW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
pub fn rstcyc(&self) -> RstcycR {
RstcycR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bits 0:3 - The cycles of SCL during bus reset"]
#[inline(always)]
#[must_use]
pub fn rstcyc(&mut self) -> RstcycW<RccrSpec> {
RstcycW::new(self, 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RccrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "Bus Reset Cycle Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RccrSpec;
impl crate::RegisterSpec for RccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rccr::R`](R) reader structure"]
impl crate::Readable for RccrSpec {}
#[doc = "`write(|w| ..)` method takes [`rccr::W`](W) writer structure"]
impl crate::Writable for RccrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCCR to value 0x09"]
impl crate::Resettable for RccrSpec {
const RESET_VALUE: u32 = 0x09;
}
}
#[doc = "BMR (rw) register accessor: Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmr`]
module"]
#[doc(alias = "BMR")]
pub type Bmr = crate::Reg<bmr::BmrSpec>;
#[doc = "Bus Monitor Register"]
pub mod bmr {
#[doc = "Register `BMR` reader"]
pub type R = crate::R<BmrSpec>;
#[doc = "Register `BMR` writer"]
pub type W = crate::W<BmrSpec>;
#[doc = "Field `SDA` reader - value of the SDA pin."]
pub type SdaR = crate::BitReader;
#[doc = "Field `SDA` writer - value of the SDA pin."]
pub type SdaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCL` reader - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclR = crate::BitReader;
#[doc = "Field `SCL` writer - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
pub type SclW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
pub fn sda(&self) -> SdaR {
SdaR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
pub fn scl(&self) -> SclR {
SclR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - value of the SDA pin."]
#[inline(always)]
#[must_use]
pub fn sda(&mut self) -> SdaW<BmrSpec> {
SdaW::new(self, 0)
}
#[doc = "Bit 1 - value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset."]
#[inline(always)]
#[must_use]
pub fn scl(&mut self) -> SclW<BmrSpec> {
SclW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BmrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Bus Monitor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BmrSpec;
impl crate::RegisterSpec for BmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bmr::R`](R) reader structure"]
impl crate::Readable for BmrSpec {}
#[doc = "`write(|w| ..)` method takes [`bmr::W`](W) writer structure"]
impl crate::Writable for BmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BMR to value 0x03"]
impl crate::Resettable for BmrSpec {
const RESET_VALUE: u32 = 0x03;
}
}
#[doc = "DNR (rw) register accessor: DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dnr`]
module"]
#[doc(alias = "DNR")]
pub type Dnr = crate::Reg<dnr::DnrSpec>;
#[doc = "DMA number register"]
pub mod dnr {
#[doc = "Register `DNR` reader"]
pub type R = crate::R<DnrSpec>;
#[doc = "Register `DNR` writer"]
pub type W = crate::W<DnrSpec>;
#[doc = "Field `NDT` reader - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - Write as number of data to transfer in byte. Read as left data number to transfer"]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8 - Write as number of data to transfer in byte. Read as left data number to transfer"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<DnrSpec> {
NdtW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DnrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "DMA number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dnr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dnr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DnrSpec;
impl crate::RegisterSpec for DnrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dnr::R`](R) reader structure"]
impl crate::Readable for DnrSpec {}
#[doc = "`write(|w| ..)` method takes [`dnr::W`](W) writer structure"]
impl crate::Writable for DnrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DNR to value 0"]
impl crate::Resettable for DnrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FIFO (rw) register accessor: FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`]
module"]
#[doc(alias = "FIFO")]
pub type Fifo = crate::Reg<fifo::FifoSpec>;
#[doc = "FIFO Register"]
pub mod fifo {
#[doc = "Register `FIFO` reader"]
pub type R = crate::R<FifoSpec>;
#[doc = "Register `FIFO` writer"]
pub type W = crate::W<FifoSpec>;
#[doc = "Field `DATA` reader - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataR = crate::FieldReader;
#[doc = "Field `DATA` writer - Write to push send data into FIFO. Read to pop received data from FIFO"]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Write to push send data into FIFO. Read to pop received data from FIFO"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<FifoSpec> {
DataW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<FifoSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "FIFO Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoSpec;
impl crate::RegisterSpec for FifoSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fifo::R`](R) reader structure"]
impl crate::Readable for FifoSpec {}
#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"]
impl crate::Writable for FifoSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FIFO to value 0"]
impl crate::Resettable for FifoSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "HPSYS_GPIO"]
pub struct HpsysGpio {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for HpsysGpio {}
impl HpsysGpio {
#[doc = r"Pointer to the register block"]
pub const PTR: *const hpsys_gpio::RegisterBlock = 0x500a_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const hpsys_gpio::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for HpsysGpio {
type Target = hpsys_gpio::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for HpsysGpio {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HpsysGpio").finish()
}
}
#[doc = "HPSYS_GPIO"]
pub mod hpsys_gpio {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
dir0: Dir0,
dor0: Dor0,
dosr0: Dosr0,
docr0: Docr0,
doer0: Doer0,
doesr0: Doesr0,
doecr0: Doecr0,
ier0: Ier0,
iesr0: Iesr0,
iecr0: Iecr0,
itr0: Itr0,
itsr0: Itsr0,
itcr0: Itcr0,
iphr0: Iphr0,
iphsr0: Iphsr0,
iphcr0: Iphcr0,
iplr0: Iplr0,
iplsr0: Iplsr0,
iplcr0: Iplcr0,
isr0: Isr0,
rsvd3: Rsvd3,
_reserved21: [u8; 0x0c],
oemr0: Oemr0,
oemsr0: Oemsr0,
oemcr0: Oemcr0,
rsvd2: Rsvd2,
_reserved25: [u8; 0x10],
dir1: Dir1,
dor1: Dor1,
dosr1: Dosr1,
docr1: Docr1,
doer1: Doer1,
doesr1: Doesr1,
doecr1: Doecr1,
ier1: Ier1,
iesr1: Iesr1,
iecr1: Iecr1,
itr1: Itr1,
itsr1: Itsr1,
itcr1: Itcr1,
iphr1: Iphr1,
iphsr1: Iphsr1,
iphcr1: Iphcr1,
iplr1: Iplr1,
iplsr1: Iplsr1,
iplcr1: Iplcr1,
isr1: Isr1,
rsvd1: Rsvd1,
_reserved46: [u8; 0x0c],
oemr1: Oemr1,
oemsr1: Oemsr1,
oemcr1: Oemcr1,
}
impl RegisterBlock {
#[doc = "0x00 - Data Input Register"]
#[inline(always)]
pub const fn dir0(&self) -> &Dir0 {
&self.dir0
}
#[doc = "0x04 - Data Output Register"]
#[inline(always)]
pub const fn dor0(&self) -> &Dor0 {
&self.dor0
}
#[doc = "0x08 - Data Output Set Register"]
#[inline(always)]
pub const fn dosr0(&self) -> &Dosr0 {
&self.dosr0
}
#[doc = "0x0c - Data Output Clear Register"]
#[inline(always)]
pub const fn docr0(&self) -> &Docr0 {
&self.docr0
}
#[doc = "0x10 - Data Output Enable Register"]
#[inline(always)]
pub const fn doer0(&self) -> &Doer0 {
&self.doer0
}
#[doc = "0x14 - Data Output Enable Set Register"]
#[inline(always)]
pub const fn doesr0(&self) -> &Doesr0 {
&self.doesr0
}
#[doc = "0x18 - Data Output Enable Clear Register"]
#[inline(always)]
pub const fn doecr0(&self) -> &Doecr0 {
&self.doecr0
}
#[doc = "0x1c - Interrupt Enable Register"]
#[inline(always)]
pub const fn ier0(&self) -> &Ier0 {
&self.ier0
}
#[doc = "0x20 - Interrupt Enable Set Register"]
#[inline(always)]
pub const fn iesr0(&self) -> &Iesr0 {
&self.iesr0
}
#[doc = "0x24 - Interrupt Enable Clear Register"]
#[inline(always)]
pub const fn iecr0(&self) -> &Iecr0 {
&self.iecr0
}
#[doc = "0x28 - Interrupt Type Register"]
#[inline(always)]
pub const fn itr0(&self) -> &Itr0 {
&self.itr0
}
#[doc = "0x2c - Interrupt Type Set Register"]
#[inline(always)]
pub const fn itsr0(&self) -> &Itsr0 {
&self.itsr0
}
#[doc = "0x30 - Interrupt Type Clear Register"]
#[inline(always)]
pub const fn itcr0(&self) -> &Itcr0 {
&self.itcr0
}
#[doc = "0x34 - Interrupt Polarity High Register"]
#[inline(always)]
pub const fn iphr0(&self) -> &Iphr0 {
&self.iphr0
}
#[doc = "0x38 - Interrupt Polarity High Set Register"]
#[inline(always)]
pub const fn iphsr0(&self) -> &Iphsr0 {
&self.iphsr0
}
#[doc = "0x3c - Interrupt Polarity High Clear Register"]
#[inline(always)]
pub const fn iphcr0(&self) -> &Iphcr0 {
&self.iphcr0
}
#[doc = "0x40 - Interrupt Polarity Low Register"]
#[inline(always)]
pub const fn iplr0(&self) -> &Iplr0 {
&self.iplr0
}
#[doc = "0x44 - Interrupt Polarity Low Set Register"]
#[inline(always)]
pub const fn iplsr0(&self) -> &Iplsr0 {
&self.iplsr0
}
#[doc = "0x48 - Interrupt Polarity Low Clear Register"]
#[inline(always)]
pub const fn iplcr0(&self) -> &Iplcr0 {
&self.iplcr0
}
#[doc = "0x4c - Interrupt Status Register"]
#[inline(always)]
pub const fn isr0(&self) -> &Isr0 {
&self.isr0
}
#[doc = "0x50 - "]
#[inline(always)]
pub const fn rsvd3(&self) -> &Rsvd3 {
&self.rsvd3
}
#[doc = "0x60 - output mode Register"]
#[inline(always)]
pub const fn oemr0(&self) -> &Oemr0 {
&self.oemr0
}
#[doc = "0x64 - output mode Set Register"]
#[inline(always)]
pub const fn oemsr0(&self) -> &Oemsr0 {
&self.oemsr0
}
#[doc = "0x68 - output mode Clear Register"]
#[inline(always)]
pub const fn oemcr0(&self) -> &Oemcr0 {
&self.oemcr0
}
#[doc = "0x6c - "]
#[inline(always)]
pub const fn rsvd2(&self) -> &Rsvd2 {
&self.rsvd2
}
#[doc = "0x80 - Data Input Register"]
#[inline(always)]
pub const fn dir1(&self) -> &Dir1 {
&self.dir1
}
#[doc = "0x84 - Data Output Register"]
#[inline(always)]
pub const fn dor1(&self) -> &Dor1 {
&self.dor1
}
#[doc = "0x88 - Data Output Set Register"]
#[inline(always)]
pub const fn dosr1(&self) -> &Dosr1 {
&self.dosr1
}
#[doc = "0x8c - Data Output Clear Register"]
#[inline(always)]
pub const fn docr1(&self) -> &Docr1 {
&self.docr1
}
#[doc = "0x90 - Data Output Enable Register"]
#[inline(always)]
pub const fn doer1(&self) -> &Doer1 {
&self.doer1
}
#[doc = "0x94 - Data Output Enable Set Register"]
#[inline(always)]
pub const fn doesr1(&self) -> &Doesr1 {
&self.doesr1
}
#[doc = "0x98 - Data Output Enable Clear Register"]
#[inline(always)]
pub const fn doecr1(&self) -> &Doecr1 {
&self.doecr1
}
#[doc = "0x9c - Interrupt Enable Register"]
#[inline(always)]
pub const fn ier1(&self) -> &Ier1 {
&self.ier1
}
#[doc = "0xa0 - Interrupt Enable Set Register"]
#[inline(always)]
pub const fn iesr1(&self) -> &Iesr1 {
&self.iesr1
}
#[doc = "0xa4 - Interrupt Enable Clear Register"]
#[inline(always)]
pub const fn iecr1(&self) -> &Iecr1 {
&self.iecr1
}
#[doc = "0xa8 - Interrupt Type Register"]
#[inline(always)]
pub const fn itr1(&self) -> &Itr1 {
&self.itr1
}
#[doc = "0xac - Interrupt Type Set Register"]
#[inline(always)]
pub const fn itsr1(&self) -> &Itsr1 {
&self.itsr1
}
#[doc = "0xb0 - Interrupt Type Clear Register"]
#[inline(always)]
pub const fn itcr1(&self) -> &Itcr1 {
&self.itcr1
}
#[doc = "0xb4 - Interrupt Polarity High Register"]
#[inline(always)]
pub const fn iphr1(&self) -> &Iphr1 {
&self.iphr1
}
#[doc = "0xb8 - Interrupt Polarity High Set Register"]
#[inline(always)]
pub const fn iphsr1(&self) -> &Iphsr1 {
&self.iphsr1
}
#[doc = "0xbc - Interrupt Polarity High Clear Register"]
#[inline(always)]
pub const fn iphcr1(&self) -> &Iphcr1 {
&self.iphcr1
}
#[doc = "0xc0 - Interrupt Polarity Low Register"]
#[inline(always)]
pub const fn iplr1(&self) -> &Iplr1 {
&self.iplr1
}
#[doc = "0xc4 - Interrupt Polarity Low Set Register"]
#[inline(always)]
pub const fn iplsr1(&self) -> &Iplsr1 {
&self.iplsr1
}
#[doc = "0xc8 - Interrupt Polarity Low Clear Register"]
#[inline(always)]
pub const fn iplcr1(&self) -> &Iplcr1 {
&self.iplcr1
}
#[doc = "0xcc - Interrupt Status Register"]
#[inline(always)]
pub const fn isr1(&self) -> &Isr1 {
&self.isr1
}
#[doc = "0xd0 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0xe0 - output mode Register"]
#[inline(always)]
pub const fn oemr1(&self) -> &Oemr1 {
&self.oemr1
}
#[doc = "0xe4 - output mode Set Register"]
#[inline(always)]
pub const fn oemsr1(&self) -> &Oemsr1 {
&self.oemsr1
}
#[doc = "0xe8 - output mode Clear Register"]
#[inline(always)]
pub const fn oemcr1(&self) -> &Oemcr1 {
&self.oemcr1
}
}
#[doc = "DIR0 (rw) register accessor: Data Input Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dir0`]
module"]
#[doc(alias = "DIR0")]
pub type Dir0 = crate::Reg<dir0::Dir0Spec>;
#[doc = "Data Input Register"]
pub mod dir0 {
#[doc = "Register `DIR0` reader"]
pub type R = crate::R<Dir0Spec>;
#[doc = "Register `DIR0` writer"]
pub type W = crate::W<Dir0Spec>;
#[doc = "Field `IN` reader - GPIO\\[31:0\\]
input value"]
pub type InR = crate::FieldReader<u32>;
#[doc = "Field `IN` writer - GPIO\\[31:0\\]
input value"]
pub type InW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
input value"]
#[inline(always)]
pub fn in_(&self) -> InR {
InR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
input value"]
#[inline(always)]
#[must_use]
pub fn in_(&mut self) -> InW<Dir0Spec> {
InW::new(self, 0)
}
}
#[doc = "Data Input Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dir0Spec;
impl crate::RegisterSpec for Dir0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dir0::R`](R) reader structure"]
impl crate::Readable for Dir0Spec {}
#[doc = "`write(|w| ..)` method takes [`dir0::W`](W) writer structure"]
impl crate::Writable for Dir0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIR0 to value 0"]
impl crate::Resettable for Dir0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOR0 (rw) register accessor: Data Output Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dor0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dor0`]
module"]
#[doc(alias = "DOR0")]
pub type Dor0 = crate::Reg<dor0::Dor0Spec>;
#[doc = "Data Output Register"]
pub mod dor0 {
#[doc = "Register `DOR0` reader"]
pub type R = crate::R<Dor0Spec>;
#[doc = "Register `DOR0` writer"]
pub type W = crate::W<Dor0Spec>;
#[doc = "Field `OUT` reader - GPIO\\[31:0\\]
output value if output enabled"]
pub type OutR = crate::FieldReader<u32>;
#[doc = "Field `OUT` writer - GPIO\\[31:0\\]
output value if output enabled"]
pub type OutW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
output value if output enabled"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
output value if output enabled"]
#[inline(always)]
#[must_use]
pub fn out(&mut self) -> OutW<Dor0Spec> {
OutW::new(self, 0)
}
}
#[doc = "Data Output Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dor0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dor0Spec;
impl crate::RegisterSpec for Dor0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dor0::R`](R) reader structure"]
impl crate::Readable for Dor0Spec {}
#[doc = "`write(|w| ..)` method takes [`dor0::W`](W) writer structure"]
impl crate::Writable for Dor0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOR0 to value 0"]
impl crate::Resettable for Dor0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOSR0 (rw) register accessor: Data Output Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dosr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dosr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dosr0`]
module"]
#[doc(alias = "DOSR0")]
pub type Dosr0 = crate::Reg<dosr0::Dosr0Spec>;
#[doc = "Data Output Set Register"]
pub mod dosr0 {
#[doc = "Register `DOSR0` reader"]
pub type R = crate::R<Dosr0Spec>;
#[doc = "Register `DOSR0` writer"]
pub type W = crate::W<Dosr0Spec>;
#[doc = "Field `DOS` reader - set 1 to pull up output of corresponding GPIO\\[31:0\\]"]
pub type DosR = crate::FieldReader<u32>;
#[doc = "Field `DOS` writer - set 1 to pull up output of corresponding GPIO\\[31:0\\]"]
pub type DosW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 to pull up output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn dos(&self) -> DosR {
DosR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 to pull up output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn dos(&mut self) -> DosW<Dosr0Spec> {
DosW::new(self, 0)
}
}
#[doc = "Data Output Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dosr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dosr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dosr0Spec;
impl crate::RegisterSpec for Dosr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dosr0::R`](R) reader structure"]
impl crate::Readable for Dosr0Spec {}
#[doc = "`write(|w| ..)` method takes [`dosr0::W`](W) writer structure"]
impl crate::Writable for Dosr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOSR0 to value 0"]
impl crate::Resettable for Dosr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOCR0 (rw) register accessor: Data Output Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`docr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`docr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@docr0`]
module"]
#[doc(alias = "DOCR0")]
pub type Docr0 = crate::Reg<docr0::Docr0Spec>;
#[doc = "Data Output Clear Register"]
pub mod docr0 {
#[doc = "Register `DOCR0` reader"]
pub type R = crate::R<Docr0Spec>;
#[doc = "Register `DOCR0` writer"]
pub type W = crate::W<Docr0Spec>;
#[doc = "Field `DOC` reader - set 1 to pull down output of corresponding GPIO\\[31:0\\]"]
pub type DocR = crate::FieldReader<u32>;
#[doc = "Field `DOC` writer - set 1 to pull down output of corresponding GPIO\\[31:0\\]"]
pub type DocW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 to pull down output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn doc(&self) -> DocR {
DocR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 to pull down output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn doc(&mut self) -> DocW<Docr0Spec> {
DocW::new(self, 0)
}
}
#[doc = "Data Output Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`docr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`docr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Docr0Spec;
impl crate::RegisterSpec for Docr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`docr0::R`](R) reader structure"]
impl crate::Readable for Docr0Spec {}
#[doc = "`write(|w| ..)` method takes [`docr0::W`](W) writer structure"]
impl crate::Writable for Docr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOCR0 to value 0"]
impl crate::Resettable for Docr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOER0 (rw) register accessor: Data Output Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doer0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doer0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doer0`]
module"]
#[doc(alias = "DOER0")]
pub type Doer0 = crate::Reg<doer0::Doer0Spec>;
#[doc = "Data Output Enable Register"]
pub mod doer0 {
#[doc = "Register `DOER0` reader"]
pub type R = crate::R<Doer0Spec>;
#[doc = "Register `DOER0` writer"]
pub type W = crate::W<Doer0Spec>;
#[doc = "Field `DOE` reader - GPIO\\[31:0\\]
output enable"]
pub type DoeR = crate::FieldReader<u32>;
#[doc = "Field `DOE` writer - GPIO\\[31:0\\]
output enable"]
pub type DoeW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
output enable"]
#[inline(always)]
pub fn doe(&self) -> DoeR {
DoeR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
output enable"]
#[inline(always)]
#[must_use]
pub fn doe(&mut self) -> DoeW<Doer0Spec> {
DoeW::new(self, 0)
}
}
#[doc = "Data Output Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doer0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doer0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Doer0Spec;
impl crate::RegisterSpec for Doer0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`doer0::R`](R) reader structure"]
impl crate::Readable for Doer0Spec {}
#[doc = "`write(|w| ..)` method takes [`doer0::W`](W) writer structure"]
impl crate::Writable for Doer0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOER0 to value 0"]
impl crate::Resettable for Doer0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOESR0 (rw) register accessor: Data Output Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doesr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doesr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doesr0`]
module"]
#[doc(alias = "DOESR0")]
pub type Doesr0 = crate::Reg<doesr0::Doesr0Spec>;
#[doc = "Data Output Enable Set Register"]
pub mod doesr0 {
#[doc = "Register `DOESR0` reader"]
pub type R = crate::R<Doesr0Spec>;
#[doc = "Register `DOESR0` writer"]
pub type W = crate::W<Doesr0Spec>;
#[doc = "Field `DOES` reader - set 1 to enable output of corresponding GPIO\\[31:0\\]"]
pub type DoesR = crate::FieldReader<u32>;
#[doc = "Field `DOES` writer - set 1 to enable output of corresponding GPIO\\[31:0\\]"]
pub type DoesW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 to enable output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn does(&self) -> DoesR {
DoesR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 to enable output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn does(&mut self) -> DoesW<Doesr0Spec> {
DoesW::new(self, 0)
}
}
#[doc = "Data Output Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doesr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doesr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Doesr0Spec;
impl crate::RegisterSpec for Doesr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`doesr0::R`](R) reader structure"]
impl crate::Readable for Doesr0Spec {}
#[doc = "`write(|w| ..)` method takes [`doesr0::W`](W) writer structure"]
impl crate::Writable for Doesr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOESR0 to value 0"]
impl crate::Resettable for Doesr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOECR0 (rw) register accessor: Data Output Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doecr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doecr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doecr0`]
module"]
#[doc(alias = "DOECR0")]
pub type Doecr0 = crate::Reg<doecr0::Doecr0Spec>;
#[doc = "Data Output Enable Clear Register"]
pub mod doecr0 {
#[doc = "Register `DOECR0` reader"]
pub type R = crate::R<Doecr0Spec>;
#[doc = "Register `DOECR0` writer"]
pub type W = crate::W<Doecr0Spec>;
#[doc = "Field `DOEC` reader - set 1 to disable output of corresponding GPIO\\[31:0\\]"]
pub type DoecR = crate::FieldReader<u32>;
#[doc = "Field `DOEC` writer - set 1 to disable output of corresponding GPIO\\[31:0\\]"]
pub type DoecW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 to disable output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn doec(&self) -> DoecR {
DoecR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 to disable output of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn doec(&mut self) -> DoecW<Doecr0Spec> {
DoecW::new(self, 0)
}
}
#[doc = "Data Output Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doecr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doecr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Doecr0Spec;
impl crate::RegisterSpec for Doecr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`doecr0::R`](R) reader structure"]
impl crate::Readable for Doecr0Spec {}
#[doc = "`write(|w| ..)` method takes [`doecr0::W`](W) writer structure"]
impl crate::Writable for Doecr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOECR0 to value 0"]
impl crate::Resettable for Doecr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER0 (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier0`]
module"]
#[doc(alias = "IER0")]
pub type Ier0 = crate::Reg<ier0::Ier0Spec>;
#[doc = "Interrupt Enable Register"]
pub mod ier0 {
#[doc = "Register `IER0` reader"]
pub type R = crate::R<Ier0Spec>;
#[doc = "Register `IER0` writer"]
pub type W = crate::W<Ier0Spec>;
#[doc = "Field `IER` reader - GPIO\\[31:0\\]
interrupt enable"]
pub type IerR = crate::FieldReader<u32>;
#[doc = "Field `IER` writer - GPIO\\[31:0\\]
interrupt enable"]
pub type IerW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
interrupt enable"]
#[inline(always)]
pub fn ier(&self) -> IerR {
IerR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
interrupt enable"]
#[inline(always)]
#[must_use]
pub fn ier(&mut self) -> IerW<Ier0Spec> {
IerW::new(self, 0)
}
}
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ier0Spec;
impl crate::RegisterSpec for Ier0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier0::R`](R) reader structure"]
impl crate::Readable for Ier0Spec {}
#[doc = "`write(|w| ..)` method takes [`ier0::W`](W) writer structure"]
impl crate::Writable for Ier0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER0 to value 0"]
impl crate::Resettable for Ier0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IESR0 (rw) register accessor: Interrupt Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iesr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iesr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesr0`]
module"]
#[doc(alias = "IESR0")]
pub type Iesr0 = crate::Reg<iesr0::Iesr0Spec>;
#[doc = "Interrupt Enable Set Register"]
pub mod iesr0 {
#[doc = "Register `IESR0` reader"]
pub type R = crate::R<Iesr0Spec>;
#[doc = "Register `IESR0` writer"]
pub type W = crate::W<Iesr0Spec>;
#[doc = "Field `IES` reader - set 1 to enable interrupt of corresponding GPIO\\[31:0\\]"]
pub type IesR = crate::FieldReader<u32>;
#[doc = "Field `IES` writer - set 1 to enable interrupt of corresponding GPIO\\[31:0\\]"]
pub type IesW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 to enable interrupt of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn ies(&self) -> IesR {
IesR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 to enable interrupt of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn ies(&mut self) -> IesW<Iesr0Spec> {
IesW::new(self, 0)
}
}
#[doc = "Interrupt Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iesr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iesr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iesr0Spec;
impl crate::RegisterSpec for Iesr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iesr0::R`](R) reader structure"]
impl crate::Readable for Iesr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iesr0::W`](W) writer structure"]
impl crate::Writable for Iesr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IESR0 to value 0"]
impl crate::Resettable for Iesr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IECR0 (rw) register accessor: Interrupt Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iecr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iecr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecr0`]
module"]
#[doc(alias = "IECR0")]
pub type Iecr0 = crate::Reg<iecr0::Iecr0Spec>;
#[doc = "Interrupt Enable Clear Register"]
pub mod iecr0 {
#[doc = "Register `IECR0` reader"]
pub type R = crate::R<Iecr0Spec>;
#[doc = "Register `IECR0` writer"]
pub type W = crate::W<Iecr0Spec>;
#[doc = "Field `IEC` reader - set 1 to disable interrupt of corresponding GPIO\\[31:0\\]"]
pub type IecR = crate::FieldReader<u32>;
#[doc = "Field `IEC` writer - set 1 to disable interrupt of corresponding GPIO\\[31:0\\]"]
pub type IecW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 to disable interrupt of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn iec(&self) -> IecR {
IecR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 to disable interrupt of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn iec(&mut self) -> IecW<Iecr0Spec> {
IecW::new(self, 0)
}
}
#[doc = "Interrupt Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iecr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iecr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iecr0Spec;
impl crate::RegisterSpec for Iecr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iecr0::R`](R) reader structure"]
impl crate::Readable for Iecr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iecr0::W`](W) writer structure"]
impl crate::Writable for Iecr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IECR0 to value 0"]
impl crate::Resettable for Iecr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ITR0 (rw) register accessor: Interrupt Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@itr0`]
module"]
#[doc(alias = "ITR0")]
pub type Itr0 = crate::Reg<itr0::Itr0Spec>;
#[doc = "Interrupt Type Register"]
pub mod itr0 {
#[doc = "Register `ITR0` reader"]
pub type R = crate::R<Itr0Spec>;
#[doc = "Register `ITR0` writer"]
pub type W = crate::W<Itr0Spec>;
#[doc = "Field `ITR` reader - GPIO\\[31:0\\]
interrupt type"]
pub type ItrR = crate::FieldReader<u32>;
#[doc = "Field `ITR` writer - GPIO\\[31:0\\]
interrupt type"]
pub type ItrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
interrupt type"]
#[inline(always)]
pub fn itr(&self) -> ItrR {
ItrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - GPIO\\[31:0\\]
interrupt type"]
#[inline(always)]
#[must_use]
pub fn itr(&mut self) -> ItrW<Itr0Spec> {
ItrW::new(self, 0)
}
}
#[doc = "Interrupt Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Itr0Spec;
impl crate::RegisterSpec for Itr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`itr0::R`](R) reader structure"]
impl crate::Readable for Itr0Spec {}
#[doc = "`write(|w| ..)` method takes [`itr0::W`](W) writer structure"]
impl crate::Writable for Itr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ITR0 to value 0"]
impl crate::Resettable for Itr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ITSR0 (rw) register accessor: Interrupt Type Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itsr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itsr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@itsr0`]
module"]
#[doc(alias = "ITSR0")]
pub type Itsr0 = crate::Reg<itsr0::Itsr0Spec>;
#[doc = "Interrupt Type Set Register"]
pub mod itsr0 {
#[doc = "Register `ITSR0` reader"]
pub type R = crate::R<Itsr0Spec>;
#[doc = "Register `ITSR0` writer"]
pub type W = crate::W<Itsr0Spec>;
#[doc = "Field `ITS` reader - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
pub type ItsR = crate::FieldReader<u32>;
#[doc = "Field `ITS` writer - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
pub type ItsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn its(&self) -> ItsR {
ItsR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn its(&mut self) -> ItsW<Itsr0Spec> {
ItsW::new(self, 0)
}
}
#[doc = "Interrupt Type Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itsr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itsr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Itsr0Spec;
impl crate::RegisterSpec for Itsr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`itsr0::R`](R) reader structure"]
impl crate::Readable for Itsr0Spec {}
#[doc = "`write(|w| ..)` method takes [`itsr0::W`](W) writer structure"]
impl crate::Writable for Itsr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ITSR0 to value 0"]
impl crate::Resettable for Itsr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ITCR0 (rw) register accessor: Interrupt Type Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itcr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itcr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@itcr0`]
module"]
#[doc(alias = "ITCR0")]
pub type Itcr0 = crate::Reg<itcr0::Itcr0Spec>;
#[doc = "Interrupt Type Clear Register"]
pub mod itcr0 {
#[doc = "Register `ITCR0` reader"]
pub type R = crate::R<Itcr0Spec>;
#[doc = "Register `ITCR0` writer"]
pub type W = crate::W<Itcr0Spec>;
#[doc = "Field `ITC` reader - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
pub type ItcR = crate::FieldReader<u32>;
#[doc = "Field `ITC` writer - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
pub type ItcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn itc(&self) -> ItcR {
ItcR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn itc(&mut self) -> ItcW<Itcr0Spec> {
ItcW::new(self, 0)
}
}
#[doc = "Interrupt Type Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itcr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itcr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Itcr0Spec;
impl crate::RegisterSpec for Itcr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`itcr0::R`](R) reader structure"]
impl crate::Readable for Itcr0Spec {}
#[doc = "`write(|w| ..)` method takes [`itcr0::W`](W) writer structure"]
impl crate::Writable for Itcr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ITCR0 to value 0"]
impl crate::Resettable for Itcr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPHR0 (rw) register accessor: Interrupt Polarity High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iphr0`]
module"]
#[doc(alias = "IPHR0")]
pub type Iphr0 = crate::Reg<iphr0::Iphr0Spec>;
#[doc = "Interrupt Polarity High Register"]
pub mod iphr0 {
#[doc = "Register `IPHR0` reader"]
pub type R = crate::R<Iphr0Spec>;
#[doc = "Register `IPHR0` writer"]
pub type W = crate::W<Iphr0Spec>;
#[doc = "Field `IPH` reader - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IphR = crate::FieldReader<u32>;
#[doc = "Field `IPH` writer - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IphW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn iph(&self) -> IphR {
IphR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn iph(&mut self) -> IphW<Iphr0Spec> {
IphW::new(self, 0)
}
}
#[doc = "Interrupt Polarity High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iphr0Spec;
impl crate::RegisterSpec for Iphr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iphr0::R`](R) reader structure"]
impl crate::Readable for Iphr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iphr0::W`](W) writer structure"]
impl crate::Writable for Iphr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPHR0 to value 0"]
impl crate::Resettable for Iphr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPHSR0 (rw) register accessor: Interrupt Polarity High Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphsr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphsr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iphsr0`]
module"]
#[doc(alias = "IPHSR0")]
pub type Iphsr0 = crate::Reg<iphsr0::Iphsr0Spec>;
#[doc = "Interrupt Polarity High Set Register"]
pub mod iphsr0 {
#[doc = "Register `IPHSR0` reader"]
pub type R = crate::R<Iphsr0Spec>;
#[doc = "Register `IPHSR0` writer"]
pub type W = crate::W<Iphsr0Spec>;
#[doc = "Field `IPHS` reader - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IphsR = crate::FieldReader<u32>;
#[doc = "Field `IPHS` writer - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IphsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn iphs(&self) -> IphsR {
IphsR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn iphs(&mut self) -> IphsW<Iphsr0Spec> {
IphsW::new(self, 0)
}
}
#[doc = "Interrupt Polarity High Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphsr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphsr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iphsr0Spec;
impl crate::RegisterSpec for Iphsr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iphsr0::R`](R) reader structure"]
impl crate::Readable for Iphsr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iphsr0::W`](W) writer structure"]
impl crate::Writable for Iphsr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPHSR0 to value 0"]
impl crate::Resettable for Iphsr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPHCR0 (rw) register accessor: Interrupt Polarity High Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphcr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphcr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iphcr0`]
module"]
#[doc(alias = "IPHCR0")]
pub type Iphcr0 = crate::Reg<iphcr0::Iphcr0Spec>;
#[doc = "Interrupt Polarity High Clear Register"]
pub mod iphcr0 {
#[doc = "Register `IPHCR0` reader"]
pub type R = crate::R<Iphcr0Spec>;
#[doc = "Register `IPHCR0` writer"]
pub type W = crate::W<Iphcr0Spec>;
#[doc = "Field `IPHC` reader - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IphcR = crate::FieldReader<u32>;
#[doc = "Field `IPHC` writer - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IphcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn iphc(&self) -> IphcR {
IphcR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn iphc(&mut self) -> IphcW<Iphcr0Spec> {
IphcW::new(self, 0)
}
}
#[doc = "Interrupt Polarity High Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphcr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphcr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iphcr0Spec;
impl crate::RegisterSpec for Iphcr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iphcr0::R`](R) reader structure"]
impl crate::Readable for Iphcr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iphcr0::W`](W) writer structure"]
impl crate::Writable for Iphcr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPHCR0 to value 0"]
impl crate::Resettable for Iphcr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPLR0 (rw) register accessor: Interrupt Polarity Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iplr0`]
module"]
#[doc(alias = "IPLR0")]
pub type Iplr0 = crate::Reg<iplr0::Iplr0Spec>;
#[doc = "Interrupt Polarity Low Register"]
pub mod iplr0 {
#[doc = "Register `IPLR0` reader"]
pub type R = crate::R<Iplr0Spec>;
#[doc = "Register `IPLR0` writer"]
pub type W = crate::W<Iplr0Spec>;
#[doc = "Field `IPL` reader - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IplR = crate::FieldReader<u32>;
#[doc = "Field `IPL` writer - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IplW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn ipl(&self) -> IplR {
IplR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn ipl(&mut self) -> IplW<Iplr0Spec> {
IplW::new(self, 0)
}
}
#[doc = "Interrupt Polarity Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iplr0Spec;
impl crate::RegisterSpec for Iplr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iplr0::R`](R) reader structure"]
impl crate::Readable for Iplr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iplr0::W`](W) writer structure"]
impl crate::Writable for Iplr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPLR0 to value 0"]
impl crate::Resettable for Iplr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPLSR0 (rw) register accessor: Interrupt Polarity Low Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplsr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplsr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iplsr0`]
module"]
#[doc(alias = "IPLSR0")]
pub type Iplsr0 = crate::Reg<iplsr0::Iplsr0Spec>;
#[doc = "Interrupt Polarity Low Set Register"]
pub mod iplsr0 {
#[doc = "Register `IPLSR0` reader"]
pub type R = crate::R<Iplsr0Spec>;
#[doc = "Register `IPLSR0` writer"]
pub type W = crate::W<Iplsr0Spec>;
#[doc = "Field `IPLS` reader - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IplsR = crate::FieldReader<u32>;
#[doc = "Field `IPLS` writer - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IplsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn ipls(&self) -> IplsR {
IplsR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn ipls(&mut self) -> IplsW<Iplsr0Spec> {
IplsW::new(self, 0)
}
}
#[doc = "Interrupt Polarity Low Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplsr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplsr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iplsr0Spec;
impl crate::RegisterSpec for Iplsr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iplsr0::R`](R) reader structure"]
impl crate::Readable for Iplsr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iplsr0::W`](W) writer structure"]
impl crate::Writable for Iplsr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPLSR0 to value 0"]
impl crate::Resettable for Iplsr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPLCR0 (rw) register accessor: Interrupt Polarity Low Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplcr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplcr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iplcr0`]
module"]
#[doc(alias = "IPLCR0")]
pub type Iplcr0 = crate::Reg<iplcr0::Iplcr0Spec>;
#[doc = "Interrupt Polarity Low Clear Register"]
pub mod iplcr0 {
#[doc = "Register `IPLCR0` reader"]
pub type R = crate::R<Iplcr0Spec>;
#[doc = "Register `IPLCR0` writer"]
pub type W = crate::W<Iplcr0Spec>;
#[doc = "Field `IPLC` reader - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IplcR = crate::FieldReader<u32>;
#[doc = "Field `IPLC` writer - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
pub type IplcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn iplc(&self) -> IplcR {
IplcR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn iplc(&mut self) -> IplcW<Iplcr0Spec> {
IplcW::new(self, 0)
}
}
#[doc = "Interrupt Polarity Low Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplcr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplcr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iplcr0Spec;
impl crate::RegisterSpec for Iplcr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iplcr0::R`](R) reader structure"]
impl crate::Readable for Iplcr0Spec {}
#[doc = "`write(|w| ..)` method takes [`iplcr0::W`](W) writer structure"]
impl crate::Writable for Iplcr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPLCR0 to value 0"]
impl crate::Resettable for Iplcr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR0 (rw) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr0`]
module"]
#[doc(alias = "ISR0")]
pub type Isr0 = crate::Reg<isr0::Isr0Spec>;
#[doc = "Interrupt Status Register"]
pub mod isr0 {
#[doc = "Register `ISR0` reader"]
pub type R = crate::R<Isr0Spec>;
#[doc = "Register `ISR0` writer"]
pub type W = crate::W<Isr0Spec>;
#[doc = "Field `IS` reader - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[31:0\\]"]
pub type IsR = crate::FieldReader<u32>;
#[doc = "Field `IS` writer - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[31:0\\]"]
pub type IsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn is(&self) -> IsR {
IsR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn is(&mut self) -> IsW<Isr0Spec> {
IsW::new(self, 0)
}
}
#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isr0Spec;
impl crate::RegisterSpec for Isr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr0::R`](R) reader structure"]
impl crate::Readable for Isr0Spec {}
#[doc = "`write(|w| ..)` method takes [`isr0::W`](W) writer structure"]
impl crate::Writable for Isr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR0 to value 0"]
impl crate::Resettable for Isr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd3`]
module"]
#[doc(alias = "RSVD3")]
pub type Rsvd3 = crate::Reg<rsvd3::Rsvd3Spec>;
#[doc = ""]
pub mod rsvd3 {
#[doc = "Register `RSVD3` reader"]
pub type R = crate::R<Rsvd3Spec>;
#[doc = "Register `RSVD3` writer"]
pub type W = crate::W<Rsvd3Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd3Spec;
impl crate::RegisterSpec for Rsvd3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd3::R`](R) reader structure"]
impl crate::Readable for Rsvd3Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd3::W`](W) writer structure"]
impl crate::Writable for Rsvd3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD3 to value 0"]
impl crate::Resettable for Rsvd3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OEMR0 (rw) register accessor: output mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oemr0`]
module"]
#[doc(alias = "OEMR0")]
pub type Oemr0 = crate::Reg<oemr0::Oemr0Spec>;
#[doc = "output mode Register"]
pub mod oemr0 {
#[doc = "Register `OEMR0` reader"]
pub type R = crate::R<Oemr0Spec>;
#[doc = "Register `OEMR0` writer"]
pub type W = crate::W<Oemr0Spec>;
#[doc = "Field `OEM` reader - output mode of corresponding GPIO\\[31:0\\]"]
pub type OemR = crate::FieldReader<u32>;
#[doc = "Field `OEM` writer - output mode of corresponding GPIO\\[31:0\\]"]
pub type OemW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - output mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn oem(&self) -> OemR {
OemR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - output mode of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn oem(&mut self) -> OemW<Oemr0Spec> {
OemW::new(self, 0)
}
}
#[doc = "output mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Oemr0Spec;
impl crate::RegisterSpec for Oemr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`oemr0::R`](R) reader structure"]
impl crate::Readable for Oemr0Spec {}
#[doc = "`write(|w| ..)` method takes [`oemr0::W`](W) writer structure"]
impl crate::Writable for Oemr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OEMR0 to value 0"]
impl crate::Resettable for Oemr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OEMSR0 (rw) register accessor: output mode Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemsr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemsr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oemsr0`]
module"]
#[doc(alias = "OEMSR0")]
pub type Oemsr0 = crate::Reg<oemsr0::Oemsr0Spec>;
#[doc = "output mode Set Register"]
pub mod oemsr0 {
#[doc = "Register `OEMSR0` reader"]
pub type R = crate::R<Oemsr0Spec>;
#[doc = "Register `OEMSR0` writer"]
pub type W = crate::W<Oemsr0Spec>;
#[doc = "Field `OEMS` reader - output mode Set of corresponding GPIO\\[31:0\\]"]
pub type OemsR = crate::FieldReader<u32>;
#[doc = "Field `OEMS` writer - output mode Set of corresponding GPIO\\[31:0\\]"]
pub type OemsW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - output mode Set of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn oems(&self) -> OemsR {
OemsR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - output mode Set of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn oems(&mut self) -> OemsW<Oemsr0Spec> {
OemsW::new(self, 0)
}
}
#[doc = "output mode Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemsr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemsr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Oemsr0Spec;
impl crate::RegisterSpec for Oemsr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`oemsr0::R`](R) reader structure"]
impl crate::Readable for Oemsr0Spec {}
#[doc = "`write(|w| ..)` method takes [`oemsr0::W`](W) writer structure"]
impl crate::Writable for Oemsr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OEMSR0 to value 0"]
impl crate::Resettable for Oemsr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OEMCR0 (rw) register accessor: output mode Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemcr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemcr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oemcr0`]
module"]
#[doc(alias = "OEMCR0")]
pub type Oemcr0 = crate::Reg<oemcr0::Oemcr0Spec>;
#[doc = "output mode Clear Register"]
pub mod oemcr0 {
#[doc = "Register `OEMCR0` reader"]
pub type R = crate::R<Oemcr0Spec>;
#[doc = "Register `OEMCR0` writer"]
pub type W = crate::W<Oemcr0Spec>;
#[doc = "Field `OEMC` reader - output mode Clear of corresponding GPIO\\[31:0\\]"]
pub type OemcR = crate::FieldReader<u32>;
#[doc = "Field `OEMC` writer - output mode Clear of corresponding GPIO\\[31:0\\]"]
pub type OemcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - output mode Clear of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
pub fn oemc(&self) -> OemcR {
OemcR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - output mode Clear of corresponding GPIO\\[31:0\\]"]
#[inline(always)]
#[must_use]
pub fn oemc(&mut self) -> OemcW<Oemcr0Spec> {
OemcW::new(self, 0)
}
}
#[doc = "output mode Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemcr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemcr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Oemcr0Spec;
impl crate::RegisterSpec for Oemcr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`oemcr0::R`](R) reader structure"]
impl crate::Readable for Oemcr0Spec {}
#[doc = "`write(|w| ..)` method takes [`oemcr0::W`](W) writer structure"]
impl crate::Writable for Oemcr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OEMCR0 to value 0"]
impl crate::Resettable for Oemcr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd2`]
module"]
#[doc(alias = "RSVD2")]
pub type Rsvd2 = crate::Reg<rsvd2::Rsvd2Spec>;
#[doc = ""]
pub mod rsvd2 {
#[doc = "Register `RSVD2` reader"]
pub type R = crate::R<Rsvd2Spec>;
#[doc = "Register `RSVD2` writer"]
pub type W = crate::W<Rsvd2Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd2Spec;
impl crate::RegisterSpec for Rsvd2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd2::R`](R) reader structure"]
impl crate::Readable for Rsvd2Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd2::W`](W) writer structure"]
impl crate::Writable for Rsvd2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD2 to value 0"]
impl crate::Resettable for Rsvd2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DIR1 (rw) register accessor: Data Input Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dir1`]
module"]
#[doc(alias = "DIR1")]
pub type Dir1 = crate::Reg<dir1::Dir1Spec>;
#[doc = "Data Input Register"]
pub mod dir1 {
#[doc = "Register `DIR1` reader"]
pub type R = crate::R<Dir1Spec>;
#[doc = "Register `DIR1` writer"]
pub type W = crate::W<Dir1Spec>;
#[doc = "Field `IN` reader - GPIO\\[44:32\\]
input value"]
pub type InR = crate::FieldReader<u16>;
#[doc = "Field `IN` writer - GPIO\\[44:32\\]
input value"]
pub type InW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
input value"]
#[inline(always)]
pub fn in_(&self) -> InR {
InR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
input value"]
#[inline(always)]
#[must_use]
pub fn in_(&mut self) -> InW<Dir1Spec> {
InW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dir1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Data Input Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dir1Spec;
impl crate::RegisterSpec for Dir1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dir1::R`](R) reader structure"]
impl crate::Readable for Dir1Spec {}
#[doc = "`write(|w| ..)` method takes [`dir1::W`](W) writer structure"]
impl crate::Writable for Dir1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIR1 to value 0"]
impl crate::Resettable for Dir1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOR1 (rw) register accessor: Data Output Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dor1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dor1`]
module"]
#[doc(alias = "DOR1")]
pub type Dor1 = crate::Reg<dor1::Dor1Spec>;
#[doc = "Data Output Register"]
pub mod dor1 {
#[doc = "Register `DOR1` reader"]
pub type R = crate::R<Dor1Spec>;
#[doc = "Register `DOR1` writer"]
pub type W = crate::W<Dor1Spec>;
#[doc = "Field `OUT` reader - GPIO\\[44:32\\]
output value if output enabled"]
pub type OutR = crate::FieldReader<u16>;
#[doc = "Field `OUT` writer - GPIO\\[44:32\\]
output value if output enabled"]
pub type OutW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
output value if output enabled"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
output value if output enabled"]
#[inline(always)]
#[must_use]
pub fn out(&mut self) -> OutW<Dor1Spec> {
OutW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dor1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Data Output Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dor1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dor1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dor1Spec;
impl crate::RegisterSpec for Dor1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dor1::R`](R) reader structure"]
impl crate::Readable for Dor1Spec {}
#[doc = "`write(|w| ..)` method takes [`dor1::W`](W) writer structure"]
impl crate::Writable for Dor1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOR1 to value 0"]
impl crate::Resettable for Dor1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOSR1 (rw) register accessor: Data Output Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dosr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dosr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dosr1`]
module"]
#[doc(alias = "DOSR1")]
pub type Dosr1 = crate::Reg<dosr1::Dosr1Spec>;
#[doc = "Data Output Set Register"]
pub mod dosr1 {
#[doc = "Register `DOSR1` reader"]
pub type R = crate::R<Dosr1Spec>;
#[doc = "Register `DOSR1` writer"]
pub type W = crate::W<Dosr1Spec>;
#[doc = "Field `DOS` reader - set 1 to pull up output of corresponding GPIO\\[44:32\\]"]
pub type DosR = crate::FieldReader<u16>;
#[doc = "Field `DOS` writer - set 1 to pull up output of corresponding GPIO\\[44:32\\]"]
pub type DosW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 to pull up output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn dos(&self) -> DosR {
DosR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 to pull up output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn dos(&mut self) -> DosW<Dosr1Spec> {
DosW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Dosr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Data Output Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dosr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dosr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dosr1Spec;
impl crate::RegisterSpec for Dosr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dosr1::R`](R) reader structure"]
impl crate::Readable for Dosr1Spec {}
#[doc = "`write(|w| ..)` method takes [`dosr1::W`](W) writer structure"]
impl crate::Writable for Dosr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOSR1 to value 0"]
impl crate::Resettable for Dosr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOCR1 (rw) register accessor: Data Output Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`docr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`docr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@docr1`]
module"]
#[doc(alias = "DOCR1")]
pub type Docr1 = crate::Reg<docr1::Docr1Spec>;
#[doc = "Data Output Clear Register"]
pub mod docr1 {
#[doc = "Register `DOCR1` reader"]
pub type R = crate::R<Docr1Spec>;
#[doc = "Register `DOCR1` writer"]
pub type W = crate::W<Docr1Spec>;
#[doc = "Field `DOC` reader - set 1 to pull down output of corresponding GPIO\\[44:32\\]"]
pub type DocR = crate::FieldReader<u16>;
#[doc = "Field `DOC` writer - set 1 to pull down output of corresponding GPIO\\[44:32\\]"]
pub type DocW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 to pull down output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn doc(&self) -> DocR {
DocR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 to pull down output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn doc(&mut self) -> DocW<Docr1Spec> {
DocW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Docr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Data Output Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`docr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`docr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Docr1Spec;
impl crate::RegisterSpec for Docr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`docr1::R`](R) reader structure"]
impl crate::Readable for Docr1Spec {}
#[doc = "`write(|w| ..)` method takes [`docr1::W`](W) writer structure"]
impl crate::Writable for Docr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOCR1 to value 0"]
impl crate::Resettable for Docr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOER1 (rw) register accessor: Data Output Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doer1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doer1`]
module"]
#[doc(alias = "DOER1")]
pub type Doer1 = crate::Reg<doer1::Doer1Spec>;
#[doc = "Data Output Enable Register"]
pub mod doer1 {
#[doc = "Register `DOER1` reader"]
pub type R = crate::R<Doer1Spec>;
#[doc = "Register `DOER1` writer"]
pub type W = crate::W<Doer1Spec>;
#[doc = "Field `DOE` reader - GPIO\\[44:32\\]
output enable"]
pub type DoeR = crate::FieldReader<u16>;
#[doc = "Field `DOE` writer - GPIO\\[44:32\\]
output enable"]
pub type DoeW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
output enable"]
#[inline(always)]
pub fn doe(&self) -> DoeR {
DoeR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
output enable"]
#[inline(always)]
#[must_use]
pub fn doe(&mut self) -> DoeW<Doer1Spec> {
DoeW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Doer1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Data Output Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doer1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doer1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Doer1Spec;
impl crate::RegisterSpec for Doer1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`doer1::R`](R) reader structure"]
impl crate::Readable for Doer1Spec {}
#[doc = "`write(|w| ..)` method takes [`doer1::W`](W) writer structure"]
impl crate::Writable for Doer1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOER1 to value 0"]
impl crate::Resettable for Doer1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOESR1 (rw) register accessor: Data Output Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doesr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doesr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doesr1`]
module"]
#[doc(alias = "DOESR1")]
pub type Doesr1 = crate::Reg<doesr1::Doesr1Spec>;
#[doc = "Data Output Enable Set Register"]
pub mod doesr1 {
#[doc = "Register `DOESR1` reader"]
pub type R = crate::R<Doesr1Spec>;
#[doc = "Register `DOESR1` writer"]
pub type W = crate::W<Doesr1Spec>;
#[doc = "Field `DOES` reader - set 1 to enable output of corresponding GPIO\\[44:32\\]"]
pub type DoesR = crate::FieldReader<u16>;
#[doc = "Field `DOES` writer - set 1 to enable output of corresponding GPIO\\[44:32\\]"]
pub type DoesW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 to enable output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn does(&self) -> DoesR {
DoesR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 to enable output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn does(&mut self) -> DoesW<Doesr1Spec> {
DoesW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Doesr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Data Output Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doesr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doesr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Doesr1Spec;
impl crate::RegisterSpec for Doesr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`doesr1::R`](R) reader structure"]
impl crate::Readable for Doesr1Spec {}
#[doc = "`write(|w| ..)` method takes [`doesr1::W`](W) writer structure"]
impl crate::Writable for Doesr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOESR1 to value 0"]
impl crate::Resettable for Doesr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DOECR1 (rw) register accessor: Data Output Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doecr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doecr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doecr1`]
module"]
#[doc(alias = "DOECR1")]
pub type Doecr1 = crate::Reg<doecr1::Doecr1Spec>;
#[doc = "Data Output Enable Clear Register"]
pub mod doecr1 {
#[doc = "Register `DOECR1` reader"]
pub type R = crate::R<Doecr1Spec>;
#[doc = "Register `DOECR1` writer"]
pub type W = crate::W<Doecr1Spec>;
#[doc = "Field `DOEC` reader - set 1 to disable output of corresponding GPIO\\[44:32\\]"]
pub type DoecR = crate::FieldReader<u16>;
#[doc = "Field `DOEC` writer - set 1 to disable output of corresponding GPIO\\[44:32\\]"]
pub type DoecW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 to disable output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn doec(&self) -> DoecR {
DoecR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 to disable output of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn doec(&mut self) -> DoecW<Doecr1Spec> {
DoecW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Doecr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Data Output Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doecr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doecr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Doecr1Spec;
impl crate::RegisterSpec for Doecr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`doecr1::R`](R) reader structure"]
impl crate::Readable for Doecr1Spec {}
#[doc = "`write(|w| ..)` method takes [`doecr1::W`](W) writer structure"]
impl crate::Writable for Doecr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DOECR1 to value 0"]
impl crate::Resettable for Doecr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER1 (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier1`]
module"]
#[doc(alias = "IER1")]
pub type Ier1 = crate::Reg<ier1::Ier1Spec>;
#[doc = "Interrupt Enable Register"]
pub mod ier1 {
#[doc = "Register `IER1` reader"]
pub type R = crate::R<Ier1Spec>;
#[doc = "Register `IER1` writer"]
pub type W = crate::W<Ier1Spec>;
#[doc = "Field `IER` reader - GPIO\\[44:32\\]
interrupt enable"]
pub type IerR = crate::FieldReader<u16>;
#[doc = "Field `IER` writer - GPIO\\[44:32\\]
interrupt enable"]
pub type IerW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
interrupt enable"]
#[inline(always)]
pub fn ier(&self) -> IerR {
IerR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
interrupt enable"]
#[inline(always)]
#[must_use]
pub fn ier(&mut self) -> IerW<Ier1Spec> {
IerW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ier1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ier1Spec;
impl crate::RegisterSpec for Ier1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier1::R`](R) reader structure"]
impl crate::Readable for Ier1Spec {}
#[doc = "`write(|w| ..)` method takes [`ier1::W`](W) writer structure"]
impl crate::Writable for Ier1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER1 to value 0"]
impl crate::Resettable for Ier1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IESR1 (rw) register accessor: Interrupt Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iesr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iesr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iesr1`]
module"]
#[doc(alias = "IESR1")]
pub type Iesr1 = crate::Reg<iesr1::Iesr1Spec>;
#[doc = "Interrupt Enable Set Register"]
pub mod iesr1 {
#[doc = "Register `IESR1` reader"]
pub type R = crate::R<Iesr1Spec>;
#[doc = "Register `IESR1` writer"]
pub type W = crate::W<Iesr1Spec>;
#[doc = "Field `IES` reader - set 1 to enable interrupt of corresponding GPIO\\[44:32\\]"]
pub type IesR = crate::FieldReader<u16>;
#[doc = "Field `IES` writer - set 1 to enable interrupt of corresponding GPIO\\[44:32\\]"]
pub type IesW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 to enable interrupt of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn ies(&self) -> IesR {
IesR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 to enable interrupt of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn ies(&mut self) -> IesW<Iesr1Spec> {
IesW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iesr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Enable Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iesr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iesr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iesr1Spec;
impl crate::RegisterSpec for Iesr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iesr1::R`](R) reader structure"]
impl crate::Readable for Iesr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iesr1::W`](W) writer structure"]
impl crate::Writable for Iesr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IESR1 to value 0"]
impl crate::Resettable for Iesr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IECR1 (rw) register accessor: Interrupt Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iecr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iecr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iecr1`]
module"]
#[doc(alias = "IECR1")]
pub type Iecr1 = crate::Reg<iecr1::Iecr1Spec>;
#[doc = "Interrupt Enable Clear Register"]
pub mod iecr1 {
#[doc = "Register `IECR1` reader"]
pub type R = crate::R<Iecr1Spec>;
#[doc = "Register `IECR1` writer"]
pub type W = crate::W<Iecr1Spec>;
#[doc = "Field `IEC` reader - set 1 to disable interrupt of corresponding GPIO\\[44:32\\]"]
pub type IecR = crate::FieldReader<u16>;
#[doc = "Field `IEC` writer - set 1 to disable interrupt of corresponding GPIO\\[44:32\\]"]
pub type IecW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 to disable interrupt of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn iec(&self) -> IecR {
IecR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 to disable interrupt of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn iec(&mut self) -> IecW<Iecr1Spec> {
IecW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iecr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Enable Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iecr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iecr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iecr1Spec;
impl crate::RegisterSpec for Iecr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iecr1::R`](R) reader structure"]
impl crate::Readable for Iecr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iecr1::W`](W) writer structure"]
impl crate::Writable for Iecr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IECR1 to value 0"]
impl crate::Resettable for Iecr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ITR1 (rw) register accessor: Interrupt Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@itr1`]
module"]
#[doc(alias = "ITR1")]
pub type Itr1 = crate::Reg<itr1::Itr1Spec>;
#[doc = "Interrupt Type Register"]
pub mod itr1 {
#[doc = "Register `ITR1` reader"]
pub type R = crate::R<Itr1Spec>;
#[doc = "Register `ITR1` writer"]
pub type W = crate::W<Itr1Spec>;
#[doc = "Field `ITR` reader - GPIO\\[44:32\\]
interrupt type"]
pub type ItrR = crate::FieldReader<u16>;
#[doc = "Field `ITR` writer - GPIO\\[44:32\\]
interrupt type"]
pub type ItrW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
interrupt type"]
#[inline(always)]
pub fn itr(&self) -> ItrR {
ItrR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - GPIO\\[44:32\\]
interrupt type"]
#[inline(always)]
#[must_use]
pub fn itr(&mut self) -> ItrW<Itr1Spec> {
ItrW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Itr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Itr1Spec;
impl crate::RegisterSpec for Itr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`itr1::R`](R) reader structure"]
impl crate::Readable for Itr1Spec {}
#[doc = "`write(|w| ..)` method takes [`itr1::W`](W) writer structure"]
impl crate::Writable for Itr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ITR1 to value 0"]
impl crate::Resettable for Itr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ITSR1 (rw) register accessor: Interrupt Type Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itsr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@itsr1`]
module"]
#[doc(alias = "ITSR1")]
pub type Itsr1 = crate::Reg<itsr1::Itsr1Spec>;
#[doc = "Interrupt Type Set Register"]
pub mod itsr1 {
#[doc = "Register `ITSR1` reader"]
pub type R = crate::R<Itsr1Spec>;
#[doc = "Register `ITSR1` writer"]
pub type W = crate::W<Itsr1Spec>;
#[doc = "Field `ITS` reader - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
pub type ItsR = crate::FieldReader<u16>;
#[doc = "Field `ITS` writer - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
pub type ItsW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn its(&self) -> ItsR {
ItsR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 for edge-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn its(&mut self) -> ItsW<Itsr1Spec> {
ItsW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Itsr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Type Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itsr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Itsr1Spec;
impl crate::RegisterSpec for Itsr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`itsr1::R`](R) reader structure"]
impl crate::Readable for Itsr1Spec {}
#[doc = "`write(|w| ..)` method takes [`itsr1::W`](W) writer structure"]
impl crate::Writable for Itsr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ITSR1 to value 0"]
impl crate::Resettable for Itsr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ITCR1 (rw) register accessor: Interrupt Type Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itcr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itcr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@itcr1`]
module"]
#[doc(alias = "ITCR1")]
pub type Itcr1 = crate::Reg<itcr1::Itcr1Spec>;
#[doc = "Interrupt Type Clear Register"]
pub mod itcr1 {
#[doc = "Register `ITCR1` reader"]
pub type R = crate::R<Itcr1Spec>;
#[doc = "Register `ITCR1` writer"]
pub type W = crate::W<Itcr1Spec>;
#[doc = "Field `ITC` reader - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
pub type ItcR = crate::FieldReader<u16>;
#[doc = "Field `ITC` writer - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
pub type ItcW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn itc(&self) -> ItcR {
ItcR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 for level-sensitive interrupt mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn itc(&mut self) -> ItcW<Itcr1Spec> {
ItcW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Itcr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Type Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itcr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itcr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Itcr1Spec;
impl crate::RegisterSpec for Itcr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`itcr1::R`](R) reader structure"]
impl crate::Readable for Itcr1Spec {}
#[doc = "`write(|w| ..)` method takes [`itcr1::W`](W) writer structure"]
impl crate::Writable for Itcr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ITCR1 to value 0"]
impl crate::Resettable for Itcr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPHR1 (rw) register accessor: Interrupt Polarity High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iphr1`]
module"]
#[doc(alias = "IPHR1")]
pub type Iphr1 = crate::Reg<iphr1::Iphr1Spec>;
#[doc = "Interrupt Polarity High Register"]
pub mod iphr1 {
#[doc = "Register `IPHR1` reader"]
pub type R = crate::R<Iphr1Spec>;
#[doc = "Register `IPHR1` writer"]
pub type W = crate::W<Iphr1Spec>;
#[doc = "Field `IPH` reader - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IphR = crate::FieldReader<u16>;
#[doc = "Field `IPH` writer - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IphW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn iph(&self) -> IphR {
IphR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn iph(&mut self) -> IphW<Iphr1Spec> {
IphW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iphr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Polarity High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iphr1Spec;
impl crate::RegisterSpec for Iphr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iphr1::R`](R) reader structure"]
impl crate::Readable for Iphr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iphr1::W`](W) writer structure"]
impl crate::Writable for Iphr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPHR1 to value 0"]
impl crate::Resettable for Iphr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPHSR1 (rw) register accessor: Interrupt Polarity High Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphsr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iphsr1`]
module"]
#[doc(alias = "IPHSR1")]
pub type Iphsr1 = crate::Reg<iphsr1::Iphsr1Spec>;
#[doc = "Interrupt Polarity High Set Register"]
pub mod iphsr1 {
#[doc = "Register `IPHSR1` reader"]
pub type R = crate::R<Iphsr1Spec>;
#[doc = "Register `IPHSR1` writer"]
pub type W = crate::W<Iphsr1Spec>;
#[doc = "Field `IPHS` reader - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IphsR = crate::FieldReader<u16>;
#[doc = "Field `IPHS` writer - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IphsW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn iphs(&self) -> IphsR {
IphsR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn iphs(&mut self) -> IphsW<Iphsr1Spec> {
IphsW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iphsr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Polarity High Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphsr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iphsr1Spec;
impl crate::RegisterSpec for Iphsr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iphsr1::R`](R) reader structure"]
impl crate::Readable for Iphsr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iphsr1::W`](W) writer structure"]
impl crate::Writable for Iphsr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPHSR1 to value 0"]
impl crate::Resettable for Iphsr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPHCR1 (rw) register accessor: Interrupt Polarity High Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphcr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphcr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iphcr1`]
module"]
#[doc(alias = "IPHCR1")]
pub type Iphcr1 = crate::Reg<iphcr1::Iphcr1Spec>;
#[doc = "Interrupt Polarity High Clear Register"]
pub mod iphcr1 {
#[doc = "Register `IPHCR1` reader"]
pub type R = crate::R<Iphcr1Spec>;
#[doc = "Register `IPHCR1` writer"]
pub type W = crate::W<Iphcr1Spec>;
#[doc = "Field `IPHC` reader - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IphcR = crate::FieldReader<u16>;
#[doc = "Field `IPHC` writer - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IphcW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn iphc(&self) -> IphcR {
IphcR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn iphc(&mut self) -> IphcW<Iphcr1Spec> {
IphcW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iphcr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Polarity High Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iphcr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iphcr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iphcr1Spec;
impl crate::RegisterSpec for Iphcr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iphcr1::R`](R) reader structure"]
impl crate::Readable for Iphcr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iphcr1::W`](W) writer structure"]
impl crate::Writable for Iphcr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPHCR1 to value 0"]
impl crate::Resettable for Iphcr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPLR1 (rw) register accessor: Interrupt Polarity Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iplr1`]
module"]
#[doc(alias = "IPLR1")]
pub type Iplr1 = crate::Reg<iplr1::Iplr1Spec>;
#[doc = "Interrupt Polarity Low Register"]
pub mod iplr1 {
#[doc = "Register `IPLR1` reader"]
pub type R = crate::R<Iplr1Spec>;
#[doc = "Register `IPLR1` writer"]
pub type W = crate::W<Iplr1Spec>;
#[doc = "Field `IPL` reader - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IplR = crate::FieldReader<u16>;
#[doc = "Field `IPL` writer - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IplW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn ipl(&self) -> IplR {
IplR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn ipl(&mut self) -> IplW<Iplr1Spec> {
IplW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iplr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Polarity Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iplr1Spec;
impl crate::RegisterSpec for Iplr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iplr1::R`](R) reader structure"]
impl crate::Readable for Iplr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iplr1::W`](W) writer structure"]
impl crate::Writable for Iplr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPLR1 to value 0"]
impl crate::Resettable for Iplr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPLSR1 (rw) register accessor: Interrupt Polarity Low Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplsr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iplsr1`]
module"]
#[doc(alias = "IPLSR1")]
pub type Iplsr1 = crate::Reg<iplsr1::Iplsr1Spec>;
#[doc = "Interrupt Polarity Low Set Register"]
pub mod iplsr1 {
#[doc = "Register `IPLSR1` reader"]
pub type R = crate::R<Iplsr1Spec>;
#[doc = "Register `IPLSR1` writer"]
pub type W = crate::W<Iplsr1Spec>;
#[doc = "Field `IPLS` reader - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IplsR = crate::FieldReader<u16>;
#[doc = "Field `IPLS` writer - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IplsW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn ipls(&self) -> IplsR {
IplsR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn ipls(&mut self) -> IplsW<Iplsr1Spec> {
IplsW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iplsr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Polarity Low Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplsr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iplsr1Spec;
impl crate::RegisterSpec for Iplsr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iplsr1::R`](R) reader structure"]
impl crate::Readable for Iplsr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iplsr1::W`](W) writer structure"]
impl crate::Writable for Iplsr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPLSR1 to value 0"]
impl crate::Resettable for Iplsr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IPLCR1 (rw) register accessor: Interrupt Polarity Low Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplcr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplcr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iplcr1`]
module"]
#[doc(alias = "IPLCR1")]
pub type Iplcr1 = crate::Reg<iplcr1::Iplcr1Spec>;
#[doc = "Interrupt Polarity Low Clear Register"]
pub mod iplcr1 {
#[doc = "Register `IPLCR1` reader"]
pub type R = crate::R<Iplcr1Spec>;
#[doc = "Register `IPLCR1` writer"]
pub type W = crate::W<Iplcr1Spec>;
#[doc = "Field `IPLC` reader - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IplcR = crate::FieldReader<u16>;
#[doc = "Field `IPLC` writer - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
pub type IplcW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn iplc(&self) -> IplcR {
IplcR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn iplc(&mut self) -> IplcW<Iplcr1Spec> {
IplcW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Iplcr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Polarity Low Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iplcr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iplcr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Iplcr1Spec;
impl crate::RegisterSpec for Iplcr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iplcr1::R`](R) reader structure"]
impl crate::Readable for Iplcr1Spec {}
#[doc = "`write(|w| ..)` method takes [`iplcr1::W`](W) writer structure"]
impl crate::Writable for Iplcr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IPLCR1 to value 0"]
impl crate::Resettable for Iplcr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR1 (rw) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr1`]
module"]
#[doc(alias = "ISR1")]
pub type Isr1 = crate::Reg<isr1::Isr1Spec>;
#[doc = "Interrupt Status Register"]
pub mod isr1 {
#[doc = "Register `ISR1` reader"]
pub type R = crate::R<Isr1Spec>;
#[doc = "Register `ISR1` writer"]
pub type W = crate::W<Isr1Spec>;
#[doc = "Field `IS` reader - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[44:32\\]"]
pub type IsR = crate::FieldReader<u16>;
#[doc = "Field `IS` writer - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[44:32\\]"]
pub type IsW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn is(&self) -> IsR {
IsR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - Interrupt status. Write 1 will clear interrupt status of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn is(&mut self) -> IsW<Isr1Spec> {
IsW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Isr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Isr1Spec;
impl crate::RegisterSpec for Isr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr1::R`](R) reader structure"]
impl crate::Readable for Isr1Spec {}
#[doc = "`write(|w| ..)` method takes [`isr1::W`](W) writer structure"]
impl crate::Writable for Isr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR1 to value 0"]
impl crate::Resettable for Isr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OEMR1 (rw) register accessor: output mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oemr1`]
module"]
#[doc(alias = "OEMR1")]
pub type Oemr1 = crate::Reg<oemr1::Oemr1Spec>;
#[doc = "output mode Register"]
pub mod oemr1 {
#[doc = "Register `OEMR1` reader"]
pub type R = crate::R<Oemr1Spec>;
#[doc = "Register `OEMR1` writer"]
pub type W = crate::W<Oemr1Spec>;
#[doc = "Field `OEM` reader - output mode of corresponding GPIO\\[44:32\\]"]
pub type OemR = crate::FieldReader<u16>;
#[doc = "Field `OEM` writer - output mode of corresponding GPIO\\[44:32\\]"]
pub type OemW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - output mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn oem(&self) -> OemR {
OemR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - output mode of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn oem(&mut self) -> OemW<Oemr1Spec> {
OemW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Oemr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "output mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Oemr1Spec;
impl crate::RegisterSpec for Oemr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`oemr1::R`](R) reader structure"]
impl crate::Readable for Oemr1Spec {}
#[doc = "`write(|w| ..)` method takes [`oemr1::W`](W) writer structure"]
impl crate::Writable for Oemr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OEMR1 to value 0"]
impl crate::Resettable for Oemr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OEMSR1 (rw) register accessor: output mode Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemsr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oemsr1`]
module"]
#[doc(alias = "OEMSR1")]
pub type Oemsr1 = crate::Reg<oemsr1::Oemsr1Spec>;
#[doc = "output mode Set Register"]
pub mod oemsr1 {
#[doc = "Register `OEMSR1` reader"]
pub type R = crate::R<Oemsr1Spec>;
#[doc = "Register `OEMSR1` writer"]
pub type W = crate::W<Oemsr1Spec>;
#[doc = "Field `OEMS` reader - output mode Set of corresponding GPIO\\[44:32\\]"]
pub type OemsR = crate::FieldReader<u16>;
#[doc = "Field `OEMS` writer - output mode Set of corresponding GPIO\\[44:32\\]"]
pub type OemsW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - output mode Set of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn oems(&self) -> OemsR {
OemsR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - output mode Set of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn oems(&mut self) -> OemsW<Oemsr1Spec> {
OemsW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Oemsr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "output mode Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemsr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Oemsr1Spec;
impl crate::RegisterSpec for Oemsr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`oemsr1::R`](R) reader structure"]
impl crate::Readable for Oemsr1Spec {}
#[doc = "`write(|w| ..)` method takes [`oemsr1::W`](W) writer structure"]
impl crate::Writable for Oemsr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OEMSR1 to value 0"]
impl crate::Resettable for Oemsr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OEMCR1 (rw) register accessor: output mode Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemcr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemcr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oemcr1`]
module"]
#[doc(alias = "OEMCR1")]
pub type Oemcr1 = crate::Reg<oemcr1::Oemcr1Spec>;
#[doc = "output mode Clear Register"]
pub mod oemcr1 {
#[doc = "Register `OEMCR1` reader"]
pub type R = crate::R<Oemcr1Spec>;
#[doc = "Register `OEMCR1` writer"]
pub type W = crate::W<Oemcr1Spec>;
#[doc = "Field `OEMC` reader - output mode Clear of corresponding GPIO\\[44:32\\]"]
pub type OemcR = crate::FieldReader<u16>;
#[doc = "Field `OEMC` writer - output mode Clear of corresponding GPIO\\[44:32\\]"]
pub type OemcW<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:12 - output mode Clear of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
pub fn oemc(&self) -> OemcR {
OemcR::new((self.bits & 0x1fff) as u16)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bits 0:12 - output mode Clear of corresponding GPIO\\[44:32\\]"]
#[inline(always)]
#[must_use]
pub fn oemc(&mut self) -> OemcW<Oemcr1Spec> {
OemcW::new(self, 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Oemcr1Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "output mode Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oemcr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oemcr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Oemcr1Spec;
impl crate::RegisterSpec for Oemcr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`oemcr1::R`](R) reader structure"]
impl crate::Readable for Oemcr1Spec {}
#[doc = "`write(|w| ..)` method takes [`oemcr1::W`](W) writer structure"]
impl crate::Writable for Oemcr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OEMCR1 to value 0"]
impl crate::Resettable for Oemcr1Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "BTIM2"]
pub struct Btim2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Btim2 {}
impl Btim2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const btim2::RegisterBlock = 0x500b_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const btim2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Btim2 {
type Target = btim2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Btim2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Btim2").finish()
}
}
#[doc = "BTIM2"]
pub mod btim2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
smcr: Smcr,
dier: Dier,
sr: Sr,
egr: Egr,
rsvd1: Rsvd1,
_reserved7: [u8; 0x08],
cnt: Cnt,
psc: Psc,
arr: Arr,
}
impl RegisterBlock {
#[doc = "0x00 - TIM control register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - TIM control register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - TIM slave mode control register"]
#[inline(always)]
pub const fn smcr(&self) -> &Smcr {
&self.smcr
}
#[doc = "0x0c - TIM DMA/Interrupt enable register"]
#[inline(always)]
pub const fn dier(&self) -> &Dier {
&self.dier
}
#[doc = "0x10 - TIM status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Event generation register"]
#[inline(always)]
pub const fn egr(&self) -> &Egr {
&self.egr
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x24 - Counter"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x28 - Prescaler"]
#[inline(always)]
pub const fn psc(&self) -> &Psc {
&self.psc
}
#[doc = "0x2c - Auto-reload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
}
#[doc = "CR1 (rw) register accessor: TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "TIM control register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `CEN` reader - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UDIS` reader - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisR = crate::BitReader;
#[doc = "Field `UDIS` writer - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `URS` reader - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsR = crate::BitReader;
#[doc = "Field `URS` writer - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OPM` reader - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmR = crate::BitReader;
#[doc = "Field `OPM` writer - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ARPE` reader - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeR = crate::BitReader;
#[doc = "Field `ARPE` writer - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
pub fn udis(&self) -> UdisR {
UdisR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
pub fn urs(&self) -> UrsR {
UrsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
pub fn opm(&self) -> OpmR {
OpmR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
pub fn arpe(&self) -> ArpeR {
ArpeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CenW<Cr1Spec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UdisW<Cr1Spec> {
UdisW::new(self, 1)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> UrsW<Cr1Spec> {
UrsW::new(self, 2)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OpmW<Cr1Spec> {
OpmW::new(self, 3)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ArpeW<Cr1Spec> {
ArpeW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "TIM control register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MMS` reader - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsR = crate::FieldReader;
#[doc = "Field `MMS` writer - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
pub fn mms(&self) -> MmsR {
MmsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MmsW<Cr2Spec> {
MmsW::new(self, 4)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 6)
}
}
#[doc = "TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMCR (rw) register accessor: TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcr`]
module"]
#[doc(alias = "SMCR")]
pub type Smcr = crate::Reg<smcr::SmcrSpec>;
#[doc = "TIM slave mode control register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub type R = crate::R<SmcrSpec>;
#[doc = "Register `SMCR` writer"]
pub type W = crate::W<SmcrSpec>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::FieldReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TS` reader - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsR = crate::FieldReader;
#[doc = "Field `TS` writer - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSM` reader - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmR = crate::BitReader;
#[doc = "Field `MSM` writer - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SMS` reader - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsR = crate::FieldReader;
#[doc = "Field `SMS` writer - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GTS` reader - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsR = crate::FieldReader;
#[doc = "Field `GTS` writer - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `GTP` reader - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpR = crate::BitReader;
#[doc = "Field `GTP` writer - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GM` reader - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmR = crate::BitReader;
#[doc = "Field `GM` writer - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn ts(&self) -> TsR {
TsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
pub fn msm(&self) -> MsmR {
MsmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
pub fn sms(&self) -> SmsR {
SmsR::new(((self.bits >> 16) & 7) as u8)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn gts(&self) -> GtsR {
GtsR::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
pub fn gtp(&self) -> GtpR {
GtpR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
pub fn gm(&self) -> GmR {
GmR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<SmcrSpec> {
Rsvd5W::new(self, 0)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TsW<SmcrSpec> {
TsW::new(self, 4)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<SmcrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MsmW<SmcrSpec> {
MsmW::new(self, 7)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<SmcrSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SmsW<SmcrSpec> {
SmsW::new(self, 16)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SmcrSpec> {
Rsvd2W::new(self, 19)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn gts(&mut self) -> GtsW<SmcrSpec> {
GtsW::new(self, 20)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
#[must_use]
pub fn gtp(&mut self) -> GtpW<SmcrSpec> {
GtpW::new(self, 22)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
#[must_use]
pub fn gm(&mut self) -> GmW<SmcrSpec> {
GmW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SmcrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmcrSpec;
impl crate::RegisterSpec for SmcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smcr::R`](R) reader structure"]
impl crate::Readable for SmcrSpec {}
#[doc = "`write(|w| ..)` method takes [`smcr::W`](W) writer structure"]
impl crate::Writable for SmcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SmcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DIER (rw) register accessor: TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dier`]
module"]
#[doc(alias = "DIER")]
pub type Dier = crate::Reg<dier::DierSpec>;
#[doc = "TIM DMA/Interrupt enable register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub type R = crate::R<DierSpec>;
#[doc = "Register `DIER` writer"]
pub type W = crate::W<DierSpec>;
#[doc = "Field `UIE` reader - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieR = crate::BitReader;
#[doc = "Field `UIE` writer - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `UDE` reader - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeR = crate::BitReader;
#[doc = "Field `UDE` writer - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
pub fn uie(&self) -> UieR {
UieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x7f) as u8)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
pub fn ude(&self) -> UdeR {
UdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UieW<DierSpec> {
UieW::new(self, 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DierSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UdeW<DierSpec> {
UdeW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DierSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DierSpec;
impl crate::RegisterSpec for DierSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dier::R`](R) reader structure"]
impl crate::Readable for DierSpec {}
#[doc = "`write(|w| ..)` method takes [`dier::W`](W) writer structure"]
impl crate::Writable for DierSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DierSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "TIM status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `UIF` reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifR = crate::BitReader;
#[doc = "Field `UIF` writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
pub fn uif(&self) -> UifR {
UifR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UifW<SrSpec> {
UifW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EGR (rw) register accessor: Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@egr`]
module"]
#[doc(alias = "EGR")]
pub type Egr = crate::Reg<egr::EgrSpec>;
#[doc = "Event generation register"]
pub mod egr {
#[doc = "Register `EGR` reader"]
pub type R = crate::R<EgrSpec>;
#[doc = "Register `EGR` writer"]
pub type W = crate::W<EgrSpec>;
#[doc = "Field `UG` reader - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgR = crate::BitReader;
#[doc = "Field `UG` writer - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
pub fn ug(&self) -> UgR {
UgR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UgW<EgrSpec> {
UgW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<EgrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EgrSpec;
impl crate::RegisterSpec for EgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`egr::R`](R) reader structure"]
impl crate::Readable for EgrSpec {}
#[doc = "`write(|w| ..)` method takes [`egr::W`](W) writer structure"]
impl crate::Writable for EgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "Counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - counter value"]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - counter value"]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
}
#[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSC (rw) register accessor: Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`]
module"]
#[doc(alias = "PSC")]
pub type Psc = crate::Reg<psc::PscSpec>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub type R = crate::R<PscSpec>;
#[doc = "Register `PSC` writer"]
pub type W = crate::W<PscSpec>;
#[doc = "Field `PSC` reader - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscR = crate::FieldReader<u16>;
#[doc = "Field `PSC` writer - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
pub fn psc(&self) -> PscR {
PscR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PscW<PscSpec> {
PscW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PscSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PscSpec;
impl crate::RegisterSpec for PscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate::Readable for PscSpec {}
#[doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate::Writable for PscSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PscSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "Auto-reload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
}
#[doc = "Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "HPSYS_AON"]
pub struct HpsysAon {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for HpsysAon {}
impl HpsysAon {
#[doc = r"Pointer to the register block"]
pub const PTR: *const hpsys_aon::RegisterBlock = 0x500c_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const hpsys_aon::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for HpsysAon {
type Target = hpsys_aon::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for HpsysAon {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HpsysAon").finish()
}
}
#[doc = "HPSYS_AON"]
pub mod hpsys_aon {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
pmr: Pmr,
cr1: Cr1,
cr2: Cr2,
cr3: Cr3,
acr: Acr,
lscr: Lscr,
dscr: Dscr,
sbcr: Sbcr,
wer: Wer,
wsr: Wsr,
wcr: Wcr,
issr: Issr,
anacr: Anacr,
gtimr: Gtimr,
reserve0: Reserve0,
reserve1: Reserve1,
}
impl RegisterBlock {
#[doc = "0x00 - Power Mode Register"]
#[inline(always)]
pub const fn pmr(&self) -> &Pmr {
&self.pmr
}
#[doc = "0x04 - Control Register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x08 - Control Register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x0c - Control Register 3"]
#[inline(always)]
pub const fn cr3(&self) -> &Cr3 {
&self.cr3
}
#[doc = "0x10 - Active Mode Control register"]
#[inline(always)]
pub const fn acr(&self) -> &Acr {
&self.acr
}
#[doc = "0x14 - Light Sleep Ctrl Register"]
#[inline(always)]
pub const fn lscr(&self) -> &Lscr {
&self.lscr
}
#[doc = "0x18 - Deep Sleep Ctrl Register"]
#[inline(always)]
pub const fn dscr(&self) -> &Dscr {
&self.dscr
}
#[doc = "0x1c - Standby Mode Ctrl Register"]
#[inline(always)]
pub const fn sbcr(&self) -> &Sbcr {
&self.sbcr
}
#[doc = "0x20 - Wakeup Enable register"]
#[inline(always)]
pub const fn wer(&self) -> &Wer {
&self.wer
}
#[doc = "0x24 - Wakeup Status register"]
#[inline(always)]
pub const fn wsr(&self) -> &Wsr {
&self.wsr
}
#[doc = "0x28 - Wakeup Clear register"]
#[inline(always)]
pub const fn wcr(&self) -> &Wcr {
&self.wcr
}
#[doc = "0x2c - Inter System Wakeup Register"]
#[inline(always)]
pub const fn issr(&self) -> &Issr {
&self.issr
}
#[doc = "0x30 - Analog Control Register"]
#[inline(always)]
pub const fn anacr(&self) -> &Anacr {
&self.anacr
}
#[doc = "0x34 - Global Timer Register"]
#[inline(always)]
pub const fn gtimr(&self) -> &Gtimr {
&self.gtimr
}
#[doc = "0x38 - Reserve Register 0"]
#[inline(always)]
pub const fn reserve0(&self) -> &Reserve0 {
&self.reserve0
}
#[doc = "0x3c - Reserve Register 1"]
#[inline(always)]
pub const fn reserve1(&self) -> &Reserve1 {
&self.reserve1
}
}
#[doc = "PMR (rw) register accessor: Power Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmr`]
module"]
#[doc(alias = "PMR")]
pub type Pmr = crate::Reg<pmr::PmrSpec>;
#[doc = "Power Mode Register"]
pub mod pmr {
#[doc = "Register `PMR` reader"]
pub type R = crate::R<PmrSpec>;
#[doc = "Register `PMR` writer"]
pub type W = crate::W<PmrSpec>;
#[doc = "Field `MODE` reader - Power Mode: 2'h0 - active; 2'h1 - light sleep; 2'h2 - deep sleep; 2'h3 - standby"]
pub type ModeR = crate::FieldReader;
#[doc = "Field `MODE` writer - Power Mode: 2'h0 - active; 2'h1 - light sleep; 2'h2 - deep sleep; 2'h3 - standby"]
pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bits 0:1 - Power Mode: 2'h0 - active; 2'h1 - light sleep; 2'h2 - deep sleep; 2'h3 - standby"]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bits 0:1 - Power Mode: 2'h0 - active; 2'h1 - light sleep; 2'h2 - deep sleep; 2'h3 - standby"]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<PmrSpec> {
ModeW::new(self, 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PmrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Power Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PmrSpec;
impl crate::RegisterSpec for PmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pmr::R`](R) reader structure"]
impl crate::Readable for PmrSpec {}
#[doc = "`write(|w| ..)` method takes [`pmr::W`](W) writer structure"]
impl crate::Writable for PmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PMR to value 0"]
impl crate::Resettable for PmrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `PIN0_MODE` reader - mode for wakeup PIN0 (PA24) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
pub type Pin0ModeR = crate::FieldReader;
#[doc = "Field `PIN0_MODE` writer - mode for wakeup PIN0 (PA24) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
pub type Pin0ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN1_MODE` reader - mode for wakeup PIN1 (PA25)"]
pub type Pin1ModeR = crate::FieldReader;
#[doc = "Field `PIN1_MODE` writer - mode for wakeup PIN1 (PA25)"]
pub type Pin1ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN2_MODE` reader - mode for wakeup PIN2 (PA26)"]
pub type Pin2ModeR = crate::FieldReader;
#[doc = "Field `PIN2_MODE` writer - mode for wakeup PIN2 (PA26)"]
pub type Pin2ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN3_MODE` reader - mode for wakeup PIN3 (PA27)"]
pub type Pin3ModeR = crate::FieldReader;
#[doc = "Field `PIN3_MODE` writer - mode for wakeup PIN3 (PA27)"]
pub type Pin3ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
#[doc = "Field `GTIM_EN` reader - Enable global timer"]
pub type GtimEnR = crate::BitReader;
#[doc = "Field `GTIM_EN` writer - Enable global timer"]
pub type GtimEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - mode for wakeup PIN0 (PA24) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
#[inline(always)]
pub fn pin0_mode(&self) -> Pin0ModeR {
Pin0ModeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - mode for wakeup PIN1 (PA25)"]
#[inline(always)]
pub fn pin1_mode(&self) -> Pin1ModeR {
Pin1ModeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:8 - mode for wakeup PIN2 (PA26)"]
#[inline(always)]
pub fn pin2_mode(&self) -> Pin2ModeR {
Pin2ModeR::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bits 9:11 - mode for wakeup PIN3 (PA27)"]
#[inline(always)]
pub fn pin3_mode(&self) -> Pin3ModeR {
Pin3ModeR::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bits 12:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 12) & 0x0007_ffff)
}
#[doc = "Bit 31 - Enable global timer"]
#[inline(always)]
pub fn gtim_en(&self) -> GtimEnR {
GtimEnR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - mode for wakeup PIN0 (PA24) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
#[inline(always)]
#[must_use]
pub fn pin0_mode(&mut self) -> Pin0ModeW<Cr1Spec> {
Pin0ModeW::new(self, 0)
}
#[doc = "Bits 3:5 - mode for wakeup PIN1 (PA25)"]
#[inline(always)]
#[must_use]
pub fn pin1_mode(&mut self) -> Pin1ModeW<Cr1Spec> {
Pin1ModeW::new(self, 3)
}
#[doc = "Bits 6:8 - mode for wakeup PIN2 (PA26)"]
#[inline(always)]
#[must_use]
pub fn pin2_mode(&mut self) -> Pin2ModeW<Cr1Spec> {
Pin2ModeW::new(self, 6)
}
#[doc = "Bits 9:11 - mode for wakeup PIN3 (PA27)"]
#[inline(always)]
#[must_use]
pub fn pin3_mode(&mut self) -> Pin3ModeW<Cr1Spec> {
Pin3ModeW::new(self, 9)
}
#[doc = "Bits 12:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 12)
}
#[doc = "Bit 31 - Enable global timer"]
#[inline(always)]
#[must_use]
pub fn gtim_en(&mut self) -> GtimEnW<Cr1Spec> {
GtimEnW::new(self, 31)
}
}
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `PIN10_MODE` reader - mode for wakeup PIN10 (PA34) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
pub type Pin10ModeR = crate::FieldReader;
#[doc = "Field `PIN10_MODE` writer - mode for wakeup PIN10 (PA34) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
pub type Pin10ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN11_MODE` reader - mode for wakeup PIN11 (PA35)"]
pub type Pin11ModeR = crate::FieldReader;
#[doc = "Field `PIN11_MODE` writer - mode for wakeup PIN11 (PA35)"]
pub type Pin11ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN12_MODE` reader - mode for wakeup PIN12 (PA36)"]
pub type Pin12ModeR = crate::FieldReader;
#[doc = "Field `PIN12_MODE` writer - mode for wakeup PIN12 (PA36)"]
pub type Pin12ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN13_MODE` reader - mode for wakeup PIN13 (PA37)"]
pub type Pin13ModeR = crate::FieldReader;
#[doc = "Field `PIN13_MODE` writer - mode for wakeup PIN13 (PA37)"]
pub type Pin13ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN14_MODE` reader - mode for wakeup PIN14 (PA38)"]
pub type Pin14ModeR = crate::FieldReader;
#[doc = "Field `PIN14_MODE` writer - mode for wakeup PIN14 (PA38)"]
pub type Pin14ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN15_MODE` reader - mode for wakeup PIN15 (PA39)"]
pub type Pin15ModeR = crate::FieldReader;
#[doc = "Field `PIN15_MODE` writer - mode for wakeup PIN15 (PA39)"]
pub type Pin15ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:8 - mode for wakeup PIN10 (PA34) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
#[inline(always)]
pub fn pin10_mode(&self) -> Pin10ModeR {
Pin10ModeR::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bits 9:11 - mode for wakeup PIN11 (PA35)"]
#[inline(always)]
pub fn pin11_mode(&self) -> Pin11ModeR {
Pin11ModeR::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bits 12:14 - mode for wakeup PIN12 (PA36)"]
#[inline(always)]
pub fn pin12_mode(&self) -> Pin12ModeR {
Pin12ModeR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:17 - mode for wakeup PIN13 (PA37)"]
#[inline(always)]
pub fn pin13_mode(&self) -> Pin13ModeR {
Pin13ModeR::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:20 - mode for wakeup PIN14 (PA38)"]
#[inline(always)]
pub fn pin14_mode(&self) -> Pin14ModeR {
Pin14ModeR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:23 - mode for wakeup PIN15 (PA39)"]
#[inline(always)]
pub fn pin15_mode(&self) -> Pin15ModeR {
Pin15ModeR::new(((self.bits >> 21) & 7) as u8)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 6:8 - mode for wakeup PIN10 (PA34) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
#[inline(always)]
#[must_use]
pub fn pin10_mode(&mut self) -> Pin10ModeW<Cr2Spec> {
Pin10ModeW::new(self, 6)
}
#[doc = "Bits 9:11 - mode for wakeup PIN11 (PA35)"]
#[inline(always)]
#[must_use]
pub fn pin11_mode(&mut self) -> Pin11ModeW<Cr2Spec> {
Pin11ModeW::new(self, 9)
}
#[doc = "Bits 12:14 - mode for wakeup PIN12 (PA36)"]
#[inline(always)]
#[must_use]
pub fn pin12_mode(&mut self) -> Pin12ModeW<Cr2Spec> {
Pin12ModeW::new(self, 12)
}
#[doc = "Bits 15:17 - mode for wakeup PIN13 (PA37)"]
#[inline(always)]
#[must_use]
pub fn pin13_mode(&mut self) -> Pin13ModeW<Cr2Spec> {
Pin13ModeW::new(self, 15)
}
#[doc = "Bits 18:20 - mode for wakeup PIN14 (PA38)"]
#[inline(always)]
#[must_use]
pub fn pin14_mode(&mut self) -> Pin14ModeW<Cr2Spec> {
Pin14ModeW::new(self, 18)
}
#[doc = "Bits 21:23 - mode for wakeup PIN15 (PA39)"]
#[inline(always)]
#[must_use]
pub fn pin15_mode(&mut self) -> Pin15ModeW<Cr2Spec> {
Pin15ModeW::new(self, 21)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 24)
}
}
#[doc = "Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR3 (rw) register accessor: Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr3`]
module"]
#[doc(alias = "CR3")]
pub type Cr3 = crate::Reg<cr3::Cr3Spec>;
#[doc = "Control Register 3"]
pub mod cr3 {
#[doc = "Register `CR3` reader"]
pub type R = crate::R<Cr3Spec>;
#[doc = "Register `CR3` writer"]
pub type W = crate::W<Cr3Spec>;
#[doc = "Field `PIN16_MODE` reader - mode for wakeup PIN16 (PA40) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
pub type Pin16ModeR = crate::FieldReader;
#[doc = "Field `PIN16_MODE` writer - mode for wakeup PIN16 (PA40) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
pub type Pin16ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN17_MODE` reader - mode for wakeup PIN17 (PA41)"]
pub type Pin17ModeR = crate::FieldReader;
#[doc = "Field `PIN17_MODE` writer - mode for wakeup PIN17 (PA41)"]
pub type Pin17ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN18_MODE` reader - mode for wakeup PIN18 (PA42)"]
pub type Pin18ModeR = crate::FieldReader;
#[doc = "Field `PIN18_MODE` writer - mode for wakeup PIN18 (PA42)"]
pub type Pin18ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN19_MODE` reader - mode for wakeup PIN19 (PA43)"]
pub type Pin19ModeR = crate::FieldReader;
#[doc = "Field `PIN19_MODE` writer - mode for wakeup PIN19 (PA43)"]
pub type Pin19ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `PIN20_MODE` reader - mode for wakeup PIN20 (PA44)"]
pub type Pin20ModeR = crate::FieldReader;
#[doc = "Field `PIN20_MODE` writer - mode for wakeup PIN20 (PA44)"]
pub type Pin20ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bits 0:2 - mode for wakeup PIN16 (PA40) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
#[inline(always)]
pub fn pin16_mode(&self) -> Pin16ModeR {
Pin16ModeR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - mode for wakeup PIN17 (PA41)"]
#[inline(always)]
pub fn pin17_mode(&self) -> Pin17ModeR {
Pin17ModeR::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:8 - mode for wakeup PIN18 (PA42)"]
#[inline(always)]
pub fn pin18_mode(&self) -> Pin18ModeR {
Pin18ModeR::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bits 9:11 - mode for wakeup PIN19 (PA43)"]
#[inline(always)]
pub fn pin19_mode(&self) -> Pin19ModeR {
Pin19ModeR::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bits 12:14 - mode for wakeup PIN20 (PA44)"]
#[inline(always)]
pub fn pin20_mode(&self) -> Pin20ModeR {
Pin20ModeR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bits 0:2 - mode for wakeup PIN16 (PA40) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge"]
#[inline(always)]
#[must_use]
pub fn pin16_mode(&mut self) -> Pin16ModeW<Cr3Spec> {
Pin16ModeW::new(self, 0)
}
#[doc = "Bits 3:5 - mode for wakeup PIN17 (PA41)"]
#[inline(always)]
#[must_use]
pub fn pin17_mode(&mut self) -> Pin17ModeW<Cr3Spec> {
Pin17ModeW::new(self, 3)
}
#[doc = "Bits 6:8 - mode for wakeup PIN18 (PA42)"]
#[inline(always)]
#[must_use]
pub fn pin18_mode(&mut self) -> Pin18ModeW<Cr3Spec> {
Pin18ModeW::new(self, 6)
}
#[doc = "Bits 9:11 - mode for wakeup PIN19 (PA43)"]
#[inline(always)]
#[must_use]
pub fn pin19_mode(&mut self) -> Pin19ModeW<Cr3Spec> {
Pin19ModeW::new(self, 9)
}
#[doc = "Bits 12:14 - mode for wakeup PIN20 (PA44)"]
#[inline(always)]
#[must_use]
pub fn pin20_mode(&mut self) -> Pin20ModeW<Cr3Spec> {
Pin20ModeW::new(self, 12)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr3Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr3Spec;
impl crate::RegisterSpec for Cr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr3::R`](R) reader structure"]
impl crate::Readable for Cr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cr3::W`](W) writer structure"]
impl crate::Writable for Cr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR3 to value 0"]
impl crate::Resettable for Cr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ACR (rw) register accessor: Active Mode Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acr`]
module"]
#[doc(alias = "ACR")]
pub type Acr = crate::Reg<acr::AcrSpec>;
#[doc = "Active Mode Control register"]
pub mod acr {
#[doc = "Register `ACR` reader"]
pub type R = crate::R<AcrSpec>;
#[doc = "Register `ACR` writer"]
pub type W = crate::W<AcrSpec>;
#[doc = "Field `HRC48_REQ` reader - Request HRC48 in active mode"]
pub type Hrc48ReqR = crate::BitReader;
#[doc = "Field `HRC48_REQ` writer - Request HRC48 in active mode"]
pub type Hrc48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HXT48_REQ` reader - Request HXT48 in active mode"]
pub type Hxt48ReqR = crate::BitReader;
#[doc = "Field `HXT48_REQ` writer - Request HXT48 in active mode"]
pub type Hxt48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
#[doc = "Field `HRC48_RDY` reader - Indicate HRC48 is ready"]
pub type Hrc48RdyR = crate::BitReader;
#[doc = "Field `HRC48_RDY` writer - Indicate HRC48 is ready"]
pub type Hrc48RdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HXT48_RDY` reader - Indicate HXT48 is ready"]
pub type Hxt48RdyR = crate::BitReader;
#[doc = "Field `HXT48_RDY` writer - Indicate HXT48 is ready"]
pub type Hxt48RdyW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Request HRC48 in active mode"]
#[inline(always)]
pub fn hrc48_req(&self) -> Hrc48ReqR {
Hrc48ReqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request HXT48 in active mode"]
#[inline(always)]
pub fn hxt48_req(&self) -> Hxt48ReqR {
Hxt48ReqR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:29"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x0fff_ffff)
}
#[doc = "Bit 30 - Indicate HRC48 is ready"]
#[inline(always)]
pub fn hrc48_rdy(&self) -> Hrc48RdyR {
Hrc48RdyR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Indicate HXT48 is ready"]
#[inline(always)]
pub fn hxt48_rdy(&self) -> Hxt48RdyR {
Hxt48RdyR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Request HRC48 in active mode"]
#[inline(always)]
#[must_use]
pub fn hrc48_req(&mut self) -> Hrc48ReqW<AcrSpec> {
Hrc48ReqW::new(self, 0)
}
#[doc = "Bit 1 - Request HXT48 in active mode"]
#[inline(always)]
#[must_use]
pub fn hxt48_req(&mut self) -> Hxt48ReqW<AcrSpec> {
Hxt48ReqW::new(self, 1)
}
#[doc = "Bits 2:29"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AcrSpec> {
RsvdW::new(self, 2)
}
#[doc = "Bit 30 - Indicate HRC48 is ready"]
#[inline(always)]
#[must_use]
pub fn hrc48_rdy(&mut self) -> Hrc48RdyW<AcrSpec> {
Hrc48RdyW::new(self, 30)
}
#[doc = "Bit 31 - Indicate HXT48 is ready"]
#[inline(always)]
#[must_use]
pub fn hxt48_rdy(&mut self) -> Hxt48RdyW<AcrSpec> {
Hxt48RdyW::new(self, 31)
}
}
#[doc = "Active Mode Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AcrSpec;
impl crate::RegisterSpec for AcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`acr::R`](R) reader structure"]
impl crate::Readable for AcrSpec {}
#[doc = "`write(|w| ..)` method takes [`acr::W`](W) writer structure"]
impl crate::Writable for AcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ACR to value 0"]
impl crate::Resettable for AcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "LSCR (rw) register accessor: Light Sleep Ctrl Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lscr`]
module"]
#[doc(alias = "LSCR")]
pub type Lscr = crate::Reg<lscr::LscrSpec>;
#[doc = "Light Sleep Ctrl Register"]
pub mod lscr {
#[doc = "Register `LSCR` reader"]
pub type R = crate::R<LscrSpec>;
#[doc = "Register `LSCR` writer"]
pub type W = crate::W<LscrSpec>;
#[doc = "Field `HRC48_REQ` reader - Request HRC48 in Light Sleep mode"]
pub type Hrc48ReqR = crate::BitReader;
#[doc = "Field `HRC48_REQ` writer - Request HRC48 in Light Sleep mode"]
pub type Hrc48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HXT48_REQ` reader - Request HXT48 in Light Sleep mode"]
pub type Hxt48ReqR = crate::BitReader;
#[doc = "Field `HXT48_REQ` writer - Request HXT48 in Light Sleep mode"]
pub type Hxt48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PWR_REQ` reader - Request power during Light Sleep mode"]
pub type PwrReqR = crate::BitReader;
#[doc = "Field `PWR_REQ` writer - Request power during Light Sleep mode"]
pub type PwrReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bit 0 - Request HRC48 in Light Sleep mode"]
#[inline(always)]
pub fn hrc48_req(&self) -> Hrc48ReqR {
Hrc48ReqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request HXT48 in Light Sleep mode"]
#[inline(always)]
pub fn hxt48_req(&self) -> Hxt48ReqR {
Hxt48ReqR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request power during Light Sleep mode"]
#[inline(always)]
pub fn pwr_req(&self) -> PwrReqR {
PwrReqR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Request HRC48 in Light Sleep mode"]
#[inline(always)]
#[must_use]
pub fn hrc48_req(&mut self) -> Hrc48ReqW<LscrSpec> {
Hrc48ReqW::new(self, 0)
}
#[doc = "Bit 1 - Request HXT48 in Light Sleep mode"]
#[inline(always)]
#[must_use]
pub fn hxt48_req(&mut self) -> Hxt48ReqW<LscrSpec> {
Hxt48ReqW::new(self, 1)
}
#[doc = "Bit 2 - Request power during Light Sleep mode"]
#[inline(always)]
#[must_use]
pub fn pwr_req(&mut self) -> PwrReqW<LscrSpec> {
PwrReqW::new(self, 2)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<LscrSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "Light Sleep Ctrl Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LscrSpec;
impl crate::RegisterSpec for LscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lscr::R`](R) reader structure"]
impl crate::Readable for LscrSpec {}
#[doc = "`write(|w| ..)` method takes [`lscr::W`](W) writer structure"]
impl crate::Writable for LscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets LSCR to value 0"]
impl crate::Resettable for LscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DSCR (rw) register accessor: Deep Sleep Ctrl Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dscr`]
module"]
#[doc(alias = "DSCR")]
pub type Dscr = crate::Reg<dscr::DscrSpec>;
#[doc = "Deep Sleep Ctrl Register"]
pub mod dscr {
#[doc = "Register `DSCR` reader"]
pub type R = crate::R<DscrSpec>;
#[doc = "Register `DSCR` writer"]
pub type W = crate::W<DscrSpec>;
#[doc = "Field `HRC48_REQ` reader - Request HRC48 in Deep Sleep mode"]
pub type Hrc48ReqR = crate::BitReader;
#[doc = "Field `HRC48_REQ` writer - Request HRC48 in Deep Sleep mode"]
pub type Hrc48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HXT48_REQ` reader - Request HXT48 in Deep Sleep mode"]
pub type Hxt48ReqR = crate::BitReader;
#[doc = "Field `HXT48_REQ` writer - Request HXT48 in Deep Sleep mode"]
pub type Hxt48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PWR_REQ` reader - Request power during Deep Sleep mode"]
pub type PwrReqR = crate::BitReader;
#[doc = "Field `PWR_REQ` writer - Request power during Deep Sleep mode"]
pub type PwrReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bit 0 - Request HRC48 in Deep Sleep mode"]
#[inline(always)]
pub fn hrc48_req(&self) -> Hrc48ReqR {
Hrc48ReqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request HXT48 in Deep Sleep mode"]
#[inline(always)]
pub fn hxt48_req(&self) -> Hxt48ReqR {
Hxt48ReqR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request power during Deep Sleep mode"]
#[inline(always)]
pub fn pwr_req(&self) -> PwrReqR {
PwrReqR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Request HRC48 in Deep Sleep mode"]
#[inline(always)]
#[must_use]
pub fn hrc48_req(&mut self) -> Hrc48ReqW<DscrSpec> {
Hrc48ReqW::new(self, 0)
}
#[doc = "Bit 1 - Request HXT48 in Deep Sleep mode"]
#[inline(always)]
#[must_use]
pub fn hxt48_req(&mut self) -> Hxt48ReqW<DscrSpec> {
Hxt48ReqW::new(self, 1)
}
#[doc = "Bit 2 - Request power during Deep Sleep mode"]
#[inline(always)]
#[must_use]
pub fn pwr_req(&mut self) -> PwrReqW<DscrSpec> {
PwrReqW::new(self, 2)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DscrSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "Deep Sleep Ctrl Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DscrSpec;
impl crate::RegisterSpec for DscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dscr::R`](R) reader structure"]
impl crate::Readable for DscrSpec {}
#[doc = "`write(|w| ..)` method takes [`dscr::W`](W) writer structure"]
impl crate::Writable for DscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DSCR to value 0"]
impl crate::Resettable for DscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SBCR (rw) register accessor: Standby Mode Ctrl Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbcr`]
module"]
#[doc(alias = "SBCR")]
pub type Sbcr = crate::Reg<sbcr::SbcrSpec>;
#[doc = "Standby Mode Ctrl Register"]
pub mod sbcr {
#[doc = "Register `SBCR` reader"]
pub type R = crate::R<SbcrSpec>;
#[doc = "Register `SBCR` writer"]
pub type W = crate::W<SbcrSpec>;
#[doc = "Field `HRC48_REQ` reader - Request HRC48 in Standby mode"]
pub type Hrc48ReqR = crate::BitReader;
#[doc = "Field `HRC48_REQ` writer - Request HRC48 in Standby mode"]
pub type Hrc48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HXT48_REQ` reader - Request HXT48 in Standby mode"]
pub type Hxt48ReqR = crate::BitReader;
#[doc = "Field `HXT48_REQ` writer - Request HXT48 in Standby mode"]
pub type Hxt48ReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PWR_REQ` reader - Request power during Standby mode"]
pub type PwrReqR = crate::BitReader;
#[doc = "Field `PWR_REQ` writer - Request power during Standby mode"]
pub type PwrReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
impl R {
#[doc = "Bit 0 - Request HRC48 in Standby mode"]
#[inline(always)]
pub fn hrc48_req(&self) -> Hrc48ReqR {
Hrc48ReqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request HXT48 in Standby mode"]
#[inline(always)]
pub fn hxt48_req(&self) -> Hxt48ReqR {
Hxt48ReqR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request power during Standby mode"]
#[inline(always)]
pub fn pwr_req(&self) -> PwrReqR {
PwrReqR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 3) & 0x1fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Request HRC48 in Standby mode"]
#[inline(always)]
#[must_use]
pub fn hrc48_req(&mut self) -> Hrc48ReqW<SbcrSpec> {
Hrc48ReqW::new(self, 0)
}
#[doc = "Bit 1 - Request HXT48 in Standby mode"]
#[inline(always)]
#[must_use]
pub fn hxt48_req(&mut self) -> Hxt48ReqW<SbcrSpec> {
Hxt48ReqW::new(self, 1)
}
#[doc = "Bit 2 - Request power during Standby mode"]
#[inline(always)]
#[must_use]
pub fn pwr_req(&mut self) -> PwrReqW<SbcrSpec> {
PwrReqW::new(self, 2)
}
#[doc = "Bits 3:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SbcrSpec> {
RsvdW::new(self, 3)
}
}
#[doc = "Standby Mode Ctrl Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SbcrSpec;
impl crate::RegisterSpec for SbcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sbcr::R`](R) reader structure"]
impl crate::Readable for SbcrSpec {}
#[doc = "`write(|w| ..)` method takes [`sbcr::W`](W) writer structure"]
impl crate::Writable for SbcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SBCR to value 0"]
impl crate::Resettable for SbcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WER (rw) register accessor: Wakeup Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wer`]
module"]
#[doc(alias = "WER")]
pub type Wer = crate::Reg<wer::WerSpec>;
#[doc = "Wakeup Enable register"]
pub mod wer {
#[doc = "Register `WER` reader"]
pub type R = crate::R<WerSpec>;
#[doc = "Register `WER` writer"]
pub type W = crate::W<WerSpec>;
#[doc = "Field `RTC` reader - Set 1 to enable RTC as wakeup source"]
pub type RtcR = crate::BitReader;
#[doc = "Field `RTC` writer - Set 1 to enable RTC as wakeup source"]
pub type RtcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO1` reader - Set 1 to enable IO(PA) as wakeup source"]
pub type Gpio1R = crate::BitReader;
#[doc = "Field `GPIO1` writer - Set 1 to enable IO(PA) as wakeup source"]
pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LPTIM1` reader - Set 1 to enable LPTIM1 as wakeup source"]
pub type Lptim1R = crate::BitReader;
#[doc = "Field `LPTIM1` writer - Set 1 to enable LPTIM1 as wakeup source"]
pub type Lptim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMUC` reader - Set 1 to enable PMUC as wakeup source"]
pub type PmucR = crate::BitReader;
#[doc = "Field `PMUC` writer - Set 1 to enable PMUC as wakeup source"]
pub type PmucW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `LP2HP_REQ` reader - Set 1 to enable LPSYS request as wakeup source"]
pub type Lp2hpReqR = crate::BitReader;
#[doc = "Field `LP2HP_REQ` writer - Set 1 to enable LPSYS request as wakeup source"]
pub type Lp2hpReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LP2HP_IRQ` reader - Set 1 to enable MAILBOX2 as wakeup source"]
pub type Lp2hpIrqR = crate::BitReader;
#[doc = "Field `LP2HP_IRQ` writer - Set 1 to enable MAILBOX2 as wakeup source"]
pub type Lp2hpIrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN0` reader - Set 1 to enable PA24 as wakeup source"]
pub type Pin0R = crate::BitReader;
#[doc = "Field `PIN0` writer - Set 1 to enable PA24 as wakeup source"]
pub type Pin0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN1` reader - Set 1 to enable PA25 as wakeup source"]
pub type Pin1R = crate::BitReader;
#[doc = "Field `PIN1` writer - Set 1 to enable PA25 as wakeup source"]
pub type Pin1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN2` reader - Set 1 to enable PA26 as wakeup source"]
pub type Pin2R = crate::BitReader;
#[doc = "Field `PIN2` writer - Set 1 to enable PA26 as wakeup source"]
pub type Pin2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN3` reader - Set 1 to enable PA27 as wakeup source"]
pub type Pin3R = crate::BitReader;
#[doc = "Field `PIN3` writer - Set 1 to enable PA27 as wakeup source"]
pub type Pin3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `PIN10` reader - Set 1 to enable PA34 as wakeup source"]
pub type Pin10R = crate::BitReader;
#[doc = "Field `PIN10` writer - Set 1 to enable PA34 as wakeup source"]
pub type Pin10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN11` reader - Set 1 to enable PA35 as wakeup source"]
pub type Pin11R = crate::BitReader;
#[doc = "Field `PIN11` writer - Set 1 to enable PA35 as wakeup source"]
pub type Pin11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN12` reader - Set 1 to enable PA36 as wakeup source"]
pub type Pin12R = crate::BitReader;
#[doc = "Field `PIN12` writer - Set 1 to enable PA36 as wakeup source"]
pub type Pin12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN13` reader - Set 1 to enable PA37 as wakeup source"]
pub type Pin13R = crate::BitReader;
#[doc = "Field `PIN13` writer - Set 1 to enable PA37 as wakeup source"]
pub type Pin13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN14` reader - Set 1 to enable PA38 as wakeup source"]
pub type Pin14R = crate::BitReader;
#[doc = "Field `PIN14` writer - Set 1 to enable PA38 as wakeup source"]
pub type Pin14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN15` reader - Set 1 to enable PA39 as wakeup source"]
pub type Pin15R = crate::BitReader;
#[doc = "Field `PIN15` writer - Set 1 to enable PA39 as wakeup source"]
pub type Pin15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN16` reader - Set 1 to enable PA40 as wakeup source"]
pub type Pin16R = crate::BitReader;
#[doc = "Field `PIN16` writer - Set 1 to enable PA40 as wakeup source"]
pub type Pin16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN17` reader - Set 1 to enable PA41 as wakeup source"]
pub type Pin17R = crate::BitReader;
#[doc = "Field `PIN17` writer - Set 1 to enable PA41 as wakeup source"]
pub type Pin17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN18` reader - Set 1 to enable PA42 as wakeup source"]
pub type Pin18R = crate::BitReader;
#[doc = "Field `PIN18` writer - Set 1 to enable PA42 as wakeup source"]
pub type Pin18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN19` reader - Set 1 to enable PA43 as wakeup source"]
pub type Pin19R = crate::BitReader;
#[doc = "Field `PIN19` writer - Set 1 to enable PA43 as wakeup source"]
pub type Pin19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN20` reader - Set 1 to enable PA44 as wakeup source"]
pub type Pin20R = crate::BitReader;
#[doc = "Field `PIN20` writer - Set 1 to enable PA44 as wakeup source"]
pub type Pin20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bit 0 - Set 1 to enable RTC as wakeup source"]
#[inline(always)]
pub fn rtc(&self) -> RtcR {
RtcR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Set 1 to enable IO(PA) as wakeup source"]
#[inline(always)]
pub fn gpio1(&self) -> Gpio1R {
Gpio1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Set 1 to enable LPTIM1 as wakeup source"]
#[inline(always)]
pub fn lptim1(&self) -> Lptim1R {
Lptim1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Set 1 to enable PMUC as wakeup source"]
#[inline(always)]
pub fn pmuc(&self) -> PmucR {
PmucR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6 - Set 1 to enable LPSYS request as wakeup source"]
#[inline(always)]
pub fn lp2hp_req(&self) -> Lp2hpReqR {
Lp2hpReqR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Set 1 to enable MAILBOX2 as wakeup source"]
#[inline(always)]
pub fn lp2hp_irq(&self) -> Lp2hpIrqR {
Lp2hpIrqR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Set 1 to enable PA24 as wakeup source"]
#[inline(always)]
pub fn pin0(&self) -> Pin0R {
Pin0R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Set 1 to enable PA25 as wakeup source"]
#[inline(always)]
pub fn pin1(&self) -> Pin1R {
Pin1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Set 1 to enable PA26 as wakeup source"]
#[inline(always)]
pub fn pin2(&self) -> Pin2R {
Pin2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Set 1 to enable PA27 as wakeup source"]
#[inline(always)]
pub fn pin3(&self) -> Pin3R {
Pin3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:17"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 0x3f) as u8)
}
#[doc = "Bit 18 - Set 1 to enable PA34 as wakeup source"]
#[inline(always)]
pub fn pin10(&self) -> Pin10R {
Pin10R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Set 1 to enable PA35 as wakeup source"]
#[inline(always)]
pub fn pin11(&self) -> Pin11R {
Pin11R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Set 1 to enable PA36 as wakeup source"]
#[inline(always)]
pub fn pin12(&self) -> Pin12R {
Pin12R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Set 1 to enable PA37 as wakeup source"]
#[inline(always)]
pub fn pin13(&self) -> Pin13R {
Pin13R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Set 1 to enable PA38 as wakeup source"]
#[inline(always)]
pub fn pin14(&self) -> Pin14R {
Pin14R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Set 1 to enable PA39 as wakeup source"]
#[inline(always)]
pub fn pin15(&self) -> Pin15R {
Pin15R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Set 1 to enable PA40 as wakeup source"]
#[inline(always)]
pub fn pin16(&self) -> Pin16R {
Pin16R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Set 1 to enable PA41 as wakeup source"]
#[inline(always)]
pub fn pin17(&self) -> Pin17R {
Pin17R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Set 1 to enable PA42 as wakeup source"]
#[inline(always)]
pub fn pin18(&self) -> Pin18R {
Pin18R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Set 1 to enable PA43 as wakeup source"]
#[inline(always)]
pub fn pin19(&self) -> Pin19R {
Pin19R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Set 1 to enable PA44 as wakeup source"]
#[inline(always)]
pub fn pin20(&self) -> Pin20R {
Pin20R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0 - Set 1 to enable RTC as wakeup source"]
#[inline(always)]
#[must_use]
pub fn rtc(&mut self) -> RtcW<WerSpec> {
RtcW::new(self, 0)
}
#[doc = "Bit 1 - Set 1 to enable IO(PA) as wakeup source"]
#[inline(always)]
#[must_use]
pub fn gpio1(&mut self) -> Gpio1W<WerSpec> {
Gpio1W::new(self, 1)
}
#[doc = "Bit 2 - Set 1 to enable LPTIM1 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn lptim1(&mut self) -> Lptim1W<WerSpec> {
Lptim1W::new(self, 2)
}
#[doc = "Bit 3 - Set 1 to enable PMUC as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pmuc(&mut self) -> PmucW<WerSpec> {
PmucW::new(self, 3)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<WerSpec> {
Rsvd3W::new(self, 4)
}
#[doc = "Bit 6 - Set 1 to enable LPSYS request as wakeup source"]
#[inline(always)]
#[must_use]
pub fn lp2hp_req(&mut self) -> Lp2hpReqW<WerSpec> {
Lp2hpReqW::new(self, 6)
}
#[doc = "Bit 7 - Set 1 to enable MAILBOX2 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn lp2hp_irq(&mut self) -> Lp2hpIrqW<WerSpec> {
Lp2hpIrqW::new(self, 7)
}
#[doc = "Bit 8 - Set 1 to enable PA24 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin0(&mut self) -> Pin0W<WerSpec> {
Pin0W::new(self, 8)
}
#[doc = "Bit 9 - Set 1 to enable PA25 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin1(&mut self) -> Pin1W<WerSpec> {
Pin1W::new(self, 9)
}
#[doc = "Bit 10 - Set 1 to enable PA26 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin2(&mut self) -> Pin2W<WerSpec> {
Pin2W::new(self, 10)
}
#[doc = "Bit 11 - Set 1 to enable PA27 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin3(&mut self) -> Pin3W<WerSpec> {
Pin3W::new(self, 11)
}
#[doc = "Bits 12:17"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<WerSpec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bit 18 - Set 1 to enable PA34 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin10(&mut self) -> Pin10W<WerSpec> {
Pin10W::new(self, 18)
}
#[doc = "Bit 19 - Set 1 to enable PA35 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin11(&mut self) -> Pin11W<WerSpec> {
Pin11W::new(self, 19)
}
#[doc = "Bit 20 - Set 1 to enable PA36 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin12(&mut self) -> Pin12W<WerSpec> {
Pin12W::new(self, 20)
}
#[doc = "Bit 21 - Set 1 to enable PA37 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin13(&mut self) -> Pin13W<WerSpec> {
Pin13W::new(self, 21)
}
#[doc = "Bit 22 - Set 1 to enable PA38 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin14(&mut self) -> Pin14W<WerSpec> {
Pin14W::new(self, 22)
}
#[doc = "Bit 23 - Set 1 to enable PA39 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin15(&mut self) -> Pin15W<WerSpec> {
Pin15W::new(self, 23)
}
#[doc = "Bit 24 - Set 1 to enable PA40 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin16(&mut self) -> Pin16W<WerSpec> {
Pin16W::new(self, 24)
}
#[doc = "Bit 25 - Set 1 to enable PA41 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin17(&mut self) -> Pin17W<WerSpec> {
Pin17W::new(self, 25)
}
#[doc = "Bit 26 - Set 1 to enable PA42 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin18(&mut self) -> Pin18W<WerSpec> {
Pin18W::new(self, 26)
}
#[doc = "Bit 27 - Set 1 to enable PA43 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin19(&mut self) -> Pin19W<WerSpec> {
Pin19W::new(self, 27)
}
#[doc = "Bit 28 - Set 1 to enable PA44 as wakeup source"]
#[inline(always)]
#[must_use]
pub fn pin20(&mut self) -> Pin20W<WerSpec> {
Pin20W::new(self, 28)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WerSpec> {
RsvdW::new(self, 29)
}
}
#[doc = "Wakeup Enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wer::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WerSpec;
impl crate::RegisterSpec for WerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wer::R`](R) reader structure"]
impl crate::Readable for WerSpec {}
#[doc = "`write(|w| ..)` method takes [`wer::W`](W) writer structure"]
impl crate::Writable for WerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WER to value 0"]
impl crate::Resettable for WerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WSR (rw) register accessor: Wakeup Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wsr`]
module"]
#[doc(alias = "WSR")]
pub type Wsr = crate::Reg<wsr::WsrSpec>;
#[doc = "Wakeup Status register"]
pub mod wsr {
#[doc = "Register `WSR` reader"]
pub type R = crate::R<WsrSpec>;
#[doc = "Register `WSR` writer"]
pub type W = crate::W<WsrSpec>;
#[doc = "Field `RTC` reader - Indicates the wakeup status from RTC. Note: the status is masked by WER"]
pub type RtcR = crate::BitReader;
#[doc = "Field `RTC` writer - Indicates the wakeup status from RTC. Note: the status is masked by WER"]
pub type RtcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO1` reader - Indicates the wakeup status from IO(PA). Note: the status is masked by WER"]
pub type Gpio1R = crate::BitReader;
#[doc = "Field `GPIO1` writer - Indicates the wakeup status from IO(PA). Note: the status is masked by WER"]
pub type Gpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LPTIM1` reader - Indicates the wakeup status from LPTIM1. Note: the status is masked by WER"]
pub type Lptim1R = crate::BitReader;
#[doc = "Field `LPTIM1` writer - Indicates the wakeup status from LPTIM1. Note: the status is masked by WER"]
pub type Lptim1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMUC` reader - Indicates the wakeup status from PMUC. Note: the status is masked by WER"]
pub type PmucR = crate::BitReader;
#[doc = "Field `PMUC` writer - Indicates the wakeup status from PMUC. Note: the status is masked by WER"]
pub type PmucW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `LP2HP_REQ` reader - Indicates the wakeup status from LPSYS request. Note: the status is masked by WER"]
pub type Lp2hpReqR = crate::BitReader;
#[doc = "Field `LP2HP_REQ` writer - Indicates the wakeup status from LPSYS request. Note: the status is masked by WER"]
pub type Lp2hpReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LP2HP_IRQ` reader - Indicates the wakeup status from MAILBOX2. Note: the status is masked by WER"]
pub type Lp2hpIrqR = crate::BitReader;
#[doc = "Field `LP2HP_IRQ` writer - Indicates the wakeup status from MAILBOX2. Note: the status is masked by WER"]
pub type Lp2hpIrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN0` reader - Indicates the wakeup status from PA24 request. Note: the status is masked by WER"]
pub type Pin0R = crate::BitReader;
#[doc = "Field `PIN0` writer - Indicates the wakeup status from PA24 request. Note: the status is masked by WER"]
pub type Pin0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN1` reader - Indicates the wakeup status from PA25 request. Note: the status is masked by WER"]
pub type Pin1R = crate::BitReader;
#[doc = "Field `PIN1` writer - Indicates the wakeup status from PA25 request. Note: the status is masked by WER"]
pub type Pin1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN2` reader - Indicates the wakeup status from PA26 request. Note: the status is masked by WER"]
pub type Pin2R = crate::BitReader;
#[doc = "Field `PIN2` writer - Indicates the wakeup status from PA26 request. Note: the status is masked by WER"]
pub type Pin2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN3` reader - Indicates the wakeup status from PA27 request. Note: the status is masked by WER"]
pub type Pin3R = crate::BitReader;
#[doc = "Field `PIN3` writer - Indicates the wakeup status from PA27 request. Note: the status is masked by WER"]
pub type Pin3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `PIN10` reader - Indicates the wakeup status from PA34 request. Note: the status is masked by WER"]
pub type Pin10R = crate::BitReader;
#[doc = "Field `PIN10` writer - Indicates the wakeup status from PA34 request. Note: the status is masked by WER"]
pub type Pin10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN11` reader - Indicates the wakeup status from PA35 request. Note: the status is masked by WER"]
pub type Pin11R = crate::BitReader;
#[doc = "Field `PIN11` writer - Indicates the wakeup status from PA35 request. Note: the status is masked by WER"]
pub type Pin11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN12` reader - Indicates the wakeup status from PA36 request. Note: the status is masked by WER"]
pub type Pin12R = crate::BitReader;
#[doc = "Field `PIN12` writer - Indicates the wakeup status from PA36 request. Note: the status is masked by WER"]
pub type Pin12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN13` reader - Indicates the wakeup status from PA37 request. Note: the status is masked by WER"]
pub type Pin13R = crate::BitReader;
#[doc = "Field `PIN13` writer - Indicates the wakeup status from PA37 request. Note: the status is masked by WER"]
pub type Pin13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN14` reader - Indicates the wakeup status from PA38 request. Note: the status is masked by WER"]
pub type Pin14R = crate::BitReader;
#[doc = "Field `PIN14` writer - Indicates the wakeup status from PA38 request. Note: the status is masked by WER"]
pub type Pin14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN15` reader - Indicates the wakeup status from PA39 request. Note: the status is masked by WER"]
pub type Pin15R = crate::BitReader;
#[doc = "Field `PIN15` writer - Indicates the wakeup status from PA39 request. Note: the status is masked by WER"]
pub type Pin15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN16` reader - Indicates the wakeup status from PA40 request. Note: the status is masked by WER"]
pub type Pin16R = crate::BitReader;
#[doc = "Field `PIN16` writer - Indicates the wakeup status from PA40 request. Note: the status is masked by WER"]
pub type Pin16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN17` reader - Indicates the wakeup status from PA41 request. Note: the status is masked by WER"]
pub type Pin17R = crate::BitReader;
#[doc = "Field `PIN17` writer - Indicates the wakeup status from PA41 request. Note: the status is masked by WER"]
pub type Pin17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN18` reader - Indicates the wakeup status from PA42 request. Note: the status is masked by WER"]
pub type Pin18R = crate::BitReader;
#[doc = "Field `PIN18` writer - Indicates the wakeup status from PA42 request. Note: the status is masked by WER"]
pub type Pin18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN19` reader - Indicates the wakeup status from PA43 request. Note: the status is masked by WER"]
pub type Pin19R = crate::BitReader;
#[doc = "Field `PIN19` writer - Indicates the wakeup status from PA43 request. Note: the status is masked by WER"]
pub type Pin19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN20` reader - Indicates the wakeup status from PA44 request. Note: the status is masked by WER"]
pub type Pin20R = crate::BitReader;
#[doc = "Field `PIN20` writer - Indicates the wakeup status from PA44 request. Note: the status is masked by WER"]
pub type Pin20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bit 0 - Indicates the wakeup status from RTC. Note: the status is masked by WER"]
#[inline(always)]
pub fn rtc(&self) -> RtcR {
RtcR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Indicates the wakeup status from IO(PA). Note: the status is masked by WER"]
#[inline(always)]
pub fn gpio1(&self) -> Gpio1R {
Gpio1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Indicates the wakeup status from LPTIM1. Note: the status is masked by WER"]
#[inline(always)]
pub fn lptim1(&self) -> Lptim1R {
Lptim1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Indicates the wakeup status from PMUC. Note: the status is masked by WER"]
#[inline(always)]
pub fn pmuc(&self) -> PmucR {
PmucR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6 - Indicates the wakeup status from LPSYS request. Note: the status is masked by WER"]
#[inline(always)]
pub fn lp2hp_req(&self) -> Lp2hpReqR {
Lp2hpReqR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Indicates the wakeup status from MAILBOX2. Note: the status is masked by WER"]
#[inline(always)]
pub fn lp2hp_irq(&self) -> Lp2hpIrqR {
Lp2hpIrqR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Indicates the wakeup status from PA24 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin0(&self) -> Pin0R {
Pin0R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Indicates the wakeup status from PA25 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin1(&self) -> Pin1R {
Pin1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Indicates the wakeup status from PA26 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin2(&self) -> Pin2R {
Pin2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Indicates the wakeup status from PA27 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin3(&self) -> Pin3R {
Pin3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:17"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 0x3f) as u8)
}
#[doc = "Bit 18 - Indicates the wakeup status from PA34 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin10(&self) -> Pin10R {
Pin10R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Indicates the wakeup status from PA35 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin11(&self) -> Pin11R {
Pin11R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Indicates the wakeup status from PA36 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin12(&self) -> Pin12R {
Pin12R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Indicates the wakeup status from PA37 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin13(&self) -> Pin13R {
Pin13R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Indicates the wakeup status from PA38 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin14(&self) -> Pin14R {
Pin14R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Indicates the wakeup status from PA39 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin15(&self) -> Pin15R {
Pin15R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Indicates the wakeup status from PA40 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin16(&self) -> Pin16R {
Pin16R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Indicates the wakeup status from PA41 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin17(&self) -> Pin17R {
Pin17R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Indicates the wakeup status from PA42 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin18(&self) -> Pin18R {
Pin18R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Indicates the wakeup status from PA43 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin19(&self) -> Pin19R {
Pin19R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Indicates the wakeup status from PA44 request. Note: the status is masked by WER"]
#[inline(always)]
pub fn pin20(&self) -> Pin20R {
Pin20R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0 - Indicates the wakeup status from RTC. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn rtc(&mut self) -> RtcW<WsrSpec> {
RtcW::new(self, 0)
}
#[doc = "Bit 1 - Indicates the wakeup status from IO(PA). Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn gpio1(&mut self) -> Gpio1W<WsrSpec> {
Gpio1W::new(self, 1)
}
#[doc = "Bit 2 - Indicates the wakeup status from LPTIM1. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn lptim1(&mut self) -> Lptim1W<WsrSpec> {
Lptim1W::new(self, 2)
}
#[doc = "Bit 3 - Indicates the wakeup status from PMUC. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pmuc(&mut self) -> PmucW<WsrSpec> {
PmucW::new(self, 3)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<WsrSpec> {
Rsvd3W::new(self, 4)
}
#[doc = "Bit 6 - Indicates the wakeup status from LPSYS request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn lp2hp_req(&mut self) -> Lp2hpReqW<WsrSpec> {
Lp2hpReqW::new(self, 6)
}
#[doc = "Bit 7 - Indicates the wakeup status from MAILBOX2. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn lp2hp_irq(&mut self) -> Lp2hpIrqW<WsrSpec> {
Lp2hpIrqW::new(self, 7)
}
#[doc = "Bit 8 - Indicates the wakeup status from PA24 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin0(&mut self) -> Pin0W<WsrSpec> {
Pin0W::new(self, 8)
}
#[doc = "Bit 9 - Indicates the wakeup status from PA25 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin1(&mut self) -> Pin1W<WsrSpec> {
Pin1W::new(self, 9)
}
#[doc = "Bit 10 - Indicates the wakeup status from PA26 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin2(&mut self) -> Pin2W<WsrSpec> {
Pin2W::new(self, 10)
}
#[doc = "Bit 11 - Indicates the wakeup status from PA27 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin3(&mut self) -> Pin3W<WsrSpec> {
Pin3W::new(self, 11)
}
#[doc = "Bits 12:17"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<WsrSpec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bit 18 - Indicates the wakeup status from PA34 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin10(&mut self) -> Pin10W<WsrSpec> {
Pin10W::new(self, 18)
}
#[doc = "Bit 19 - Indicates the wakeup status from PA35 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin11(&mut self) -> Pin11W<WsrSpec> {
Pin11W::new(self, 19)
}
#[doc = "Bit 20 - Indicates the wakeup status from PA36 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin12(&mut self) -> Pin12W<WsrSpec> {
Pin12W::new(self, 20)
}
#[doc = "Bit 21 - Indicates the wakeup status from PA37 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin13(&mut self) -> Pin13W<WsrSpec> {
Pin13W::new(self, 21)
}
#[doc = "Bit 22 - Indicates the wakeup status from PA38 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin14(&mut self) -> Pin14W<WsrSpec> {
Pin14W::new(self, 22)
}
#[doc = "Bit 23 - Indicates the wakeup status from PA39 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin15(&mut self) -> Pin15W<WsrSpec> {
Pin15W::new(self, 23)
}
#[doc = "Bit 24 - Indicates the wakeup status from PA40 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin16(&mut self) -> Pin16W<WsrSpec> {
Pin16W::new(self, 24)
}
#[doc = "Bit 25 - Indicates the wakeup status from PA41 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin17(&mut self) -> Pin17W<WsrSpec> {
Pin17W::new(self, 25)
}
#[doc = "Bit 26 - Indicates the wakeup status from PA42 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin18(&mut self) -> Pin18W<WsrSpec> {
Pin18W::new(self, 26)
}
#[doc = "Bit 27 - Indicates the wakeup status from PA43 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin19(&mut self) -> Pin19W<WsrSpec> {
Pin19W::new(self, 27)
}
#[doc = "Bit 28 - Indicates the wakeup status from PA44 request. Note: the status is masked by WER"]
#[inline(always)]
#[must_use]
pub fn pin20(&mut self) -> Pin20W<WsrSpec> {
Pin20W::new(self, 28)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WsrSpec> {
RsvdW::new(self, 29)
}
}
#[doc = "Wakeup Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WsrSpec;
impl crate::RegisterSpec for WsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wsr::R`](R) reader structure"]
impl crate::Readable for WsrSpec {}
#[doc = "`write(|w| ..)` method takes [`wsr::W`](W) writer structure"]
impl crate::Writable for WsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WSR to value 0"]
impl crate::Resettable for WsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WCR (rw) register accessor: Wakeup Clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wcr`]
module"]
#[doc(alias = "WCR")]
pub type Wcr = crate::Reg<wcr::WcrSpec>;
#[doc = "Wakeup Clear register"]
pub mod wcr {
#[doc = "Register `WCR` reader"]
pub type R = crate::R<WcrSpec>;
#[doc = "Register `WCR` writer"]
pub type W = crate::W<WcrSpec>;
#[doc = "Field `RSVD3` reader - Note: for RTC/IO(PA)/LPTIM/PMUC, clear the wakeup status directly in the orignal module"]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - Note: for RTC/IO(PA)/LPTIM/PMUC, clear the wakeup status directly in the orignal module"]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `PIN0` reader - Write 1 to clear PA24 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin0R = crate::BitReader;
#[doc = "Field `PIN0` writer - Write 1 to clear PA24 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN1` reader - Write 1 to clear PA25 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin1R = crate::BitReader;
#[doc = "Field `PIN1` writer - Write 1 to clear PA25 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN2` reader - Write 1 to clear PA26 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin2R = crate::BitReader;
#[doc = "Field `PIN2` writer - Write 1 to clear PA26 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN3` reader - Write 1 to clear PA27 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin3R = crate::BitReader;
#[doc = "Field `PIN3` writer - Write 1 to clear PA27 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `PIN10` reader - Write 1 to clear PA34 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin10R = crate::BitReader;
#[doc = "Field `PIN10` writer - Write 1 to clear PA34 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN11` reader - Write 1 to clear PA35 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin11R = crate::BitReader;
#[doc = "Field `PIN11` writer - Write 1 to clear PA35 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN12` reader - Write 1 to clear PA36 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin12R = crate::BitReader;
#[doc = "Field `PIN12` writer - Write 1 to clear PA36 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN13` reader - Write 1 to clear PA37 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin13R = crate::BitReader;
#[doc = "Field `PIN13` writer - Write 1 to clear PA37 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN14` reader - Write 1 to clear PA38 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin14R = crate::BitReader;
#[doc = "Field `PIN14` writer - Write 1 to clear PA38 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN15` reader - Write 1 to clear PA39 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin15R = crate::BitReader;
#[doc = "Field `PIN15` writer - Write 1 to clear PA39 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN16` reader - Write 1 to clear PA40 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin16R = crate::BitReader;
#[doc = "Field `PIN16` writer - Write 1 to clear PA40 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN17` reader - Write 1 to clear PA41 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin17R = crate::BitReader;
#[doc = "Field `PIN17` writer - Write 1 to clear PA41 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN18` reader - Write 1 to clear PA42 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin18R = crate::BitReader;
#[doc = "Field `PIN18` writer - Write 1 to clear PA42 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN19` reader - Write 1 to clear PA43 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin19R = crate::BitReader;
#[doc = "Field `PIN19` writer - Write 1 to clear PA43 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PIN20` reader - Write 1 to clear PA44 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin20R = crate::BitReader;
#[doc = "Field `PIN20` writer - Write 1 to clear PA44 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
pub type Pin20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `AON` reader - Write 1 to clear the AON wakeup IRQ status"]
pub type AonR = crate::BitReader;
#[doc = "Field `AON` writer - Write 1 to clear the AON wakeup IRQ status"]
pub type AonW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:7 - Note: for RTC/IO(PA)/LPTIM/PMUC, clear the wakeup status directly in the orignal module"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - Write 1 to clear PA24 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin0(&self) -> Pin0R {
Pin0R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Write 1 to clear PA25 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin1(&self) -> Pin1R {
Pin1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Write 1 to clear PA26 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin2(&self) -> Pin2R {
Pin2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Write 1 to clear PA27 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin3(&self) -> Pin3R {
Pin3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:17"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 12) & 0x3f) as u8)
}
#[doc = "Bit 18 - Write 1 to clear PA34 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin10(&self) -> Pin10R {
Pin10R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Write 1 to clear PA35 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin11(&self) -> Pin11R {
Pin11R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Write 1 to clear PA36 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin12(&self) -> Pin12R {
Pin12R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Write 1 to clear PA37 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin13(&self) -> Pin13R {
Pin13R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Write 1 to clear PA38 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin14(&self) -> Pin14R {
Pin14R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Write 1 to clear PA39 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin15(&self) -> Pin15R {
Pin15R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Write 1 to clear PA40 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin16(&self) -> Pin16R {
Pin16R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Write 1 to clear PA41 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin17(&self) -> Pin17R {
Pin17R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Write 1 to clear PA42 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin18(&self) -> Pin18R {
Pin18R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Write 1 to clear PA43 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin19(&self) -> Pin19R {
Pin19R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Write 1 to clear PA44 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
pub fn pin20(&self) -> Pin20R {
Pin20R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bits 29:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 3) as u8)
}
#[doc = "Bit 31 - Write 1 to clear the AON wakeup IRQ status"]
#[inline(always)]
pub fn aon(&self) -> AonR {
AonR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7 - Note: for RTC/IO(PA)/LPTIM/PMUC, clear the wakeup status directly in the orignal module"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<WcrSpec> {
Rsvd3W::new(self, 0)
}
#[doc = "Bit 8 - Write 1 to clear PA24 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin0(&mut self) -> Pin0W<WcrSpec> {
Pin0W::new(self, 8)
}
#[doc = "Bit 9 - Write 1 to clear PA25 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin1(&mut self) -> Pin1W<WcrSpec> {
Pin1W::new(self, 9)
}
#[doc = "Bit 10 - Write 1 to clear PA26 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin2(&mut self) -> Pin2W<WcrSpec> {
Pin2W::new(self, 10)
}
#[doc = "Bit 11 - Write 1 to clear PA27 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin3(&mut self) -> Pin3W<WcrSpec> {
Pin3W::new(self, 11)
}
#[doc = "Bits 12:17"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<WcrSpec> {
Rsvd2W::new(self, 12)
}
#[doc = "Bit 18 - Write 1 to clear PA34 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin10(&mut self) -> Pin10W<WcrSpec> {
Pin10W::new(self, 18)
}
#[doc = "Bit 19 - Write 1 to clear PA35 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin11(&mut self) -> Pin11W<WcrSpec> {
Pin11W::new(self, 19)
}
#[doc = "Bit 20 - Write 1 to clear PA36 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin12(&mut self) -> Pin12W<WcrSpec> {
Pin12W::new(self, 20)
}
#[doc = "Bit 21 - Write 1 to clear PA37 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin13(&mut self) -> Pin13W<WcrSpec> {
Pin13W::new(self, 21)
}
#[doc = "Bit 22 - Write 1 to clear PA38 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin14(&mut self) -> Pin14W<WcrSpec> {
Pin14W::new(self, 22)
}
#[doc = "Bit 23 - Write 1 to clear PA39 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin15(&mut self) -> Pin15W<WcrSpec> {
Pin15W::new(self, 23)
}
#[doc = "Bit 24 - Write 1 to clear PA40 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin16(&mut self) -> Pin16W<WcrSpec> {
Pin16W::new(self, 24)
}
#[doc = "Bit 25 - Write 1 to clear PA41 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin17(&mut self) -> Pin17W<WcrSpec> {
Pin17W::new(self, 25)
}
#[doc = "Bit 26 - Write 1 to clear PA42 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin18(&mut self) -> Pin18W<WcrSpec> {
Pin18W::new(self, 26)
}
#[doc = "Bit 27 - Write 1 to clear PA43 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin19(&mut self) -> Pin19W<WcrSpec> {
Pin19W::new(self, 27)
}
#[doc = "Bit 28 - Write 1 to clear PA44 wakeup source. Only valid if PIN wakeup is configured as edge trigger"]
#[inline(always)]
#[must_use]
pub fn pin20(&mut self) -> Pin20W<WcrSpec> {
Pin20W::new(self, 28)
}
#[doc = "Bits 29:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WcrSpec> {
RsvdW::new(self, 29)
}
#[doc = "Bit 31 - Write 1 to clear the AON wakeup IRQ status"]
#[inline(always)]
#[must_use]
pub fn aon(&mut self) -> AonW<WcrSpec> {
AonW::new(self, 31)
}
}
#[doc = "Wakeup Clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WcrSpec;
impl crate::RegisterSpec for WcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wcr::R`](R) reader structure"]
impl crate::Readable for WcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wcr::W`](W) writer structure"]
impl crate::Writable for WcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WCR to value 0"]
impl crate::Resettable for WcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISSR (rw) register accessor: Inter System Wakeup Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`issr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`issr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@issr`]
module"]
#[doc(alias = "ISSR")]
pub type Issr = crate::Reg<issr::IssrSpec>;
#[doc = "Inter System Wakeup Register"]
pub mod issr {
#[doc = "Register `ISSR` reader"]
pub type R = crate::R<IssrSpec>;
#[doc = "Register `ISSR` writer"]
pub type W = crate::W<IssrSpec>;
#[doc = "Field `HP2LP_REQ` reader - write 1 to request LPSYS to stay in active mode"]
pub type Hp2lpReqR = crate::BitReader;
#[doc = "Field `HP2LP_REQ` writer - write 1 to request LPSYS to stay in active mode"]
pub type Hp2lpReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LP2HP_REQ` reader - indicate LPSYS request exists"]
pub type Lp2hpReqR = crate::BitReader;
#[doc = "Field `LP2HP_REQ` writer - indicate LPSYS request exists"]
pub type Lp2hpReqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `HP_ACTIVE` reader - write 1 to indicates HPSYS is active"]
pub type HpActiveR = crate::BitReader;
#[doc = "Field `HP_ACTIVE` writer - write 1 to indicates HPSYS is active"]
pub type HpActiveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LP_ACTIVE` reader - read 1 indicates LPSYS is active"]
pub type LpActiveR = crate::BitReader;
#[doc = "Field `LP_ACTIVE` writer - read 1 indicates LPSYS is active"]
pub type LpActiveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bit 0 - write 1 to request LPSYS to stay in active mode"]
#[inline(always)]
pub fn hp2lp_req(&self) -> Hp2lpReqR {
Hp2lpReqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - indicate LPSYS request exists"]
#[inline(always)]
pub fn lp2hp_req(&self) -> Lp2hpReqR {
Lp2hpReqR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4 - write 1 to indicates HPSYS is active"]
#[inline(always)]
pub fn hp_active(&self) -> HpActiveR {
HpActiveR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - read 1 indicates LPSYS is active"]
#[inline(always)]
pub fn lp_active(&self) -> LpActiveR {
LpActiveR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - write 1 to request LPSYS to stay in active mode"]
#[inline(always)]
#[must_use]
pub fn hp2lp_req(&mut self) -> Hp2lpReqW<IssrSpec> {
Hp2lpReqW::new(self, 0)
}
#[doc = "Bit 1 - indicate LPSYS request exists"]
#[inline(always)]
#[must_use]
pub fn lp2hp_req(&mut self) -> Lp2hpReqW<IssrSpec> {
Lp2hpReqW::new(self, 1)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IssrSpec> {
Rsvd2W::new(self, 2)
}
#[doc = "Bit 4 - write 1 to indicates HPSYS is active"]
#[inline(always)]
#[must_use]
pub fn hp_active(&mut self) -> HpActiveW<IssrSpec> {
HpActiveW::new(self, 4)
}
#[doc = "Bit 5 - read 1 indicates LPSYS is active"]
#[inline(always)]
#[must_use]
pub fn lp_active(&mut self) -> LpActiveW<IssrSpec> {
LpActiveW::new(self, 5)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IssrSpec> {
RsvdW::new(self, 6)
}
}
#[doc = "Inter System Wakeup Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`issr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`issr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IssrSpec;
impl crate::RegisterSpec for IssrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`issr::R`](R) reader structure"]
impl crate::Readable for IssrSpec {}
#[doc = "`write(|w| ..)` method takes [`issr::W`](W) writer structure"]
impl crate::Writable for IssrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISSR to value 0"]
impl crate::Resettable for IssrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ANACR (rw) register accessor: Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`anacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`anacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@anacr`]
module"]
#[doc(alias = "ANACR")]
pub type Anacr = crate::Reg<anacr::AnacrSpec>;
#[doc = "Analog Control Register"]
pub mod anacr {
#[doc = "Register `ANACR` reader"]
pub type R = crate::R<AnacrSpec>;
#[doc = "Register `ANACR` writer"]
pub type W = crate::W<AnacrSpec>;
#[doc = "Field `PA_ISO` reader - Set 1 to force IO(PA) into retention mode"]
pub type PaIsoR = crate::BitReader;
#[doc = "Field `PA_ISO` writer - Set 1 to force IO(PA) into retention mode"]
pub type PaIsoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VHP_ISO` reader - Set 1 to force off all HPSYS related analog modules"]
pub type VhpIsoR = crate::BitReader;
#[doc = "Field `VHP_ISO` writer - Set 1 to force off all HPSYS related analog modules"]
pub type VhpIsoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - Set 1 to force IO(PA) into retention mode"]
#[inline(always)]
pub fn pa_iso(&self) -> PaIsoR {
PaIsoR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Set 1 to force off all HPSYS related analog modules"]
#[inline(always)]
pub fn vhp_iso(&self) -> VhpIsoR {
VhpIsoR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Set 1 to force IO(PA) into retention mode"]
#[inline(always)]
#[must_use]
pub fn pa_iso(&mut self) -> PaIsoW<AnacrSpec> {
PaIsoW::new(self, 0)
}
#[doc = "Bit 1 - Set 1 to force off all HPSYS related analog modules"]
#[inline(always)]
#[must_use]
pub fn vhp_iso(&mut self) -> VhpIsoW<AnacrSpec> {
VhpIsoW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AnacrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`anacr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`anacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AnacrSpec;
impl crate::RegisterSpec for AnacrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`anacr::R`](R) reader structure"]
impl crate::Readable for AnacrSpec {}
#[doc = "`write(|w| ..)` method takes [`anacr::W`](W) writer structure"]
impl crate::Writable for AnacrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ANACR to value 0"]
impl crate::Resettable for AnacrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GTIMR (rw) register accessor: Global Timer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtimr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtimr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gtimr`]
module"]
#[doc(alias = "GTIMR")]
pub type Gtimr = crate::Reg<gtimr::GtimrSpec>;
#[doc = "Global Timer Register"]
pub mod gtimr {
#[doc = "Register `GTIMR` reader"]
pub type R = crate::R<GtimrSpec>;
#[doc = "Register `GTIMR` writer"]
pub type W = crate::W<GtimrSpec>;
#[doc = "Field `CNT` reader - Global timer value"]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - Global timer value"]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Global timer value"]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Global timer value"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<GtimrSpec> {
CntW::new(self, 0)
}
}
#[doc = "Global Timer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtimr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtimr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GtimrSpec;
impl crate::RegisterSpec for GtimrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gtimr::R`](R) reader structure"]
impl crate::Readable for GtimrSpec {}
#[doc = "`write(|w| ..)` method takes [`gtimr::W`](W) writer structure"]
impl crate::Writable for GtimrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GTIMR to value 0"]
impl crate::Resettable for GtimrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RESERVE0 (rw) register accessor: Reserve Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reserve0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reserve0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserve0`]
module"]
#[doc(alias = "RESERVE0")]
pub type Reserve0 = crate::Reg<reserve0::Reserve0Spec>;
#[doc = "Reserve Register 0"]
pub mod reserve0 {
#[doc = "Register `RESERVE0` reader"]
pub type R = crate::R<Reserve0Spec>;
#[doc = "Register `RESERVE0` writer"]
pub type W = crate::W<Reserve0Spec>;
#[doc = "Field `DATA` reader - "]
pub type DataR = crate::FieldReader<u32>;
#[doc = "Field `DATA` writer - "]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<Reserve0Spec> {
DataW::new(self, 0)
}
}
#[doc = "Reserve Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reserve0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reserve0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserve0Spec;
impl crate::RegisterSpec for Reserve0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`reserve0::R`](R) reader structure"]
impl crate::Readable for Reserve0Spec {}
#[doc = "`write(|w| ..)` method takes [`reserve0::W`](W) writer structure"]
impl crate::Writable for Reserve0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RESERVE0 to value 0"]
impl crate::Resettable for Reserve0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RESERVE1 (rw) register accessor: Reserve Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reserve1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reserve1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reserve1`]
module"]
#[doc(alias = "RESERVE1")]
pub type Reserve1 = crate::Reg<reserve1::Reserve1Spec>;
#[doc = "Reserve Register 1"]
pub mod reserve1 {
#[doc = "Register `RESERVE1` reader"]
pub type R = crate::R<Reserve1Spec>;
#[doc = "Register `RESERVE1` writer"]
pub type W = crate::W<Reserve1Spec>;
#[doc = "Field `DATA` reader - "]
pub type DataR = crate::FieldReader<u32>;
#[doc = "Field `DATA` writer - "]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<Reserve1Spec> {
DataW::new(self, 0)
}
}
#[doc = "Reserve Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reserve1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reserve1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Reserve1Spec;
impl crate::RegisterSpec for Reserve1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`reserve1::R`](R) reader structure"]
impl crate::Readable for Reserve1Spec {}
#[doc = "`write(|w| ..)` method takes [`reserve1::W`](W) writer structure"]
impl crate::Writable for Reserve1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RESERVE1 to value 0"]
impl crate::Resettable for Reserve1Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "LPTIM1"]
pub struct Lptim1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Lptim1 {}
impl Lptim1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const lptim1::RegisterBlock = 0x500c_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const lptim1::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Lptim1 {
type Target = lptim1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Lptim1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Lptim1").finish()
}
}
#[doc = "LPTIM1"]
pub mod lptim1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
isr: Isr,
icr: Icr,
ier: Ier,
cfgr: Cfgr,
cr: Cr,
cmp: Cmp,
arr: Arr,
cnt: Cnt,
rcr: Rcr,
}
impl RegisterBlock {
#[doc = "0x00 - LPTIM interrupt and status register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x04 - LPTIM interrupt and status clear register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x08 - LPTIM interrupt and wakeup enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x0c - LPTIM configuration register"]
#[inline(always)]
pub const fn cfgr(&self) -> &Cfgr {
&self.cfgr
}
#[doc = "0x10 - LPTIM control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x14 - LPTIM compare register"]
#[inline(always)]
pub const fn cmp(&self) -> &Cmp {
&self.cmp
}
#[doc = "0x18 - LPTIM autoreload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
#[doc = "0x1c - LPTIM counter register"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x20 - LPTIM repetition register"]
#[inline(always)]
pub const fn rcr(&self) -> &Rcr {
&self.rcr
}
}
#[doc = "ISR (rw) register accessor: LPTIM interrupt and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "LPTIM interrupt and status register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `UE` reader - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OF` reader - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
pub type OfR = crate::BitReader;
#[doc = "Field `OF` writer - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC` reader - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
pub type OcR = crate::BitReader;
#[doc = "Field `OC` writer - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
pub type OcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ET` reader - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
pub type EtR = crate::BitReader;
#[doc = "Field `ET` writer - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
pub type EtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `UEWKUP` reader - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type UewkupR = crate::BitReader;
#[doc = "Field `UEWKUP` writer - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type UewkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFWKUP` reader - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OfwkupR = crate::BitReader;
#[doc = "Field `OFWKUP` writer - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OfwkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCWKUP` reader - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OcwkupR = crate::BitReader;
#[doc = "Field `OCWKUP` writer - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OcwkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0 - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn of(&self) -> OfR {
OfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn oc(&self) -> OcR {
OcR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn et(&self) -> EtR {
EtR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn uewkup(&self) -> UewkupR {
UewkupR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ofwkup(&self) -> OfwkupR {
OfwkupR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ocwkup(&self) -> OcwkupR {
OcwkupR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0 - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<IsrSpec> {
UeW::new(self, 0)
}
#[doc = "Bit 1 - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn of(&mut self) -> OfW<IsrSpec> {
OfW::new(self, 1)
}
#[doc = "Bit 2 - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn oc(&mut self) -> OcW<IsrSpec> {
OcW::new(self, 2)
}
#[doc = "Bit 3 - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn et(&mut self) -> EtW<IsrSpec> {
EtW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn uewkup(&mut self) -> UewkupW<IsrSpec> {
UewkupW::new(self, 8)
}
#[doc = "Bit 9 - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ofwkup(&mut self) -> OfwkupW<IsrSpec> {
OfwkupW::new(self, 9)
}
#[doc = "Bit 10 - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ocwkup(&mut self) -> OcwkupW<IsrSpec> {
OcwkupW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "LPTIM interrupt and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: LPTIM interrupt and status clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "LPTIM interrupt and status clear register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `UECLR` reader - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
pub type UeclrR = crate::BitReader;
#[doc = "Field `UECLR` writer - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
pub type UeclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFCLR` reader - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
pub type OfclrR = crate::BitReader;
#[doc = "Field `OFCLR` writer - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
pub type OfclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCCLR` reader - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
pub type OcclrR = crate::BitReader;
#[doc = "Field `OCCLR` writer - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
pub type OcclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETCLR` reader - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
pub type EtclrR = crate::BitReader;
#[doc = "Field `ETCLR` writer - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
pub type EtclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `WKUPCLR` reader - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
pub type WkupclrR = crate::BitReader;
#[doc = "Field `WKUPCLR` writer - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
pub type WkupclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
#[inline(always)]
pub fn ueclr(&self) -> UeclrR {
UeclrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn ofclr(&self) -> OfclrR {
OfclrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn occlr(&self) -> OcclrR {
OcclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn etclr(&self) -> EtclrR {
EtclrR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
#[inline(always)]
pub fn wkupclr(&self) -> WkupclrR {
WkupclrR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
#[inline(always)]
#[must_use]
pub fn ueclr(&mut self) -> UeclrW<IcrSpec> {
UeclrW::new(self, 0)
}
#[doc = "Bit 1 - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn ofclr(&mut self) -> OfclrW<IcrSpec> {
OfclrW::new(self, 1)
}
#[doc = "Bit 2 - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn occlr(&mut self) -> OcclrW<IcrSpec> {
OcclrW::new(self, 2)
}
#[doc = "Bit 3 - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn etclr(&mut self) -> EtclrW<IcrSpec> {
EtclrW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
#[inline(always)]
#[must_use]
pub fn wkupclr(&mut self) -> WkupclrW<IcrSpec> {
WkupclrW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "LPTIM interrupt and status clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER (rw) register accessor: LPTIM interrupt and wakeup enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "LPTIM interrupt and wakeup enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `UEIE` reader - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
pub type UeieR = crate::BitReader;
#[doc = "Field `UEIE` writer - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
pub type UeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCIE` reader - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
pub type OcieR = crate::BitReader;
#[doc = "Field `OCIE` writer - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
pub type OcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETIE` reader - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
pub type EtieR = crate::BitReader;
#[doc = "Field `ETIE` writer - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
pub type EtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `UEWE` reader - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
pub type UeweR = crate::BitReader;
#[doc = "Field `UEWE` writer - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
pub type UeweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFWE` reader - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
pub type OfweR = crate::BitReader;
#[doc = "Field `OFWE` writer - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
pub type OfweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCWE` reader - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
pub type OcweR = crate::BitReader;
#[doc = "Field `OCWE` writer - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
pub type OcweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0 - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
#[inline(always)]
pub fn ueie(&self) -> UeieR {
UeieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
#[inline(always)]
pub fn ocie(&self) -> OcieR {
OcieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
#[inline(always)]
pub fn etie(&self) -> EtieR {
EtieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
#[inline(always)]
pub fn uewe(&self) -> UeweR {
UeweR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
#[inline(always)]
pub fn ofwe(&self) -> OfweR {
OfweR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
#[inline(always)]
pub fn ocwe(&self) -> OcweR {
OcweR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ueie(&mut self) -> UeieW<IerSpec> {
UeieW::new(self, 0)
}
#[doc = "Bit 1 - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ofie(&mut self) -> OfieW<IerSpec> {
OfieW::new(self, 1)
}
#[doc = "Bit 2 - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ocie(&mut self) -> OcieW<IerSpec> {
OcieW::new(self, 2)
}
#[doc = "Bit 3 - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn etie(&mut self) -> EtieW<IerSpec> {
EtieW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IerSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn uewe(&mut self) -> UeweW<IerSpec> {
UeweW::new(self, 8)
}
#[doc = "Bit 9 - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn ofwe(&mut self) -> OfweW<IerSpec> {
OfweW::new(self, 9)
}
#[doc = "Bit 10 - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn ocwe(&mut self) -> OcweW<IerSpec> {
OcweW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IerSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "LPTIM interrupt and wakeup enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CFGR (rw) register accessor: LPTIM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr`]
module"]
#[doc(alias = "CFGR")]
pub type Cfgr = crate::Reg<cfgr::CfgrSpec>;
#[doc = "LPTIM configuration register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub type R = crate::R<CfgrSpec>;
#[doc = "Register `CFGR` writer"]
pub type W = crate::W<CfgrSpec>;
#[doc = "Field `CKSEL` reader - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
pub type CkselR = crate::BitReader;
#[doc = "Field `CKSEL` writer - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
pub type CkselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CKPOL` reader - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
pub type CkpolR = crate::FieldReader;
#[doc = "Field `CKPOL` writer - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
pub type CkpolW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CKFLT` reader - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
pub type CkfltR = crate::FieldReader;
#[doc = "Field `CKFLT` writer - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
pub type CkfltW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `INTCKSEL` reader - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
pub type IntckselR = crate::BitReader;
#[doc = "Field `INTCKSEL` writer - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
pub type IntckselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRGFLT` reader - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
pub type TrgfltR = crate::FieldReader;
#[doc = "Field `TRGFLT` writer - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
pub type TrgfltW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `EXTCKSEL` reader - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
pub type ExtckselR = crate::BitReader;
#[doc = "Field `EXTCKSEL` writer - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
pub type ExtckselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRESC` reader - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
pub type PrescR = crate::FieldReader;
#[doc = "Field `PRESC` writer - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
pub type PrescW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRIGSEL` reader - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
pub type TrigselR = crate::FieldReader;
#[doc = "Field `TRIGSEL` writer - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
pub type TrigselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRIGEN` reader - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
pub type TrigenR = crate::FieldReader;
#[doc = "Field `TRIGEN` writer - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
pub type TrigenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `TIMOUT` reader - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
pub type TimoutR = crate::BitReader;
#[doc = "Field `TIMOUT` writer - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
pub type TimoutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WAVE` reader - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
pub type WaveR = crate::BitReader;
#[doc = "Field `WAVE` writer - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
pub type WaveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WAVPOL` reader - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
pub type WavpolR = crate::BitReader;
#[doc = "Field `WAVPOL` writer - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
pub type WavpolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COUNTMODE` reader - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
pub type CountmodeR = crate::BitReader;
#[doc = "Field `COUNTMODE` writer - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
pub type CountmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bit 0 - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
#[inline(always)]
pub fn cksel(&self) -> CkselR {
CkselR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
#[inline(always)]
pub fn ckpol(&self) -> CkpolR {
CkpolR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
#[inline(always)]
pub fn ckflt(&self) -> CkfltR {
CkfltR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
#[inline(always)]
pub fn intcksel(&self) -> IntckselR {
IntckselR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
#[inline(always)]
pub fn trgflt(&self) -> TrgfltR {
TrgfltR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8 - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
#[inline(always)]
pub fn extcksel(&self) -> ExtckselR {
ExtckselR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:11 - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
#[inline(always)]
pub fn presc(&self) -> PrescR {
PrescR::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15 - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
#[inline(always)]
pub fn trigsel(&self) -> TrigselR {
TrigselR::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18 - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
#[inline(always)]
pub fn trigen(&self) -> TrigenR {
TrigenR::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bit 19 - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
#[inline(always)]
pub fn timout(&self) -> TimoutR {
TimoutR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
#[inline(always)]
pub fn wave(&self) -> WaveR {
WaveR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
pub fn wavpol(&self) -> WavpolR {
WavpolR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
#[inline(always)]
pub fn countmode(&self) -> CountmodeR {
CountmodeR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0 - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
#[inline(always)]
#[must_use]
pub fn cksel(&mut self) -> CkselW<CfgrSpec> {
CkselW::new(self, 0)
}
#[doc = "Bits 1:2 - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
#[inline(always)]
#[must_use]
pub fn ckpol(&mut self) -> CkpolW<CfgrSpec> {
CkpolW::new(self, 1)
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
#[inline(always)]
#[must_use]
pub fn ckflt(&mut self) -> CkfltW<CfgrSpec> {
CkfltW::new(self, 3)
}
#[doc = "Bit 5 - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
#[inline(always)]
#[must_use]
pub fn intcksel(&mut self) -> IntckselW<CfgrSpec> {
IntckselW::new(self, 5)
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
#[inline(always)]
#[must_use]
pub fn trgflt(&mut self) -> TrgfltW<CfgrSpec> {
TrgfltW::new(self, 6)
}
#[doc = "Bit 8 - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
#[inline(always)]
#[must_use]
pub fn extcksel(&mut self) -> ExtckselW<CfgrSpec> {
ExtckselW::new(self, 8)
}
#[doc = "Bits 9:11 - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
#[inline(always)]
#[must_use]
pub fn presc(&mut self) -> PrescW<CfgrSpec> {
PrescW::new(self, 9)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CfgrSpec> {
Rsvd4W::new(self, 12)
}
#[doc = "Bits 13:15 - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
#[inline(always)]
#[must_use]
pub fn trigsel(&mut self) -> TrigselW<CfgrSpec> {
TrigselW::new(self, 13)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CfgrSpec> {
Rsvd3W::new(self, 16)
}
#[doc = "Bits 17:18 - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
#[inline(always)]
#[must_use]
pub fn trigen(&mut self) -> TrigenW<CfgrSpec> {
TrigenW::new(self, 17)
}
#[doc = "Bit 19 - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
#[inline(always)]
#[must_use]
pub fn timout(&mut self) -> TimoutW<CfgrSpec> {
TimoutW::new(self, 19)
}
#[doc = "Bit 20 - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
#[inline(always)]
#[must_use]
pub fn wave(&mut self) -> WaveW<CfgrSpec> {
WaveW::new(self, 20)
}
#[doc = "Bit 21 - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
#[must_use]
pub fn wavpol(&mut self) -> WavpolW<CfgrSpec> {
WavpolW::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CfgrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bit 23 - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
#[inline(always)]
#[must_use]
pub fn countmode(&mut self) -> CountmodeW<CfgrSpec> {
CountmodeW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CfgrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgrSpec;
impl crate::RegisterSpec for CfgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cfgr::R`](R) reader structure"]
impl crate::Readable for CfgrSpec {}
#[doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"]
impl crate::Writable for CfgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CFGR to value 0"]
impl crate::Resettable for CfgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR (rw) register accessor: LPTIM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "LPTIM control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `ENABLE` reader - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
pub type EnableR = crate::BitReader;
#[doc = "Field `ENABLE` writer - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SNGSTRT` reader - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
pub type SngstrtR = crate::BitReader;
#[doc = "Field `SNGSTRT` writer - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
pub type SngstrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CNTSTRT` reader - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
pub type CntstrtR = crate::BitReader;
#[doc = "Field `CNTSTRT` writer - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
pub type CntstrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COUNTRST` reader - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
pub type CountrstR = crate::BitReader;
#[doc = "Field `COUNTRST` writer - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
pub type CountrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
#[inline(always)]
pub fn enable(&self) -> EnableR {
EnableR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
#[inline(always)]
pub fn sngstrt(&self) -> SngstrtR {
SngstrtR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
#[inline(always)]
pub fn cntstrt(&self) -> CntstrtR {
CntstrtR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
#[inline(always)]
pub fn countrst(&self) -> CountrstR {
CountrstR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<CrSpec> {
EnableW::new(self, 0)
}
#[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
#[inline(always)]
#[must_use]
pub fn sngstrt(&mut self) -> SngstrtW<CrSpec> {
SngstrtW::new(self, 1)
}
#[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
#[inline(always)]
#[must_use]
pub fn cntstrt(&mut self) -> CntstrtW<CrSpec> {
CntstrtW::new(self, 2)
}
#[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
#[inline(always)]
#[must_use]
pub fn countrst(&mut self) -> CountrstW<CrSpec> {
CountrstW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "LPTIM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CMP (rw) register accessor: LPTIM compare register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp`]
module"]
#[doc(alias = "CMP")]
pub type Cmp = crate::Reg<cmp::CmpSpec>;
#[doc = "LPTIM compare register"]
pub mod cmp {
#[doc = "Register `CMP` reader"]
pub type R = crate::R<CmpSpec>;
#[doc = "Register `CMP` writer"]
pub type W = crate::W<CmpSpec>;
#[doc = "Field `CMP` reader - Compare value CMP is the compare value used by the LPTIM."]
pub type CmpR = crate::FieldReader<u32>;
#[doc = "Field `CMP` writer - Compare value CMP is the compare value used by the LPTIM."]
pub type CmpW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Compare value CMP is the compare value used by the LPTIM."]
#[inline(always)]
pub fn cmp(&self) -> CmpR {
CmpR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Compare value CMP is the compare value used by the LPTIM."]
#[inline(always)]
#[must_use]
pub fn cmp(&mut self) -> CmpW<CmpSpec> {
CmpW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CmpSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM compare register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpSpec;
impl crate::RegisterSpec for CmpSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cmp::R`](R) reader structure"]
impl crate::Readable for CmpSpec {}
#[doc = "`write(|w| ..)` method takes [`cmp::W`](W) writer structure"]
impl crate::Writable for CmpSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMP to value 0"]
impl crate::Resettable for CmpSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: LPTIM autoreload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "LPTIM autoreload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ArrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM autoreload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: LPTIM counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "LPTIM counter register"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CntSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RCR (rw) register accessor: LPTIM repetition register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcr`]
module"]
#[doc(alias = "RCR")]
pub type Rcr = crate::Reg<rcr::RcrSpec>;
#[doc = "LPTIM repetition register"]
pub mod rcr {
#[doc = "Register `RCR` reader"]
pub type R = crate::R<RcrSpec>;
#[doc = "Register `RCR` writer"]
pub type W = crate::W<RcrSpec>;
#[doc = "Field `REP` reader - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
pub type RepR = crate::FieldReader;
#[doc = "Field `REP` writer - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
pub type RepW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
#[inline(always)]
pub fn rep(&self) -> RepR {
RepR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
#[inline(always)]
#[must_use]
pub fn rep(&mut self) -> RepW<RcrSpec> {
RepW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "LPTIM repetition register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RcrSpec;
impl crate::RegisterSpec for RcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rcr::R`](R) reader structure"]
impl crate::Readable for RcrSpec {}
#[doc = "`write(|w| ..)` method takes [`rcr::W`](W) writer structure"]
impl crate::Writable for RcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCR to value 0"]
impl crate::Resettable for RcrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "LPTIM2"]
pub struct Lptim2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Lptim2 {}
impl Lptim2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const lptim2::RegisterBlock = 0x500c_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const lptim2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Lptim2 {
type Target = lptim2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Lptim2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Lptim2").finish()
}
}
#[doc = "LPTIM2"]
pub mod lptim2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
isr: Isr,
icr: Icr,
ier: Ier,
cfgr: Cfgr,
cr: Cr,
cmp: Cmp,
arr: Arr,
cnt: Cnt,
rcr: Rcr,
}
impl RegisterBlock {
#[doc = "0x00 - LPTIM interrupt and status register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x04 - LPTIM interrupt and status clear register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x08 - LPTIM interrupt and wakeup enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x0c - LPTIM configuration register"]
#[inline(always)]
pub const fn cfgr(&self) -> &Cfgr {
&self.cfgr
}
#[doc = "0x10 - LPTIM control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x14 - LPTIM compare register"]
#[inline(always)]
pub const fn cmp(&self) -> &Cmp {
&self.cmp
}
#[doc = "0x18 - LPTIM autoreload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
#[doc = "0x1c - LPTIM counter register"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x20 - LPTIM repetition register"]
#[inline(always)]
pub const fn rcr(&self) -> &Rcr {
&self.rcr
}
}
#[doc = "ISR (rw) register accessor: LPTIM interrupt and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "LPTIM interrupt and status register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `UE` reader - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OF` reader - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
pub type OfR = crate::BitReader;
#[doc = "Field `OF` writer - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC` reader - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
pub type OcR = crate::BitReader;
#[doc = "Field `OC` writer - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
pub type OcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ET` reader - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
pub type EtR = crate::BitReader;
#[doc = "Field `ET` writer - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
pub type EtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `UEWKUP` reader - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type UewkupR = crate::BitReader;
#[doc = "Field `UEWKUP` writer - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type UewkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFWKUP` reader - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OfwkupR = crate::BitReader;
#[doc = "Field `OFWKUP` writer - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OfwkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCWKUP` reader - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OcwkupR = crate::BitReader;
#[doc = "Field `OCWKUP` writer - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OcwkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0 - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn of(&self) -> OfR {
OfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn oc(&self) -> OcR {
OcR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn et(&self) -> EtR {
EtR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn uewkup(&self) -> UewkupR {
UewkupR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ofwkup(&self) -> OfwkupR {
OfwkupR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ocwkup(&self) -> OcwkupR {
OcwkupR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0 - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<IsrSpec> {
UeW::new(self, 0)
}
#[doc = "Bit 1 - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn of(&mut self) -> OfW<IsrSpec> {
OfW::new(self, 1)
}
#[doc = "Bit 2 - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn oc(&mut self) -> OcW<IsrSpec> {
OcW::new(self, 2)
}
#[doc = "Bit 3 - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn et(&mut self) -> EtW<IsrSpec> {
EtW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn uewkup(&mut self) -> UewkupW<IsrSpec> {
UewkupW::new(self, 8)
}
#[doc = "Bit 9 - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ofwkup(&mut self) -> OfwkupW<IsrSpec> {
OfwkupW::new(self, 9)
}
#[doc = "Bit 10 - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ocwkup(&mut self) -> OcwkupW<IsrSpec> {
OcwkupW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "LPTIM interrupt and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: LPTIM interrupt and status clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "LPTIM interrupt and status clear register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `UECLR` reader - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
pub type UeclrR = crate::BitReader;
#[doc = "Field `UECLR` writer - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
pub type UeclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFCLR` reader - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
pub type OfclrR = crate::BitReader;
#[doc = "Field `OFCLR` writer - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
pub type OfclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCCLR` reader - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
pub type OcclrR = crate::BitReader;
#[doc = "Field `OCCLR` writer - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
pub type OcclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETCLR` reader - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
pub type EtclrR = crate::BitReader;
#[doc = "Field `ETCLR` writer - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
pub type EtclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `WKUPCLR` reader - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
pub type WkupclrR = crate::BitReader;
#[doc = "Field `WKUPCLR` writer - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
pub type WkupclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
#[inline(always)]
pub fn ueclr(&self) -> UeclrR {
UeclrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn ofclr(&self) -> OfclrR {
OfclrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn occlr(&self) -> OcclrR {
OcclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn etclr(&self) -> EtclrR {
EtclrR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
#[inline(always)]
pub fn wkupclr(&self) -> WkupclrR {
WkupclrR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
#[inline(always)]
#[must_use]
pub fn ueclr(&mut self) -> UeclrW<IcrSpec> {
UeclrW::new(self, 0)
}
#[doc = "Bit 1 - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn ofclr(&mut self) -> OfclrW<IcrSpec> {
OfclrW::new(self, 1)
}
#[doc = "Bit 2 - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn occlr(&mut self) -> OcclrW<IcrSpec> {
OcclrW::new(self, 2)
}
#[doc = "Bit 3 - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn etclr(&mut self) -> EtclrW<IcrSpec> {
EtclrW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
#[inline(always)]
#[must_use]
pub fn wkupclr(&mut self) -> WkupclrW<IcrSpec> {
WkupclrW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "LPTIM interrupt and status clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER (rw) register accessor: LPTIM interrupt and wakeup enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "LPTIM interrupt and wakeup enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `UEIE` reader - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
pub type UeieR = crate::BitReader;
#[doc = "Field `UEIE` writer - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
pub type UeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCIE` reader - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
pub type OcieR = crate::BitReader;
#[doc = "Field `OCIE` writer - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
pub type OcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETIE` reader - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
pub type EtieR = crate::BitReader;
#[doc = "Field `ETIE` writer - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
pub type EtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `UEWE` reader - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
pub type UeweR = crate::BitReader;
#[doc = "Field `UEWE` writer - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
pub type UeweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFWE` reader - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
pub type OfweR = crate::BitReader;
#[doc = "Field `OFWE` writer - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
pub type OfweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCWE` reader - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
pub type OcweR = crate::BitReader;
#[doc = "Field `OCWE` writer - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
pub type OcweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0 - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
#[inline(always)]
pub fn ueie(&self) -> UeieR {
UeieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
#[inline(always)]
pub fn ocie(&self) -> OcieR {
OcieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
#[inline(always)]
pub fn etie(&self) -> EtieR {
EtieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
#[inline(always)]
pub fn uewe(&self) -> UeweR {
UeweR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
#[inline(always)]
pub fn ofwe(&self) -> OfweR {
OfweR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
#[inline(always)]
pub fn ocwe(&self) -> OcweR {
OcweR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ueie(&mut self) -> UeieW<IerSpec> {
UeieW::new(self, 0)
}
#[doc = "Bit 1 - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ofie(&mut self) -> OfieW<IerSpec> {
OfieW::new(self, 1)
}
#[doc = "Bit 2 - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ocie(&mut self) -> OcieW<IerSpec> {
OcieW::new(self, 2)
}
#[doc = "Bit 3 - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn etie(&mut self) -> EtieW<IerSpec> {
EtieW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IerSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn uewe(&mut self) -> UeweW<IerSpec> {
UeweW::new(self, 8)
}
#[doc = "Bit 9 - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn ofwe(&mut self) -> OfweW<IerSpec> {
OfweW::new(self, 9)
}
#[doc = "Bit 10 - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn ocwe(&mut self) -> OcweW<IerSpec> {
OcweW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IerSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "LPTIM interrupt and wakeup enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CFGR (rw) register accessor: LPTIM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr`]
module"]
#[doc(alias = "CFGR")]
pub type Cfgr = crate::Reg<cfgr::CfgrSpec>;
#[doc = "LPTIM configuration register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub type R = crate::R<CfgrSpec>;
#[doc = "Register `CFGR` writer"]
pub type W = crate::W<CfgrSpec>;
#[doc = "Field `CKSEL` reader - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
pub type CkselR = crate::BitReader;
#[doc = "Field `CKSEL` writer - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
pub type CkselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CKPOL` reader - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
pub type CkpolR = crate::FieldReader;
#[doc = "Field `CKPOL` writer - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
pub type CkpolW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CKFLT` reader - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
pub type CkfltR = crate::FieldReader;
#[doc = "Field `CKFLT` writer - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
pub type CkfltW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `INTCKSEL` reader - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
pub type IntckselR = crate::BitReader;
#[doc = "Field `INTCKSEL` writer - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
pub type IntckselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRGFLT` reader - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
pub type TrgfltR = crate::FieldReader;
#[doc = "Field `TRGFLT` writer - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
pub type TrgfltW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `EXTCKSEL` reader - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
pub type ExtckselR = crate::BitReader;
#[doc = "Field `EXTCKSEL` writer - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
pub type ExtckselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRESC` reader - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
pub type PrescR = crate::FieldReader;
#[doc = "Field `PRESC` writer - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
pub type PrescW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRIGSEL` reader - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
pub type TrigselR = crate::FieldReader;
#[doc = "Field `TRIGSEL` writer - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
pub type TrigselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRIGEN` reader - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
pub type TrigenR = crate::FieldReader;
#[doc = "Field `TRIGEN` writer - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
pub type TrigenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `TIMOUT` reader - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
pub type TimoutR = crate::BitReader;
#[doc = "Field `TIMOUT` writer - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
pub type TimoutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WAVE` reader - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
pub type WaveR = crate::BitReader;
#[doc = "Field `WAVE` writer - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
pub type WaveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WAVPOL` reader - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
pub type WavpolR = crate::BitReader;
#[doc = "Field `WAVPOL` writer - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
pub type WavpolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COUNTMODE` reader - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
pub type CountmodeR = crate::BitReader;
#[doc = "Field `COUNTMODE` writer - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
pub type CountmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bit 0 - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
#[inline(always)]
pub fn cksel(&self) -> CkselR {
CkselR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
#[inline(always)]
pub fn ckpol(&self) -> CkpolR {
CkpolR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
#[inline(always)]
pub fn ckflt(&self) -> CkfltR {
CkfltR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
#[inline(always)]
pub fn intcksel(&self) -> IntckselR {
IntckselR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
#[inline(always)]
pub fn trgflt(&self) -> TrgfltR {
TrgfltR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8 - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
#[inline(always)]
pub fn extcksel(&self) -> ExtckselR {
ExtckselR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:11 - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
#[inline(always)]
pub fn presc(&self) -> PrescR {
PrescR::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15 - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
#[inline(always)]
pub fn trigsel(&self) -> TrigselR {
TrigselR::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18 - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
#[inline(always)]
pub fn trigen(&self) -> TrigenR {
TrigenR::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bit 19 - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
#[inline(always)]
pub fn timout(&self) -> TimoutR {
TimoutR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
#[inline(always)]
pub fn wave(&self) -> WaveR {
WaveR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
pub fn wavpol(&self) -> WavpolR {
WavpolR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
#[inline(always)]
pub fn countmode(&self) -> CountmodeR {
CountmodeR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0 - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
#[inline(always)]
#[must_use]
pub fn cksel(&mut self) -> CkselW<CfgrSpec> {
CkselW::new(self, 0)
}
#[doc = "Bits 1:2 - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
#[inline(always)]
#[must_use]
pub fn ckpol(&mut self) -> CkpolW<CfgrSpec> {
CkpolW::new(self, 1)
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
#[inline(always)]
#[must_use]
pub fn ckflt(&mut self) -> CkfltW<CfgrSpec> {
CkfltW::new(self, 3)
}
#[doc = "Bit 5 - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
#[inline(always)]
#[must_use]
pub fn intcksel(&mut self) -> IntckselW<CfgrSpec> {
IntckselW::new(self, 5)
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
#[inline(always)]
#[must_use]
pub fn trgflt(&mut self) -> TrgfltW<CfgrSpec> {
TrgfltW::new(self, 6)
}
#[doc = "Bit 8 - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
#[inline(always)]
#[must_use]
pub fn extcksel(&mut self) -> ExtckselW<CfgrSpec> {
ExtckselW::new(self, 8)
}
#[doc = "Bits 9:11 - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
#[inline(always)]
#[must_use]
pub fn presc(&mut self) -> PrescW<CfgrSpec> {
PrescW::new(self, 9)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CfgrSpec> {
Rsvd4W::new(self, 12)
}
#[doc = "Bits 13:15 - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
#[inline(always)]
#[must_use]
pub fn trigsel(&mut self) -> TrigselW<CfgrSpec> {
TrigselW::new(self, 13)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CfgrSpec> {
Rsvd3W::new(self, 16)
}
#[doc = "Bits 17:18 - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
#[inline(always)]
#[must_use]
pub fn trigen(&mut self) -> TrigenW<CfgrSpec> {
TrigenW::new(self, 17)
}
#[doc = "Bit 19 - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
#[inline(always)]
#[must_use]
pub fn timout(&mut self) -> TimoutW<CfgrSpec> {
TimoutW::new(self, 19)
}
#[doc = "Bit 20 - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
#[inline(always)]
#[must_use]
pub fn wave(&mut self) -> WaveW<CfgrSpec> {
WaveW::new(self, 20)
}
#[doc = "Bit 21 - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
#[must_use]
pub fn wavpol(&mut self) -> WavpolW<CfgrSpec> {
WavpolW::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CfgrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bit 23 - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
#[inline(always)]
#[must_use]
pub fn countmode(&mut self) -> CountmodeW<CfgrSpec> {
CountmodeW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CfgrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgrSpec;
impl crate::RegisterSpec for CfgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cfgr::R`](R) reader structure"]
impl crate::Readable for CfgrSpec {}
#[doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"]
impl crate::Writable for CfgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CFGR to value 0"]
impl crate::Resettable for CfgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR (rw) register accessor: LPTIM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "LPTIM control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `ENABLE` reader - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
pub type EnableR = crate::BitReader;
#[doc = "Field `ENABLE` writer - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SNGSTRT` reader - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
pub type SngstrtR = crate::BitReader;
#[doc = "Field `SNGSTRT` writer - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
pub type SngstrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CNTSTRT` reader - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
pub type CntstrtR = crate::BitReader;
#[doc = "Field `CNTSTRT` writer - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
pub type CntstrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COUNTRST` reader - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
pub type CountrstR = crate::BitReader;
#[doc = "Field `COUNTRST` writer - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
pub type CountrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
#[inline(always)]
pub fn enable(&self) -> EnableR {
EnableR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
#[inline(always)]
pub fn sngstrt(&self) -> SngstrtR {
SngstrtR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
#[inline(always)]
pub fn cntstrt(&self) -> CntstrtR {
CntstrtR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
#[inline(always)]
pub fn countrst(&self) -> CountrstR {
CountrstR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<CrSpec> {
EnableW::new(self, 0)
}
#[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
#[inline(always)]
#[must_use]
pub fn sngstrt(&mut self) -> SngstrtW<CrSpec> {
SngstrtW::new(self, 1)
}
#[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
#[inline(always)]
#[must_use]
pub fn cntstrt(&mut self) -> CntstrtW<CrSpec> {
CntstrtW::new(self, 2)
}
#[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
#[inline(always)]
#[must_use]
pub fn countrst(&mut self) -> CountrstW<CrSpec> {
CountrstW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "LPTIM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CMP (rw) register accessor: LPTIM compare register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp`]
module"]
#[doc(alias = "CMP")]
pub type Cmp = crate::Reg<cmp::CmpSpec>;
#[doc = "LPTIM compare register"]
pub mod cmp {
#[doc = "Register `CMP` reader"]
pub type R = crate::R<CmpSpec>;
#[doc = "Register `CMP` writer"]
pub type W = crate::W<CmpSpec>;
#[doc = "Field `CMP` reader - Compare value CMP is the compare value used by the LPTIM."]
pub type CmpR = crate::FieldReader<u32>;
#[doc = "Field `CMP` writer - Compare value CMP is the compare value used by the LPTIM."]
pub type CmpW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Compare value CMP is the compare value used by the LPTIM."]
#[inline(always)]
pub fn cmp(&self) -> CmpR {
CmpR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Compare value CMP is the compare value used by the LPTIM."]
#[inline(always)]
#[must_use]
pub fn cmp(&mut self) -> CmpW<CmpSpec> {
CmpW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CmpSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM compare register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpSpec;
impl crate::RegisterSpec for CmpSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cmp::R`](R) reader structure"]
impl crate::Readable for CmpSpec {}
#[doc = "`write(|w| ..)` method takes [`cmp::W`](W) writer structure"]
impl crate::Writable for CmpSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMP to value 0"]
impl crate::Resettable for CmpSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: LPTIM autoreload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "LPTIM autoreload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ArrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM autoreload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: LPTIM counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "LPTIM counter register"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CntSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RCR (rw) register accessor: LPTIM repetition register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcr`]
module"]
#[doc(alias = "RCR")]
pub type Rcr = crate::Reg<rcr::RcrSpec>;
#[doc = "LPTIM repetition register"]
pub mod rcr {
#[doc = "Register `RCR` reader"]
pub type R = crate::R<RcrSpec>;
#[doc = "Register `RCR` writer"]
pub type W = crate::W<RcrSpec>;
#[doc = "Field `REP` reader - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
pub type RepR = crate::FieldReader;
#[doc = "Field `REP` writer - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
pub type RepW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
#[inline(always)]
pub fn rep(&self) -> RepR {
RepR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
#[inline(always)]
#[must_use]
pub fn rep(&mut self) -> RepW<RcrSpec> {
RepW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "LPTIM repetition register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RcrSpec;
impl crate::RegisterSpec for RcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rcr::R`](R) reader structure"]
impl crate::Readable for RcrSpec {}
#[doc = "`write(|w| ..)` method takes [`rcr::W`](W) writer structure"]
impl crate::Writable for RcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCR to value 0"]
impl crate::Resettable for RcrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "RTC"]
pub struct Rtc {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Rtc {}
impl Rtc {
#[doc = r"Pointer to the register block"]
pub const PTR: *const rtc::RegisterBlock = 0x500c_b000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const rtc::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Rtc {
type Target = rtc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Rtc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rtc").finish()
}
}
#[doc = "RTC"]
pub mod rtc {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
tr: Tr,
dr: Dr,
cr: Cr,
isr: Isr,
psclr: Psclr,
wutr: Wutr,
alrmtr: Alrmtr,
alrmdr: Alrmdr,
shiftr: Shiftr,
tstr: Tstr,
tsdr: Tsdr,
or: Or,
bkp0r: Bkp0r,
bkp1r: Bkp1r,
bkp2r: Bkp2r,
bkp3r: Bkp3r,
bkp4r: Bkp4r,
bkp5r: Bkp5r,
bkp6r: Bkp6r,
bkp7r: Bkp7r,
bkp8r: Bkp8r,
bkp9r: Bkp9r,
pbrcr: Pbrcr,
pbr0r: Pbr0r,
pbr1r: Pbr1r,
pbr2r: Pbr2r,
pbr3r: Pbr3r,
pawk1r: Pawk1r,
pawk2r: Pawk2r,
pawk3r: Pawk3r,
}
impl RegisterBlock {
#[doc = "0x00 - Time Register"]
#[inline(always)]
pub const fn tr(&self) -> &Tr {
&self.tr
}
#[doc = "0x04 - Date Register"]
#[inline(always)]
pub const fn dr(&self) -> &Dr {
&self.dr
}
#[doc = "0x08 - Control Register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x0c - Initialization and Status Register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x10 - Prescaler Register"]
#[inline(always)]
pub const fn psclr(&self) -> &Psclr {
&self.psclr
}
#[doc = "0x14 - Wakeup Timer Register"]
#[inline(always)]
pub const fn wutr(&self) -> &Wutr {
&self.wutr
}
#[doc = "0x18 - Alarm Time Register"]
#[inline(always)]
pub const fn alrmtr(&self) -> &Alrmtr {
&self.alrmtr
}
#[doc = "0x1c - Alarm Date Register"]
#[inline(always)]
pub const fn alrmdr(&self) -> &Alrmdr {
&self.alrmdr
}
#[doc = "0x20 - Shift Control Register"]
#[inline(always)]
pub const fn shiftr(&self) -> &Shiftr {
&self.shiftr
}
#[doc = "0x24 - Timestamp Time Register"]
#[inline(always)]
pub const fn tstr(&self) -> &Tstr {
&self.tstr
}
#[doc = "0x28 - Timestamp Date Register"]
#[inline(always)]
pub const fn tsdr(&self) -> &Tsdr {
&self.tsdr
}
#[doc = "0x2c - "]
#[inline(always)]
pub const fn or(&self) -> &Or {
&self.or
}
#[doc = "0x30 - Backup 0 Register"]
#[inline(always)]
pub const fn bkp0r(&self) -> &Bkp0r {
&self.bkp0r
}
#[doc = "0x34 - Backup 1 Register"]
#[inline(always)]
pub const fn bkp1r(&self) -> &Bkp1r {
&self.bkp1r
}
#[doc = "0x38 - Backup 2 Register"]
#[inline(always)]
pub const fn bkp2r(&self) -> &Bkp2r {
&self.bkp2r
}
#[doc = "0x3c - Backup 3 Register"]
#[inline(always)]
pub const fn bkp3r(&self) -> &Bkp3r {
&self.bkp3r
}
#[doc = "0x40 - Backup 4 Register"]
#[inline(always)]
pub const fn bkp4r(&self) -> &Bkp4r {
&self.bkp4r
}
#[doc = "0x44 - Backup 5 Register"]
#[inline(always)]
pub const fn bkp5r(&self) -> &Bkp5r {
&self.bkp5r
}
#[doc = "0x48 - Backup 6 Register"]
#[inline(always)]
pub const fn bkp6r(&self) -> &Bkp6r {
&self.bkp6r
}
#[doc = "0x4c - Backup 7 Register"]
#[inline(always)]
pub const fn bkp7r(&self) -> &Bkp7r {
&self.bkp7r
}
#[doc = "0x50 - Backup 8 Register"]
#[inline(always)]
pub const fn bkp8r(&self) -> &Bkp8r {
&self.bkp8r
}
#[doc = "0x54 - Backup 9 Register"]
#[inline(always)]
pub const fn bkp9r(&self) -> &Bkp9r {
&self.bkp9r
}
#[doc = "0x58 - PBR Control Register"]
#[inline(always)]
pub const fn pbrcr(&self) -> &Pbrcr {
&self.pbrcr
}
#[doc = "0x5c - PBR0 Register"]
#[inline(always)]
pub const fn pbr0r(&self) -> &Pbr0r {
&self.pbr0r
}
#[doc = "0x60 - PBR1 Register"]
#[inline(always)]
pub const fn pbr1r(&self) -> &Pbr1r {
&self.pbr1r
}
#[doc = "0x64 - PBR2 Register"]
#[inline(always)]
pub const fn pbr2r(&self) -> &Pbr2r {
&self.pbr2r
}
#[doc = "0x68 - PBR3 Register"]
#[inline(always)]
pub const fn pbr3r(&self) -> &Pbr3r {
&self.pbr3r
}
#[doc = "0x6c - PA Wakeup Register 1"]
#[inline(always)]
pub const fn pawk1r(&self) -> &Pawk1r {
&self.pawk1r
}
#[doc = "0x70 - PA Wakeup Register 2"]
#[inline(always)]
pub const fn pawk2r(&self) -> &Pawk2r {
&self.pawk2r
}
#[doc = "0x74 - PA Wakeup Register 3"]
#[inline(always)]
pub const fn pawk3r(&self) -> &Pawk3r {
&self.pawk3r
}
}
#[doc = "TR (rw) register accessor: Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tr`]
module"]
#[doc(alias = "TR")]
pub type Tr = crate::Reg<tr::TrSpec>;
#[doc = "Time Register"]
pub mod tr {
#[doc = "Register `TR` reader"]
pub type R = crate::R<TrSpec>;
#[doc = "Register `TR` writer"]
pub type W = crate::W<TrSpec>;
#[doc = "Field `SS` reader - "]
pub type SsR = crate::FieldReader<u16>;
#[doc = "Field `SS` writer - "]
pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SU` reader - "]
pub type SuR = crate::FieldReader;
#[doc = "Field `SU` writer - "]
pub type SuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `ST` reader - "]
pub type StR = crate::FieldReader;
#[doc = "Field `ST` writer - "]
pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `MNU` reader - "]
pub type MnuR = crate::FieldReader;
#[doc = "Field `MNU` writer - "]
pub type MnuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MNT` reader - "]
pub type MntR = crate::FieldReader;
#[doc = "Field `MNT` writer - "]
pub type MntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `HU` reader - "]
pub type HuR = crate::FieldReader;
#[doc = "Field `HU` writer - "]
pub type HuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `HT` reader - "]
pub type HtR = crate::FieldReader;
#[doc = "Field `HT` writer - "]
pub type HtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PM` reader - "]
pub type PmR = crate::BitReader;
#[doc = "Field `PM` writer - "]
pub type PmW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn ss(&self) -> SsR {
SsR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:14"]
#[inline(always)]
pub fn su(&self) -> SuR {
SuR::new(((self.bits >> 11) & 0x0f) as u8)
}
#[doc = "Bits 15:17"]
#[inline(always)]
pub fn st(&self) -> StR {
StR::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:21"]
#[inline(always)]
pub fn mnu(&self) -> MnuR {
MnuR::new(((self.bits >> 18) & 0x0f) as u8)
}
#[doc = "Bits 22:24"]
#[inline(always)]
pub fn mnt(&self) -> MntR {
MntR::new(((self.bits >> 22) & 7) as u8)
}
#[doc = "Bits 25:28"]
#[inline(always)]
pub fn hu(&self) -> HuR {
HuR::new(((self.bits >> 25) & 0x0f) as u8)
}
#[doc = "Bits 29:30"]
#[inline(always)]
pub fn ht(&self) -> HtR {
HtR::new(((self.bits >> 29) & 3) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn pm(&self) -> PmR {
PmR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn ss(&mut self) -> SsW<TrSpec> {
SsW::new(self, 0)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TrSpec> {
RsvdW::new(self, 10)
}
#[doc = "Bits 11:14"]
#[inline(always)]
#[must_use]
pub fn su(&mut self) -> SuW<TrSpec> {
SuW::new(self, 11)
}
#[doc = "Bits 15:17"]
#[inline(always)]
#[must_use]
pub fn st(&mut self) -> StW<TrSpec> {
StW::new(self, 15)
}
#[doc = "Bits 18:21"]
#[inline(always)]
#[must_use]
pub fn mnu(&mut self) -> MnuW<TrSpec> {
MnuW::new(self, 18)
}
#[doc = "Bits 22:24"]
#[inline(always)]
#[must_use]
pub fn mnt(&mut self) -> MntW<TrSpec> {
MntW::new(self, 22)
}
#[doc = "Bits 25:28"]
#[inline(always)]
#[must_use]
pub fn hu(&mut self) -> HuW<TrSpec> {
HuW::new(self, 25)
}
#[doc = "Bits 29:30"]
#[inline(always)]
#[must_use]
pub fn ht(&mut self) -> HtW<TrSpec> {
HtW::new(self, 29)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn pm(&mut self) -> PmW<TrSpec> {
PmW::new(self, 31)
}
}
#[doc = "Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TrSpec;
impl crate::RegisterSpec for TrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tr::R`](R) reader structure"]
impl crate::Readable for TrSpec {}
#[doc = "`write(|w| ..)` method takes [`tr::W`](W) writer structure"]
impl crate::Writable for TrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TR to value 0"]
impl crate::Resettable for TrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DR (rw) register accessor: Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`]
module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "Date Register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `DU` reader - "]
pub type DuR = crate::FieldReader;
#[doc = "Field `DU` writer - "]
pub type DuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DT` reader - "]
pub type DtR = crate::FieldReader;
#[doc = "Field `DT` writer - "]
pub type DtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MU` reader - "]
pub type MuR = crate::FieldReader;
#[doc = "Field `MU` writer - "]
pub type MuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MT` reader - "]
pub type MtR = crate::BitReader;
#[doc = "Field `MT` writer - "]
pub type MtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WD` reader - "]
pub type WdR = crate::FieldReader;
#[doc = "Field `WD` writer - "]
pub type WdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `YU` reader - "]
pub type YuR = crate::FieldReader;
#[doc = "Field `YU` writer - "]
pub type YuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `YT` reader - "]
pub type YtR = crate::FieldReader;
#[doc = "Field `YT` writer - "]
pub type YtW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CB` reader - century bit, 0 - 2000s, 1 - 1900s/2100s"]
pub type CbR = crate::BitReader;
#[doc = "Field `CB` writer - century bit, 0 - 2000s, 1 - 1900s/2100s"]
pub type CbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `ERR` reader - "]
pub type ErrR = crate::BitReader;
#[doc = "Field `ERR` writer - "]
pub type ErrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn du(&self) -> DuR {
DuR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn dt(&self) -> DtR {
DtR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn mu(&self) -> MuR {
MuR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn mt(&self) -> MtR {
MtR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15"]
#[inline(always)]
pub fn wd(&self) -> WdR {
WdR::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn yu(&self) -> YuR {
YuR::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23"]
#[inline(always)]
pub fn yt(&self) -> YtR {
YtR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24 - century bit, 0 - 2000s, 1 - 1900s/2100s"]
#[inline(always)]
pub fn cb(&self) -> CbR {
CbR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 25) & 0x3f) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn err(&self) -> ErrR {
ErrR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn du(&mut self) -> DuW<DrSpec> {
DuW::new(self, 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn dt(&mut self) -> DtW<DrSpec> {
DtW::new(self, 4)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn mu(&mut self) -> MuW<DrSpec> {
MuW::new(self, 8)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn mt(&mut self) -> MtW<DrSpec> {
MtW::new(self, 12)
}
#[doc = "Bits 13:15"]
#[inline(always)]
#[must_use]
pub fn wd(&mut self) -> WdW<DrSpec> {
WdW::new(self, 13)
}
#[doc = "Bits 16:19"]
#[inline(always)]
#[must_use]
pub fn yu(&mut self) -> YuW<DrSpec> {
YuW::new(self, 16)
}
#[doc = "Bits 20:23"]
#[inline(always)]
#[must_use]
pub fn yt(&mut self) -> YtW<DrSpec> {
YtW::new(self, 20)
}
#[doc = "Bit 24 - century bit, 0 - 2000s, 1 - 1900s/2100s"]
#[inline(always)]
#[must_use]
pub fn cb(&mut self) -> CbW<DrSpec> {
CbW::new(self, 24)
}
#[doc = "Bits 25:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DrSpec> {
RsvdW::new(self, 25)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn err(&mut self) -> ErrW<DrSpec> {
ErrW::new(self, 31)
}
}
#[doc = "Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `WUCKSEL` reader - "]
pub type WuckselR = crate::BitReader;
#[doc = "Field `WUCKSEL` writer - "]
pub type WuckselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `TSEDGE` reader - "]
pub type TsedgeR = crate::BitReader;
#[doc = "Field `TSEDGE` writer - "]
pub type TsedgeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `FMT` reader - "]
pub type FmtR = crate::BitReader;
#[doc = "Field `FMT` writer - "]
pub type FmtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALRME` reader - "]
pub type AlrmeR = crate::BitReader;
#[doc = "Field `ALRME` writer - "]
pub type AlrmeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WUTE` reader - "]
pub type WuteR = crate::BitReader;
#[doc = "Field `WUTE` writer - "]
pub type WuteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSE` reader - "]
pub type TseR = crate::BitReader;
#[doc = "Field `TSE` writer - "]
pub type TseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALRMIE` reader - "]
pub type AlrmieR = crate::BitReader;
#[doc = "Field `ALRMIE` writer - "]
pub type AlrmieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WUTIE` reader - "]
pub type WutieR = crate::BitReader;
#[doc = "Field `WUTIE` writer - "]
pub type WutieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSIE` reader - "]
pub type TsieR = crate::BitReader;
#[doc = "Field `TSIE` writer - "]
pub type TsieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn wucksel(&self) -> WuckselR {
WuckselR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tsedge(&self) -> TsedgeR {
TsedgeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn fmt(&self) -> FmtR {
FmtR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn alrme(&self) -> AlrmeR {
AlrmeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn wute(&self) -> WuteR {
WuteR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn tse(&self) -> TseR {
TseR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn alrmie(&self) -> AlrmieR {
AlrmieR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn wutie(&self) -> WutieR {
WutieR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn tsie(&self) -> TsieR {
TsieR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn wucksel(&mut self) -> WuckselW<CrSpec> {
WuckselW::new(self, 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CrSpec> {
Rsvd4W::new(self, 1)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tsedge(&mut self) -> TsedgeW<CrSpec> {
TsedgeW::new(self, 3)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CrSpec> {
Rsvd3W::new(self, 4)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn fmt(&mut self) -> FmtW<CrSpec> {
FmtW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CrSpec> {
Rsvd2W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn alrme(&mut self) -> AlrmeW<CrSpec> {
AlrmeW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn wute(&mut self) -> WuteW<CrSpec> {
WuteW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn tse(&mut self) -> TseW<CrSpec> {
TseW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn alrmie(&mut self) -> AlrmieW<CrSpec> {
AlrmieW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn wutie(&mut self) -> WutieW<CrSpec> {
WutieW::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn tsie(&mut self) -> TsieW<CrSpec> {
TsieW::new(self, 13)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 14)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR (rw) register accessor: Initialization and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "Initialization and Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `ALRMWF` reader - "]
pub type AlrmwfR = crate::BitReader;
#[doc = "Field `ALRMWF` writer - "]
pub type AlrmwfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALRMF` reader - "]
pub type AlrmfR = crate::BitReader;
#[doc = "Field `ALRMF` writer - "]
pub type AlrmfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WUTWF` reader - "]
pub type WutwfR = crate::BitReader;
#[doc = "Field `WUTWF` writer - "]
pub type WutwfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WUTF` reader - "]
pub type WutfR = crate::BitReader;
#[doc = "Field `WUTF` writer - "]
pub type WutfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSF` reader - "]
pub type TsfR = crate::BitReader;
#[doc = "Field `TSF` writer - "]
pub type TsfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TSOVF` reader - "]
pub type TsovfR = crate::BitReader;
#[doc = "Field `TSOVF` writer - "]
pub type TsovfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SHPF` reader - "]
pub type ShpfR = crate::BitReader;
#[doc = "Field `SHPF` writer - "]
pub type ShpfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSF` reader - "]
pub type RsfR = crate::BitReader;
#[doc = "Field `RSF` writer - "]
pub type RsfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INITS` reader - "]
pub type InitsR = crate::BitReader;
#[doc = "Field `INITS` writer - "]
pub type InitsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INITF` reader - "]
pub type InitfR = crate::BitReader;
#[doc = "Field `INITF` writer - "]
pub type InitfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INIT` reader - "]
pub type InitR = crate::BitReader;
#[doc = "Field `INIT` writer - "]
pub type InitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn alrmwf(&self) -> AlrmwfR {
AlrmwfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn alrmf(&self) -> AlrmfR {
AlrmfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn wutwf(&self) -> WutwfR {
WutwfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn wutf(&self) -> WutfR {
WutfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn tsf(&self) -> TsfR {
TsfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tsovf(&self) -> TsovfR {
TsovfR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn shpf(&self) -> ShpfR {
ShpfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rsf(&self) -> RsfR {
RsfR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn inits(&self) -> InitsR {
InitsR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn initf(&self) -> InitfR {
InitfR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn init(&self) -> InitR {
InitR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn alrmwf(&mut self) -> AlrmwfW<IsrSpec> {
AlrmwfW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn alrmf(&mut self) -> AlrmfW<IsrSpec> {
AlrmfW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn wutwf(&mut self) -> WutwfW<IsrSpec> {
WutwfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn wutf(&mut self) -> WutfW<IsrSpec> {
WutfW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn tsf(&mut self) -> TsfW<IsrSpec> {
TsfW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn tsovf(&mut self) -> TsovfW<IsrSpec> {
TsovfW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn shpf(&mut self) -> ShpfW<IsrSpec> {
ShpfW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rsf(&mut self) -> RsfW<IsrSpec> {
RsfW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn inits(&mut self) -> InitsW<IsrSpec> {
InitsW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn initf(&mut self) -> InitfW<IsrSpec> {
InitfW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn init(&mut self) -> InitW<IsrSpec> {
InitW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "Initialization and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSCLR (rw) register accessor: Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psclr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psclr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psclr`]
module"]
#[doc(alias = "PSCLR")]
pub type Psclr = crate::Reg<psclr::PsclrSpec>;
#[doc = "Prescaler Register"]
pub mod psclr {
#[doc = "Register `PSCLR` reader"]
pub type R = crate::R<PsclrSpec>;
#[doc = "Register `PSCLR` writer"]
pub type W = crate::W<PsclrSpec>;
#[doc = "Field `DIVB` reader - "]
pub type DivbR = crate::FieldReader<u16>;
#[doc = "Field `DIVB` writer - "]
pub type DivbW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `DIVA_FRAC` reader - "]
pub type DivaFracR = crate::FieldReader<u16>;
#[doc = "Field `DIVA_FRAC` writer - "]
pub type DivaFracW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
#[doc = "Field `DIVA_INT` reader - "]
pub type DivaIntR = crate::FieldReader;
#[doc = "Field `DIVA_INT` writer - "]
pub type DivaIntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn divb(&self) -> DivbR {
DivbR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bits 10:23"]
#[inline(always)]
pub fn diva_frac(&self) -> DivaFracR {
DivaFracR::new(((self.bits >> 10) & 0x3fff) as u16)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn diva_int(&self) -> DivaIntR {
DivaIntR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn divb(&mut self) -> DivbW<PsclrSpec> {
DivbW::new(self, 0)
}
#[doc = "Bits 10:23"]
#[inline(always)]
#[must_use]
pub fn diva_frac(&mut self) -> DivaFracW<PsclrSpec> {
DivaFracW::new(self, 10)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn diva_int(&mut self) -> DivaIntW<PsclrSpec> {
DivaIntW::new(self, 24)
}
}
#[doc = "Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psclr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psclr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PsclrSpec;
impl crate::RegisterSpec for PsclrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psclr::R`](R) reader structure"]
impl crate::Readable for PsclrSpec {}
#[doc = "`write(|w| ..)` method takes [`psclr::W`](W) writer structure"]
impl crate::Writable for PsclrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSCLR to value 0"]
impl crate::Resettable for PsclrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WUTR (rw) register accessor: Wakeup Timer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wutr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wutr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wutr`]
module"]
#[doc(alias = "WUTR")]
pub type Wutr = crate::Reg<wutr::WutrSpec>;
#[doc = "Wakeup Timer Register"]
pub mod wutr {
#[doc = "Register `WUTR` reader"]
pub type R = crate::R<WutrSpec>;
#[doc = "Register `WUTR` writer"]
pub type W = crate::W<WutrSpec>;
#[doc = "Field `WUT` reader - "]
pub type WutR = crate::FieldReader<u32>;
#[doc = "Field `WUT` writer - "]
pub type WutW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bits 0:17"]
#[inline(always)]
pub fn wut(&self) -> WutR {
WutR::new(self.bits & 0x0003_ffff)
}
#[doc = "Bits 18:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 18) & 0x3fff) as u16)
}
}
impl W {
#[doc = "Bits 0:17"]
#[inline(always)]
#[must_use]
pub fn wut(&mut self) -> WutW<WutrSpec> {
WutW::new(self, 0)
}
#[doc = "Bits 18:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WutrSpec> {
RsvdW::new(self, 18)
}
}
#[doc = "Wakeup Timer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wutr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wutr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WutrSpec;
impl crate::RegisterSpec for WutrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wutr::R`](R) reader structure"]
impl crate::Readable for WutrSpec {}
#[doc = "`write(|w| ..)` method takes [`wutr::W`](W) writer structure"]
impl crate::Writable for WutrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WUTR to value 0"]
impl crate::Resettable for WutrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ALRMTR (rw) register accessor: Alarm Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`alrmtr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrmtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@alrmtr`]
module"]
#[doc(alias = "ALRMTR")]
pub type Alrmtr = crate::Reg<alrmtr::AlrmtrSpec>;
#[doc = "Alarm Time Register"]
pub mod alrmtr {
#[doc = "Register `ALRMTR` reader"]
pub type R = crate::R<AlrmtrSpec>;
#[doc = "Register `ALRMTR` writer"]
pub type W = crate::W<AlrmtrSpec>;
#[doc = "Field `SS` reader - "]
pub type SsR = crate::FieldReader<u16>;
#[doc = "Field `SS` writer - "]
pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SU` reader - "]
pub type SuR = crate::FieldReader;
#[doc = "Field `SU` writer - "]
pub type SuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `ST` reader - "]
pub type StR = crate::FieldReader;
#[doc = "Field `ST` writer - "]
pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `MNU` reader - "]
pub type MnuR = crate::FieldReader;
#[doc = "Field `MNU` writer - "]
pub type MnuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MNT` reader - "]
pub type MntR = crate::FieldReader;
#[doc = "Field `MNT` writer - "]
pub type MntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `HU` reader - "]
pub type HuR = crate::FieldReader;
#[doc = "Field `HU` writer - "]
pub type HuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `HT` reader - "]
pub type HtR = crate::FieldReader;
#[doc = "Field `HT` writer - "]
pub type HtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PM` reader - "]
pub type PmR = crate::BitReader;
#[doc = "Field `PM` writer - "]
pub type PmW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn ss(&self) -> SsR {
SsR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:14"]
#[inline(always)]
pub fn su(&self) -> SuR {
SuR::new(((self.bits >> 11) & 0x0f) as u8)
}
#[doc = "Bits 15:17"]
#[inline(always)]
pub fn st(&self) -> StR {
StR::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:21"]
#[inline(always)]
pub fn mnu(&self) -> MnuR {
MnuR::new(((self.bits >> 18) & 0x0f) as u8)
}
#[doc = "Bits 22:24"]
#[inline(always)]
pub fn mnt(&self) -> MntR {
MntR::new(((self.bits >> 22) & 7) as u8)
}
#[doc = "Bits 25:28"]
#[inline(always)]
pub fn hu(&self) -> HuR {
HuR::new(((self.bits >> 25) & 0x0f) as u8)
}
#[doc = "Bits 29:30"]
#[inline(always)]
pub fn ht(&self) -> HtR {
HtR::new(((self.bits >> 29) & 3) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn pm(&self) -> PmR {
PmR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn ss(&mut self) -> SsW<AlrmtrSpec> {
SsW::new(self, 0)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AlrmtrSpec> {
RsvdW::new(self, 10)
}
#[doc = "Bits 11:14"]
#[inline(always)]
#[must_use]
pub fn su(&mut self) -> SuW<AlrmtrSpec> {
SuW::new(self, 11)
}
#[doc = "Bits 15:17"]
#[inline(always)]
#[must_use]
pub fn st(&mut self) -> StW<AlrmtrSpec> {
StW::new(self, 15)
}
#[doc = "Bits 18:21"]
#[inline(always)]
#[must_use]
pub fn mnu(&mut self) -> MnuW<AlrmtrSpec> {
MnuW::new(self, 18)
}
#[doc = "Bits 22:24"]
#[inline(always)]
#[must_use]
pub fn mnt(&mut self) -> MntW<AlrmtrSpec> {
MntW::new(self, 22)
}
#[doc = "Bits 25:28"]
#[inline(always)]
#[must_use]
pub fn hu(&mut self) -> HuW<AlrmtrSpec> {
HuW::new(self, 25)
}
#[doc = "Bits 29:30"]
#[inline(always)]
#[must_use]
pub fn ht(&mut self) -> HtW<AlrmtrSpec> {
HtW::new(self, 29)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn pm(&mut self) -> PmW<AlrmtrSpec> {
PmW::new(self, 31)
}
}
#[doc = "Alarm Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`alrmtr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrmtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AlrmtrSpec;
impl crate::RegisterSpec for AlrmtrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`alrmtr::R`](R) reader structure"]
impl crate::Readable for AlrmtrSpec {}
#[doc = "`write(|w| ..)` method takes [`alrmtr::W`](W) writer structure"]
impl crate::Writable for AlrmtrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ALRMTR to value 0"]
impl crate::Resettable for AlrmtrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ALRMDR (rw) register accessor: Alarm Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`alrmdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrmdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@alrmdr`]
module"]
#[doc(alias = "ALRMDR")]
pub type Alrmdr = crate::Reg<alrmdr::AlrmdrSpec>;
#[doc = "Alarm Date Register"]
pub mod alrmdr {
#[doc = "Register `ALRMDR` reader"]
pub type R = crate::R<AlrmdrSpec>;
#[doc = "Register `ALRMDR` writer"]
pub type W = crate::W<AlrmdrSpec>;
#[doc = "Field `DU` reader - "]
pub type DuR = crate::FieldReader;
#[doc = "Field `DU` writer - "]
pub type DuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DT` reader - "]
pub type DtR = crate::FieldReader;
#[doc = "Field `DT` writer - "]
pub type DtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MU` reader - "]
pub type MuR = crate::FieldReader;
#[doc = "Field `MU` writer - "]
pub type MuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MT` reader - "]
pub type MtR = crate::BitReader;
#[doc = "Field `MT` writer - "]
pub type MtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WD` reader - "]
pub type WdR = crate::FieldReader;
#[doc = "Field `WD` writer - "]
pub type WdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MSKSS` reader - "]
pub type MskssR = crate::FieldReader;
#[doc = "Field `MSKSS` writer - "]
pub type MskssW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MSKS` reader - "]
pub type MsksR = crate::BitReader;
#[doc = "Field `MSKS` writer - "]
pub type MsksW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSKMN` reader - "]
pub type MskmnR = crate::BitReader;
#[doc = "Field `MSKMN` writer - "]
pub type MskmnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSKH` reader - "]
pub type MskhR = crate::BitReader;
#[doc = "Field `MSKH` writer - "]
pub type MskhW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSKD` reader - "]
pub type MskdR = crate::BitReader;
#[doc = "Field `MSKD` writer - "]
pub type MskdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSKM` reader - "]
pub type MskmR = crate::BitReader;
#[doc = "Field `MSKM` writer - "]
pub type MskmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSKWD` reader - "]
pub type MskwdR = crate::BitReader;
#[doc = "Field `MSKWD` writer - "]
pub type MskwdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn du(&self) -> DuR {
DuR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn dt(&self) -> DtR {
DtR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn mu(&self) -> MuR {
MuR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn mt(&self) -> MtR {
MtR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15"]
#[inline(always)]
pub fn wd(&self) -> WdR {
WdR::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23"]
#[inline(always)]
pub fn mskss(&self) -> MskssR {
MskssR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn msks(&self) -> MsksR {
MsksR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn mskmn(&self) -> MskmnR {
MskmnR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn mskh(&self) -> MskhR {
MskhR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn mskd(&self) -> MskdR {
MskdR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn mskm(&self) -> MskmR {
MskmR::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn mskwd(&self) -> MskwdR {
MskwdR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn du(&mut self) -> DuW<AlrmdrSpec> {
DuW::new(self, 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn dt(&mut self) -> DtW<AlrmdrSpec> {
DtW::new(self, 4)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<AlrmdrSpec> {
Rsvd3W::new(self, 6)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn mu(&mut self) -> MuW<AlrmdrSpec> {
MuW::new(self, 8)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn mt(&mut self) -> MtW<AlrmdrSpec> {
MtW::new(self, 12)
}
#[doc = "Bits 13:15"]
#[inline(always)]
#[must_use]
pub fn wd(&mut self) -> WdW<AlrmdrSpec> {
WdW::new(self, 13)
}
#[doc = "Bits 16:19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<AlrmdrSpec> {
Rsvd2W::new(self, 16)
}
#[doc = "Bits 20:23"]
#[inline(always)]
#[must_use]
pub fn mskss(&mut self) -> MskssW<AlrmdrSpec> {
MskssW::new(self, 20)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn msks(&mut self) -> MsksW<AlrmdrSpec> {
MsksW::new(self, 24)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn mskmn(&mut self) -> MskmnW<AlrmdrSpec> {
MskmnW::new(self, 25)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn mskh(&mut self) -> MskhW<AlrmdrSpec> {
MskhW::new(self, 26)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn mskd(&mut self) -> MskdW<AlrmdrSpec> {
MskdW::new(self, 27)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn mskm(&mut self) -> MskmW<AlrmdrSpec> {
MskmW::new(self, 28)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn mskwd(&mut self) -> MskwdW<AlrmdrSpec> {
MskwdW::new(self, 29)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<AlrmdrSpec> {
RsvdW::new(self, 30)
}
}
#[doc = "Alarm Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`alrmdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alrmdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AlrmdrSpec;
impl crate::RegisterSpec for AlrmdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`alrmdr::R`](R) reader structure"]
impl crate::Readable for AlrmdrSpec {}
#[doc = "`write(|w| ..)` method takes [`alrmdr::W`](W) writer structure"]
impl crate::Writable for AlrmdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ALRMDR to value 0"]
impl crate::Resettable for AlrmdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SHIFTR (rw) register accessor: Shift Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shiftr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shiftr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shiftr`]
module"]
#[doc(alias = "SHIFTR")]
pub type Shiftr = crate::Reg<shiftr::ShiftrSpec>;
#[doc = "Shift Control Register"]
pub mod shiftr {
#[doc = "Register `SHIFTR` reader"]
pub type R = crate::R<ShiftrSpec>;
#[doc = "Register `SHIFTR` writer"]
pub type W = crate::W<ShiftrSpec>;
#[doc = "Field `SUBFS` reader - "]
pub type SubfsR = crate::FieldReader<u16>;
#[doc = "Field `SUBFS` writer - "]
pub type SubfsW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
#[doc = "Field `ADD1S` reader - "]
pub type Add1sR = crate::BitReader;
#[doc = "Field `ADD1S` writer - "]
pub type Add1sW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn subfs(&self) -> SubfsR {
SubfsR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bits 10:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x001f_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn add1s(&self) -> Add1sR {
Add1sR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn subfs(&mut self) -> SubfsW<ShiftrSpec> {
SubfsW::new(self, 0)
}
#[doc = "Bits 10:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ShiftrSpec> {
RsvdW::new(self, 10)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn add1s(&mut self) -> Add1sW<ShiftrSpec> {
Add1sW::new(self, 31)
}
}
#[doc = "Shift Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shiftr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shiftr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ShiftrSpec;
impl crate::RegisterSpec for ShiftrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`shiftr::R`](R) reader structure"]
impl crate::Readable for ShiftrSpec {}
#[doc = "`write(|w| ..)` method takes [`shiftr::W`](W) writer structure"]
impl crate::Writable for ShiftrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SHIFTR to value 0"]
impl crate::Resettable for ShiftrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TSTR (rw) register accessor: Timestamp Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstr`]
module"]
#[doc(alias = "TSTR")]
pub type Tstr = crate::Reg<tstr::TstrSpec>;
#[doc = "Timestamp Time Register"]
pub mod tstr {
#[doc = "Register `TSTR` reader"]
pub type R = crate::R<TstrSpec>;
#[doc = "Register `TSTR` writer"]
pub type W = crate::W<TstrSpec>;
#[doc = "Field `SS` reader - "]
pub type SsR = crate::FieldReader<u16>;
#[doc = "Field `SS` writer - "]
pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::BitReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SU` reader - "]
pub type SuR = crate::FieldReader;
#[doc = "Field `SU` writer - "]
pub type SuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `ST` reader - "]
pub type StR = crate::FieldReader;
#[doc = "Field `ST` writer - "]
pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `MNU` reader - "]
pub type MnuR = crate::FieldReader;
#[doc = "Field `MNU` writer - "]
pub type MnuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MNT` reader - "]
pub type MntR = crate::FieldReader;
#[doc = "Field `MNT` writer - "]
pub type MntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `HU` reader - "]
pub type HuR = crate::FieldReader;
#[doc = "Field `HU` writer - "]
pub type HuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `HT` reader - "]
pub type HtR = crate::FieldReader;
#[doc = "Field `HT` writer - "]
pub type HtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PM` reader - "]
pub type PmR = crate::BitReader;
#[doc = "Field `PM` writer - "]
pub type PmW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn ss(&self) -> SsR {
SsR::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:14"]
#[inline(always)]
pub fn su(&self) -> SuR {
SuR::new(((self.bits >> 11) & 0x0f) as u8)
}
#[doc = "Bits 15:17"]
#[inline(always)]
pub fn st(&self) -> StR {
StR::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:21"]
#[inline(always)]
pub fn mnu(&self) -> MnuR {
MnuR::new(((self.bits >> 18) & 0x0f) as u8)
}
#[doc = "Bits 22:24"]
#[inline(always)]
pub fn mnt(&self) -> MntR {
MntR::new(((self.bits >> 22) & 7) as u8)
}
#[doc = "Bits 25:28"]
#[inline(always)]
pub fn hu(&self) -> HuR {
HuR::new(((self.bits >> 25) & 0x0f) as u8)
}
#[doc = "Bits 29:30"]
#[inline(always)]
pub fn ht(&self) -> HtR {
HtR::new(((self.bits >> 29) & 3) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn pm(&self) -> PmR {
PmR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn ss(&mut self) -> SsW<TstrSpec> {
SsW::new(self, 0)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TstrSpec> {
RsvdW::new(self, 10)
}
#[doc = "Bits 11:14"]
#[inline(always)]
#[must_use]
pub fn su(&mut self) -> SuW<TstrSpec> {
SuW::new(self, 11)
}
#[doc = "Bits 15:17"]
#[inline(always)]
#[must_use]
pub fn st(&mut self) -> StW<TstrSpec> {
StW::new(self, 15)
}
#[doc = "Bits 18:21"]
#[inline(always)]
#[must_use]
pub fn mnu(&mut self) -> MnuW<TstrSpec> {
MnuW::new(self, 18)
}
#[doc = "Bits 22:24"]
#[inline(always)]
#[must_use]
pub fn mnt(&mut self) -> MntW<TstrSpec> {
MntW::new(self, 22)
}
#[doc = "Bits 25:28"]
#[inline(always)]
#[must_use]
pub fn hu(&mut self) -> HuW<TstrSpec> {
HuW::new(self, 25)
}
#[doc = "Bits 29:30"]
#[inline(always)]
#[must_use]
pub fn ht(&mut self) -> HtW<TstrSpec> {
HtW::new(self, 29)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn pm(&mut self) -> PmW<TstrSpec> {
PmW::new(self, 31)
}
}
#[doc = "Timestamp Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TstrSpec;
impl crate::RegisterSpec for TstrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tstr::R`](R) reader structure"]
impl crate::Readable for TstrSpec {}
#[doc = "`write(|w| ..)` method takes [`tstr::W`](W) writer structure"]
impl crate::Writable for TstrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TSTR to value 0"]
impl crate::Resettable for TstrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TSDR (rw) register accessor: Timestamp Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsdr`]
module"]
#[doc(alias = "TSDR")]
pub type Tsdr = crate::Reg<tsdr::TsdrSpec>;
#[doc = "Timestamp Date Register"]
pub mod tsdr {
#[doc = "Register `TSDR` reader"]
pub type R = crate::R<TsdrSpec>;
#[doc = "Register `TSDR` writer"]
pub type W = crate::W<TsdrSpec>;
#[doc = "Field `DU` reader - "]
pub type DuR = crate::FieldReader;
#[doc = "Field `DU` writer - "]
pub type DuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DT` reader - "]
pub type DtR = crate::FieldReader;
#[doc = "Field `DT` writer - "]
pub type DtW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MU` reader - "]
pub type MuR = crate::FieldReader;
#[doc = "Field `MU` writer - "]
pub type MuW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MT` reader - "]
pub type MtR = crate::BitReader;
#[doc = "Field `MT` writer - "]
pub type MtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WD` reader - "]
pub type WdR = crate::FieldReader;
#[doc = "Field `WD` writer - "]
pub type WdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn du(&self) -> DuR {
DuR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn dt(&self) -> DtR {
DtR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn mu(&self) -> MuR {
MuR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn mt(&self) -> MtR {
MtR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15"]
#[inline(always)]
pub fn wd(&self) -> WdR {
WdR::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn du(&mut self) -> DuW<TsdrSpec> {
DuW::new(self, 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn dt(&mut self) -> DtW<TsdrSpec> {
DtW::new(self, 4)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<TsdrSpec> {
Rsvd2W::new(self, 6)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn mu(&mut self) -> MuW<TsdrSpec> {
MuW::new(self, 8)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn mt(&mut self) -> MtW<TsdrSpec> {
MtW::new(self, 12)
}
#[doc = "Bits 13:15"]
#[inline(always)]
#[must_use]
pub fn wd(&mut self) -> WdW<TsdrSpec> {
WdW::new(self, 13)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TsdrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Timestamp Date Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TsdrSpec;
impl crate::RegisterSpec for TsdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tsdr::R`](R) reader structure"]
impl crate::Readable for TsdrSpec {}
#[doc = "`write(|w| ..)` method takes [`tsdr::W`](W) writer structure"]
impl crate::Writable for TsdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TSDR to value 0"]
impl crate::Resettable for TsdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@or`]
module"]
#[doc(alias = "OR")]
pub type Or = crate::Reg<or::OrSpec>;
#[doc = ""]
pub mod or {
#[doc = "Register `OR` reader"]
pub type R = crate::R<OrSpec>;
#[doc = "Register `OR` writer"]
pub type W = crate::W<OrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<OrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`or::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`or::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OrSpec;
impl crate::RegisterSpec for OrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`or::R`](R) reader structure"]
impl crate::Readable for OrSpec {}
#[doc = "`write(|w| ..)` method takes [`or::W`](W) writer structure"]
impl crate::Writable for OrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OR to value 0"]
impl crate::Resettable for OrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP0R (rw) register accessor: Backup 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp0r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp0r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp0r`]
module"]
#[doc(alias = "BKP0R")]
pub type Bkp0r = crate::Reg<bkp0r::Bkp0rSpec>;
#[doc = "Backup 0 Register"]
pub mod bkp0r {
#[doc = "Register `BKP0R` reader"]
pub type R = crate::R<Bkp0rSpec>;
#[doc = "Register `BKP0R` writer"]
pub type W = crate::W<Bkp0rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp0rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp0r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp0r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp0rSpec;
impl crate::RegisterSpec for Bkp0rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp0r::R`](R) reader structure"]
impl crate::Readable for Bkp0rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp0r::W`](W) writer structure"]
impl crate::Writable for Bkp0rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP0R to value 0"]
impl crate::Resettable for Bkp0rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP1R (rw) register accessor: Backup 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp1r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp1r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp1r`]
module"]
#[doc(alias = "BKP1R")]
pub type Bkp1r = crate::Reg<bkp1r::Bkp1rSpec>;
#[doc = "Backup 1 Register"]
pub mod bkp1r {
#[doc = "Register `BKP1R` reader"]
pub type R = crate::R<Bkp1rSpec>;
#[doc = "Register `BKP1R` writer"]
pub type W = crate::W<Bkp1rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp1rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp1r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp1r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp1rSpec;
impl crate::RegisterSpec for Bkp1rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp1r::R`](R) reader structure"]
impl crate::Readable for Bkp1rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp1r::W`](W) writer structure"]
impl crate::Writable for Bkp1rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP1R to value 0"]
impl crate::Resettable for Bkp1rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP2R (rw) register accessor: Backup 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp2r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp2r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp2r`]
module"]
#[doc(alias = "BKP2R")]
pub type Bkp2r = crate::Reg<bkp2r::Bkp2rSpec>;
#[doc = "Backup 2 Register"]
pub mod bkp2r {
#[doc = "Register `BKP2R` reader"]
pub type R = crate::R<Bkp2rSpec>;
#[doc = "Register `BKP2R` writer"]
pub type W = crate::W<Bkp2rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp2rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp2r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp2r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp2rSpec;
impl crate::RegisterSpec for Bkp2rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp2r::R`](R) reader structure"]
impl crate::Readable for Bkp2rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp2r::W`](W) writer structure"]
impl crate::Writable for Bkp2rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP2R to value 0"]
impl crate::Resettable for Bkp2rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP3R (rw) register accessor: Backup 3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp3r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp3r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp3r`]
module"]
#[doc(alias = "BKP3R")]
pub type Bkp3r = crate::Reg<bkp3r::Bkp3rSpec>;
#[doc = "Backup 3 Register"]
pub mod bkp3r {
#[doc = "Register `BKP3R` reader"]
pub type R = crate::R<Bkp3rSpec>;
#[doc = "Register `BKP3R` writer"]
pub type W = crate::W<Bkp3rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp3rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp3r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp3r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp3rSpec;
impl crate::RegisterSpec for Bkp3rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp3r::R`](R) reader structure"]
impl crate::Readable for Bkp3rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp3r::W`](W) writer structure"]
impl crate::Writable for Bkp3rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP3R to value 0"]
impl crate::Resettable for Bkp3rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP4R (rw) register accessor: Backup 4 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp4r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp4r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp4r`]
module"]
#[doc(alias = "BKP4R")]
pub type Bkp4r = crate::Reg<bkp4r::Bkp4rSpec>;
#[doc = "Backup 4 Register"]
pub mod bkp4r {
#[doc = "Register `BKP4R` reader"]
pub type R = crate::R<Bkp4rSpec>;
#[doc = "Register `BKP4R` writer"]
pub type W = crate::W<Bkp4rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp4rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 4 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp4r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp4r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp4rSpec;
impl crate::RegisterSpec for Bkp4rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp4r::R`](R) reader structure"]
impl crate::Readable for Bkp4rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp4r::W`](W) writer structure"]
impl crate::Writable for Bkp4rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP4R to value 0"]
impl crate::Resettable for Bkp4rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP5R (rw) register accessor: Backup 5 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp5r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp5r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp5r`]
module"]
#[doc(alias = "BKP5R")]
pub type Bkp5r = crate::Reg<bkp5r::Bkp5rSpec>;
#[doc = "Backup 5 Register"]
pub mod bkp5r {
#[doc = "Register `BKP5R` reader"]
pub type R = crate::R<Bkp5rSpec>;
#[doc = "Register `BKP5R` writer"]
pub type W = crate::W<Bkp5rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp5rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 5 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp5r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp5r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp5rSpec;
impl crate::RegisterSpec for Bkp5rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp5r::R`](R) reader structure"]
impl crate::Readable for Bkp5rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp5r::W`](W) writer structure"]
impl crate::Writable for Bkp5rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP5R to value 0"]
impl crate::Resettable for Bkp5rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP6R (rw) register accessor: Backup 6 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp6r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp6r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp6r`]
module"]
#[doc(alias = "BKP6R")]
pub type Bkp6r = crate::Reg<bkp6r::Bkp6rSpec>;
#[doc = "Backup 6 Register"]
pub mod bkp6r {
#[doc = "Register `BKP6R` reader"]
pub type R = crate::R<Bkp6rSpec>;
#[doc = "Register `BKP6R` writer"]
pub type W = crate::W<Bkp6rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp6rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 6 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp6r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp6r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp6rSpec;
impl crate::RegisterSpec for Bkp6rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp6r::R`](R) reader structure"]
impl crate::Readable for Bkp6rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp6r::W`](W) writer structure"]
impl crate::Writable for Bkp6rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP6R to value 0"]
impl crate::Resettable for Bkp6rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP7R (rw) register accessor: Backup 7 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp7r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp7r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp7r`]
module"]
#[doc(alias = "BKP7R")]
pub type Bkp7r = crate::Reg<bkp7r::Bkp7rSpec>;
#[doc = "Backup 7 Register"]
pub mod bkp7r {
#[doc = "Register `BKP7R` reader"]
pub type R = crate::R<Bkp7rSpec>;
#[doc = "Register `BKP7R` writer"]
pub type W = crate::W<Bkp7rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp7rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 7 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp7r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp7r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp7rSpec;
impl crate::RegisterSpec for Bkp7rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp7r::R`](R) reader structure"]
impl crate::Readable for Bkp7rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp7r::W`](W) writer structure"]
impl crate::Writable for Bkp7rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP7R to value 0"]
impl crate::Resettable for Bkp7rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP8R (rw) register accessor: Backup 8 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp8r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp8r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp8r`]
module"]
#[doc(alias = "BKP8R")]
pub type Bkp8r = crate::Reg<bkp8r::Bkp8rSpec>;
#[doc = "Backup 8 Register"]
pub mod bkp8r {
#[doc = "Register `BKP8R` reader"]
pub type R = crate::R<Bkp8rSpec>;
#[doc = "Register `BKP8R` writer"]
pub type W = crate::W<Bkp8rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp8rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 8 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp8r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp8r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp8rSpec;
impl crate::RegisterSpec for Bkp8rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp8r::R`](R) reader structure"]
impl crate::Readable for Bkp8rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp8r::W`](W) writer structure"]
impl crate::Writable for Bkp8rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP8R to value 0"]
impl crate::Resettable for Bkp8rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BKP9R (rw) register accessor: Backup 9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp9r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp9r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp9r`]
module"]
#[doc(alias = "BKP9R")]
pub type Bkp9r = crate::Reg<bkp9r::Bkp9rSpec>;
#[doc = "Backup 9 Register"]
pub mod bkp9r {
#[doc = "Register `BKP9R` reader"]
pub type R = crate::R<Bkp9rSpec>;
#[doc = "Register `BKP9R` writer"]
pub type W = crate::W<Bkp9rSpec>;
#[doc = "Field `BKP` reader - "]
pub type BkpR = crate::FieldReader<u32>;
#[doc = "Field `BKP` writer - "]
pub type BkpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BkpW<Bkp9rSpec> {
BkpW::new(self, 0)
}
}
#[doc = "Backup 9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bkp9r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bkp9r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bkp9rSpec;
impl crate::RegisterSpec for Bkp9rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp9r::R`](R) reader structure"]
impl crate::Readable for Bkp9rSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp9r::W`](W) writer structure"]
impl crate::Writable for Bkp9rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BKP9R to value 0"]
impl crate::Resettable for Bkp9rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PBRCR (rw) register accessor: PBR Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbrcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbrcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbrcr`]
module"]
#[doc(alias = "PBRCR")]
pub type Pbrcr = crate::Reg<pbrcr::PbrcrSpec>;
#[doc = "PBR Control Register"]
pub mod pbrcr {
#[doc = "Register `PBRCR` reader"]
pub type R = crate::R<PbrcrSpec>;
#[doc = "Register `PBRCR` writer"]
pub type W = crate::W<PbrcrSpec>;
#[doc = "Field `RTO` reader - "]
pub type RtoR = crate::BitReader;
#[doc = "Field `RTO` writer - "]
pub type RtoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SNS` reader - "]
pub type SnsR = crate::BitReader;
#[doc = "Field `SNS` writer - "]
pub type SnsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rto(&self) -> RtoR {
RtoR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn sns(&self) -> SnsR {
SnsR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn rto(&mut self) -> RtoW<PbrcrSpec> {
RtoW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn sns(&mut self) -> SnsW<PbrcrSpec> {
SnsW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PbrcrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "PBR Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbrcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbrcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbrcrSpec;
impl crate::RegisterSpec for PbrcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pbrcr::R`](R) reader structure"]
impl crate::Readable for PbrcrSpec {}
#[doc = "`write(|w| ..)` method takes [`pbrcr::W`](W) writer structure"]
impl crate::Writable for PbrcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PBRCR to value 0"]
impl crate::Resettable for PbrcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PBR0R (rw) register accessor: PBR0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr0r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr0r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbr0r`]
module"]
#[doc(alias = "PBR0R")]
pub type Pbr0r = crate::Reg<pbr0r::Pbr0rSpec>;
#[doc = "PBR0 Register"]
pub mod pbr0r {
#[doc = "Register `PBR0R` reader"]
pub type R = crate::R<Pbr0rSpec>;
#[doc = "Register `PBR0R` writer"]
pub type W = crate::W<Pbr0rSpec>;
#[doc = "Field `OUT` reader - "]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - "]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - "]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - "]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE` reader - "]
pub type IeR = crate::BitReader;
#[doc = "Field `IE` writer - "]
pub type IeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DS0` reader - "]
pub type Ds0R = crate::BitReader;
#[doc = "Field `DS0` writer - "]
pub type Ds0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DS1` reader - "]
pub type Ds1R = crate::BitReader;
#[doc = "Field `DS1` writer - "]
pub type Ds1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IN` reader - "]
pub type InR = crate::BitReader;
#[doc = "Field `IN` writer - "]
pub type InW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL` reader - "]
pub type SelR = crate::FieldReader;
#[doc = "Field `SEL` writer - "]
pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `FORCE1` reader - special use. Set 1 to force output 1"]
pub type Force1R = crate::BitReader;
#[doc = "Field `FORCE1` writer - special use. Set 1 to force output 1"]
pub type Force1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ie(&self) -> IeR {
IeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ds0(&self) -> Ds0R {
Ds0R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ds1(&self) -> Ds1R {
Ds1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn in_(&self) -> InR {
InR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn sel(&self) -> SelR {
SelR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 15) & 0xffff) as u16)
}
#[doc = "Bit 31 - special use. Set 1 to force output 1"]
#[inline(always)]
pub fn force1(&self) -> Force1R {
Force1R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn out(&mut self) -> OutW<Pbr0rSpec> {
OutW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn oe(&mut self) -> OeW<Pbr0rSpec> {
OeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ie(&mut self) -> IeW<Pbr0rSpec> {
IeW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<Pbr0rSpec> {
PeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Pbr0rSpec> {
PsW::new(self, 4)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Pbr0rSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ds0(&mut self) -> Ds0W<Pbr0rSpec> {
Ds0W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ds1(&mut self) -> Ds1W<Pbr0rSpec> {
Ds1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn in_(&mut self) -> InW<Pbr0rSpec> {
InW::new(self, 9)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Pbr0rSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn sel(&mut self) -> SelW<Pbr0rSpec> {
SelW::new(self, 12)
}
#[doc = "Bits 15:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Pbr0rSpec> {
RsvdW::new(self, 15)
}
#[doc = "Bit 31 - special use. Set 1 to force output 1"]
#[inline(always)]
#[must_use]
pub fn force1(&mut self) -> Force1W<Pbr0rSpec> {
Force1W::new(self, 31)
}
}
#[doc = "PBR0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr0r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr0r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pbr0rSpec;
impl crate::RegisterSpec for Pbr0rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pbr0r::R`](R) reader structure"]
impl crate::Readable for Pbr0rSpec {}
#[doc = "`write(|w| ..)` method takes [`pbr0r::W`](W) writer structure"]
impl crate::Writable for Pbr0rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PBR0R to value 0"]
impl crate::Resettable for Pbr0rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PBR1R (rw) register accessor: PBR1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr1r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr1r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbr1r`]
module"]
#[doc(alias = "PBR1R")]
pub type Pbr1r = crate::Reg<pbr1r::Pbr1rSpec>;
#[doc = "PBR1 Register"]
pub mod pbr1r {
#[doc = "Register `PBR1R` reader"]
pub type R = crate::R<Pbr1rSpec>;
#[doc = "Register `PBR1R` writer"]
pub type W = crate::W<Pbr1rSpec>;
#[doc = "Field `OUT` reader - "]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - "]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - "]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - "]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE` reader - "]
pub type IeR = crate::BitReader;
#[doc = "Field `IE` writer - "]
pub type IeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DS0` reader - "]
pub type Ds0R = crate::BitReader;
#[doc = "Field `DS0` writer - "]
pub type Ds0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DS1` reader - "]
pub type Ds1R = crate::BitReader;
#[doc = "Field `DS1` writer - "]
pub type Ds1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IN` reader - "]
pub type InR = crate::BitReader;
#[doc = "Field `IN` writer - "]
pub type InW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL` reader - "]
pub type SelR = crate::FieldReader;
#[doc = "Field `SEL` writer - "]
pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ie(&self) -> IeR {
IeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ds0(&self) -> Ds0R {
Ds0R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ds1(&self) -> Ds1R {
Ds1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn in_(&self) -> InR {
InR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn sel(&self) -> SelR {
SelR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn out(&mut self) -> OutW<Pbr1rSpec> {
OutW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn oe(&mut self) -> OeW<Pbr1rSpec> {
OeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ie(&mut self) -> IeW<Pbr1rSpec> {
IeW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<Pbr1rSpec> {
PeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Pbr1rSpec> {
PsW::new(self, 4)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Pbr1rSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ds0(&mut self) -> Ds0W<Pbr1rSpec> {
Ds0W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ds1(&mut self) -> Ds1W<Pbr1rSpec> {
Ds1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn in_(&mut self) -> InW<Pbr1rSpec> {
InW::new(self, 9)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Pbr1rSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn sel(&mut self) -> SelW<Pbr1rSpec> {
SelW::new(self, 12)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Pbr1rSpec> {
RsvdW::new(self, 15)
}
}
#[doc = "PBR1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr1r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr1r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pbr1rSpec;
impl crate::RegisterSpec for Pbr1rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pbr1r::R`](R) reader structure"]
impl crate::Readable for Pbr1rSpec {}
#[doc = "`write(|w| ..)` method takes [`pbr1r::W`](W) writer structure"]
impl crate::Writable for Pbr1rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PBR1R to value 0"]
impl crate::Resettable for Pbr1rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PBR2R (rw) register accessor: PBR2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr2r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr2r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbr2r`]
module"]
#[doc(alias = "PBR2R")]
pub type Pbr2r = crate::Reg<pbr2r::Pbr2rSpec>;
#[doc = "PBR2 Register"]
pub mod pbr2r {
#[doc = "Register `PBR2R` reader"]
pub type R = crate::R<Pbr2rSpec>;
#[doc = "Register `PBR2R` writer"]
pub type W = crate::W<Pbr2rSpec>;
#[doc = "Field `OUT` reader - "]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - "]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - "]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - "]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE` reader - "]
pub type IeR = crate::BitReader;
#[doc = "Field `IE` writer - "]
pub type IeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DS0` reader - "]
pub type Ds0R = crate::BitReader;
#[doc = "Field `DS0` writer - "]
pub type Ds0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DS1` reader - "]
pub type Ds1R = crate::BitReader;
#[doc = "Field `DS1` writer - "]
pub type Ds1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IN` reader - "]
pub type InR = crate::BitReader;
#[doc = "Field `IN` writer - "]
pub type InW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL` reader - "]
pub type SelR = crate::FieldReader;
#[doc = "Field `SEL` writer - "]
pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ie(&self) -> IeR {
IeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ds0(&self) -> Ds0R {
Ds0R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ds1(&self) -> Ds1R {
Ds1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn in_(&self) -> InR {
InR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn sel(&self) -> SelR {
SelR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn out(&mut self) -> OutW<Pbr2rSpec> {
OutW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn oe(&mut self) -> OeW<Pbr2rSpec> {
OeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ie(&mut self) -> IeW<Pbr2rSpec> {
IeW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<Pbr2rSpec> {
PeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Pbr2rSpec> {
PsW::new(self, 4)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Pbr2rSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ds0(&mut self) -> Ds0W<Pbr2rSpec> {
Ds0W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ds1(&mut self) -> Ds1W<Pbr2rSpec> {
Ds1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn in_(&mut self) -> InW<Pbr2rSpec> {
InW::new(self, 9)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Pbr2rSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn sel(&mut self) -> SelW<Pbr2rSpec> {
SelW::new(self, 12)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Pbr2rSpec> {
RsvdW::new(self, 15)
}
}
#[doc = "PBR2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr2r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr2r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pbr2rSpec;
impl crate::RegisterSpec for Pbr2rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pbr2r::R`](R) reader structure"]
impl crate::Readable for Pbr2rSpec {}
#[doc = "`write(|w| ..)` method takes [`pbr2r::W`](W) writer structure"]
impl crate::Writable for Pbr2rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PBR2R to value 0"]
impl crate::Resettable for Pbr2rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PBR3R (rw) register accessor: PBR3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr3r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr3r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbr3r`]
module"]
#[doc(alias = "PBR3R")]
pub type Pbr3r = crate::Reg<pbr3r::Pbr3rSpec>;
#[doc = "PBR3 Register"]
pub mod pbr3r {
#[doc = "Register `PBR3R` reader"]
pub type R = crate::R<Pbr3rSpec>;
#[doc = "Register `PBR3R` writer"]
pub type W = crate::W<Pbr3rSpec>;
#[doc = "Field `OUT` reader - "]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - "]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - "]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - "]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE` reader - "]
pub type IeR = crate::BitReader;
#[doc = "Field `IE` writer - "]
pub type IeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DS0` reader - "]
pub type Ds0R = crate::BitReader;
#[doc = "Field `DS0` writer - "]
pub type Ds0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DS1` reader - "]
pub type Ds1R = crate::BitReader;
#[doc = "Field `DS1` writer - "]
pub type Ds1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IN` reader - "]
pub type InR = crate::BitReader;
#[doc = "Field `IN` writer - "]
pub type InW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SEL` reader - "]
pub type SelR = crate::FieldReader;
#[doc = "Field `SEL` writer - "]
pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ie(&self) -> IeR {
IeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ds0(&self) -> Ds0R {
Ds0R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ds1(&self) -> Ds1R {
Ds1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn in_(&self) -> InR {
InR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn sel(&self) -> SelR {
SelR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn out(&mut self) -> OutW<Pbr3rSpec> {
OutW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn oe(&mut self) -> OeW<Pbr3rSpec> {
OeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ie(&mut self) -> IeW<Pbr3rSpec> {
IeW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<Pbr3rSpec> {
PeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Pbr3rSpec> {
PsW::new(self, 4)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Pbr3rSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ds0(&mut self) -> Ds0W<Pbr3rSpec> {
Ds0W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ds1(&mut self) -> Ds1W<Pbr3rSpec> {
Ds1W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn in_(&mut self) -> InW<Pbr3rSpec> {
InW::new(self, 9)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Pbr3rSpec> {
Rsvd2W::new(self, 10)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn sel(&mut self) -> SelW<Pbr3rSpec> {
SelW::new(self, 12)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Pbr3rSpec> {
RsvdW::new(self, 15)
}
}
#[doc = "PBR3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pbr3r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pbr3r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pbr3rSpec;
impl crate::RegisterSpec for Pbr3rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pbr3r::R`](R) reader structure"]
impl crate::Readable for Pbr3rSpec {}
#[doc = "`write(|w| ..)` method takes [`pbr3r::W`](W) writer structure"]
impl crate::Writable for Pbr3rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PBR3R to value 0"]
impl crate::Resettable for Pbr3rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PAWK1R (rw) register accessor: PA Wakeup Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pawk1r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pawk1r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pawk1r`]
module"]
#[doc(alias = "PAWK1R")]
pub type Pawk1r = crate::Reg<pawk1r::Pawk1rSpec>;
#[doc = "PA Wakeup Register 1"]
pub mod pawk1r {
#[doc = "Register `PAWK1R` reader"]
pub type R = crate::R<Pawk1rSpec>;
#[doc = "Register `PAWK1R` writer"]
pub type W = crate::W<Pawk1rSpec>;
#[doc = "Field `PE` reader - Enable PA34 WKUP pull-down by default"]
pub type PeR = crate::FieldReader<u32>;
#[doc = "Field `PE` writer - Enable PA34 WKUP pull-down by default"]
pub type PeW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
impl R {
#[doc = "Bits 0:16 - Enable PA34 WKUP pull-down by default"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(self.bits & 0x0001_ffff)
}
#[doc = "Bits 17:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 17) & 0x7fff) as u16)
}
}
impl W {
#[doc = "Bits 0:16 - Enable PA34 WKUP pull-down by default"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<Pawk1rSpec> {
PeW::new(self, 0)
}
#[doc = "Bits 17:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Pawk1rSpec> {
RsvdW::new(self, 17)
}
}
#[doc = "PA Wakeup Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pawk1r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pawk1r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pawk1rSpec;
impl crate::RegisterSpec for Pawk1rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pawk1r::R`](R) reader structure"]
impl crate::Readable for Pawk1rSpec {}
#[doc = "`write(|w| ..)` method takes [`pawk1r::W`](W) writer structure"]
impl crate::Writable for Pawk1rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PAWK1R to value 0"]
impl crate::Resettable for Pawk1rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PAWK2R (rw) register accessor: PA Wakeup Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pawk2r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pawk2r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pawk2r`]
module"]
#[doc(alias = "PAWK2R")]
pub type Pawk2r = crate::Reg<pawk2r::Pawk2rSpec>;
#[doc = "PA Wakeup Register 2"]
pub mod pawk2r {
#[doc = "Register `PAWK2R` reader"]
pub type R = crate::R<Pawk2rSpec>;
#[doc = "Register `PAWK2R` writer"]
pub type W = crate::W<Pawk2rSpec>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::FieldReader<u32>;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
impl R {
#[doc = "Bits 0:16"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(self.bits & 0x0001_ffff)
}
#[doc = "Bits 17:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 17) & 0x7fff) as u16)
}
}
impl W {
#[doc = "Bits 0:16"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Pawk2rSpec> {
PsW::new(self, 0)
}
#[doc = "Bits 17:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Pawk2rSpec> {
RsvdW::new(self, 17)
}
}
#[doc = "PA Wakeup Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pawk2r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pawk2r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pawk2rSpec;
impl crate::RegisterSpec for Pawk2rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pawk2r::R`](R) reader structure"]
impl crate::Readable for Pawk2rSpec {}
#[doc = "`write(|w| ..)` method takes [`pawk2r::W`](W) writer structure"]
impl crate::Writable for Pawk2rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PAWK2R to value 0"]
impl crate::Resettable for Pawk2rSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PAWK3R (rw) register accessor: PA Wakeup Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pawk3r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pawk3r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pawk3r`]
module"]
#[doc(alias = "PAWK3R")]
pub type Pawk3r = crate::Reg<pawk3r::Pawk3rSpec>;
#[doc = "PA Wakeup Register 3"]
pub mod pawk3r {
#[doc = "Register `PAWK3R` reader"]
pub type R = crate::R<Pawk3rSpec>;
#[doc = "Register `PAWK3R` writer"]
pub type W = crate::W<Pawk3rSpec>;
#[doc = "Field `IS` reader - "]
pub type IsR = crate::FieldReader<u32>;
#[doc = "Field `IS` writer - "]
pub type IsW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
impl R {
#[doc = "Bits 0:16"]
#[inline(always)]
pub fn is(&self) -> IsR {
IsR::new(self.bits & 0x0001_ffff)
}
#[doc = "Bits 17:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 17) & 0x7fff) as u16)
}
}
impl W {
#[doc = "Bits 0:16"]
#[inline(always)]
#[must_use]
pub fn is(&mut self) -> IsW<Pawk3rSpec> {
IsW::new(self, 0)
}
#[doc = "Bits 17:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Pawk3rSpec> {
RsvdW::new(self, 17)
}
}
#[doc = "PA Wakeup Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pawk3r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pawk3r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pawk3rSpec;
impl crate::RegisterSpec for Pawk3rSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pawk3r::R`](R) reader structure"]
impl crate::Readable for Pawk3rSpec {}
#[doc = "`write(|w| ..)` method takes [`pawk3r::W`](W) writer structure"]
impl crate::Writable for Pawk3rSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PAWK3R to value 0"]
impl crate::Resettable for Pawk3rSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "IWDT"]
pub struct Iwdt {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Iwdt {}
impl Iwdt {
#[doc = r"Pointer to the register block"]
pub const PTR: *const iwdt::RegisterBlock = 0x500c_c000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const iwdt::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Iwdt {
type Target = iwdt::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Iwdt {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Iwdt").finish()
}
}
#[doc = "IWDT"]
pub mod iwdt {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
wdt_cvr0: WdtCvr0,
wdt_cvr1: WdtCvr1,
wdt_cr: WdtCr,
wdt_ccr: WdtCcr,
wdt_icr: WdtIcr,
wdt_sr: WdtSr,
wdt_wp: WdtWp,
wdt_fg: WdtFg,
}
impl RegisterBlock {
#[doc = "0x00 - WatchDog Counter Value 0"]
#[inline(always)]
pub const fn wdt_cvr0(&self) -> &WdtCvr0 {
&self.wdt_cvr0
}
#[doc = "0x04 - WatchDog Counter Value 1"]
#[inline(always)]
pub const fn wdt_cvr1(&self) -> &WdtCvr1 {
&self.wdt_cvr1
}
#[doc = "0x08 - WatchDog Control Register"]
#[inline(always)]
pub const fn wdt_cr(&self) -> &WdtCr {
&self.wdt_cr
}
#[doc = "0x0c - WatchDog Counter Control Register"]
#[inline(always)]
pub const fn wdt_ccr(&self) -> &WdtCcr {
&self.wdt_ccr
}
#[doc = "0x10 - WatchDog Interrupt Clear Register"]
#[inline(always)]
pub const fn wdt_icr(&self) -> &WdtIcr {
&self.wdt_icr
}
#[doc = "0x14 - WatchDog Status Register"]
#[inline(always)]
pub const fn wdt_sr(&self) -> &WdtSr {
&self.wdt_sr
}
#[doc = "0x18 - WatchDog Write Protect Register"]
#[inline(always)]
pub const fn wdt_wp(&self) -> &WdtWp {
&self.wdt_wp
}
#[doc = "0x1c - WatchDog Flag Register"]
#[inline(always)]
pub const fn wdt_fg(&self) -> &WdtFg {
&self.wdt_fg
}
}
#[doc = "WDT_CVR0 (rw) register accessor: WatchDog Counter Value 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cvr0`]
module"]
#[doc(alias = "WDT_CVR0")]
pub type WdtCvr0 = crate::Reg<wdt_cvr0::WdtCvr0Spec>;
#[doc = "WatchDog Counter Value 0"]
pub mod wdt_cvr0 {
#[doc = "Register `WDT_CVR0` reader"]
pub type R = crate::R<WdtCvr0Spec>;
#[doc = "Register `WDT_CVR0` writer"]
pub type W = crate::W<WdtCvr0Spec>;
#[doc = "Field `COUNT_VALUE_0` reader - Count Value for 1st TimeOut"]
pub type CountValue0R = crate::FieldReader<u32>;
#[doc = "Field `COUNT_VALUE_0` writer - Count Value for 1st TimeOut"]
pub type CountValue0W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Count Value for 1st TimeOut"]
#[inline(always)]
pub fn count_value_0(&self) -> CountValue0R {
CountValue0R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Count Value for 1st TimeOut"]
#[inline(always)]
#[must_use]
pub fn count_value_0(&mut self) -> CountValue0W<WdtCvr0Spec> {
CountValue0W::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCvr0Spec> {
RsvdW::new(self, 24)
}
}
#[doc = "WatchDog Counter Value 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCvr0Spec;
impl crate::RegisterSpec for WdtCvr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cvr0::R`](R) reader structure"]
impl crate::Readable for WdtCvr0Spec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cvr0::W`](W) writer structure"]
impl crate::Writable for WdtCvr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CVR0 to value 0"]
impl crate::Resettable for WdtCvr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CVR1 (rw) register accessor: WatchDog Counter Value 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cvr1`]
module"]
#[doc(alias = "WDT_CVR1")]
pub type WdtCvr1 = crate::Reg<wdt_cvr1::WdtCvr1Spec>;
#[doc = "WatchDog Counter Value 1"]
pub mod wdt_cvr1 {
#[doc = "Register `WDT_CVR1` reader"]
pub type R = crate::R<WdtCvr1Spec>;
#[doc = "Register `WDT_CVR1` writer"]
pub type W = crate::W<WdtCvr1Spec>;
#[doc = "Field `COUNT_VALUE_1` reader - Count Value for 2nd TimeOut"]
pub type CountValue1R = crate::FieldReader<u32>;
#[doc = "Field `COUNT_VALUE_1` writer - Count Value for 2nd TimeOut"]
pub type CountValue1W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Count Value for 2nd TimeOut"]
#[inline(always)]
pub fn count_value_1(&self) -> CountValue1R {
CountValue1R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Count Value for 2nd TimeOut"]
#[inline(always)]
#[must_use]
pub fn count_value_1(&mut self) -> CountValue1W<WdtCvr1Spec> {
CountValue1W::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCvr1Spec> {
RsvdW::new(self, 24)
}
}
#[doc = "WatchDog Counter Value 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCvr1Spec;
impl crate::RegisterSpec for WdtCvr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cvr1::R`](R) reader structure"]
impl crate::Readable for WdtCvr1Spec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cvr1::W`](W) writer structure"]
impl crate::Writable for WdtCvr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CVR1 to value 0"]
impl crate::Resettable for WdtCvr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CR (rw) register accessor: WatchDog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cr`]
module"]
#[doc(alias = "WDT_CR")]
pub type WdtCr = crate::Reg<wdt_cr::WdtCrSpec>;
#[doc = "WatchDog Control Register"]
pub mod wdt_cr {
#[doc = "Register `WDT_CR` reader"]
pub type R = crate::R<WdtCrSpec>;
#[doc = "Register `WDT_CR` writer"]
pub type W = crate::W<WdtCrSpec>;
#[doc = "Field `RESET_LENGTH` reader - reset pulse length in number of wdt clock cycles"]
pub type ResetLengthR = crate::FieldReader;
#[doc = "Field `RESET_LENGTH` writer - reset pulse length in number of wdt clock cycles"]
pub type ResetLengthW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RESPONSE_MODE` reader - 0:reset only, 1:interrupt and reset"]
pub type ResponseModeR = crate::BitReader;
#[doc = "Field `RESPONSE_MODE` writer - 0:reset only, 1:interrupt and reset"]
pub type ResponseModeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2 - reset pulse length in number of wdt clock cycles"]
#[inline(always)]
pub fn reset_length(&self) -> ResetLengthR {
ResetLengthR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 0:reset only, 1:interrupt and reset"]
#[inline(always)]
pub fn response_mode(&self) -> ResponseModeR {
ResponseModeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2 - reset pulse length in number of wdt clock cycles"]
#[inline(always)]
#[must_use]
pub fn reset_length(&mut self) -> ResetLengthW<WdtCrSpec> {
ResetLengthW::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<WdtCrSpec> {
Rsvd2W::new(self, 3)
}
#[doc = "Bit 4 - 0:reset only, 1:interrupt and reset"]
#[inline(always)]
#[must_use]
pub fn response_mode(&mut self) -> ResponseModeW<WdtCrSpec> {
ResponseModeW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "WatchDog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCrSpec;
impl crate::RegisterSpec for WdtCrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cr::R`](R) reader structure"]
impl crate::Readable for WdtCrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cr::W`](W) writer structure"]
impl crate::Writable for WdtCrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CR to value 0"]
impl crate::Resettable for WdtCrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CCR (rw) register accessor: WatchDog Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ccr`]
module"]
#[doc(alias = "WDT_CCR")]
pub type WdtCcr = crate::Reg<wdt_ccr::WdtCcrSpec>;
#[doc = "WatchDog Counter Control Register"]
pub mod wdt_ccr {
#[doc = "Register `WDT_CCR` reader"]
pub type R = crate::R<WdtCcrSpec>;
#[doc = "Register `WDT_CCR` writer"]
pub type W = crate::W<WdtCcrSpec>;
#[doc = "Field `COUNTER_CONTROL` reader - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
pub type CounterControlR = crate::FieldReader;
#[doc = "Field `COUNTER_CONTROL` writer - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
pub type CounterControlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
#[inline(always)]
pub fn counter_control(&self) -> CounterControlR {
CounterControlR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
#[inline(always)]
#[must_use]
pub fn counter_control(&mut self) -> CounterControlW<WdtCcrSpec> {
CounterControlW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "WatchDog Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCcrSpec;
impl crate::RegisterSpec for WdtCcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_ccr::R`](R) reader structure"]
impl crate::Readable for WdtCcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_ccr::W`](W) writer structure"]
impl crate::Writable for WdtCcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CCR to value 0"]
impl crate::Resettable for WdtCcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_ICR (rw) register accessor: WatchDog Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_icr`]
module"]
#[doc(alias = "WDT_ICR")]
pub type WdtIcr = crate::Reg<wdt_icr::WdtIcrSpec>;
#[doc = "WatchDog Interrupt Clear Register"]
pub mod wdt_icr {
#[doc = "Register `WDT_ICR` reader"]
pub type R = crate::R<WdtIcrSpec>;
#[doc = "Register `WDT_ICR` writer"]
pub type W = crate::W<WdtIcrSpec>;
#[doc = "Field `INT_CLR` reader - SinglePulse /A pulse to clear interrupt"]
pub type IntClrR = crate::BitReader;
#[doc = "Field `INT_CLR` writer - SinglePulse /A pulse to clear interrupt"]
pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - SinglePulse /A pulse to clear interrupt"]
#[inline(always)]
pub fn int_clr(&self) -> IntClrR {
IntClrR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SinglePulse /A pulse to clear interrupt"]
#[inline(always)]
#[must_use]
pub fn int_clr(&mut self) -> IntClrW<WdtIcrSpec> {
IntClrW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtIcrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "WatchDog Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtIcrSpec;
impl crate::RegisterSpec for WdtIcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_icr::R`](R) reader structure"]
impl crate::Readable for WdtIcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_icr::W`](W) writer structure"]
impl crate::Writable for WdtIcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_ICR to value 0"]
impl crate::Resettable for WdtIcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_SR (rw) register accessor: WatchDog Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_sr`]
module"]
#[doc(alias = "WDT_SR")]
pub type WdtSr = crate::Reg<wdt_sr::WdtSrSpec>;
#[doc = "WatchDog Status Register"]
pub mod wdt_sr {
#[doc = "Register `WDT_SR` reader"]
pub type R = crate::R<WdtSrSpec>;
#[doc = "Register `WDT_SR` writer"]
pub type W = crate::W<WdtSrSpec>;
#[doc = "Field `INT_ASSERT` reader - Interrupt assert when 1"]
pub type IntAssertR = crate::BitReader;
#[doc = "Field `INT_ASSERT` writer - Interrupt assert when 1"]
pub type IntAssertW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WDT_ACTIVE` reader - Watchdog runs when 1, else 0"]
pub type WdtActiveR = crate::BitReader;
#[doc = "Field `WDT_ACTIVE` writer - Watchdog runs when 1, else 0"]
pub type WdtActiveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - Interrupt assert when 1"]
#[inline(always)]
pub fn int_assert(&self) -> IntAssertR {
IntAssertR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Watchdog runs when 1, else 0"]
#[inline(always)]
pub fn wdt_active(&self) -> WdtActiveR {
WdtActiveR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Interrupt assert when 1"]
#[inline(always)]
#[must_use]
pub fn int_assert(&mut self) -> IntAssertW<WdtSrSpec> {
IntAssertW::new(self, 0)
}
#[doc = "Bit 1 - Watchdog runs when 1, else 0"]
#[inline(always)]
#[must_use]
pub fn wdt_active(&mut self) -> WdtActiveW<WdtSrSpec> {
WdtActiveW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtSrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "WatchDog Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtSrSpec;
impl crate::RegisterSpec for WdtSrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_sr::R`](R) reader structure"]
impl crate::Readable for WdtSrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_sr::W`](W) writer structure"]
impl crate::Writable for WdtSrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_SR to value 0"]
impl crate::Resettable for WdtSrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_WP (rw) register accessor: WatchDog Write Protect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_wp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_wp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_wp`]
module"]
#[doc(alias = "WDT_WP")]
pub type WdtWp = crate::Reg<wdt_wp::WdtWpSpec>;
#[doc = "WatchDog Write Protect Register"]
pub mod wdt_wp {
#[doc = "Register `WDT_WP` reader"]
pub type R = crate::R<WdtWpSpec>;
#[doc = "Register `WDT_WP` writer"]
pub type W = crate::W<WdtWpSpec>;
#[doc = "Field `WRPT` reader - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
pub type WrptR = crate::FieldReader<u32>;
#[doc = "Field `WRPT` writer - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
pub type WrptW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
#[doc = "Field `WRPT_ST` reader - 1 indicates write protect is active"]
pub type WrptStR = crate::BitReader;
#[doc = "Field `WRPT_ST` writer - 1 indicates write protect is active"]
pub type WrptStW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:30 - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
#[inline(always)]
pub fn wrpt(&self) -> WrptR {
WrptR::new(self.bits & 0x7fff_ffff)
}
#[doc = "Bit 31 - 1 indicates write protect is active"]
#[inline(always)]
pub fn wrpt_st(&self) -> WrptStR {
WrptStR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:30 - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
#[inline(always)]
#[must_use]
pub fn wrpt(&mut self) -> WrptW<WdtWpSpec> {
WrptW::new(self, 0)
}
#[doc = "Bit 31 - 1 indicates write protect is active"]
#[inline(always)]
#[must_use]
pub fn wrpt_st(&mut self) -> WrptStW<WdtWpSpec> {
WrptStW::new(self, 31)
}
}
#[doc = "WatchDog Write Protect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_wp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_wp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtWpSpec;
impl crate::RegisterSpec for WdtWpSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_wp::R`](R) reader structure"]
impl crate::Readable for WdtWpSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_wp::W`](W) writer structure"]
impl crate::Writable for WdtWpSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_WP to value 0"]
impl crate::Resettable for WdtWpSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_FG (rw) register accessor: WatchDog Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_fg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_fg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_fg`]
module"]
#[doc(alias = "WDT_FG")]
pub type WdtFg = crate::Reg<wdt_fg::WdtFgSpec>;
#[doc = "WatchDog Flag Register"]
pub mod wdt_fg {
#[doc = "Register `WDT_FG` reader"]
pub type R = crate::R<WdtFgSpec>;
#[doc = "Register `WDT_FG` writer"]
pub type W = crate::W<WdtFgSpec>;
#[doc = "Field `RST_FG_CLR` reader - SinglePulse/A pulse to clear reset flag"]
pub type RstFgClrR = crate::BitReader;
#[doc = "Field `RST_FG_CLR` writer - SinglePulse/A pulse to clear reset flag"]
pub type RstFgClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RST_FG` reader - 1 indicates wdt has already reset system"]
pub type RstFgR = crate::BitReader;
#[doc = "Field `RST_FG` writer - 1 indicates wdt has already reset system"]
pub type RstFgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYNC_FG_CLR` reader - SinglePulse/A pulse to clear sync flag"]
pub type SyncFgClrR = crate::BitReader;
#[doc = "Field `SYNC_FG_CLR` writer - SinglePulse/A pulse to clear sync flag"]
pub type SyncFgClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYNC_FG` reader - 1 indicates one transition from system clk to wdt clk has complicated"]
pub type SyncFgR = crate::BitReader;
#[doc = "Field `SYNC_FG` writer - 1 indicates one transition from system clk to wdt clk has complicated"]
pub type SyncFgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - SinglePulse/A pulse to clear reset flag"]
#[inline(always)]
pub fn rst_fg_clr(&self) -> RstFgClrR {
RstFgClrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1 indicates wdt has already reset system"]
#[inline(always)]
pub fn rst_fg(&self) -> RstFgR {
RstFgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SinglePulse/A pulse to clear sync flag"]
#[inline(always)]
pub fn sync_fg_clr(&self) -> SyncFgClrR {
SyncFgClrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 1 indicates one transition from system clk to wdt clk has complicated"]
#[inline(always)]
pub fn sync_fg(&self) -> SyncFgR {
SyncFgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SinglePulse/A pulse to clear reset flag"]
#[inline(always)]
#[must_use]
pub fn rst_fg_clr(&mut self) -> RstFgClrW<WdtFgSpec> {
RstFgClrW::new(self, 0)
}
#[doc = "Bit 1 - 1 indicates wdt has already reset system"]
#[inline(always)]
#[must_use]
pub fn rst_fg(&mut self) -> RstFgW<WdtFgSpec> {
RstFgW::new(self, 1)
}
#[doc = "Bit 2 - SinglePulse/A pulse to clear sync flag"]
#[inline(always)]
#[must_use]
pub fn sync_fg_clr(&mut self) -> SyncFgClrW<WdtFgSpec> {
SyncFgClrW::new(self, 2)
}
#[doc = "Bit 3 - 1 indicates one transition from system clk to wdt clk has complicated"]
#[inline(always)]
#[must_use]
pub fn sync_fg(&mut self) -> SyncFgW<WdtFgSpec> {
SyncFgW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtFgSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "WatchDog Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_fg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_fg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtFgSpec;
impl crate::RegisterSpec for WdtFgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_fg::R`](R) reader structure"]
impl crate::Readable for WdtFgSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_fg::W`](W) writer structure"]
impl crate::Writable for WdtFgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_FG to value 0"]
impl crate::Resettable for WdtFgSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "DMAC2"]
pub struct Dmac2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Dmac2 {}
impl Dmac2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dmac2::RegisterBlock = 0x4000_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dmac2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Dmac2 {
type Target = dmac2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Dmac2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dmac2").finish()
}
}
#[doc = "DMAC2"]
pub mod dmac2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
isr: Isr,
ifcr: Ifcr,
ccr1: Ccr1,
cndtr1: Cndtr1,
cpar1: Cpar1,
cm0ar1: Cm0ar1,
cbsr1: Cbsr1,
ccr2: Ccr2,
cndtr2: Cndtr2,
cpar2: Cpar2,
cm0ar2: Cm0ar2,
cbsr2: Cbsr2,
ccr3: Ccr3,
cndtr3: Cndtr3,
cpar3: Cpar3,
cm0ar3: Cm0ar3,
cbsr3: Cbsr3,
ccr4: Ccr4,
cndtr4: Cndtr4,
cpar4: Cpar4,
cm0ar4: Cm0ar4,
cbsr4: Cbsr4,
ccr5: Ccr5,
cndtr5: Cndtr5,
cpar5: Cpar5,
cm0ar5: Cm0ar5,
cbsr5: Cbsr5,
ccr6: Ccr6,
cndtr6: Cndtr6,
cpar6: Cpar6,
cm0ar6: Cm0ar6,
cbsr6: Cbsr6,
ccr7: Ccr7,
cndtr7: Cndtr7,
cpar7: Cpar7,
cm0ar7: Cm0ar7,
cbsr7: Cbsr7,
ccr8: Ccr8,
cndtr8: Cndtr8,
cpar8: Cpar8,
cm0ar8: Cm0ar8,
cbsr8: Cbsr8,
cselr1: Cselr1,
cselr2: Cselr2,
}
impl RegisterBlock {
#[doc = "0x00 - "]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x04 - "]
#[inline(always)]
pub const fn ifcr(&self) -> &Ifcr {
&self.ifcr
}
#[doc = "0x08 - "]
#[inline(always)]
pub const fn ccr1(&self) -> &Ccr1 {
&self.ccr1
}
#[doc = "0x0c - "]
#[inline(always)]
pub const fn cndtr1(&self) -> &Cndtr1 {
&self.cndtr1
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn cpar1(&self) -> &Cpar1 {
&self.cpar1
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn cm0ar1(&self) -> &Cm0ar1 {
&self.cm0ar1
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn cbsr1(&self) -> &Cbsr1 {
&self.cbsr1
}
#[doc = "0x1c - "]
#[inline(always)]
pub const fn ccr2(&self) -> &Ccr2 {
&self.ccr2
}
#[doc = "0x20 - "]
#[inline(always)]
pub const fn cndtr2(&self) -> &Cndtr2 {
&self.cndtr2
}
#[doc = "0x24 - "]
#[inline(always)]
pub const fn cpar2(&self) -> &Cpar2 {
&self.cpar2
}
#[doc = "0x28 - "]
#[inline(always)]
pub const fn cm0ar2(&self) -> &Cm0ar2 {
&self.cm0ar2
}
#[doc = "0x2c - "]
#[inline(always)]
pub const fn cbsr2(&self) -> &Cbsr2 {
&self.cbsr2
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn ccr3(&self) -> &Ccr3 {
&self.ccr3
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn cndtr3(&self) -> &Cndtr3 {
&self.cndtr3
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn cpar3(&self) -> &Cpar3 {
&self.cpar3
}
#[doc = "0x3c - "]
#[inline(always)]
pub const fn cm0ar3(&self) -> &Cm0ar3 {
&self.cm0ar3
}
#[doc = "0x40 - "]
#[inline(always)]
pub const fn cbsr3(&self) -> &Cbsr3 {
&self.cbsr3
}
#[doc = "0x44 - "]
#[inline(always)]
pub const fn ccr4(&self) -> &Ccr4 {
&self.ccr4
}
#[doc = "0x48 - "]
#[inline(always)]
pub const fn cndtr4(&self) -> &Cndtr4 {
&self.cndtr4
}
#[doc = "0x4c - "]
#[inline(always)]
pub const fn cpar4(&self) -> &Cpar4 {
&self.cpar4
}
#[doc = "0x50 - "]
#[inline(always)]
pub const fn cm0ar4(&self) -> &Cm0ar4 {
&self.cm0ar4
}
#[doc = "0x54 - "]
#[inline(always)]
pub const fn cbsr4(&self) -> &Cbsr4 {
&self.cbsr4
}
#[doc = "0x58 - "]
#[inline(always)]
pub const fn ccr5(&self) -> &Ccr5 {
&self.ccr5
}
#[doc = "0x5c - "]
#[inline(always)]
pub const fn cndtr5(&self) -> &Cndtr5 {
&self.cndtr5
}
#[doc = "0x60 - "]
#[inline(always)]
pub const fn cpar5(&self) -> &Cpar5 {
&self.cpar5
}
#[doc = "0x64 - "]
#[inline(always)]
pub const fn cm0ar5(&self) -> &Cm0ar5 {
&self.cm0ar5
}
#[doc = "0x68 - "]
#[inline(always)]
pub const fn cbsr5(&self) -> &Cbsr5 {
&self.cbsr5
}
#[doc = "0x6c - "]
#[inline(always)]
pub const fn ccr6(&self) -> &Ccr6 {
&self.ccr6
}
#[doc = "0x70 - "]
#[inline(always)]
pub const fn cndtr6(&self) -> &Cndtr6 {
&self.cndtr6
}
#[doc = "0x74 - "]
#[inline(always)]
pub const fn cpar6(&self) -> &Cpar6 {
&self.cpar6
}
#[doc = "0x78 - "]
#[inline(always)]
pub const fn cm0ar6(&self) -> &Cm0ar6 {
&self.cm0ar6
}
#[doc = "0x7c - "]
#[inline(always)]
pub const fn cbsr6(&self) -> &Cbsr6 {
&self.cbsr6
}
#[doc = "0x80 - "]
#[inline(always)]
pub const fn ccr7(&self) -> &Ccr7 {
&self.ccr7
}
#[doc = "0x84 - "]
#[inline(always)]
pub const fn cndtr7(&self) -> &Cndtr7 {
&self.cndtr7
}
#[doc = "0x88 - "]
#[inline(always)]
pub const fn cpar7(&self) -> &Cpar7 {
&self.cpar7
}
#[doc = "0x8c - "]
#[inline(always)]
pub const fn cm0ar7(&self) -> &Cm0ar7 {
&self.cm0ar7
}
#[doc = "0x90 - "]
#[inline(always)]
pub const fn cbsr7(&self) -> &Cbsr7 {
&self.cbsr7
}
#[doc = "0x94 - "]
#[inline(always)]
pub const fn ccr8(&self) -> &Ccr8 {
&self.ccr8
}
#[doc = "0x98 - "]
#[inline(always)]
pub const fn cndtr8(&self) -> &Cndtr8 {
&self.cndtr8
}
#[doc = "0x9c - "]
#[inline(always)]
pub const fn cpar8(&self) -> &Cpar8 {
&self.cpar8
}
#[doc = "0xa0 - "]
#[inline(always)]
pub const fn cm0ar8(&self) -> &Cm0ar8 {
&self.cm0ar8
}
#[doc = "0xa4 - "]
#[inline(always)]
pub const fn cbsr8(&self) -> &Cbsr8 {
&self.cbsr8
}
#[doc = "0xa8 - "]
#[inline(always)]
pub const fn cselr1(&self) -> &Cselr1 {
&self.cselr1
}
#[doc = "0xac - "]
#[inline(always)]
pub const fn cselr2(&self) -> &Cselr2 {
&self.cselr2
}
}
#[doc = "ISR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = ""]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `GIF1` reader - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
pub type Gif1R = crate::BitReader;
#[doc = "Field `GIF1` writer - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
pub type Gif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF1` reader - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
pub type Tcif1R = crate::BitReader;
#[doc = "Field `TCIF1` writer - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
pub type Tcif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF1` reader - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
pub type Htif1R = crate::BitReader;
#[doc = "Field `HTIF1` writer - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
pub type Htif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF1` reader - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
pub type Teif1R = crate::BitReader;
#[doc = "Field `TEIF1` writer - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
pub type Teif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF2` reader - channel global interrupt flag"]
pub type Gif2R = crate::BitReader;
#[doc = "Field `GIF2` writer - channel global interrupt flag"]
pub type Gif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF2` reader - channel transfer complete flag"]
pub type Tcif2R = crate::BitReader;
#[doc = "Field `TCIF2` writer - channel transfer complete flag"]
pub type Tcif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF2` reader - channel half transfer flag"]
pub type Htif2R = crate::BitReader;
#[doc = "Field `HTIF2` writer - channel half transfer flag"]
pub type Htif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF2` reader - channel transfer error flag"]
pub type Teif2R = crate::BitReader;
#[doc = "Field `TEIF2` writer - channel transfer error flag"]
pub type Teif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF3` reader - channel global interrupt flag"]
pub type Gif3R = crate::BitReader;
#[doc = "Field `GIF3` writer - channel global interrupt flag"]
pub type Gif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF3` reader - channel transfer complete flag"]
pub type Tcif3R = crate::BitReader;
#[doc = "Field `TCIF3` writer - channel transfer complete flag"]
pub type Tcif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF3` reader - channel half transfer flag"]
pub type Htif3R = crate::BitReader;
#[doc = "Field `HTIF3` writer - channel half transfer flag"]
pub type Htif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF3` reader - channel transfer error flag"]
pub type Teif3R = crate::BitReader;
#[doc = "Field `TEIF3` writer - channel transfer error flag"]
pub type Teif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF4` reader - channel global interrupt flag"]
pub type Gif4R = crate::BitReader;
#[doc = "Field `GIF4` writer - channel global interrupt flag"]
pub type Gif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF4` reader - channel transfer complete flag"]
pub type Tcif4R = crate::BitReader;
#[doc = "Field `TCIF4` writer - channel transfer complete flag"]
pub type Tcif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF4` reader - channel half transfer flag"]
pub type Htif4R = crate::BitReader;
#[doc = "Field `HTIF4` writer - channel half transfer flag"]
pub type Htif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF4` reader - channel transfer error flag"]
pub type Teif4R = crate::BitReader;
#[doc = "Field `TEIF4` writer - channel transfer error flag"]
pub type Teif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF5` reader - channel global interrupt flag"]
pub type Gif5R = crate::BitReader;
#[doc = "Field `GIF5` writer - channel global interrupt flag"]
pub type Gif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF5` reader - channel transfer complete flag"]
pub type Tcif5R = crate::BitReader;
#[doc = "Field `TCIF5` writer - channel transfer complete flag"]
pub type Tcif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF5` reader - channel half transfer flag"]
pub type Htif5R = crate::BitReader;
#[doc = "Field `HTIF5` writer - channel half transfer flag"]
pub type Htif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF5` reader - channel transfer error flag"]
pub type Teif5R = crate::BitReader;
#[doc = "Field `TEIF5` writer - channel transfer error flag"]
pub type Teif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF6` reader - channel global interrupt flag"]
pub type Gif6R = crate::BitReader;
#[doc = "Field `GIF6` writer - channel global interrupt flag"]
pub type Gif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF6` reader - channel transfer complete flag"]
pub type Tcif6R = crate::BitReader;
#[doc = "Field `TCIF6` writer - channel transfer complete flag"]
pub type Tcif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF6` reader - channel half transfer flag"]
pub type Htif6R = crate::BitReader;
#[doc = "Field `HTIF6` writer - channel half transfer flag"]
pub type Htif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF6` reader - channel transfer error flag"]
pub type Teif6R = crate::BitReader;
#[doc = "Field `TEIF6` writer - channel transfer error flag"]
pub type Teif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF7` reader - channel global interrupt flag"]
pub type Gif7R = crate::BitReader;
#[doc = "Field `GIF7` writer - channel global interrupt flag"]
pub type Gif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF7` reader - channel transfer complete flag"]
pub type Tcif7R = crate::BitReader;
#[doc = "Field `TCIF7` writer - channel transfer complete flag"]
pub type Tcif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF7` reader - channel half transfer flag"]
pub type Htif7R = crate::BitReader;
#[doc = "Field `HTIF7` writer - channel half transfer flag"]
pub type Htif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF7` reader - channel transfer error flag"]
pub type Teif7R = crate::BitReader;
#[doc = "Field `TEIF7` writer - channel transfer error flag"]
pub type Teif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GIF8` reader - channel global interrupt flag"]
pub type Gif8R = crate::BitReader;
#[doc = "Field `GIF8` writer - channel global interrupt flag"]
pub type Gif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIF8` reader - channel transfer complete flag"]
pub type Tcif8R = crate::BitReader;
#[doc = "Field `TCIF8` writer - channel transfer complete flag"]
pub type Tcif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIF8` reader - channel half transfer flag"]
pub type Htif8R = crate::BitReader;
#[doc = "Field `HTIF8` writer - channel half transfer flag"]
pub type Htif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIF8` reader - channel transfer error flag"]
pub type Teif8R = crate::BitReader;
#[doc = "Field `TEIF8` writer - channel transfer error flag"]
pub type Teif8W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
#[inline(always)]
pub fn gif1(&self) -> Gif1R {
Gif1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
#[inline(always)]
pub fn tcif1(&self) -> Tcif1R {
Tcif1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
#[inline(always)]
pub fn htif1(&self) -> Htif1R {
Htif1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
#[inline(always)]
pub fn teif1(&self) -> Teif1R {
Teif1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - channel global interrupt flag"]
#[inline(always)]
pub fn gif2(&self) -> Gif2R {
Gif2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif2(&self) -> Tcif2R {
Tcif2R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - channel half transfer flag"]
#[inline(always)]
pub fn htif2(&self) -> Htif2R {
Htif2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - channel transfer error flag"]
#[inline(always)]
pub fn teif2(&self) -> Teif2R {
Teif2R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - channel global interrupt flag"]
#[inline(always)]
pub fn gif3(&self) -> Gif3R {
Gif3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif3(&self) -> Tcif3R {
Tcif3R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - channel half transfer flag"]
#[inline(always)]
pub fn htif3(&self) -> Htif3R {
Htif3R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - channel transfer error flag"]
#[inline(always)]
pub fn teif3(&self) -> Teif3R {
Teif3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - channel global interrupt flag"]
#[inline(always)]
pub fn gif4(&self) -> Gif4R {
Gif4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif4(&self) -> Tcif4R {
Tcif4R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - channel half transfer flag"]
#[inline(always)]
pub fn htif4(&self) -> Htif4R {
Htif4R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - channel transfer error flag"]
#[inline(always)]
pub fn teif4(&self) -> Teif4R {
Teif4R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - channel global interrupt flag"]
#[inline(always)]
pub fn gif5(&self) -> Gif5R {
Gif5R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif5(&self) -> Tcif5R {
Tcif5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - channel half transfer flag"]
#[inline(always)]
pub fn htif5(&self) -> Htif5R {
Htif5R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - channel transfer error flag"]
#[inline(always)]
pub fn teif5(&self) -> Teif5R {
Teif5R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - channel global interrupt flag"]
#[inline(always)]
pub fn gif6(&self) -> Gif6R {
Gif6R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif6(&self) -> Tcif6R {
Tcif6R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - channel half transfer flag"]
#[inline(always)]
pub fn htif6(&self) -> Htif6R {
Htif6R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - channel transfer error flag"]
#[inline(always)]
pub fn teif6(&self) -> Teif6R {
Teif6R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - channel global interrupt flag"]
#[inline(always)]
pub fn gif7(&self) -> Gif7R {
Gif7R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif7(&self) -> Tcif7R {
Tcif7R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - channel half transfer flag"]
#[inline(always)]
pub fn htif7(&self) -> Htif7R {
Htif7R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - channel transfer error flag"]
#[inline(always)]
pub fn teif7(&self) -> Teif7R {
Teif7R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - channel global interrupt flag"]
#[inline(always)]
pub fn gif8(&self) -> Gif8R {
Gif8R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - channel transfer complete flag"]
#[inline(always)]
pub fn tcif8(&self) -> Tcif8R {
Tcif8R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - channel half transfer flag"]
#[inline(always)]
pub fn htif8(&self) -> Htif8R {
Htif8R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - channel transfer error flag"]
#[inline(always)]
pub fn teif8(&self) -> Teif8R {
Teif8R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared."]
#[inline(always)]
#[must_use]
pub fn gif1(&mut self) -> Gif1W<IsrSpec> {
Gif1W::new(self, 0)
}
#[doc = "Bit 1 - channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF."]
#[inline(always)]
#[must_use]
pub fn tcif1(&mut self) -> Tcif1W<IsrSpec> {
Tcif1W::new(self, 1)
}
#[doc = "Bit 2 - channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF."]
#[inline(always)]
#[must_use]
pub fn htif1(&mut self) -> Htif1W<IsrSpec> {
Htif1W::new(self, 2)
}
#[doc = "Bit 3 - channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF."]
#[inline(always)]
#[must_use]
pub fn teif1(&mut self) -> Teif1W<IsrSpec> {
Teif1W::new(self, 3)
}
#[doc = "Bit 4 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif2(&mut self) -> Gif2W<IsrSpec> {
Gif2W::new(self, 4)
}
#[doc = "Bit 5 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif2(&mut self) -> Tcif2W<IsrSpec> {
Tcif2W::new(self, 5)
}
#[doc = "Bit 6 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif2(&mut self) -> Htif2W<IsrSpec> {
Htif2W::new(self, 6)
}
#[doc = "Bit 7 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif2(&mut self) -> Teif2W<IsrSpec> {
Teif2W::new(self, 7)
}
#[doc = "Bit 8 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif3(&mut self) -> Gif3W<IsrSpec> {
Gif3W::new(self, 8)
}
#[doc = "Bit 9 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif3(&mut self) -> Tcif3W<IsrSpec> {
Tcif3W::new(self, 9)
}
#[doc = "Bit 10 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif3(&mut self) -> Htif3W<IsrSpec> {
Htif3W::new(self, 10)
}
#[doc = "Bit 11 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif3(&mut self) -> Teif3W<IsrSpec> {
Teif3W::new(self, 11)
}
#[doc = "Bit 12 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif4(&mut self) -> Gif4W<IsrSpec> {
Gif4W::new(self, 12)
}
#[doc = "Bit 13 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif4(&mut self) -> Tcif4W<IsrSpec> {
Tcif4W::new(self, 13)
}
#[doc = "Bit 14 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif4(&mut self) -> Htif4W<IsrSpec> {
Htif4W::new(self, 14)
}
#[doc = "Bit 15 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif4(&mut self) -> Teif4W<IsrSpec> {
Teif4W::new(self, 15)
}
#[doc = "Bit 16 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif5(&mut self) -> Gif5W<IsrSpec> {
Gif5W::new(self, 16)
}
#[doc = "Bit 17 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif5(&mut self) -> Tcif5W<IsrSpec> {
Tcif5W::new(self, 17)
}
#[doc = "Bit 18 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif5(&mut self) -> Htif5W<IsrSpec> {
Htif5W::new(self, 18)
}
#[doc = "Bit 19 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif5(&mut self) -> Teif5W<IsrSpec> {
Teif5W::new(self, 19)
}
#[doc = "Bit 20 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif6(&mut self) -> Gif6W<IsrSpec> {
Gif6W::new(self, 20)
}
#[doc = "Bit 21 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif6(&mut self) -> Tcif6W<IsrSpec> {
Tcif6W::new(self, 21)
}
#[doc = "Bit 22 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif6(&mut self) -> Htif6W<IsrSpec> {
Htif6W::new(self, 22)
}
#[doc = "Bit 23 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif6(&mut self) -> Teif6W<IsrSpec> {
Teif6W::new(self, 23)
}
#[doc = "Bit 24 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif7(&mut self) -> Gif7W<IsrSpec> {
Gif7W::new(self, 24)
}
#[doc = "Bit 25 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif7(&mut self) -> Tcif7W<IsrSpec> {
Tcif7W::new(self, 25)
}
#[doc = "Bit 26 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif7(&mut self) -> Htif7W<IsrSpec> {
Htif7W::new(self, 26)
}
#[doc = "Bit 27 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif7(&mut self) -> Teif7W<IsrSpec> {
Teif7W::new(self, 27)
}
#[doc = "Bit 28 - channel global interrupt flag"]
#[inline(always)]
#[must_use]
pub fn gif8(&mut self) -> Gif8W<IsrSpec> {
Gif8W::new(self, 28)
}
#[doc = "Bit 29 - channel transfer complete flag"]
#[inline(always)]
#[must_use]
pub fn tcif8(&mut self) -> Tcif8W<IsrSpec> {
Tcif8W::new(self, 29)
}
#[doc = "Bit 30 - channel half transfer flag"]
#[inline(always)]
#[must_use]
pub fn htif8(&mut self) -> Htif8W<IsrSpec> {
Htif8W::new(self, 30)
}
#[doc = "Bit 31 - channel transfer error flag"]
#[inline(always)]
#[must_use]
pub fn teif8(&mut self) -> Teif8W<IsrSpec> {
Teif8W::new(self, 31)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IFCR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifcr`]
module"]
#[doc(alias = "IFCR")]
pub type Ifcr = crate::Reg<ifcr::IfcrSpec>;
#[doc = ""]
pub mod ifcr {
#[doc = "Register `IFCR` reader"]
pub type R = crate::R<IfcrSpec>;
#[doc = "Register `IFCR` writer"]
pub type W = crate::W<IfcrSpec>;
#[doc = "Field `CGIF1` reader - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
pub type Cgif1R = crate::BitReader;
#[doc = "Field `CGIF1` writer - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
pub type Cgif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF1` reader - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
pub type Ctcif1R = crate::BitReader;
#[doc = "Field `CTCIF1` writer - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
pub type Ctcif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF1` reader - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
pub type Chtif1R = crate::BitReader;
#[doc = "Field `CHTIF1` writer - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
pub type Chtif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF1` reader - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
pub type Cteif1R = crate::BitReader;
#[doc = "Field `CTEIF1` writer - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
pub type Cteif1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF2` reader - CGIF, global interrupt flag clear"]
pub type Cgif2R = crate::BitReader;
#[doc = "Field `CGIF2` writer - CGIF, global interrupt flag clear"]
pub type Cgif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF2` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif2R = crate::BitReader;
#[doc = "Field `CTCIF2` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF2` reader - CHTIF, half transfer flag clear"]
pub type Chtif2R = crate::BitReader;
#[doc = "Field `CHTIF2` writer - CHTIF, half transfer flag clear"]
pub type Chtif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF2` reader - CTEIF, transfer error flag clear"]
pub type Cteif2R = crate::BitReader;
#[doc = "Field `CTEIF2` writer - CTEIF, transfer error flag clear"]
pub type Cteif2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF3` reader - CGIF, global interrupt flag clear"]
pub type Cgif3R = crate::BitReader;
#[doc = "Field `CGIF3` writer - CGIF, global interrupt flag clear"]
pub type Cgif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF3` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif3R = crate::BitReader;
#[doc = "Field `CTCIF3` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF3` reader - CHTIF, half transfer flag clear"]
pub type Chtif3R = crate::BitReader;
#[doc = "Field `CHTIF3` writer - CHTIF, half transfer flag clear"]
pub type Chtif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF3` reader - CTEIF, transfer error flag clear"]
pub type Cteif3R = crate::BitReader;
#[doc = "Field `CTEIF3` writer - CTEIF, transfer error flag clear"]
pub type Cteif3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF4` reader - CGIF, global interrupt flag clear"]
pub type Cgif4R = crate::BitReader;
#[doc = "Field `CGIF4` writer - CGIF, global interrupt flag clear"]
pub type Cgif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF4` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif4R = crate::BitReader;
#[doc = "Field `CTCIF4` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF4` reader - CHTIF, half transfer flag clear"]
pub type Chtif4R = crate::BitReader;
#[doc = "Field `CHTIF4` writer - CHTIF, half transfer flag clear"]
pub type Chtif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF4` reader - CTEIF, transfer error flag clear"]
pub type Cteif4R = crate::BitReader;
#[doc = "Field `CTEIF4` writer - CTEIF, transfer error flag clear"]
pub type Cteif4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF5` reader - CGIF, global interrupt flag clear"]
pub type Cgif5R = crate::BitReader;
#[doc = "Field `CGIF5` writer - CGIF, global interrupt flag clear"]
pub type Cgif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF5` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif5R = crate::BitReader;
#[doc = "Field `CTCIF5` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF5` reader - CHTIF, half transfer flag clear"]
pub type Chtif5R = crate::BitReader;
#[doc = "Field `CHTIF5` writer - CHTIF, half transfer flag clear"]
pub type Chtif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF5` reader - CTEIF, transfer error flag clear"]
pub type Cteif5R = crate::BitReader;
#[doc = "Field `CTEIF5` writer - CTEIF, transfer error flag clear"]
pub type Cteif5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF6` reader - CGIF, global interrupt flag clear"]
pub type Cgif6R = crate::BitReader;
#[doc = "Field `CGIF6` writer - CGIF, global interrupt flag clear"]
pub type Cgif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF6` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif6R = crate::BitReader;
#[doc = "Field `CTCIF6` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF6` reader - CHTIF, half transfer flag clear"]
pub type Chtif6R = crate::BitReader;
#[doc = "Field `CHTIF6` writer - CHTIF, half transfer flag clear"]
pub type Chtif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF6` reader - CTEIF, transfer error flag clear"]
pub type Cteif6R = crate::BitReader;
#[doc = "Field `CTEIF6` writer - CTEIF, transfer error flag clear"]
pub type Cteif6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF7` reader - CGIF, global interrupt flag clear"]
pub type Cgif7R = crate::BitReader;
#[doc = "Field `CGIF7` writer - CGIF, global interrupt flag clear"]
pub type Cgif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF7` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif7R = crate::BitReader;
#[doc = "Field `CTCIF7` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF7` reader - CHTIF, half transfer flag clear"]
pub type Chtif7R = crate::BitReader;
#[doc = "Field `CHTIF7` writer - CHTIF, half transfer flag clear"]
pub type Chtif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF7` reader - CTEIF, transfer error flag clear"]
pub type Cteif7R = crate::BitReader;
#[doc = "Field `CTEIF7` writer - CTEIF, transfer error flag clear"]
pub type Cteif7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CGIF8` reader - CGIF, global interrupt flag clear"]
pub type Cgif8R = crate::BitReader;
#[doc = "Field `CGIF8` writer - CGIF, global interrupt flag clear"]
pub type Cgif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTCIF8` reader - CTCIF, transfer complete flag clear"]
pub type Ctcif8R = crate::BitReader;
#[doc = "Field `CTCIF8` writer - CTCIF, transfer complete flag clear"]
pub type Ctcif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHTIF8` reader - CHTIF, half transfer flag clear"]
pub type Chtif8R = crate::BitReader;
#[doc = "Field `CHTIF8` writer - CHTIF, half transfer flag clear"]
pub type Chtif8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTEIF8` reader - CTEIF, transfer error flag clear"]
pub type Cteif8R = crate::BitReader;
#[doc = "Field `CTEIF8` writer - CTEIF, transfer error flag clear"]
pub type Cteif8W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
#[inline(always)]
pub fn cgif1(&self) -> Cgif1R {
Cgif1R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
#[inline(always)]
pub fn ctcif1(&self) -> Ctcif1R {
Ctcif1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
#[inline(always)]
pub fn chtif1(&self) -> Chtif1R {
Chtif1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
#[inline(always)]
pub fn cteif1(&self) -> Cteif1R {
Cteif1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif2(&self) -> Cgif2R {
Cgif2R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif2(&self) -> Ctcif2R {
Ctcif2R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif2(&self) -> Chtif2R {
Chtif2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif2(&self) -> Cteif2R {
Cteif2R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif3(&self) -> Cgif3R {
Cgif3R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif3(&self) -> Ctcif3R {
Ctcif3R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif3(&self) -> Chtif3R {
Chtif3R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif3(&self) -> Cteif3R {
Cteif3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif4(&self) -> Cgif4R {
Cgif4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif4(&self) -> Ctcif4R {
Ctcif4R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif4(&self) -> Chtif4R {
Chtif4R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif4(&self) -> Cteif4R {
Cteif4R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif5(&self) -> Cgif5R {
Cgif5R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif5(&self) -> Ctcif5R {
Ctcif5R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif5(&self) -> Chtif5R {
Chtif5R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif5(&self) -> Cteif5R {
Cteif5R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif6(&self) -> Cgif6R {
Cgif6R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif6(&self) -> Ctcif6R {
Ctcif6R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif6(&self) -> Chtif6R {
Chtif6R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif6(&self) -> Cteif6R {
Cteif6R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif7(&self) -> Cgif7R {
Cgif7R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif7(&self) -> Ctcif7R {
Ctcif7R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif7(&self) -> Chtif7R {
Chtif7R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif7(&self) -> Cteif7R {
Cteif7R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - CGIF, global interrupt flag clear"]
#[inline(always)]
pub fn cgif8(&self) -> Cgif8R {
Cgif8R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - CTCIF, transfer complete flag clear"]
#[inline(always)]
pub fn ctcif8(&self) -> Ctcif8R {
Ctcif8R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - CHTIF, half transfer flag clear"]
#[inline(always)]
pub fn chtif8(&self) -> Chtif8R {
Chtif8R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - CTEIF, transfer error flag clear"]
#[inline(always)]
pub fn cteif8(&self) -> Cteif8R {
Cteif8R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF."]
#[inline(always)]
#[must_use]
pub fn cgif1(&mut self) -> Cgif1W<IfcrSpec> {
Cgif1W::new(self, 0)
}
#[doc = "Bit 1 - CTCIF, transfer complete flag clear. Write 1 to clear TCIF."]
#[inline(always)]
#[must_use]
pub fn ctcif1(&mut self) -> Ctcif1W<IfcrSpec> {
Ctcif1W::new(self, 1)
}
#[doc = "Bit 2 - CHTIF, half transfer flag clear. Write 1 to clear HTIF."]
#[inline(always)]
#[must_use]
pub fn chtif1(&mut self) -> Chtif1W<IfcrSpec> {
Chtif1W::new(self, 2)
}
#[doc = "Bit 3 - CTEIF, transfer error flag clear. Write 1 to clear TEIF."]
#[inline(always)]
#[must_use]
pub fn cteif1(&mut self) -> Cteif1W<IfcrSpec> {
Cteif1W::new(self, 3)
}
#[doc = "Bit 4 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif2(&mut self) -> Cgif2W<IfcrSpec> {
Cgif2W::new(self, 4)
}
#[doc = "Bit 5 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif2(&mut self) -> Ctcif2W<IfcrSpec> {
Ctcif2W::new(self, 5)
}
#[doc = "Bit 6 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif2(&mut self) -> Chtif2W<IfcrSpec> {
Chtif2W::new(self, 6)
}
#[doc = "Bit 7 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif2(&mut self) -> Cteif2W<IfcrSpec> {
Cteif2W::new(self, 7)
}
#[doc = "Bit 8 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif3(&mut self) -> Cgif3W<IfcrSpec> {
Cgif3W::new(self, 8)
}
#[doc = "Bit 9 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif3(&mut self) -> Ctcif3W<IfcrSpec> {
Ctcif3W::new(self, 9)
}
#[doc = "Bit 10 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif3(&mut self) -> Chtif3W<IfcrSpec> {
Chtif3W::new(self, 10)
}
#[doc = "Bit 11 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif3(&mut self) -> Cteif3W<IfcrSpec> {
Cteif3W::new(self, 11)
}
#[doc = "Bit 12 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif4(&mut self) -> Cgif4W<IfcrSpec> {
Cgif4W::new(self, 12)
}
#[doc = "Bit 13 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif4(&mut self) -> Ctcif4W<IfcrSpec> {
Ctcif4W::new(self, 13)
}
#[doc = "Bit 14 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif4(&mut self) -> Chtif4W<IfcrSpec> {
Chtif4W::new(self, 14)
}
#[doc = "Bit 15 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif4(&mut self) -> Cteif4W<IfcrSpec> {
Cteif4W::new(self, 15)
}
#[doc = "Bit 16 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif5(&mut self) -> Cgif5W<IfcrSpec> {
Cgif5W::new(self, 16)
}
#[doc = "Bit 17 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif5(&mut self) -> Ctcif5W<IfcrSpec> {
Ctcif5W::new(self, 17)
}
#[doc = "Bit 18 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif5(&mut self) -> Chtif5W<IfcrSpec> {
Chtif5W::new(self, 18)
}
#[doc = "Bit 19 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif5(&mut self) -> Cteif5W<IfcrSpec> {
Cteif5W::new(self, 19)
}
#[doc = "Bit 20 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif6(&mut self) -> Cgif6W<IfcrSpec> {
Cgif6W::new(self, 20)
}
#[doc = "Bit 21 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif6(&mut self) -> Ctcif6W<IfcrSpec> {
Ctcif6W::new(self, 21)
}
#[doc = "Bit 22 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif6(&mut self) -> Chtif6W<IfcrSpec> {
Chtif6W::new(self, 22)
}
#[doc = "Bit 23 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif6(&mut self) -> Cteif6W<IfcrSpec> {
Cteif6W::new(self, 23)
}
#[doc = "Bit 24 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif7(&mut self) -> Cgif7W<IfcrSpec> {
Cgif7W::new(self, 24)
}
#[doc = "Bit 25 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif7(&mut self) -> Ctcif7W<IfcrSpec> {
Ctcif7W::new(self, 25)
}
#[doc = "Bit 26 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif7(&mut self) -> Chtif7W<IfcrSpec> {
Chtif7W::new(self, 26)
}
#[doc = "Bit 27 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif7(&mut self) -> Cteif7W<IfcrSpec> {
Cteif7W::new(self, 27)
}
#[doc = "Bit 28 - CGIF, global interrupt flag clear"]
#[inline(always)]
#[must_use]
pub fn cgif8(&mut self) -> Cgif8W<IfcrSpec> {
Cgif8W::new(self, 28)
}
#[doc = "Bit 29 - CTCIF, transfer complete flag clear"]
#[inline(always)]
#[must_use]
pub fn ctcif8(&mut self) -> Ctcif8W<IfcrSpec> {
Ctcif8W::new(self, 29)
}
#[doc = "Bit 30 - CHTIF, half transfer flag clear"]
#[inline(always)]
#[must_use]
pub fn chtif8(&mut self) -> Chtif8W<IfcrSpec> {
Chtif8W::new(self, 30)
}
#[doc = "Bit 31 - CTEIF, transfer error flag clear"]
#[inline(always)]
#[must_use]
pub fn cteif8(&mut self) -> Cteif8W<IfcrSpec> {
Cteif8W::new(self, 31)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IfcrSpec;
impl crate::RegisterSpec for IfcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ifcr::R`](R) reader structure"]
impl crate::Readable for IfcrSpec {}
#[doc = "`write(|w| ..)` method takes [`ifcr::W`](W) writer structure"]
impl crate::Writable for IfcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IFCR to value 0"]
impl crate::Resettable for IfcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`]
module"]
#[doc(alias = "CCR1")]
pub type Ccr1 = crate::Reg<ccr1::Ccr1Spec>;
#[doc = ""]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub type R = crate::R<Ccr1Spec>;
#[doc = "Register `CCR1` writer"]
pub type W = crate::W<Ccr1Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr1Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr1Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr1Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr1Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr1Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr1Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr1Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr1Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr1Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr1Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr1Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr1Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr1Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr1Spec;
impl crate::RegisterSpec for Ccr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"]
impl crate::Readable for Ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"]
impl crate::Writable for Ccr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for Ccr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr1`]
module"]
#[doc(alias = "CNDTR1")]
pub type Cndtr1 = crate::Reg<cndtr1::Cndtr1Spec>;
#[doc = ""]
pub mod cndtr1 {
#[doc = "Register `CNDTR1` reader"]
pub type R = crate::R<Cndtr1Spec>;
#[doc = "Register `CNDTR1` writer"]
pub type W = crate::W<Cndtr1Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr1Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr1Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr1Spec;
impl crate::RegisterSpec for Cndtr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr1::R`](R) reader structure"]
impl crate::Readable for Cndtr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr1::W`](W) writer structure"]
impl crate::Writable for Cndtr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR1 to value 0"]
impl crate::Resettable for Cndtr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar1`]
module"]
#[doc(alias = "CPAR1")]
pub type Cpar1 = crate::Reg<cpar1::Cpar1Spec>;
#[doc = ""]
pub mod cpar1 {
#[doc = "Register `CPAR1` reader"]
pub type R = crate::R<Cpar1Spec>;
#[doc = "Register `CPAR1` writer"]
pub type W = crate::W<Cpar1Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar1Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar1Spec;
impl crate::RegisterSpec for Cpar1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar1::R`](R) reader structure"]
impl crate::Readable for Cpar1Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar1::W`](W) writer structure"]
impl crate::Writable for Cpar1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR1 to value 0"]
impl crate::Resettable for Cpar1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar1`]
module"]
#[doc(alias = "CM0AR1")]
pub type Cm0ar1 = crate::Reg<cm0ar1::Cm0ar1Spec>;
#[doc = ""]
pub mod cm0ar1 {
#[doc = "Register `CM0AR1` reader"]
pub type R = crate::R<Cm0ar1Spec>;
#[doc = "Register `CM0AR1` writer"]
pub type W = crate::W<Cm0ar1Spec>;
#[doc = "Field `MA` reader - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar1Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar1Spec;
impl crate::RegisterSpec for Cm0ar1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar1::R`](R) reader structure"]
impl crate::Readable for Cm0ar1Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar1::W`](W) writer structure"]
impl crate::Writable for Cm0ar1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR1 to value 0"]
impl crate::Resettable for Cm0ar1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr1`]
module"]
#[doc(alias = "CBSR1")]
pub type Cbsr1 = crate::Reg<cbsr1::Cbsr1Spec>;
#[doc = ""]
pub mod cbsr1 {
#[doc = "Register `CBSR1` reader"]
pub type R = crate::R<Cbsr1Spec>;
#[doc = "Register `CBSR1` writer"]
pub type W = crate::W<Cbsr1Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr1Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr1Spec;
impl crate::RegisterSpec for Cbsr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr1::R`](R) reader structure"]
impl crate::Readable for Cbsr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr1::W`](W) writer structure"]
impl crate::Writable for Cbsr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR1 to value 0"]
impl crate::Resettable for Cbsr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`]
module"]
#[doc(alias = "CCR2")]
pub type Ccr2 = crate::Reg<ccr2::Ccr2Spec>;
#[doc = ""]
pub mod ccr2 {
#[doc = "Register `CCR2` reader"]
pub type R = crate::R<Ccr2Spec>;
#[doc = "Register `CCR2` writer"]
pub type W = crate::W<Ccr2Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr2Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr2Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr2Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr2Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr2Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr2Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr2Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr2Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr2Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr2Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr2Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr2Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr2Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr2Spec;
impl crate::RegisterSpec for Ccr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"]
impl crate::Readable for Ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"]
impl crate::Writable for Ccr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR2 to value 0"]
impl crate::Resettable for Ccr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr2`]
module"]
#[doc(alias = "CNDTR2")]
pub type Cndtr2 = crate::Reg<cndtr2::Cndtr2Spec>;
#[doc = ""]
pub mod cndtr2 {
#[doc = "Register `CNDTR2` reader"]
pub type R = crate::R<Cndtr2Spec>;
#[doc = "Register `CNDTR2` writer"]
pub type W = crate::W<Cndtr2Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr2Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr2Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr2Spec;
impl crate::RegisterSpec for Cndtr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr2::R`](R) reader structure"]
impl crate::Readable for Cndtr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr2::W`](W) writer structure"]
impl crate::Writable for Cndtr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR2 to value 0"]
impl crate::Resettable for Cndtr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar2`]
module"]
#[doc(alias = "CPAR2")]
pub type Cpar2 = crate::Reg<cpar2::Cpar2Spec>;
#[doc = ""]
pub mod cpar2 {
#[doc = "Register `CPAR2` reader"]
pub type R = crate::R<Cpar2Spec>;
#[doc = "Register `CPAR2` writer"]
pub type W = crate::W<Cpar2Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar2Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar2Spec;
impl crate::RegisterSpec for Cpar2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar2::R`](R) reader structure"]
impl crate::Readable for Cpar2Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar2::W`](W) writer structure"]
impl crate::Writable for Cpar2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR2 to value 0"]
impl crate::Resettable for Cpar2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar2`]
module"]
#[doc(alias = "CM0AR2")]
pub type Cm0ar2 = crate::Reg<cm0ar2::Cm0ar2Spec>;
#[doc = ""]
pub mod cm0ar2 {
#[doc = "Register `CM0AR2` reader"]
pub type R = crate::R<Cm0ar2Spec>;
#[doc = "Register `CM0AR2` writer"]
pub type W = crate::W<Cm0ar2Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar2Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar2Spec;
impl crate::RegisterSpec for Cm0ar2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar2::R`](R) reader structure"]
impl crate::Readable for Cm0ar2Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar2::W`](W) writer structure"]
impl crate::Writable for Cm0ar2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR2 to value 0"]
impl crate::Resettable for Cm0ar2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr2`]
module"]
#[doc(alias = "CBSR2")]
pub type Cbsr2 = crate::Reg<cbsr2::Cbsr2Spec>;
#[doc = ""]
pub mod cbsr2 {
#[doc = "Register `CBSR2` reader"]
pub type R = crate::R<Cbsr2Spec>;
#[doc = "Register `CBSR2` writer"]
pub type W = crate::W<Cbsr2Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr2Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr2Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr2Spec;
impl crate::RegisterSpec for Cbsr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr2::R`](R) reader structure"]
impl crate::Readable for Cbsr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr2::W`](W) writer structure"]
impl crate::Writable for Cbsr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR2 to value 0"]
impl crate::Resettable for Cbsr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr3`]
module"]
#[doc(alias = "CCR3")]
pub type Ccr3 = crate::Reg<ccr3::Ccr3Spec>;
#[doc = ""]
pub mod ccr3 {
#[doc = "Register `CCR3` reader"]
pub type R = crate::R<Ccr3Spec>;
#[doc = "Register `CCR3` writer"]
pub type W = crate::W<Ccr3Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr3Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr3Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr3Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr3Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr3Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr3Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr3Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr3Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr3Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr3Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr3Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr3Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr3Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr3Spec;
impl crate::RegisterSpec for Ccr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr3::R`](R) reader structure"]
impl crate::Readable for Ccr3Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr3::W`](W) writer structure"]
impl crate::Writable for Ccr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR3 to value 0"]
impl crate::Resettable for Ccr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr3`]
module"]
#[doc(alias = "CNDTR3")]
pub type Cndtr3 = crate::Reg<cndtr3::Cndtr3Spec>;
#[doc = ""]
pub mod cndtr3 {
#[doc = "Register `CNDTR3` reader"]
pub type R = crate::R<Cndtr3Spec>;
#[doc = "Register `CNDTR3` writer"]
pub type W = crate::W<Cndtr3Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr3Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr3Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr3Spec;
impl crate::RegisterSpec for Cndtr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr3::R`](R) reader structure"]
impl crate::Readable for Cndtr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr3::W`](W) writer structure"]
impl crate::Writable for Cndtr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR3 to value 0"]
impl crate::Resettable for Cndtr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar3`]
module"]
#[doc(alias = "CPAR3")]
pub type Cpar3 = crate::Reg<cpar3::Cpar3Spec>;
#[doc = ""]
pub mod cpar3 {
#[doc = "Register `CPAR3` reader"]
pub type R = crate::R<Cpar3Spec>;
#[doc = "Register `CPAR3` writer"]
pub type W = crate::W<Cpar3Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar3Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar3Spec;
impl crate::RegisterSpec for Cpar3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar3::R`](R) reader structure"]
impl crate::Readable for Cpar3Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar3::W`](W) writer structure"]
impl crate::Writable for Cpar3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR3 to value 0"]
impl crate::Resettable for Cpar3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar3`]
module"]
#[doc(alias = "CM0AR3")]
pub type Cm0ar3 = crate::Reg<cm0ar3::Cm0ar3Spec>;
#[doc = ""]
pub mod cm0ar3 {
#[doc = "Register `CM0AR3` reader"]
pub type R = crate::R<Cm0ar3Spec>;
#[doc = "Register `CM0AR3` writer"]
pub type W = crate::W<Cm0ar3Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar3Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar3Spec;
impl crate::RegisterSpec for Cm0ar3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar3::R`](R) reader structure"]
impl crate::Readable for Cm0ar3Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar3::W`](W) writer structure"]
impl crate::Writable for Cm0ar3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR3 to value 0"]
impl crate::Resettable for Cm0ar3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR3 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr3`]
module"]
#[doc(alias = "CBSR3")]
pub type Cbsr3 = crate::Reg<cbsr3::Cbsr3Spec>;
#[doc = ""]
pub mod cbsr3 {
#[doc = "Register `CBSR3` reader"]
pub type R = crate::R<Cbsr3Spec>;
#[doc = "Register `CBSR3` writer"]
pub type W = crate::W<Cbsr3Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr3Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr3Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr3Spec;
impl crate::RegisterSpec for Cbsr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr3::R`](R) reader structure"]
impl crate::Readable for Cbsr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr3::W`](W) writer structure"]
impl crate::Writable for Cbsr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR3 to value 0"]
impl crate::Resettable for Cbsr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr4`]
module"]
#[doc(alias = "CCR4")]
pub type Ccr4 = crate::Reg<ccr4::Ccr4Spec>;
#[doc = ""]
pub mod ccr4 {
#[doc = "Register `CCR4` reader"]
pub type R = crate::R<Ccr4Spec>;
#[doc = "Register `CCR4` writer"]
pub type W = crate::W<Ccr4Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr4Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr4Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr4Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr4Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr4Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr4Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr4Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr4Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr4Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr4Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr4Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr4Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr4Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr4Spec;
impl crate::RegisterSpec for Ccr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr4::R`](R) reader structure"]
impl crate::Readable for Ccr4Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr4::W`](W) writer structure"]
impl crate::Writable for Ccr4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR4 to value 0"]
impl crate::Resettable for Ccr4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr4`]
module"]
#[doc(alias = "CNDTR4")]
pub type Cndtr4 = crate::Reg<cndtr4::Cndtr4Spec>;
#[doc = ""]
pub mod cndtr4 {
#[doc = "Register `CNDTR4` reader"]
pub type R = crate::R<Cndtr4Spec>;
#[doc = "Register `CNDTR4` writer"]
pub type W = crate::W<Cndtr4Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr4Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr4Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr4Spec;
impl crate::RegisterSpec for Cndtr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr4::R`](R) reader structure"]
impl crate::Readable for Cndtr4Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr4::W`](W) writer structure"]
impl crate::Writable for Cndtr4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR4 to value 0"]
impl crate::Resettable for Cndtr4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar4`]
module"]
#[doc(alias = "CPAR4")]
pub type Cpar4 = crate::Reg<cpar4::Cpar4Spec>;
#[doc = ""]
pub mod cpar4 {
#[doc = "Register `CPAR4` reader"]
pub type R = crate::R<Cpar4Spec>;
#[doc = "Register `CPAR4` writer"]
pub type W = crate::W<Cpar4Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar4Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar4Spec;
impl crate::RegisterSpec for Cpar4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar4::R`](R) reader structure"]
impl crate::Readable for Cpar4Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar4::W`](W) writer structure"]
impl crate::Writable for Cpar4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR4 to value 0"]
impl crate::Resettable for Cpar4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar4`]
module"]
#[doc(alias = "CM0AR4")]
pub type Cm0ar4 = crate::Reg<cm0ar4::Cm0ar4Spec>;
#[doc = ""]
pub mod cm0ar4 {
#[doc = "Register `CM0AR4` reader"]
pub type R = crate::R<Cm0ar4Spec>;
#[doc = "Register `CM0AR4` writer"]
pub type W = crate::W<Cm0ar4Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar4Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar4Spec;
impl crate::RegisterSpec for Cm0ar4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar4::R`](R) reader structure"]
impl crate::Readable for Cm0ar4Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar4::W`](W) writer structure"]
impl crate::Writable for Cm0ar4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR4 to value 0"]
impl crate::Resettable for Cm0ar4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR4 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr4`]
module"]
#[doc(alias = "CBSR4")]
pub type Cbsr4 = crate::Reg<cbsr4::Cbsr4Spec>;
#[doc = ""]
pub mod cbsr4 {
#[doc = "Register `CBSR4` reader"]
pub type R = crate::R<Cbsr4Spec>;
#[doc = "Register `CBSR4` writer"]
pub type W = crate::W<Cbsr4Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr4Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr4Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr4Spec;
impl crate::RegisterSpec for Cbsr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr4::R`](R) reader structure"]
impl crate::Readable for Cbsr4Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr4::W`](W) writer structure"]
impl crate::Writable for Cbsr4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR4 to value 0"]
impl crate::Resettable for Cbsr4Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr5`]
module"]
#[doc(alias = "CCR5")]
pub type Ccr5 = crate::Reg<ccr5::Ccr5Spec>;
#[doc = ""]
pub mod ccr5 {
#[doc = "Register `CCR5` reader"]
pub type R = crate::R<Ccr5Spec>;
#[doc = "Register `CCR5` writer"]
pub type W = crate::W<Ccr5Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr5Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr5Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr5Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr5Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr5Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr5Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr5Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr5Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr5Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr5Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr5Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr5Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr5Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr5Spec;
impl crate::RegisterSpec for Ccr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr5::R`](R) reader structure"]
impl crate::Readable for Ccr5Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr5::W`](W) writer structure"]
impl crate::Writable for Ccr5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR5 to value 0"]
impl crate::Resettable for Ccr5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr5`]
module"]
#[doc(alias = "CNDTR5")]
pub type Cndtr5 = crate::Reg<cndtr5::Cndtr5Spec>;
#[doc = ""]
pub mod cndtr5 {
#[doc = "Register `CNDTR5` reader"]
pub type R = crate::R<Cndtr5Spec>;
#[doc = "Register `CNDTR5` writer"]
pub type W = crate::W<Cndtr5Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr5Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr5Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr5Spec;
impl crate::RegisterSpec for Cndtr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr5::R`](R) reader structure"]
impl crate::Readable for Cndtr5Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr5::W`](W) writer structure"]
impl crate::Writable for Cndtr5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR5 to value 0"]
impl crate::Resettable for Cndtr5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar5`]
module"]
#[doc(alias = "CPAR5")]
pub type Cpar5 = crate::Reg<cpar5::Cpar5Spec>;
#[doc = ""]
pub mod cpar5 {
#[doc = "Register `CPAR5` reader"]
pub type R = crate::R<Cpar5Spec>;
#[doc = "Register `CPAR5` writer"]
pub type W = crate::W<Cpar5Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar5Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar5Spec;
impl crate::RegisterSpec for Cpar5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar5::R`](R) reader structure"]
impl crate::Readable for Cpar5Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar5::W`](W) writer structure"]
impl crate::Writable for Cpar5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR5 to value 0"]
impl crate::Resettable for Cpar5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar5`]
module"]
#[doc(alias = "CM0AR5")]
pub type Cm0ar5 = crate::Reg<cm0ar5::Cm0ar5Spec>;
#[doc = ""]
pub mod cm0ar5 {
#[doc = "Register `CM0AR5` reader"]
pub type R = crate::R<Cm0ar5Spec>;
#[doc = "Register `CM0AR5` writer"]
pub type W = crate::W<Cm0ar5Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar5Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar5Spec;
impl crate::RegisterSpec for Cm0ar5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar5::R`](R) reader structure"]
impl crate::Readable for Cm0ar5Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar5::W`](W) writer structure"]
impl crate::Writable for Cm0ar5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR5 to value 0"]
impl crate::Resettable for Cm0ar5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR5 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr5`]
module"]
#[doc(alias = "CBSR5")]
pub type Cbsr5 = crate::Reg<cbsr5::Cbsr5Spec>;
#[doc = ""]
pub mod cbsr5 {
#[doc = "Register `CBSR5` reader"]
pub type R = crate::R<Cbsr5Spec>;
#[doc = "Register `CBSR5` writer"]
pub type W = crate::W<Cbsr5Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr5Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr5Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr5Spec;
impl crate::RegisterSpec for Cbsr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr5::R`](R) reader structure"]
impl crate::Readable for Cbsr5Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr5::W`](W) writer structure"]
impl crate::Writable for Cbsr5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR5 to value 0"]
impl crate::Resettable for Cbsr5Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr6`]
module"]
#[doc(alias = "CCR6")]
pub type Ccr6 = crate::Reg<ccr6::Ccr6Spec>;
#[doc = ""]
pub mod ccr6 {
#[doc = "Register `CCR6` reader"]
pub type R = crate::R<Ccr6Spec>;
#[doc = "Register `CCR6` writer"]
pub type W = crate::W<Ccr6Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr6Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr6Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr6Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr6Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr6Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr6Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr6Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr6Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr6Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr6Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr6Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr6Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr6Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr6Spec;
impl crate::RegisterSpec for Ccr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr6::R`](R) reader structure"]
impl crate::Readable for Ccr6Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr6::W`](W) writer structure"]
impl crate::Writable for Ccr6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR6 to value 0"]
impl crate::Resettable for Ccr6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr6`]
module"]
#[doc(alias = "CNDTR6")]
pub type Cndtr6 = crate::Reg<cndtr6::Cndtr6Spec>;
#[doc = ""]
pub mod cndtr6 {
#[doc = "Register `CNDTR6` reader"]
pub type R = crate::R<Cndtr6Spec>;
#[doc = "Register `CNDTR6` writer"]
pub type W = crate::W<Cndtr6Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr6Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr6Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr6Spec;
impl crate::RegisterSpec for Cndtr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr6::R`](R) reader structure"]
impl crate::Readable for Cndtr6Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr6::W`](W) writer structure"]
impl crate::Writable for Cndtr6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR6 to value 0"]
impl crate::Resettable for Cndtr6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar6`]
module"]
#[doc(alias = "CPAR6")]
pub type Cpar6 = crate::Reg<cpar6::Cpar6Spec>;
#[doc = ""]
pub mod cpar6 {
#[doc = "Register `CPAR6` reader"]
pub type R = crate::R<Cpar6Spec>;
#[doc = "Register `CPAR6` writer"]
pub type W = crate::W<Cpar6Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar6Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar6Spec;
impl crate::RegisterSpec for Cpar6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar6::R`](R) reader structure"]
impl crate::Readable for Cpar6Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar6::W`](W) writer structure"]
impl crate::Writable for Cpar6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR6 to value 0"]
impl crate::Resettable for Cpar6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar6`]
module"]
#[doc(alias = "CM0AR6")]
pub type Cm0ar6 = crate::Reg<cm0ar6::Cm0ar6Spec>;
#[doc = ""]
pub mod cm0ar6 {
#[doc = "Register `CM0AR6` reader"]
pub type R = crate::R<Cm0ar6Spec>;
#[doc = "Register `CM0AR6` writer"]
pub type W = crate::W<Cm0ar6Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar6Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar6Spec;
impl crate::RegisterSpec for Cm0ar6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar6::R`](R) reader structure"]
impl crate::Readable for Cm0ar6Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar6::W`](W) writer structure"]
impl crate::Writable for Cm0ar6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR6 to value 0"]
impl crate::Resettable for Cm0ar6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR6 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr6`]
module"]
#[doc(alias = "CBSR6")]
pub type Cbsr6 = crate::Reg<cbsr6::Cbsr6Spec>;
#[doc = ""]
pub mod cbsr6 {
#[doc = "Register `CBSR6` reader"]
pub type R = crate::R<Cbsr6Spec>;
#[doc = "Register `CBSR6` writer"]
pub type W = crate::W<Cbsr6Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr6Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr6Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr6Spec;
impl crate::RegisterSpec for Cbsr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr6::R`](R) reader structure"]
impl crate::Readable for Cbsr6Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr6::W`](W) writer structure"]
impl crate::Writable for Cbsr6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR6 to value 0"]
impl crate::Resettable for Cbsr6Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr7`]
module"]
#[doc(alias = "CCR7")]
pub type Ccr7 = crate::Reg<ccr7::Ccr7Spec>;
#[doc = ""]
pub mod ccr7 {
#[doc = "Register `CCR7` reader"]
pub type R = crate::R<Ccr7Spec>;
#[doc = "Register `CCR7` writer"]
pub type W = crate::W<Ccr7Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr7Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr7Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr7Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr7Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr7Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr7Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr7Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr7Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr7Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr7Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr7Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr7Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr7Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr7Spec;
impl crate::RegisterSpec for Ccr7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr7::R`](R) reader structure"]
impl crate::Readable for Ccr7Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr7::W`](W) writer structure"]
impl crate::Writable for Ccr7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR7 to value 0"]
impl crate::Resettable for Ccr7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr7`]
module"]
#[doc(alias = "CNDTR7")]
pub type Cndtr7 = crate::Reg<cndtr7::Cndtr7Spec>;
#[doc = ""]
pub mod cndtr7 {
#[doc = "Register `CNDTR7` reader"]
pub type R = crate::R<Cndtr7Spec>;
#[doc = "Register `CNDTR7` writer"]
pub type W = crate::W<Cndtr7Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr7Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr7Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr7Spec;
impl crate::RegisterSpec for Cndtr7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr7::R`](R) reader structure"]
impl crate::Readable for Cndtr7Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr7::W`](W) writer structure"]
impl crate::Writable for Cndtr7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR7 to value 0"]
impl crate::Resettable for Cndtr7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar7`]
module"]
#[doc(alias = "CPAR7")]
pub type Cpar7 = crate::Reg<cpar7::Cpar7Spec>;
#[doc = ""]
pub mod cpar7 {
#[doc = "Register `CPAR7` reader"]
pub type R = crate::R<Cpar7Spec>;
#[doc = "Register `CPAR7` writer"]
pub type W = crate::W<Cpar7Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar7Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar7Spec;
impl crate::RegisterSpec for Cpar7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar7::R`](R) reader structure"]
impl crate::Readable for Cpar7Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar7::W`](W) writer structure"]
impl crate::Writable for Cpar7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR7 to value 0"]
impl crate::Resettable for Cpar7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar7`]
module"]
#[doc(alias = "CM0AR7")]
pub type Cm0ar7 = crate::Reg<cm0ar7::Cm0ar7Spec>;
#[doc = ""]
pub mod cm0ar7 {
#[doc = "Register `CM0AR7` reader"]
pub type R = crate::R<Cm0ar7Spec>;
#[doc = "Register `CM0AR7` writer"]
pub type W = crate::W<Cm0ar7Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar7Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar7Spec;
impl crate::RegisterSpec for Cm0ar7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar7::R`](R) reader structure"]
impl crate::Readable for Cm0ar7Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar7::W`](W) writer structure"]
impl crate::Writable for Cm0ar7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR7 to value 0"]
impl crate::Resettable for Cm0ar7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR7 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr7`]
module"]
#[doc(alias = "CBSR7")]
pub type Cbsr7 = crate::Reg<cbsr7::Cbsr7Spec>;
#[doc = ""]
pub mod cbsr7 {
#[doc = "Register `CBSR7` reader"]
pub type R = crate::R<Cbsr7Spec>;
#[doc = "Register `CBSR7` writer"]
pub type W = crate::W<Cbsr7Spec>;
#[doc = "Field `BS` reader - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr7Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr7Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr7Spec;
impl crate::RegisterSpec for Cbsr7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr7::R`](R) reader structure"]
impl crate::Readable for Cbsr7Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr7::W`](W) writer structure"]
impl crate::Writable for Cbsr7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR7 to value 0"]
impl crate::Resettable for Cbsr7Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CCR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr8`]
module"]
#[doc(alias = "CCR8")]
pub type Ccr8 = crate::Reg<ccr8::Ccr8Spec>;
#[doc = ""]
pub mod ccr8 {
#[doc = "Register `CCR8` reader"]
pub type R = crate::R<Ccr8Spec>;
#[doc = "Register `CCR8` writer"]
pub type W = crate::W<Ccr8Spec>;
#[doc = "Field `EN` reader - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - transfer complete interrupt enable 0: disabled 1: enabled"]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HTIE` reader - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieR = crate::BitReader;
#[doc = "Field `HTIE` writer - half transfer interrupt enable 0: disabled 1: enabled"]
pub type HtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TEIE` reader - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieR = crate::BitReader;
#[doc = "Field `TEIE` writer - transfer error interrupt enable 0: disabled 1: enabled"]
pub type TeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DIR` reader - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirR = crate::BitReader;
#[doc = "Field `DIR` writer - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CIRC` reader - circular mode 0: disabled 1: enabled"]
pub type CircR = crate::BitReader;
#[doc = "Field `CIRC` writer - circular mode 0: disabled 1: enabled"]
pub type CircW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PINC` reader - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincR = crate::BitReader;
#[doc = "Field `PINC` writer - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
pub type PincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINC` reader - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincR = crate::BitReader;
#[doc = "Field `MINC` writer - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
pub type MincW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSIZE` reader - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeR = crate::FieldReader;
#[doc = "Field `PSIZE` writer - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type PsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MSIZE` reader - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeR = crate::FieldReader;
#[doc = "Field `MSIZE` writer - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
pub type MsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PL` reader - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlR = crate::FieldReader;
#[doc = "Field `PL` writer - priority level 00: low 01: medium 10: high 11: very high"]
pub type PlW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `MEM2MEM` reader - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memR = crate::BitReader;
#[doc = "Field `MEM2MEM` writer - memory-to-memory mode 0: disabled 1: enabled"]
pub type Mem2memW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn htie(&self) -> HtieR {
HtieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
pub fn teie(&self) -> TeieR {
TeieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn circ(&self) -> CircR {
CircR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn pinc(&self) -> PincR {
PincR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
pub fn minc(&self) -> MincR {
MincR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn psize(&self) -> PsizeR {
PsizeR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
pub fn msize(&self) -> MsizeR {
MsizeR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
pub fn pl(&self) -> PlR {
PlR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
pub fn mem2mem(&self) -> Mem2memR {
Mem2memR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 15) & 0x0001_ffff)
}
}
impl W {
#[doc = "Bit 0 - channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EnW<Ccr8Spec> {
EnW::new(self, 0)
}
#[doc = "Bit 1 - transfer complete interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Ccr8Spec> {
TcieW::new(self, 1)
}
#[doc = "Bit 2 - half transfer interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HtieW<Ccr8Spec> {
HtieW::new(self, 2)
}
#[doc = "Bit 3 - transfer error interrupt enable 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TeieW<Ccr8Spec> {
TeieW::new(self, 3)
}
#[doc = "Bit 4 - data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode."]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DirW<Ccr8Spec> {
DirW::new(self, 4)
}
#[doc = "Bit 5 - circular mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CircW<Ccr8Spec> {
CircW::new(self, 5)
}
#[doc = "Bit 6 - peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PincW<Ccr8Spec> {
PincW::new(self, 6)
}
#[doc = "Bit 7 - memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MincW<Ccr8Spec> {
MincW::new(self, 7)
}
#[doc = "Bits 8:9 - peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PsizeW<Ccr8Spec> {
PsizeW::new(self, 8)
}
#[doc = "Bits 10:11 - memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MsizeW<Ccr8Spec> {
MsizeW::new(self, 10)
}
#[doc = "Bits 12:13 - priority level 00: low 01: medium 10: high 11: very high"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PlW<Ccr8Spec> {
PlW::new(self, 12)
}
#[doc = "Bit 14 - memory-to-memory mode 0: disabled 1: enabled"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> Mem2memW<Ccr8Spec> {
Mem2memW::new(self, 14)
}
#[doc = "Bits 15:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Ccr8Spec> {
RsvdW::new(self, 15)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr8Spec;
impl crate::RegisterSpec for Ccr8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr8::R`](R) reader structure"]
impl crate::Readable for Ccr8Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr8::W`](W) writer structure"]
impl crate::Writable for Ccr8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR8 to value 0"]
impl crate::Resettable for Ccr8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNDTR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cndtr8`]
module"]
#[doc(alias = "CNDTR8")]
pub type Cndtr8 = crate::Reg<cndtr8::Cndtr8Spec>;
#[doc = ""]
pub mod cndtr8 {
#[doc = "Register `CNDTR8` reader"]
pub type R = crate::R<Cndtr8Spec>;
#[doc = "Register `CNDTR8` writer"]
pub type W = crate::W<Cndtr8Spec>;
#[doc = "Field `NDT` reader - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtR = crate::FieldReader<u16>;
#[doc = "Field `NDT` writer - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
pub type NdtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
pub fn ndt(&self) -> NdtR {
NdtR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not)."]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NdtW<Cndtr8Spec> {
NdtW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cndtr8Spec> {
RsvdW::new(self, 16)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndtr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndtr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cndtr8Spec;
impl crate::RegisterSpec for Cndtr8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cndtr8::R`](R) reader structure"]
impl crate::Readable for Cndtr8Spec {}
#[doc = "`write(|w| ..)` method takes [`cndtr8::W`](W) writer structure"]
impl crate::Writable for Cndtr8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNDTR8 to value 0"]
impl crate::Resettable for Cndtr8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CPAR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpar8`]
module"]
#[doc(alias = "CPAR8")]
pub type Cpar8 = crate::Reg<cpar8::Cpar8Spec>;
#[doc = ""]
pub mod cpar8 {
#[doc = "Register `CPAR8` reader"]
pub type R = crate::R<Cpar8Spec>;
#[doc = "Register `CPAR8` writer"]
pub type W = crate::W<Cpar8Spec>;
#[doc = "Field `PA` reader - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaR = crate::FieldReader<u32>;
#[doc = "Field `PA` writer - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
pub fn pa(&self) -> PaR {
PaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PaW<Cpar8Spec> {
PaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpar8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpar8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cpar8Spec;
impl crate::RegisterSpec for Cpar8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cpar8::R`](R) reader structure"]
impl crate::Readable for Cpar8Spec {}
#[doc = "`write(|w| ..)` method takes [`cpar8::W`](W) writer structure"]
impl crate::Writable for Cpar8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CPAR8 to value 0"]
impl crate::Resettable for Cpar8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CM0AR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm0ar8`]
module"]
#[doc(alias = "CM0AR8")]
pub type Cm0ar8 = crate::Reg<cm0ar8::Cm0ar8Spec>;
#[doc = ""]
pub mod cm0ar8 {
#[doc = "Register `CM0AR8` reader"]
pub type R = crate::R<Cm0ar8Spec>;
#[doc = "Register `CM0AR8` writer"]
pub type W = crate::W<Cm0ar8Spec>;
#[doc = "Field `MA` reader - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaR = crate::FieldReader<u32>;
#[doc = "Field `MA` writer - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
pub type MaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
pub fn ma(&self) -> MaR {
MaR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0."]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MaW<Cm0ar8Spec> {
MaW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cm0ar8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cm0ar8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cm0ar8Spec;
impl crate::RegisterSpec for Cm0ar8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cm0ar8::R`](R) reader structure"]
impl crate::Readable for Cm0ar8Spec {}
#[doc = "`write(|w| ..)` method takes [`cm0ar8::W`](W) writer structure"]
impl crate::Writable for Cm0ar8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CM0AR8 to value 0"]
impl crate::Resettable for Cm0ar8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CBSR8 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cbsr8`]
module"]
#[doc(alias = "CBSR8")]
pub type Cbsr8 = crate::Reg<cbsr8::Cbsr8Spec>;
#[doc = ""]
pub mod cbsr8 {
#[doc = "Register `CBSR8` reader"]
pub type R = crate::R<Cbsr8Spec>;
#[doc = "Register `CBSR8` writer"]
pub type W = crate::W<Cbsr8Spec>;
#[doc = "Field `BS` reader - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsR = crate::FieldReader;
#[doc = "Field `BS` writer - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
pub type BsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored."]
#[inline(always)]
#[must_use]
pub fn bs(&mut self) -> BsW<Cbsr8Spec> {
BsW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cbsr8Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbsr8Spec;
impl crate::RegisterSpec for Cbsr8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cbsr8::R`](R) reader structure"]
impl crate::Readable for Cbsr8Spec {}
#[doc = "`write(|w| ..)` method takes [`cbsr8::W`](W) writer structure"]
impl crate::Writable for Cbsr8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CBSR8 to value 0"]
impl crate::Resettable for Cbsr8Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CSELR1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cselr1`]
module"]
#[doc(alias = "CSELR1")]
pub type Cselr1 = crate::Reg<cselr1::Cselr1Spec>;
#[doc = ""]
pub mod cselr1 {
#[doc = "Register `CSELR1` reader"]
pub type R = crate::R<Cselr1Spec>;
#[doc = "Register `CSELR1` writer"]
pub type W = crate::W<Cselr1Spec>;
#[doc = "Field `C1S` reader - DMA channel 1 selection"]
pub type C1sR = crate::FieldReader;
#[doc = "Field `C1S` writer - DMA channel 1 selection"]
pub type C1sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C2S` reader - DMA channel 2 selection"]
pub type C2sR = crate::FieldReader;
#[doc = "Field `C2S` writer - DMA channel 2 selection"]
pub type C2sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C3S` reader - DMA channel 3 selection"]
pub type C3sR = crate::FieldReader;
#[doc = "Field `C3S` writer - DMA channel 3 selection"]
pub type C3sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C4S` reader - DMA channel 4 selection"]
pub type C4sR = crate::FieldReader;
#[doc = "Field `C4S` writer - DMA channel 4 selection"]
pub type C4sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5 - DMA channel 1 selection"]
#[inline(always)]
pub fn c1s(&self) -> C1sR {
C1sR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13 - DMA channel 2 selection"]
#[inline(always)]
pub fn c2s(&self) -> C2sR {
C2sR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21 - DMA channel 3 selection"]
#[inline(always)]
pub fn c3s(&self) -> C3sR {
C3sR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29 - DMA channel 4 selection"]
#[inline(always)]
pub fn c4s(&self) -> C4sR {
C4sR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - DMA channel 1 selection"]
#[inline(always)]
#[must_use]
pub fn c1s(&mut self) -> C1sW<Cselr1Spec> {
C1sW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cselr1Spec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13 - DMA channel 2 selection"]
#[inline(always)]
#[must_use]
pub fn c2s(&mut self) -> C2sW<Cselr1Spec> {
C2sW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cselr1Spec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21 - DMA channel 3 selection"]
#[inline(always)]
#[must_use]
pub fn c3s(&mut self) -> C3sW<Cselr1Spec> {
C3sW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cselr1Spec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29 - DMA channel 4 selection"]
#[inline(always)]
#[must_use]
pub fn c4s(&mut self) -> C4sW<Cselr1Spec> {
C4sW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cselr1Spec> {
RsvdW::new(self, 30)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cselr1Spec;
impl crate::RegisterSpec for Cselr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cselr1::R`](R) reader structure"]
impl crate::Readable for Cselr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cselr1::W`](W) writer structure"]
impl crate::Writable for Cselr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CSELR1 to value 0"]
impl crate::Resettable for Cselr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CSELR2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cselr2`]
module"]
#[doc(alias = "CSELR2")]
pub type Cselr2 = crate::Reg<cselr2::Cselr2Spec>;
#[doc = ""]
pub mod cselr2 {
#[doc = "Register `CSELR2` reader"]
pub type R = crate::R<Cselr2Spec>;
#[doc = "Register `CSELR2` writer"]
pub type W = crate::W<Cselr2Spec>;
#[doc = "Field `C5S` reader - DMA channel 5 selection"]
pub type C5sR = crate::FieldReader;
#[doc = "Field `C5S` writer - DMA channel 5 selection"]
pub type C5sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::FieldReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C6S` reader - DMA channel 6 selection"]
pub type C6sR = crate::FieldReader;
#[doc = "Field `C6S` writer - DMA channel 6 selection"]
pub type C6sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C7S` reader - DMA channel 7 selection"]
pub type C7sR = crate::FieldReader;
#[doc = "Field `C7S` writer - DMA channel 7 selection"]
pub type C7sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `C8S` reader - DMA channel 8 selection"]
pub type C8sR = crate::FieldReader;
#[doc = "Field `C8S` writer - DMA channel 8 selection"]
pub type C8sW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5 - DMA channel 5 selection"]
#[inline(always)]
pub fn c5s(&self) -> C5sR {
C5sR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:13 - DMA channel 6 selection"]
#[inline(always)]
pub fn c6s(&self) -> C6sR {
C6sR::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:21 - DMA channel 7 selection"]
#[inline(always)]
pub fn c7s(&self) -> C7sR {
C7sR::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:29 - DMA channel 8 selection"]
#[inline(always)]
pub fn c8s(&self) -> C8sR {
C8sR::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - DMA channel 5 selection"]
#[inline(always)]
#[must_use]
pub fn c5s(&mut self) -> C5sW<Cselr2Spec> {
C5sW::new(self, 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cselr2Spec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bits 8:13 - DMA channel 6 selection"]
#[inline(always)]
#[must_use]
pub fn c6s(&mut self) -> C6sW<Cselr2Spec> {
C6sW::new(self, 8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cselr2Spec> {
Rsvd3W::new(self, 14)
}
#[doc = "Bits 16:21 - DMA channel 7 selection"]
#[inline(always)]
#[must_use]
pub fn c7s(&mut self) -> C7sW<Cselr2Spec> {
C7sW::new(self, 16)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cselr2Spec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bits 24:29 - DMA channel 8 selection"]
#[inline(always)]
#[must_use]
pub fn c8s(&mut self) -> C8sW<Cselr2Spec> {
C8sW::new(self, 24)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cselr2Spec> {
RsvdW::new(self, 30)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cselr2Spec;
impl crate::RegisterSpec for Cselr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cselr2::R`](R) reader structure"]
impl crate::Readable for Cselr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cselr2::W`](W) writer structure"]
impl crate::Writable for Cselr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CSELR2 to value 0"]
impl crate::Resettable for Cselr2Spec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "USART4"]
pub struct Usart4 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Usart4 {}
impl Usart4 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const usart4::RegisterBlock = 0x4000_5000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const usart4::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Usart4 {
type Target = usart4::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Usart4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart4").finish()
}
}
#[doc = "USART4"]
pub mod usart4 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
cr3: Cr3,
brr: Brr,
gtpr: Gtpr,
rtor: Rtor,
rqr: Rqr,
isr: Isr,
icr: Icr,
rdr: Rdr,
tdr: Tdr,
miscr: Miscr,
drdr: Drdr,
dtdr: Dtdr,
exr: Exr,
}
impl RegisterBlock {
#[doc = "0x00 - Control Register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - Control Register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - Control Register 3"]
#[inline(always)]
pub const fn cr3(&self) -> &Cr3 {
&self.cr3
}
#[doc = "0x0c - Baud Rate Register"]
#[inline(always)]
pub const fn brr(&self) -> &Brr {
&self.brr
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn gtpr(&self) -> &Gtpr {
&self.gtpr
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn rtor(&self) -> &Rtor {
&self.rtor
}
#[doc = "0x18 - Request Register"]
#[inline(always)]
pub const fn rqr(&self) -> &Rqr {
&self.rqr
}
#[doc = "0x1c - Interrupt and Status Register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x20 - Interrupt flag Clear Register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x24 - Receive Data Register"]
#[inline(always)]
pub const fn rdr(&self) -> &Rdr {
&self.rdr
}
#[doc = "0x28 - Transmit Data Register"]
#[inline(always)]
pub const fn tdr(&self) -> &Tdr {
&self.tdr
}
#[doc = "0x2c - Miscellaneous Register"]
#[inline(always)]
pub const fn miscr(&self) -> &Miscr {
&self.miscr
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn drdr(&self) -> &Drdr {
&self.drdr
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn dtdr(&self) -> &Dtdr {
&self.dtdr
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn exr(&self) -> &Exr {
&self.exr
}
}
#[doc = "CR1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `UE` reader - "]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - "]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RE` reader - "]
pub type ReR = crate::BitReader;
#[doc = "Field `RE` writer - "]
pub type ReW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - "]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - "]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLEIE` reader - "]
pub type IdleieR = crate::BitReader;
#[doc = "Field `IDLEIE` writer - "]
pub type IdleieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNEIE` reader - "]
pub type RxneieR = crate::BitReader;
#[doc = "Field `RXNEIE` writer - "]
pub type RxneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - "]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - "]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXEIE` reader - "]
pub type TxeieR = crate::BitReader;
#[doc = "Field `TXEIE` writer - "]
pub type TxeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PEIE` reader - "]
pub type PeieR = crate::BitReader;
#[doc = "Field `PEIE` writer - "]
pub type PeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCE` reader - "]
pub type PceR = crate::BitReader;
#[doc = "Field `PCE` writer - "]
pub type PceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `OVER8` reader - "]
pub type Over8R = crate::BitReader;
#[doc = "Field `OVER8` writer - "]
pub type Over8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `M` reader - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MR = crate::FieldReader;
#[doc = "Field `M` writer - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn re(&self) -> ReR {
ReR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idleie(&self) -> IdleieR {
IdleieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxneie(&self) -> RxneieR {
RxneieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txeie(&self) -> TxeieR {
TxeieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn peie(&self) -> PeieR {
PeieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn pce(&self) -> PceR {
PceR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:13"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn over8(&self) -> Over8R {
Over8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:26"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 0x0fff) as u16)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
pub fn m(&self) -> MR {
MR::new(((self.bits >> 27) & 3) as u8)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<Cr1Spec> {
UeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cr1Spec> {
Rsvd4W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn re(&mut self) -> ReW<Cr1Spec> {
ReW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<Cr1Spec> {
TeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idleie(&mut self) -> IdleieW<Cr1Spec> {
IdleieW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxneie(&mut self) -> RxneieW<Cr1Spec> {
RxneieW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Cr1Spec> {
TcieW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txeie(&mut self) -> TxeieW<Cr1Spec> {
TxeieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn peie(&mut self) -> PeieW<Cr1Spec> {
PeieW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Cr1Spec> {
PsW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn pce(&mut self) -> PceW<Cr1Spec> {
PceW::new(self, 10)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cr1Spec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn over8(&mut self) -> Over8W<Cr1Spec> {
Over8W::new(self, 14)
}
#[doc = "Bits 15:26"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
#[must_use]
pub fn m(&mut self) -> MW<Cr1Spec> {
MW::new(self, 27)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 29)
}
}
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `STOP` reader - "]
pub type StopR = crate::FieldReader;
#[doc = "Field `STOP` writer - "]
pub type StopW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<Cr2Spec> {
StopW::new(self, 12)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 14)
}
}
#[doc = "Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR3 (rw) register accessor: Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr3`]
module"]
#[doc(alias = "CR3")]
pub type Cr3 = crate::Reg<cr3::Cr3Spec>;
#[doc = "Control Register 3"]
pub mod cr3 {
#[doc = "Register `CR3` reader"]
pub type R = crate::R<Cr3Spec>;
#[doc = "Register `CR3` writer"]
pub type W = crate::W<Cr3Spec>;
#[doc = "Field `EIE` reader - "]
pub type EieR = crate::BitReader;
#[doc = "Field `EIE` writer - "]
pub type EieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMAR` reader - "]
pub type DmarR = crate::BitReader;
#[doc = "Field `DMAR` writer - "]
pub type DmarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAT` reader - "]
pub type DmatR = crate::BitReader;
#[doc = "Field `DMAT` writer - "]
pub type DmatW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTSE` reader - "]
pub type RtseR = crate::BitReader;
#[doc = "Field `RTSE` writer - "]
pub type RtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSE` reader - "]
pub type CtseR = crate::BitReader;
#[doc = "Field `CTSE` writer - "]
pub type CtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIE` reader - "]
pub type CtsieR = crate::BitReader;
#[doc = "Field `CTSIE` writer - "]
pub type CtsieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ONEBIT` reader - "]
pub type OnebitR = crate::BitReader;
#[doc = "Field `ONEBIT` writer - "]
pub type OnebitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVRDIS` reader - "]
pub type OvrdisR = crate::BitReader;
#[doc = "Field `OVRDIS` writer - "]
pub type OvrdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn eie(&self) -> EieR {
EieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x1f) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn dmar(&self) -> DmarR {
DmarR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dmat(&self) -> DmatR {
DmatR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rtse(&self) -> RtseR {
RtseR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctse(&self) -> CtseR {
CtseR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ctsie(&self) -> CtsieR {
CtsieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn onebit(&self) -> OnebitR {
OnebitR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn ovrdis(&self) -> OvrdisR {
OvrdisR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn eie(&mut self) -> EieW<Cr3Spec> {
EieW::new(self, 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr3Spec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn dmar(&mut self) -> DmarW<Cr3Spec> {
DmarW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dmat(&mut self) -> DmatW<Cr3Spec> {
DmatW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rtse(&mut self) -> RtseW<Cr3Spec> {
RtseW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctse(&mut self) -> CtseW<Cr3Spec> {
CtseW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ctsie(&mut self) -> CtsieW<Cr3Spec> {
CtsieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn onebit(&mut self) -> OnebitW<Cr3Spec> {
OnebitW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn ovrdis(&mut self) -> OvrdisW<Cr3Spec> {
OvrdisW::new(self, 12)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr3Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr3Spec;
impl crate::RegisterSpec for Cr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr3::R`](R) reader structure"]
impl crate::Readable for Cr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cr3::W`](W) writer structure"]
impl crate::Writable for Cr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR3 to value 0"]
impl crate::Resettable for Cr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BRR (rw) register accessor: Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@brr`]
module"]
#[doc(alias = "BRR")]
pub type Brr = crate::Reg<brr::BrrSpec>;
#[doc = "Baud Rate Register"]
pub mod brr {
#[doc = "Register `BRR` reader"]
pub type R = crate::R<BrrSpec>;
#[doc = "Register `BRR` writer"]
pub type W = crate::W<BrrSpec>;
#[doc = "Field `FRAC` reader - "]
pub type FracR = crate::FieldReader;
#[doc = "Field `FRAC` writer - "]
pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `INT` reader - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntR = crate::FieldReader<u16>;
#[doc = "Field `INT` writer - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn frac(&self) -> FracR {
FracR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
pub fn int(&self) -> IntR {
IntR::new(((self.bits >> 4) & 0x0fff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn frac(&mut self) -> FracW<BrrSpec> {
FracW::new(self, 0)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
#[must_use]
pub fn int(&mut self) -> IntW<BrrSpec> {
IntW::new(self, 4)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BrrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BrrSpec;
impl crate::RegisterSpec for BrrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`brr::R`](R) reader structure"]
impl crate::Readable for BrrSpec {}
#[doc = "`write(|w| ..)` method takes [`brr::W`](W) writer structure"]
impl crate::Writable for BrrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BRR to value 0"]
impl crate::Resettable for BrrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GTPR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gtpr`]
module"]
#[doc(alias = "GTPR")]
pub type Gtpr = crate::Reg<gtpr::GtprSpec>;
#[doc = ""]
pub mod gtpr {
#[doc = "Register `GTPR` reader"]
pub type R = crate::R<GtprSpec>;
#[doc = "Register `GTPR` writer"]
pub type W = crate::W<GtprSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<GtprSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GtprSpec;
impl crate::RegisterSpec for GtprSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gtpr::R`](R) reader structure"]
impl crate::Readable for GtprSpec {}
#[doc = "`write(|w| ..)` method takes [`gtpr::W`](W) writer structure"]
impl crate::Writable for GtprSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GTPR to value 0"]
impl crate::Resettable for GtprSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RTOR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtor`]
module"]
#[doc(alias = "RTOR")]
pub type Rtor = crate::Reg<rtor::RtorSpec>;
#[doc = ""]
pub mod rtor {
#[doc = "Register `RTOR` reader"]
pub type R = crate::R<RtorSpec>;
#[doc = "Register `RTOR` writer"]
pub type W = crate::W<RtorSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RtorSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtorSpec;
impl crate::RegisterSpec for RtorSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtor::R`](R) reader structure"]
impl crate::Readable for RtorSpec {}
#[doc = "`write(|w| ..)` method takes [`rtor::W`](W) writer structure"]
impl crate::Writable for RtorSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTOR to value 0"]
impl crate::Resettable for RtorSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RQR (rw) register accessor: Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rqr`]
module"]
#[doc(alias = "RQR")]
pub type Rqr = crate::Reg<rqr::RqrSpec>;
#[doc = "Request Register"]
pub mod rqr {
#[doc = "Register `RQR` reader"]
pub type R = crate::R<RqrSpec>;
#[doc = "Register `RQR` writer"]
pub type W = crate::W<RqrSpec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RXFRQ` reader - "]
pub type RxfrqR = crate::BitReader;
#[doc = "Field `RXFRQ` writer - "]
pub type RxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXFRQ` reader - "]
pub type TxfrqR = crate::BitReader;
#[doc = "Field `TXFRQ` writer - "]
pub type TxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxfrq(&self) -> RxfrqR {
RxfrqR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn txfrq(&self) -> TxfrqR {
TxfrqR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<RqrSpec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxfrq(&mut self) -> RxfrqW<RqrSpec> {
RxfrqW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn txfrq(&mut self) -> TxfrqW<RqrSpec> {
TxfrqW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RqrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RqrSpec;
impl crate::RegisterSpec for RqrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rqr::R`](R) reader structure"]
impl crate::Readable for RqrSpec {}
#[doc = "`write(|w| ..)` method takes [`rqr::W`](W) writer structure"]
impl crate::Writable for RqrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RQR to value 0"]
impl crate::Resettable for RqrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR (rw) register accessor: Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "Interrupt and Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - "]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - "]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NF` reader - "]
pub type NfR = crate::BitReader;
#[doc = "Field `NF` writer - "]
pub type NfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORE` reader - "]
pub type OreR = crate::BitReader;
#[doc = "Field `ORE` writer - "]
pub type OreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLE` reader - "]
pub type IdleR = crate::BitReader;
#[doc = "Field `IDLE` writer - "]
pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNE` reader - "]
pub type RxneR = crate::BitReader;
#[doc = "Field `RXNE` writer - "]
pub type RxneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TC` reader - "]
pub type TcR = crate::BitReader;
#[doc = "Field `TC` writer - "]
pub type TcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - "]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - "]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIF` reader - "]
pub type CtsifR = crate::BitReader;
#[doc = "Field `CTSIF` writer - "]
pub type CtsifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTS` reader - "]
pub type CtsR = crate::BitReader;
#[doc = "Field `CTS` writer - "]
pub type CtsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn nf(&self) -> NfR {
NfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ore(&self) -> OreR {
OreR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idle(&self) -> IdleR {
IdleR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxne(&self) -> RxneR {
RxneR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tc(&self) -> TcR {
TcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctsif(&self) -> CtsifR {
CtsifR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cts(&self) -> CtsR {
CtsR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<IsrSpec> {
PeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fe(&mut self) -> FeW<IsrSpec> {
FeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn nf(&mut self) -> NfW<IsrSpec> {
NfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ore(&mut self) -> OreW<IsrSpec> {
OreW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idle(&mut self) -> IdleW<IsrSpec> {
IdleW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxne(&mut self) -> RxneW<IsrSpec> {
RxneW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tc(&mut self) -> TcW<IsrSpec> {
TcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txe(&mut self) -> TxeW<IsrSpec> {
TxeW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctsif(&mut self) -> CtsifW<IsrSpec> {
CtsifW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cts(&mut self) -> CtsW<IsrSpec> {
CtsW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "Interrupt flag Clear Register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `PECF` reader - "]
pub type PecfR = crate::BitReader;
#[doc = "Field `PECF` writer - "]
pub type PecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FECF` reader - "]
pub type FecfR = crate::BitReader;
#[doc = "Field `FECF` writer - "]
pub type FecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NCF` reader - "]
pub type NcfR = crate::BitReader;
#[doc = "Field `NCF` writer - "]
pub type NcfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORECF` reader - "]
pub type OrecfR = crate::BitReader;
#[doc = "Field `ORECF` writer - "]
pub type OrecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLECF` reader - "]
pub type IdlecfR = crate::BitReader;
#[doc = "Field `IDLECF` writer - "]
pub type IdlecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCCF` reader - "]
pub type TccfR = crate::BitReader;
#[doc = "Field `TCCF` writer - "]
pub type TccfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTSCF` reader - "]
pub type CtscfR = crate::BitReader;
#[doc = "Field `CTSCF` writer - "]
pub type CtscfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pecf(&self) -> PecfR {
PecfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fecf(&self) -> FecfR {
FecfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ncf(&self) -> NcfR {
NcfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn orecf(&self) -> OrecfR {
OrecfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idlecf(&self) -> IdlecfR {
IdlecfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tccf(&self) -> TccfR {
TccfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 7) & 3) as u8)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctscf(&self) -> CtscfR {
CtscfR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pecf(&mut self) -> PecfW<IcrSpec> {
PecfW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fecf(&mut self) -> FecfW<IcrSpec> {
FecfW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ncf(&mut self) -> NcfW<IcrSpec> {
NcfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn orecf(&mut self) -> OrecfW<IcrSpec> {
OrecfW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idlecf(&mut self) -> IdlecfW<IcrSpec> {
IdlecfW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IcrSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tccf(&mut self) -> TccfW<IcrSpec> {
TccfW::new(self, 6)
}
#[doc = "Bits 7:8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 7)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctscf(&mut self) -> CtscfW<IcrSpec> {
CtscfW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RDR (rw) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdr`]
module"]
#[doc(alias = "RDR")]
pub type Rdr = crate::Reg<rdr::RdrSpec>;
#[doc = "Receive Data Register"]
pub mod rdr {
#[doc = "Register `RDR` reader"]
pub type R = crate::R<RdrSpec>;
#[doc = "Register `RDR` writer"]
pub type W = crate::W<RdrSpec>;
#[doc = "Field `RDR` reader - "]
pub type RdrR = crate::FieldReader<u16>;
#[doc = "Field `RDR` writer - "]
pub type RdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn rdr(&self) -> RdrR {
RdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn rdr(&mut self) -> RdrW<RdrSpec> {
RdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrSpec;
impl crate::RegisterSpec for RdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rdr::R`](R) reader structure"]
impl crate::Readable for RdrSpec {}
#[doc = "`write(|w| ..)` method takes [`rdr::W`](W) writer structure"]
impl crate::Writable for RdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RDR to value 0"]
impl crate::Resettable for RdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TDR (rw) register accessor: Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`]
module"]
#[doc(alias = "TDR")]
pub type Tdr = crate::Reg<tdr::TdrSpec>;
#[doc = "Transmit Data Register"]
pub mod tdr {
#[doc = "Register `TDR` reader"]
pub type R = crate::R<TdrSpec>;
#[doc = "Register `TDR` writer"]
pub type W = crate::W<TdrSpec>;
#[doc = "Field `TDR` reader - "]
pub type TdrR = crate::FieldReader<u16>;
#[doc = "Field `TDR` writer - "]
pub type TdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn tdr(&self) -> TdrR {
TdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn tdr(&mut self) -> TdrW<TdrSpec> {
TdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TdrSpec;
impl crate::RegisterSpec for TdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tdr::R`](R) reader structure"]
impl crate::Readable for TdrSpec {}
#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"]
impl crate::Writable for TdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TDR to value 0"]
impl crate::Resettable for TdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "MISCR (rw) register accessor: Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscr`]
module"]
#[doc(alias = "MISCR")]
pub type Miscr = crate::Reg<miscr::MiscrSpec>;
#[doc = "Miscellaneous Register"]
pub mod miscr {
#[doc = "Register `MISCR` reader"]
pub type R = crate::R<MiscrSpec>;
#[doc = "Register `MISCR` writer"]
pub type W = crate::W<MiscrSpec>;
#[doc = "Field `SMPLINI` reader - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniR = crate::FieldReader;
#[doc = "Field `SMPLINI` writer - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RTSBIT` reader - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitR = crate::FieldReader;
#[doc = "Field `RTSBIT` writer - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
#[doc = "Field `AUTOCAL` reader - "]
pub type AutocalR = crate::BitReader;
#[doc = "Field `AUTOCAL` writer - "]
pub type AutocalW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
pub fn smplini(&self) -> SmpliniR {
SmpliniR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
pub fn rtsbit(&self) -> RtsbitR {
RtsbitR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x007f_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn autocal(&self) -> AutocalR {
AutocalR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
#[must_use]
pub fn smplini(&mut self) -> SmpliniW<MiscrSpec> {
SmpliniW::new(self, 0)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
#[must_use]
pub fn rtsbit(&mut self) -> RtsbitW<MiscrSpec> {
RtsbitW::new(self, 4)
}
#[doc = "Bits 8:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<MiscrSpec> {
RsvdW::new(self, 8)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn autocal(&mut self) -> AutocalW<MiscrSpec> {
AutocalW::new(self, 31)
}
}
#[doc = "Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscrSpec;
impl crate::RegisterSpec for MiscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miscr::R`](R) reader structure"]
impl crate::Readable for MiscrSpec {}
#[doc = "`write(|w| ..)` method takes [`miscr::W`](W) writer structure"]
impl crate::Writable for MiscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISCR to value 0"]
impl crate::Resettable for MiscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DRDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@drdr`]
module"]
#[doc(alias = "DRDR")]
pub type Drdr = crate::Reg<drdr::DrdrSpec>;
#[doc = ""]
pub mod drdr {
#[doc = "Register `DRDR` reader"]
pub type R = crate::R<DrdrSpec>;
#[doc = "Register `DRDR` writer"]
pub type W = crate::W<DrdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DrdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrdrSpec;
impl crate::RegisterSpec for DrdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`drdr::R`](R) reader structure"]
impl crate::Readable for DrdrSpec {}
#[doc = "`write(|w| ..)` method takes [`drdr::W`](W) writer structure"]
impl crate::Writable for DrdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DRDR to value 0"]
impl crate::Resettable for DrdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtdr`]
module"]
#[doc(alias = "DTDR")]
pub type Dtdr = crate::Reg<dtdr::DtdrSpec>;
#[doc = ""]
pub mod dtdr {
#[doc = "Register `DTDR` reader"]
pub type R = crate::R<DtdrSpec>;
#[doc = "Register `DTDR` writer"]
pub type W = crate::W<DtdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DtdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DtdrSpec;
impl crate::RegisterSpec for DtdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtdr::R`](R) reader structure"]
impl crate::Readable for DtdrSpec {}
#[doc = "`write(|w| ..)` method takes [`dtdr::W`](W) writer structure"]
impl crate::Writable for DtdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTDR to value 0"]
impl crate::Resettable for DtdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EXR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exr`]
module"]
#[doc(alias = "EXR")]
pub type Exr = crate::Reg<exr::ExrSpec>;
#[doc = ""]
pub mod exr {
#[doc = "Register `EXR` reader"]
pub type R = crate::R<ExrSpec>;
#[doc = "Register `EXR` writer"]
pub type W = crate::W<ExrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ExrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExrSpec;
impl crate::RegisterSpec for ExrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`exr::R`](R) reader structure"]
impl crate::Readable for ExrSpec {}
#[doc = "`write(|w| ..)` method takes [`exr::W`](W) writer structure"]
impl crate::Writable for ExrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EXR to value 0"]
impl crate::Resettable for ExrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "USART5"]
pub struct Usart5 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Usart5 {}
impl Usart5 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const usart5::RegisterBlock = 0x4000_6000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const usart5::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Usart5 {
type Target = usart5::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Usart5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart5").finish()
}
}
#[doc = "USART5"]
pub mod usart5 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
cr3: Cr3,
brr: Brr,
gtpr: Gtpr,
rtor: Rtor,
rqr: Rqr,
isr: Isr,
icr: Icr,
rdr: Rdr,
tdr: Tdr,
miscr: Miscr,
drdr: Drdr,
dtdr: Dtdr,
exr: Exr,
}
impl RegisterBlock {
#[doc = "0x00 - Control Register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - Control Register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - Control Register 3"]
#[inline(always)]
pub const fn cr3(&self) -> &Cr3 {
&self.cr3
}
#[doc = "0x0c - Baud Rate Register"]
#[inline(always)]
pub const fn brr(&self) -> &Brr {
&self.brr
}
#[doc = "0x10 - "]
#[inline(always)]
pub const fn gtpr(&self) -> &Gtpr {
&self.gtpr
}
#[doc = "0x14 - "]
#[inline(always)]
pub const fn rtor(&self) -> &Rtor {
&self.rtor
}
#[doc = "0x18 - Request Register"]
#[inline(always)]
pub const fn rqr(&self) -> &Rqr {
&self.rqr
}
#[doc = "0x1c - Interrupt and Status Register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x20 - Interrupt flag Clear Register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x24 - Receive Data Register"]
#[inline(always)]
pub const fn rdr(&self) -> &Rdr {
&self.rdr
}
#[doc = "0x28 - Transmit Data Register"]
#[inline(always)]
pub const fn tdr(&self) -> &Tdr {
&self.tdr
}
#[doc = "0x2c - Miscellaneous Register"]
#[inline(always)]
pub const fn miscr(&self) -> &Miscr {
&self.miscr
}
#[doc = "0x30 - "]
#[inline(always)]
pub const fn drdr(&self) -> &Drdr {
&self.drdr
}
#[doc = "0x34 - "]
#[inline(always)]
pub const fn dtdr(&self) -> &Dtdr {
&self.dtdr
}
#[doc = "0x38 - "]
#[inline(always)]
pub const fn exr(&self) -> &Exr {
&self.exr
}
}
#[doc = "CR1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `UE` reader - "]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - "]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RE` reader - "]
pub type ReR = crate::BitReader;
#[doc = "Field `RE` writer - "]
pub type ReW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TE` reader - "]
pub type TeR = crate::BitReader;
#[doc = "Field `TE` writer - "]
pub type TeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLEIE` reader - "]
pub type IdleieR = crate::BitReader;
#[doc = "Field `IDLEIE` writer - "]
pub type IdleieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNEIE` reader - "]
pub type RxneieR = crate::BitReader;
#[doc = "Field `RXNEIE` writer - "]
pub type RxneieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCIE` reader - "]
pub type TcieR = crate::BitReader;
#[doc = "Field `TCIE` writer - "]
pub type TcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXEIE` reader - "]
pub type TxeieR = crate::BitReader;
#[doc = "Field `TXEIE` writer - "]
pub type TxeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PEIE` reader - "]
pub type PeieR = crate::BitReader;
#[doc = "Field `PEIE` writer - "]
pub type PeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PS` reader - "]
pub type PsR = crate::BitReader;
#[doc = "Field `PS` writer - "]
pub type PsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCE` reader - "]
pub type PceR = crate::BitReader;
#[doc = "Field `PCE` writer - "]
pub type PceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `OVER8` reader - "]
pub type Over8R = crate::BitReader;
#[doc = "Field `OVER8` writer - "]
pub type Over8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `M` reader - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MR = crate::FieldReader;
#[doc = "Field `M` writer - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
pub type MW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn re(&self) -> ReR {
ReR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn te(&self) -> TeR {
TeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idleie(&self) -> IdleieR {
IdleieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxneie(&self) -> RxneieR {
RxneieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tcie(&self) -> TcieR {
TcieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txeie(&self) -> TxeieR {
TxeieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn peie(&self) -> PeieR {
PeieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn pce(&self) -> PceR {
PceR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:13"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn over8(&self) -> Over8R {
Over8R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 15:26"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 15) & 0x0fff) as u16)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
pub fn m(&self) -> MR {
MR::new(((self.bits >> 27) & 3) as u8)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<Cr1Spec> {
UeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<Cr1Spec> {
Rsvd4W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn re(&mut self) -> ReW<Cr1Spec> {
ReW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TeW<Cr1Spec> {
TeW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idleie(&mut self) -> IdleieW<Cr1Spec> {
IdleieW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxneie(&mut self) -> RxneieW<Cr1Spec> {
RxneieW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TcieW<Cr1Spec> {
TcieW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txeie(&mut self) -> TxeieW<Cr1Spec> {
TxeieW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn peie(&mut self) -> PeieW<Cr1Spec> {
PeieW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ps(&mut self) -> PsW<Cr1Spec> {
PsW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn pce(&mut self) -> PceW<Cr1Spec> {
PceW::new(self, 10)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<Cr1Spec> {
Rsvd3W::new(self, 11)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn over8(&mut self) -> Over8W<Cr1Spec> {
Over8W::new(self, 14)
}
#[doc = "Bits 15:26"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 15)
}
#[doc = "Bits 27:28 - 0 - 6bit, 1 - 7bit, 2 - 8bit, 3 - 9bit (including data bits and parity)"]
#[inline(always)]
#[must_use]
pub fn m(&mut self) -> MW<Cr1Spec> {
MW::new(self, 27)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 29)
}
}
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader<u16>;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `STOP` reader - "]
pub type StopR = crate::FieldReader;
#[doc = "Field `STOP` writer - "]
pub type StopW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 14) & 0x0003_ffff)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<Cr2Spec> {
StopW::new(self, 12)
}
#[doc = "Bits 14:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 14)
}
}
#[doc = "Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR3 (rw) register accessor: Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr3`]
module"]
#[doc(alias = "CR3")]
pub type Cr3 = crate::Reg<cr3::Cr3Spec>;
#[doc = "Control Register 3"]
pub mod cr3 {
#[doc = "Register `CR3` reader"]
pub type R = crate::R<Cr3Spec>;
#[doc = "Register `CR3` writer"]
pub type W = crate::W<Cr3Spec>;
#[doc = "Field `EIE` reader - "]
pub type EieR = crate::BitReader;
#[doc = "Field `EIE` writer - "]
pub type EieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `DMAR` reader - "]
pub type DmarR = crate::BitReader;
#[doc = "Field `DMAR` writer - "]
pub type DmarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAT` reader - "]
pub type DmatR = crate::BitReader;
#[doc = "Field `DMAT` writer - "]
pub type DmatW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTSE` reader - "]
pub type RtseR = crate::BitReader;
#[doc = "Field `RTSE` writer - "]
pub type RtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSE` reader - "]
pub type CtseR = crate::BitReader;
#[doc = "Field `CTSE` writer - "]
pub type CtseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIE` reader - "]
pub type CtsieR = crate::BitReader;
#[doc = "Field `CTSIE` writer - "]
pub type CtsieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ONEBIT` reader - "]
pub type OnebitR = crate::BitReader;
#[doc = "Field `ONEBIT` writer - "]
pub type OnebitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVRDIS` reader - "]
pub type OvrdisR = crate::BitReader;
#[doc = "Field `OVRDIS` writer - "]
pub type OvrdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn eie(&self) -> EieR {
EieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x1f) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn dmar(&self) -> DmarR {
DmarR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dmat(&self) -> DmatR {
DmatR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rtse(&self) -> RtseR {
RtseR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctse(&self) -> CtseR {
CtseR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ctsie(&self) -> CtsieR {
CtsieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn onebit(&self) -> OnebitR {
OnebitR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn ovrdis(&self) -> OvrdisR {
OvrdisR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 13) & 0x0007_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn eie(&mut self) -> EieW<Cr3Spec> {
EieW::new(self, 0)
}
#[doc = "Bits 1:5"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr3Spec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn dmar(&mut self) -> DmarW<Cr3Spec> {
DmarW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dmat(&mut self) -> DmatW<Cr3Spec> {
DmatW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rtse(&mut self) -> RtseW<Cr3Spec> {
RtseW::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctse(&mut self) -> CtseW<Cr3Spec> {
CtseW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ctsie(&mut self) -> CtsieW<Cr3Spec> {
CtsieW::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn onebit(&mut self) -> OnebitW<Cr3Spec> {
OnebitW::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn ovrdis(&mut self) -> OvrdisW<Cr3Spec> {
OvrdisW::new(self, 12)
}
#[doc = "Bits 13:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr3Spec> {
RsvdW::new(self, 13)
}
}
#[doc = "Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr3Spec;
impl crate::RegisterSpec for Cr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr3::R`](R) reader structure"]
impl crate::Readable for Cr3Spec {}
#[doc = "`write(|w| ..)` method takes [`cr3::W`](W) writer structure"]
impl crate::Writable for Cr3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR3 to value 0"]
impl crate::Resettable for Cr3Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "BRR (rw) register accessor: Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@brr`]
module"]
#[doc(alias = "BRR")]
pub type Brr = crate::Reg<brr::BrrSpec>;
#[doc = "Baud Rate Register"]
pub mod brr {
#[doc = "Register `BRR` reader"]
pub type R = crate::R<BrrSpec>;
#[doc = "Register `BRR` writer"]
pub type W = crate::W<BrrSpec>;
#[doc = "Field `FRAC` reader - "]
pub type FracR = crate::FieldReader;
#[doc = "Field `FRAC` writer - "]
pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `INT` reader - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntR = crate::FieldReader<u16>;
#[doc = "Field `INT` writer - Baud Rate = UCLK / (int+ frac/16) / 16"]
pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn frac(&self) -> FracR {
FracR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
pub fn int(&self) -> IntR {
IntR::new(((self.bits >> 4) & 0x0fff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn frac(&mut self) -> FracW<BrrSpec> {
FracW::new(self, 0)
}
#[doc = "Bits 4:15 - Baud Rate = UCLK / (int+ frac/16) / 16"]
#[inline(always)]
#[must_use]
pub fn int(&mut self) -> IntW<BrrSpec> {
IntW::new(self, 4)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<BrrSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BrrSpec;
impl crate::RegisterSpec for BrrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`brr::R`](R) reader structure"]
impl crate::Readable for BrrSpec {}
#[doc = "`write(|w| ..)` method takes [`brr::W`](W) writer structure"]
impl crate::Writable for BrrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets BRR to value 0"]
impl crate::Resettable for BrrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "GTPR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gtpr`]
module"]
#[doc(alias = "GTPR")]
pub type Gtpr = crate::Reg<gtpr::GtprSpec>;
#[doc = ""]
pub mod gtpr {
#[doc = "Register `GTPR` reader"]
pub type R = crate::R<GtprSpec>;
#[doc = "Register `GTPR` writer"]
pub type W = crate::W<GtprSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<GtprSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GtprSpec;
impl crate::RegisterSpec for GtprSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gtpr::R`](R) reader structure"]
impl crate::Readable for GtprSpec {}
#[doc = "`write(|w| ..)` method takes [`gtpr::W`](W) writer structure"]
impl crate::Writable for GtprSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GTPR to value 0"]
impl crate::Resettable for GtprSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RTOR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtor`]
module"]
#[doc(alias = "RTOR")]
pub type Rtor = crate::Reg<rtor::RtorSpec>;
#[doc = ""]
pub mod rtor {
#[doc = "Register `RTOR` reader"]
pub type R = crate::R<RtorSpec>;
#[doc = "Register `RTOR` writer"]
pub type W = crate::W<RtorSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RtorSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtorSpec;
impl crate::RegisterSpec for RtorSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtor::R`](R) reader structure"]
impl crate::Readable for RtorSpec {}
#[doc = "`write(|w| ..)` method takes [`rtor::W`](W) writer structure"]
impl crate::Writable for RtorSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTOR to value 0"]
impl crate::Resettable for RtorSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RQR (rw) register accessor: Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rqr`]
module"]
#[doc(alias = "RQR")]
pub type Rqr = crate::Reg<rqr::RqrSpec>;
#[doc = "Request Register"]
pub mod rqr {
#[doc = "Register `RQR` reader"]
pub type R = crate::R<RqrSpec>;
#[doc = "Register `RQR` writer"]
pub type W = crate::W<RqrSpec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RXFRQ` reader - "]
pub type RxfrqR = crate::BitReader;
#[doc = "Field `RXFRQ` writer - "]
pub type RxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXFRQ` reader - "]
pub type TxfrqR = crate::BitReader;
#[doc = "Field `TXFRQ` writer - "]
pub type TxfrqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxfrq(&self) -> RxfrqR {
RxfrqR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn txfrq(&self) -> TxfrqR {
TxfrqR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<RqrSpec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxfrq(&mut self) -> RxfrqW<RqrSpec> {
RxfrqW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn txfrq(&mut self) -> TxfrqW<RqrSpec> {
TxfrqW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RqrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rqr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rqr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RqrSpec;
impl crate::RegisterSpec for RqrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rqr::R`](R) reader structure"]
impl crate::Readable for RqrSpec {}
#[doc = "`write(|w| ..)` method takes [`rqr::W`](W) writer structure"]
impl crate::Writable for RqrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RQR to value 0"]
impl crate::Resettable for RqrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ISR (rw) register accessor: Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "Interrupt and Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `PE` reader - "]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - "]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - "]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - "]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NF` reader - "]
pub type NfR = crate::BitReader;
#[doc = "Field `NF` writer - "]
pub type NfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORE` reader - "]
pub type OreR = crate::BitReader;
#[doc = "Field `ORE` writer - "]
pub type OreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLE` reader - "]
pub type IdleR = crate::BitReader;
#[doc = "Field `IDLE` writer - "]
pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXNE` reader - "]
pub type RxneR = crate::BitReader;
#[doc = "Field `RXNE` writer - "]
pub type RxneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TC` reader - "]
pub type TcR = crate::BitReader;
#[doc = "Field `TC` writer - "]
pub type TcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - "]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - "]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTSIF` reader - "]
pub type CtsifR = crate::BitReader;
#[doc = "Field `CTSIF` writer - "]
pub type CtsifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTS` reader - "]
pub type CtsR = crate::BitReader;
#[doc = "Field `CTS` writer - "]
pub type CtsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn nf(&self) -> NfR {
NfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ore(&self) -> OreR {
OreR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idle(&self) -> IdleR {
IdleR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxne(&self) -> RxneR {
RxneR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tc(&self) -> TcR {
TcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctsif(&self) -> CtsifR {
CtsifR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cts(&self) -> CtsR {
CtsR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pe(&mut self) -> PeW<IsrSpec> {
PeW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fe(&mut self) -> FeW<IsrSpec> {
FeW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn nf(&mut self) -> NfW<IsrSpec> {
NfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ore(&mut self) -> OreW<IsrSpec> {
OreW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idle(&mut self) -> IdleW<IsrSpec> {
IdleW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxne(&mut self) -> RxneW<IsrSpec> {
RxneW::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tc(&mut self) -> TcW<IsrSpec> {
TcW::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txe(&mut self) -> TxeW<IsrSpec> {
TxeW::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctsif(&mut self) -> CtsifW<IsrSpec> {
CtsifW::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cts(&mut self) -> CtsW<IsrSpec> {
CtsW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "Interrupt and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "Interrupt flag Clear Register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `PECF` reader - "]
pub type PecfR = crate::BitReader;
#[doc = "Field `PECF` writer - "]
pub type PecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FECF` reader - "]
pub type FecfR = crate::BitReader;
#[doc = "Field `FECF` writer - "]
pub type FecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NCF` reader - "]
pub type NcfR = crate::BitReader;
#[doc = "Field `NCF` writer - "]
pub type NcfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ORECF` reader - "]
pub type OrecfR = crate::BitReader;
#[doc = "Field `ORECF` writer - "]
pub type OrecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLECF` reader - "]
pub type IdlecfR = crate::BitReader;
#[doc = "Field `IDLECF` writer - "]
pub type IdlecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TCCF` reader - "]
pub type TccfR = crate::BitReader;
#[doc = "Field `TCCF` writer - "]
pub type TccfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CTSCF` reader - "]
pub type CtscfR = crate::BitReader;
#[doc = "Field `CTSCF` writer - "]
pub type CtscfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pecf(&self) -> PecfR {
PecfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fecf(&self) -> FecfR {
FecfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ncf(&self) -> NcfR {
NcfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn orecf(&self) -> OrecfR {
OrecfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn idlecf(&self) -> IdlecfR {
IdlecfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tccf(&self) -> TccfR {
TccfR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 7:8"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 7) & 3) as u8)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ctscf(&self) -> CtscfR {
CtscfR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 10) & 0x003f_ffff)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pecf(&mut self) -> PecfW<IcrSpec> {
PecfW::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fecf(&mut self) -> FecfW<IcrSpec> {
FecfW::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ncf(&mut self) -> NcfW<IcrSpec> {
NcfW::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn orecf(&mut self) -> OrecfW<IcrSpec> {
OrecfW::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn idlecf(&mut self) -> IdlecfW<IcrSpec> {
IdlecfW::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<IcrSpec> {
Rsvd3W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tccf(&mut self) -> TccfW<IcrSpec> {
TccfW::new(self, 6)
}
#[doc = "Bits 7:8"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 7)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctscf(&mut self) -> CtscfW<IcrSpec> {
CtscfW::new(self, 9)
}
#[doc = "Bits 10:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 10)
}
}
#[doc = "Interrupt flag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RDR (rw) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdr`]
module"]
#[doc(alias = "RDR")]
pub type Rdr = crate::Reg<rdr::RdrSpec>;
#[doc = "Receive Data Register"]
pub mod rdr {
#[doc = "Register `RDR` reader"]
pub type R = crate::R<RdrSpec>;
#[doc = "Register `RDR` writer"]
pub type W = crate::W<RdrSpec>;
#[doc = "Field `RDR` reader - "]
pub type RdrR = crate::FieldReader<u16>;
#[doc = "Field `RDR` writer - "]
pub type RdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn rdr(&self) -> RdrR {
RdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn rdr(&mut self) -> RdrW<RdrSpec> {
RdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RdrSpec;
impl crate::RegisterSpec for RdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rdr::R`](R) reader structure"]
impl crate::Readable for RdrSpec {}
#[doc = "`write(|w| ..)` method takes [`rdr::W`](W) writer structure"]
impl crate::Writable for RdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RDR to value 0"]
impl crate::Resettable for RdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TDR (rw) register accessor: Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`]
module"]
#[doc(alias = "TDR")]
pub type Tdr = crate::Reg<tdr::TdrSpec>;
#[doc = "Transmit Data Register"]
pub mod tdr {
#[doc = "Register `TDR` reader"]
pub type R = crate::R<TdrSpec>;
#[doc = "Register `TDR` writer"]
pub type W = crate::W<TdrSpec>;
#[doc = "Field `TDR` reader - "]
pub type TdrR = crate::FieldReader<u16>;
#[doc = "Field `TDR` writer - "]
pub type TdrW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn tdr(&self) -> TdrR {
TdrR::new((self.bits & 0x01ff) as u16)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn tdr(&mut self) -> TdrW<TdrSpec> {
TdrW::new(self, 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<TdrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TdrSpec;
impl crate::RegisterSpec for TdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tdr::R`](R) reader structure"]
impl crate::Readable for TdrSpec {}
#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"]
impl crate::Writable for TdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TDR to value 0"]
impl crate::Resettable for TdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "MISCR (rw) register accessor: Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miscr`]
module"]
#[doc(alias = "MISCR")]
pub type Miscr = crate::Reg<miscr::MiscrSpec>;
#[doc = "Miscellaneous Register"]
pub mod miscr {
#[doc = "Register `MISCR` reader"]
pub type R = crate::R<MiscrSpec>;
#[doc = "Register `MISCR` writer"]
pub type W = crate::W<MiscrSpec>;
#[doc = "Field `SMPLINI` reader - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniR = crate::FieldReader;
#[doc = "Field `SMPLINI` writer - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
pub type SmpliniW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RTSBIT` reader - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitR = crate::FieldReader;
#[doc = "Field `RTSBIT` writer - assert RTS ahead of the frame completion (in number of bits)"]
pub type RtsbitW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
#[doc = "Field `AUTOCAL` reader - "]
pub type AutocalR = crate::BitReader;
#[doc = "Field `AUTOCAL` writer - "]
pub type AutocalW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
pub fn smplini(&self) -> SmpliniR {
SmpliniR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
pub fn rtsbit(&self) -> RtsbitR {
RtsbitR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:30"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x007f_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn autocal(&self) -> AutocalR {
AutocalR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - initial sample count, count down from this value to zero to reach the middle of the start bit in Rx"]
#[inline(always)]
#[must_use]
pub fn smplini(&mut self) -> SmpliniW<MiscrSpec> {
SmpliniW::new(self, 0)
}
#[doc = "Bits 4:7 - assert RTS ahead of the frame completion (in number of bits)"]
#[inline(always)]
#[must_use]
pub fn rtsbit(&mut self) -> RtsbitW<MiscrSpec> {
RtsbitW::new(self, 4)
}
#[doc = "Bits 8:30"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<MiscrSpec> {
RsvdW::new(self, 8)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn autocal(&mut self) -> AutocalW<MiscrSpec> {
AutocalW::new(self, 31)
}
}
#[doc = "Miscellaneous Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscrSpec;
impl crate::RegisterSpec for MiscrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miscr::R`](R) reader structure"]
impl crate::Readable for MiscrSpec {}
#[doc = "`write(|w| ..)` method takes [`miscr::W`](W) writer structure"]
impl crate::Writable for MiscrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISCR to value 0"]
impl crate::Resettable for MiscrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DRDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@drdr`]
module"]
#[doc(alias = "DRDR")]
pub type Drdr = crate::Reg<drdr::DrdrSpec>;
#[doc = ""]
pub mod drdr {
#[doc = "Register `DRDR` reader"]
pub type R = crate::R<DrdrSpec>;
#[doc = "Register `DRDR` writer"]
pub type W = crate::W<DrdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DrdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`drdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`drdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrdrSpec;
impl crate::RegisterSpec for DrdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`drdr::R`](R) reader structure"]
impl crate::Readable for DrdrSpec {}
#[doc = "`write(|w| ..)` method takes [`drdr::W`](W) writer structure"]
impl crate::Writable for DrdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DRDR to value 0"]
impl crate::Resettable for DrdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTDR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtdr`]
module"]
#[doc(alias = "DTDR")]
pub type Dtdr = crate::Reg<dtdr::DtdrSpec>;
#[doc = ""]
pub mod dtdr {
#[doc = "Register `DTDR` reader"]
pub type R = crate::R<DtdrSpec>;
#[doc = "Register `DTDR` writer"]
pub type W = crate::W<DtdrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DtdrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DtdrSpec;
impl crate::RegisterSpec for DtdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtdr::R`](R) reader structure"]
impl crate::Readable for DtdrSpec {}
#[doc = "`write(|w| ..)` method takes [`dtdr::W`](W) writer structure"]
impl crate::Writable for DtdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTDR to value 0"]
impl crate::Resettable for DtdrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EXR (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exr`]
module"]
#[doc(alias = "EXR")]
pub type Exr = crate::Reg<exr::ExrSpec>;
#[doc = ""]
pub mod exr {
#[doc = "Register `EXR` reader"]
pub type R = crate::R<ExrSpec>;
#[doc = "Register `EXR` writer"]
pub type W = crate::W<ExrSpec>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ExrSpec> {
RsvdW::new(self, 0)
}
}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExrSpec;
impl crate::RegisterSpec for ExrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`exr::R`](R) reader structure"]
impl crate::Readable for ExrSpec {}
#[doc = "`write(|w| ..)` method takes [`exr::W`](W) writer structure"]
impl crate::Writable for ExrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EXR to value 0"]
impl crate::Resettable for ExrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "BTIM3"]
pub struct Btim3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Btim3 {}
impl Btim3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const btim3::RegisterBlock = 0x4000_9000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const btim3::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Btim3 {
type Target = btim3::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Btim3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Btim3").finish()
}
}
#[doc = "BTIM3"]
pub mod btim3 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
smcr: Smcr,
dier: Dier,
sr: Sr,
egr: Egr,
rsvd1: Rsvd1,
_reserved7: [u8; 0x08],
cnt: Cnt,
psc: Psc,
arr: Arr,
}
impl RegisterBlock {
#[doc = "0x00 - TIM control register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - TIM control register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - TIM slave mode control register"]
#[inline(always)]
pub const fn smcr(&self) -> &Smcr {
&self.smcr
}
#[doc = "0x0c - TIM DMA/Interrupt enable register"]
#[inline(always)]
pub const fn dier(&self) -> &Dier {
&self.dier
}
#[doc = "0x10 - TIM status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Event generation register"]
#[inline(always)]
pub const fn egr(&self) -> &Egr {
&self.egr
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x24 - Counter"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x28 - Prescaler"]
#[inline(always)]
pub const fn psc(&self) -> &Psc {
&self.psc
}
#[doc = "0x2c - Auto-reload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
}
#[doc = "CR1 (rw) register accessor: TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "TIM control register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `CEN` reader - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UDIS` reader - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisR = crate::BitReader;
#[doc = "Field `UDIS` writer - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `URS` reader - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsR = crate::BitReader;
#[doc = "Field `URS` writer - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OPM` reader - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmR = crate::BitReader;
#[doc = "Field `OPM` writer - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ARPE` reader - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeR = crate::BitReader;
#[doc = "Field `ARPE` writer - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
pub fn udis(&self) -> UdisR {
UdisR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
pub fn urs(&self) -> UrsR {
UrsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
pub fn opm(&self) -> OpmR {
OpmR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
pub fn arpe(&self) -> ArpeR {
ArpeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CenW<Cr1Spec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UdisW<Cr1Spec> {
UdisW::new(self, 1)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> UrsW<Cr1Spec> {
UrsW::new(self, 2)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OpmW<Cr1Spec> {
OpmW::new(self, 3)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ArpeW<Cr1Spec> {
ArpeW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "TIM control register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MMS` reader - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsR = crate::FieldReader;
#[doc = "Field `MMS` writer - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
pub fn mms(&self) -> MmsR {
MmsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MmsW<Cr2Spec> {
MmsW::new(self, 4)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 6)
}
}
#[doc = "TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMCR (rw) register accessor: TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcr`]
module"]
#[doc(alias = "SMCR")]
pub type Smcr = crate::Reg<smcr::SmcrSpec>;
#[doc = "TIM slave mode control register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub type R = crate::R<SmcrSpec>;
#[doc = "Register `SMCR` writer"]
pub type W = crate::W<SmcrSpec>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::FieldReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TS` reader - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsR = crate::FieldReader;
#[doc = "Field `TS` writer - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSM` reader - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmR = crate::BitReader;
#[doc = "Field `MSM` writer - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SMS` reader - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsR = crate::FieldReader;
#[doc = "Field `SMS` writer - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GTS` reader - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsR = crate::FieldReader;
#[doc = "Field `GTS` writer - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `GTP` reader - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpR = crate::BitReader;
#[doc = "Field `GTP` writer - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GM` reader - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmR = crate::BitReader;
#[doc = "Field `GM` writer - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn ts(&self) -> TsR {
TsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
pub fn msm(&self) -> MsmR {
MsmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
pub fn sms(&self) -> SmsR {
SmsR::new(((self.bits >> 16) & 7) as u8)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn gts(&self) -> GtsR {
GtsR::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
pub fn gtp(&self) -> GtpR {
GtpR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
pub fn gm(&self) -> GmR {
GmR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<SmcrSpec> {
Rsvd5W::new(self, 0)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TsW<SmcrSpec> {
TsW::new(self, 4)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<SmcrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MsmW<SmcrSpec> {
MsmW::new(self, 7)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<SmcrSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SmsW<SmcrSpec> {
SmsW::new(self, 16)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SmcrSpec> {
Rsvd2W::new(self, 19)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn gts(&mut self) -> GtsW<SmcrSpec> {
GtsW::new(self, 20)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
#[must_use]
pub fn gtp(&mut self) -> GtpW<SmcrSpec> {
GtpW::new(self, 22)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
#[must_use]
pub fn gm(&mut self) -> GmW<SmcrSpec> {
GmW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SmcrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmcrSpec;
impl crate::RegisterSpec for SmcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smcr::R`](R) reader structure"]
impl crate::Readable for SmcrSpec {}
#[doc = "`write(|w| ..)` method takes [`smcr::W`](W) writer structure"]
impl crate::Writable for SmcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SmcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DIER (rw) register accessor: TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dier`]
module"]
#[doc(alias = "DIER")]
pub type Dier = crate::Reg<dier::DierSpec>;
#[doc = "TIM DMA/Interrupt enable register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub type R = crate::R<DierSpec>;
#[doc = "Register `DIER` writer"]
pub type W = crate::W<DierSpec>;
#[doc = "Field `UIE` reader - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieR = crate::BitReader;
#[doc = "Field `UIE` writer - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `UDE` reader - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeR = crate::BitReader;
#[doc = "Field `UDE` writer - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
pub fn uie(&self) -> UieR {
UieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x7f) as u8)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
pub fn ude(&self) -> UdeR {
UdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UieW<DierSpec> {
UieW::new(self, 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DierSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UdeW<DierSpec> {
UdeW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DierSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DierSpec;
impl crate::RegisterSpec for DierSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dier::R`](R) reader structure"]
impl crate::Readable for DierSpec {}
#[doc = "`write(|w| ..)` method takes [`dier::W`](W) writer structure"]
impl crate::Writable for DierSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DierSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "TIM status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `UIF` reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifR = crate::BitReader;
#[doc = "Field `UIF` writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
pub fn uif(&self) -> UifR {
UifR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UifW<SrSpec> {
UifW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EGR (rw) register accessor: Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@egr`]
module"]
#[doc(alias = "EGR")]
pub type Egr = crate::Reg<egr::EgrSpec>;
#[doc = "Event generation register"]
pub mod egr {
#[doc = "Register `EGR` reader"]
pub type R = crate::R<EgrSpec>;
#[doc = "Register `EGR` writer"]
pub type W = crate::W<EgrSpec>;
#[doc = "Field `UG` reader - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgR = crate::BitReader;
#[doc = "Field `UG` writer - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
pub fn ug(&self) -> UgR {
UgR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UgW<EgrSpec> {
UgW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<EgrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EgrSpec;
impl crate::RegisterSpec for EgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`egr::R`](R) reader structure"]
impl crate::Readable for EgrSpec {}
#[doc = "`write(|w| ..)` method takes [`egr::W`](W) writer structure"]
impl crate::Writable for EgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "Counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - counter value"]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - counter value"]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
}
#[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSC (rw) register accessor: Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`]
module"]
#[doc(alias = "PSC")]
pub type Psc = crate::Reg<psc::PscSpec>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub type R = crate::R<PscSpec>;
#[doc = "Register `PSC` writer"]
pub type W = crate::W<PscSpec>;
#[doc = "Field `PSC` reader - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscR = crate::FieldReader<u16>;
#[doc = "Field `PSC` writer - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
pub fn psc(&self) -> PscR {
PscR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PscW<PscSpec> {
PscW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PscSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PscSpec;
impl crate::RegisterSpec for PscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate::Readable for PscSpec {}
#[doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate::Writable for PscSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PscSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "Auto-reload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
}
#[doc = "Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "BTIM4"]
pub struct Btim4 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Btim4 {}
impl Btim4 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const btim4::RegisterBlock = 0x4000_a000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const btim4::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Btim4 {
type Target = btim4::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Btim4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Btim4").finish()
}
}
#[doc = "BTIM4"]
pub mod btim4 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
smcr: Smcr,
dier: Dier,
sr: Sr,
egr: Egr,
rsvd1: Rsvd1,
_reserved7: [u8; 0x08],
cnt: Cnt,
psc: Psc,
arr: Arr,
}
impl RegisterBlock {
#[doc = "0x00 - TIM control register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - TIM control register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - TIM slave mode control register"]
#[inline(always)]
pub const fn smcr(&self) -> &Smcr {
&self.smcr
}
#[doc = "0x0c - TIM DMA/Interrupt enable register"]
#[inline(always)]
pub const fn dier(&self) -> &Dier {
&self.dier
}
#[doc = "0x10 - TIM status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Event generation register"]
#[inline(always)]
pub const fn egr(&self) -> &Egr {
&self.egr
}
#[doc = "0x18 - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x24 - Counter"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x28 - Prescaler"]
#[inline(always)]
pub const fn psc(&self) -> &Psc {
&self.psc
}
#[doc = "0x2c - Auto-reload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
}
#[doc = "CR1 (rw) register accessor: TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`]
module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "TIM control register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `CEN` reader - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UDIS` reader - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisR = crate::BitReader;
#[doc = "Field `UDIS` writer - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
pub type UdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `URS` reader - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsR = crate::BitReader;
#[doc = "Field `URS` writer - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
pub type UrsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OPM` reader - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmR = crate::BitReader;
#[doc = "Field `OPM` writer - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
pub type OpmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `ARPE` reader - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeR = crate::BitReader;
#[doc = "Field `ARPE` writer - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
pub type ArpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
pub fn udis(&self) -> UdisR {
UdisR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
pub fn urs(&self) -> UrsR {
UrsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
pub fn opm(&self) -> OpmR {
OpmR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
pub fn arpe(&self) -> ArpeR {
ArpeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs."]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CenW<Cr1Spec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller."]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UdisW<Cr1Spec> {
UdisW::new(self, 1)
}
#[doc = "Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled."]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> UrsW<Cr1Spec> {
UrsW::new(self, 2)
}
#[doc = "Bit 3 - One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OpmW<Cr1Spec> {
OpmW::new(self, 3)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr1Spec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 7 - Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ArpeW<Cr1Spec> {
ArpeW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr1Spec> {
RsvdW::new(self, 8)
}
}
#[doc = "TIM control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR2 (rw) register accessor: TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`]
module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "TIM control register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `MMS` reader - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsR = crate::FieldReader;
#[doc = "Field `MMS` writer - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
pub type MmsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
pub fn mms(&self) -> MmsR {
MmsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 6) & 0x03ff_ffff)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<Cr2Spec> {
Rsvd2W::new(self, 0)
}
#[doc = "Bits 4:5 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating - The delayed gating trigger is selected as trigger output (TRGO)."]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MmsW<Cr2Spec> {
MmsW::new(self, 4)
}
#[doc = "Bits 6:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<Cr2Spec> {
RsvdW::new(self, 6)
}
}
#[doc = "TIM control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SMCR (rw) register accessor: TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcr`]
module"]
#[doc(alias = "SMCR")]
pub type Smcr = crate::Reg<smcr::SmcrSpec>;
#[doc = "TIM slave mode control register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub type R = crate::R<SmcrSpec>;
#[doc = "Register `SMCR` writer"]
pub type W = crate::W<SmcrSpec>;
#[doc = "Field `RSVD5` reader - "]
pub type Rsvd5R = crate::FieldReader;
#[doc = "Field `RSVD5` writer - "]
pub type Rsvd5W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TS` reader - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsR = crate::FieldReader;
#[doc = "Field `TS` writer - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type TsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MSM` reader - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmR = crate::BitReader;
#[doc = "Field `MSM` writer - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
pub type MsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::FieldReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `SMS` reader - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsR = crate::FieldReader;
#[doc = "Field `SMS` writer - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
pub type SmsW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GTS` reader - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsR = crate::FieldReader;
#[doc = "Field `GTS` writer - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
pub type GtsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `GTP` reader - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpR = crate::BitReader;
#[doc = "Field `GTP` writer - Gating trigger polarity invert 0: active at high level 1: active at low level"]
pub type GtpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GM` reader - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmR = crate::BitReader;
#[doc = "Field `GM` writer - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
pub type GmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn rsvd5(&self) -> Rsvd5R {
Rsvd5R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn ts(&self) -> TsR {
TsR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
pub fn msm(&self) -> MsmR {
MsmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
pub fn sms(&self) -> SmsR {
SmsR::new(((self.bits >> 16) & 7) as u8)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
pub fn gts(&self) -> GtsR {
GtsR::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
pub fn gtp(&self) -> GtpR {
GtpR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
pub fn gm(&self) -> GmR {
GmR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn rsvd5(&mut self) -> Rsvd5W<SmcrSpec> {
Rsvd5W::new(self, 0)
}
#[doc = "Bits 4:5 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TsW<SmcrSpec> {
TsW::new(self, 4)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<SmcrSpec> {
Rsvd4W::new(self, 6)
}
#[doc = "Bit 7 - Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MsmW<SmcrSpec> {
MsmW::new(self, 7)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<SmcrSpec> {
Rsvd3W::new(self, 8)
}
#[doc = "Bits 16:18 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter."]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SmsW<SmcrSpec> {
SmsW::new(self, 16)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<SmcrSpec> {
Rsvd2W::new(self, 19)
}
#[doc = "Bits 20:21 - Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3)"]
#[inline(always)]
#[must_use]
pub fn gts(&mut self) -> GtsW<SmcrSpec> {
GtsW::new(self, 20)
}
#[doc = "Bit 22 - Gating trigger polarity invert 0: active at high level 1: active at low level"]
#[inline(always)]
#[must_use]
pub fn gtp(&mut self) -> GtpW<SmcrSpec> {
GtpW::new(self, 22)
}
#[doc = "Bit 23 - Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection."]
#[inline(always)]
#[must_use]
pub fn gm(&mut self) -> GmW<SmcrSpec> {
GmW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SmcrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "TIM slave mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmcrSpec;
impl crate::RegisterSpec for SmcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smcr::R`](R) reader structure"]
impl crate::Readable for SmcrSpec {}
#[doc = "`write(|w| ..)` method takes [`smcr::W`](W) writer structure"]
impl crate::Writable for SmcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SmcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DIER (rw) register accessor: TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dier`]
module"]
#[doc(alias = "DIER")]
pub type Dier = crate::Reg<dier::DierSpec>;
#[doc = "TIM DMA/Interrupt enable register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub type R = crate::R<DierSpec>;
#[doc = "Register `DIER` writer"]
pub type W = crate::W<DierSpec>;
#[doc = "Field `UIE` reader - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieR = crate::BitReader;
#[doc = "Field `UIE` writer - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
pub type UieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `UDE` reader - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeR = crate::BitReader;
#[doc = "Field `UDE` writer - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
pub type UdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
pub fn uie(&self) -> UieR {
UieR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 1) & 0x7f) as u8)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
pub fn ude(&self) -> UdeR {
UdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UieW<DierSpec> {
UieW::new(self, 0)
}
#[doc = "Bits 1:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<DierSpec> {
Rsvd2W::new(self, 1)
}
#[doc = "Bit 8 - Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UdeW<DierSpec> {
UdeW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<DierSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "TIM DMA/Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DierSpec;
impl crate::RegisterSpec for DierSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dier::R`](R) reader structure"]
impl crate::Readable for DierSpec {}
#[doc = "`write(|w| ..)` method takes [`dier::W`](W) writer structure"]
impl crate::Writable for DierSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DierSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "TIM status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `UIF` reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifR = crate::BitReader;
#[doc = "Field `UIF` writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
pub type UifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
pub fn uif(&self) -> UifR {
UifR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register."]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UifW<SrSpec> {
UifW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "TIM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EGR (rw) register accessor: Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@egr`]
module"]
#[doc(alias = "EGR")]
pub type Egr = crate::Reg<egr::EgrSpec>;
#[doc = "Event generation register"]
pub mod egr {
#[doc = "Register `EGR` reader"]
pub type R = crate::R<EgrSpec>;
#[doc = "Register `EGR` writer"]
pub type W = crate::W<EgrSpec>;
#[doc = "Field `UG` reader - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgR = crate::BitReader;
#[doc = "Field `UG` writer - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
pub type UgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
pub fn ug(&self) -> UgR {
UgR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting)."]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UgW<EgrSpec> {
UgW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<EgrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "Event generation register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`egr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EgrSpec;
impl crate::RegisterSpec for EgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`egr::R`](R) reader structure"]
impl crate::Readable for EgrSpec {}
#[doc = "`write(|w| ..)` method takes [`egr::W`](W) writer structure"]
impl crate::Writable for EgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "Counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - counter value"]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - counter value"]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - counter value"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
}
#[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSC (rw) register accessor: Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`]
module"]
#[doc(alias = "PSC")]
pub type Psc = crate::Reg<psc::PscSpec>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub type R = crate::R<PscSpec>;
#[doc = "Register `PSC` writer"]
pub type W = crate::W<PscSpec>;
#[doc = "Field `PSC` reader - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscR = crate::FieldReader<u16>;
#[doc = "Field `PSC` writer - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u16>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
pub fn psc(&self) -> PscR {
PscR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescaler value The counter clock frequency is equal to fCLK / (PSC\\[15:0\\]
+ 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in “reset mode”)."]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PscW<PscSpec> {
PscW::new(self, 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<PscSpec> {
RsvdW::new(self, 16)
}
}
#[doc = "Prescaler\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PscSpec;
impl crate::RegisterSpec for PscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate::Readable for PscSpec {}
#[doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate::Writable for PscSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PscSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "Auto-reload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
}
#[doc = "Auto-reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "WDT2"]
pub struct Wdt2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Wdt2 {}
impl Wdt2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const wdt2::RegisterBlock = 0x4000_b000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const wdt2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Wdt2 {
type Target = wdt2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Wdt2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wdt2").finish()
}
}
#[doc = "WDT2"]
pub mod wdt2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
wdt_cvr0: WdtCvr0,
wdt_cvr1: WdtCvr1,
wdt_cr: WdtCr,
wdt_ccr: WdtCcr,
wdt_icr: WdtIcr,
wdt_sr: WdtSr,
wdt_wp: WdtWp,
wdt_fg: WdtFg,
}
impl RegisterBlock {
#[doc = "0x00 - WatchDog Counter Value 0"]
#[inline(always)]
pub const fn wdt_cvr0(&self) -> &WdtCvr0 {
&self.wdt_cvr0
}
#[doc = "0x04 - WatchDog Counter Value 1"]
#[inline(always)]
pub const fn wdt_cvr1(&self) -> &WdtCvr1 {
&self.wdt_cvr1
}
#[doc = "0x08 - WatchDog Control Register"]
#[inline(always)]
pub const fn wdt_cr(&self) -> &WdtCr {
&self.wdt_cr
}
#[doc = "0x0c - WatchDog Counter Control Register"]
#[inline(always)]
pub const fn wdt_ccr(&self) -> &WdtCcr {
&self.wdt_ccr
}
#[doc = "0x10 - WatchDog Interrupt Clear Register"]
#[inline(always)]
pub const fn wdt_icr(&self) -> &WdtIcr {
&self.wdt_icr
}
#[doc = "0x14 - WatchDog Status Register"]
#[inline(always)]
pub const fn wdt_sr(&self) -> &WdtSr {
&self.wdt_sr
}
#[doc = "0x18 - WatchDog Write Protect Register"]
#[inline(always)]
pub const fn wdt_wp(&self) -> &WdtWp {
&self.wdt_wp
}
#[doc = "0x1c - WatchDog Flag Register"]
#[inline(always)]
pub const fn wdt_fg(&self) -> &WdtFg {
&self.wdt_fg
}
}
#[doc = "WDT_CVR0 (rw) register accessor: WatchDog Counter Value 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cvr0`]
module"]
#[doc(alias = "WDT_CVR0")]
pub type WdtCvr0 = crate::Reg<wdt_cvr0::WdtCvr0Spec>;
#[doc = "WatchDog Counter Value 0"]
pub mod wdt_cvr0 {
#[doc = "Register `WDT_CVR0` reader"]
pub type R = crate::R<WdtCvr0Spec>;
#[doc = "Register `WDT_CVR0` writer"]
pub type W = crate::W<WdtCvr0Spec>;
#[doc = "Field `COUNT_VALUE_0` reader - Count Value for 1st TimeOut"]
pub type CountValue0R = crate::FieldReader<u32>;
#[doc = "Field `COUNT_VALUE_0` writer - Count Value for 1st TimeOut"]
pub type CountValue0W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Count Value for 1st TimeOut"]
#[inline(always)]
pub fn count_value_0(&self) -> CountValue0R {
CountValue0R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Count Value for 1st TimeOut"]
#[inline(always)]
#[must_use]
pub fn count_value_0(&mut self) -> CountValue0W<WdtCvr0Spec> {
CountValue0W::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCvr0Spec> {
RsvdW::new(self, 24)
}
}
#[doc = "WatchDog Counter Value 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCvr0Spec;
impl crate::RegisterSpec for WdtCvr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cvr0::R`](R) reader structure"]
impl crate::Readable for WdtCvr0Spec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cvr0::W`](W) writer structure"]
impl crate::Writable for WdtCvr0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CVR0 to value 0"]
impl crate::Resettable for WdtCvr0Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CVR1 (rw) register accessor: WatchDog Counter Value 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cvr1`]
module"]
#[doc(alias = "WDT_CVR1")]
pub type WdtCvr1 = crate::Reg<wdt_cvr1::WdtCvr1Spec>;
#[doc = "WatchDog Counter Value 1"]
pub mod wdt_cvr1 {
#[doc = "Register `WDT_CVR1` reader"]
pub type R = crate::R<WdtCvr1Spec>;
#[doc = "Register `WDT_CVR1` writer"]
pub type W = crate::W<WdtCvr1Spec>;
#[doc = "Field `COUNT_VALUE_1` reader - Count Value for 2nd TimeOut"]
pub type CountValue1R = crate::FieldReader<u32>;
#[doc = "Field `COUNT_VALUE_1` writer - Count Value for 2nd TimeOut"]
pub type CountValue1W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Count Value for 2nd TimeOut"]
#[inline(always)]
pub fn count_value_1(&self) -> CountValue1R {
CountValue1R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Count Value for 2nd TimeOut"]
#[inline(always)]
#[must_use]
pub fn count_value_1(&mut self) -> CountValue1W<WdtCvr1Spec> {
CountValue1W::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCvr1Spec> {
RsvdW::new(self, 24)
}
}
#[doc = "WatchDog Counter Value 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cvr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cvr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCvr1Spec;
impl crate::RegisterSpec for WdtCvr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cvr1::R`](R) reader structure"]
impl crate::Readable for WdtCvr1Spec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cvr1::W`](W) writer structure"]
impl crate::Writable for WdtCvr1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CVR1 to value 0"]
impl crate::Resettable for WdtCvr1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CR (rw) register accessor: WatchDog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cr`]
module"]
#[doc(alias = "WDT_CR")]
pub type WdtCr = crate::Reg<wdt_cr::WdtCrSpec>;
#[doc = "WatchDog Control Register"]
pub mod wdt_cr {
#[doc = "Register `WDT_CR` reader"]
pub type R = crate::R<WdtCrSpec>;
#[doc = "Register `WDT_CR` writer"]
pub type W = crate::W<WdtCrSpec>;
#[doc = "Field `RESET_LENGTH` reader - reset pulse length in number of wdt clock cycles"]
pub type ResetLengthR = crate::FieldReader;
#[doc = "Field `RESET_LENGTH` writer - reset pulse length in number of wdt clock cycles"]
pub type ResetLengthW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RESPONSE_MODE` reader - 0:reset only, 1:interrupt and reset"]
pub type ResponseModeR = crate::BitReader;
#[doc = "Field `RESPONSE_MODE` writer - 0:reset only, 1:interrupt and reset"]
pub type ResponseModeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
impl R {
#[doc = "Bits 0:2 - reset pulse length in number of wdt clock cycles"]
#[inline(always)]
pub fn reset_length(&self) -> ResetLengthR {
ResetLengthR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 0:reset only, 1:interrupt and reset"]
#[inline(always)]
pub fn response_mode(&self) -> ResponseModeR {
ResponseModeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 5) & 0x07ff_ffff)
}
}
impl W {
#[doc = "Bits 0:2 - reset pulse length in number of wdt clock cycles"]
#[inline(always)]
#[must_use]
pub fn reset_length(&mut self) -> ResetLengthW<WdtCrSpec> {
ResetLengthW::new(self, 0)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<WdtCrSpec> {
Rsvd2W::new(self, 3)
}
#[doc = "Bit 4 - 0:reset only, 1:interrupt and reset"]
#[inline(always)]
#[must_use]
pub fn response_mode(&mut self) -> ResponseModeW<WdtCrSpec> {
ResponseModeW::new(self, 4)
}
#[doc = "Bits 5:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCrSpec> {
RsvdW::new(self, 5)
}
}
#[doc = "WatchDog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCrSpec;
impl crate::RegisterSpec for WdtCrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_cr::R`](R) reader structure"]
impl crate::Readable for WdtCrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_cr::W`](W) writer structure"]
impl crate::Writable for WdtCrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CR to value 0"]
impl crate::Resettable for WdtCrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_CCR (rw) register accessor: WatchDog Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ccr`]
module"]
#[doc(alias = "WDT_CCR")]
pub type WdtCcr = crate::Reg<wdt_ccr::WdtCcrSpec>;
#[doc = "WatchDog Counter Control Register"]
pub mod wdt_ccr {
#[doc = "Register `WDT_CCR` reader"]
pub type R = crate::R<WdtCcrSpec>;
#[doc = "Register `WDT_CCR` writer"]
pub type W = crate::W<WdtCcrSpec>;
#[doc = "Field `COUNTER_CONTROL` reader - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
pub type CounterControlR = crate::FieldReader;
#[doc = "Field `COUNTER_CONTROL` writer - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
pub type CounterControlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
#[inline(always)]
pub fn counter_control(&self) -> CounterControlR {
CounterControlR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing"]
#[inline(always)]
#[must_use]
pub fn counter_control(&mut self) -> CounterControlW<WdtCcrSpec> {
CounterControlW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtCcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "WatchDog Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtCcrSpec;
impl crate::RegisterSpec for WdtCcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_ccr::R`](R) reader structure"]
impl crate::Readable for WdtCcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_ccr::W`](W) writer structure"]
impl crate::Writable for WdtCcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_CCR to value 0"]
impl crate::Resettable for WdtCcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_ICR (rw) register accessor: WatchDog Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_icr`]
module"]
#[doc(alias = "WDT_ICR")]
pub type WdtIcr = crate::Reg<wdt_icr::WdtIcrSpec>;
#[doc = "WatchDog Interrupt Clear Register"]
pub mod wdt_icr {
#[doc = "Register `WDT_ICR` reader"]
pub type R = crate::R<WdtIcrSpec>;
#[doc = "Register `WDT_ICR` writer"]
pub type W = crate::W<WdtIcrSpec>;
#[doc = "Field `INT_CLR` reader - SinglePulse /A pulse to clear interrupt"]
pub type IntClrR = crate::BitReader;
#[doc = "Field `INT_CLR` writer - SinglePulse /A pulse to clear interrupt"]
pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
impl R {
#[doc = "Bit 0 - SinglePulse /A pulse to clear interrupt"]
#[inline(always)]
pub fn int_clr(&self) -> IntClrR {
IntClrR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 1) & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SinglePulse /A pulse to clear interrupt"]
#[inline(always)]
#[must_use]
pub fn int_clr(&mut self) -> IntClrW<WdtIcrSpec> {
IntClrW::new(self, 0)
}
#[doc = "Bits 1:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtIcrSpec> {
RsvdW::new(self, 1)
}
}
#[doc = "WatchDog Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtIcrSpec;
impl crate::RegisterSpec for WdtIcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_icr::R`](R) reader structure"]
impl crate::Readable for WdtIcrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_icr::W`](W) writer structure"]
impl crate::Writable for WdtIcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_ICR to value 0"]
impl crate::Resettable for WdtIcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_SR (rw) register accessor: WatchDog Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_sr`]
module"]
#[doc(alias = "WDT_SR")]
pub type WdtSr = crate::Reg<wdt_sr::WdtSrSpec>;
#[doc = "WatchDog Status Register"]
pub mod wdt_sr {
#[doc = "Register `WDT_SR` reader"]
pub type R = crate::R<WdtSrSpec>;
#[doc = "Register `WDT_SR` writer"]
pub type W = crate::W<WdtSrSpec>;
#[doc = "Field `INT_ASSERT` reader - Interrupt assert when 1"]
pub type IntAssertR = crate::BitReader;
#[doc = "Field `INT_ASSERT` writer - Interrupt assert when 1"]
pub type IntAssertW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WDT_ACTIVE` reader - Watchdog runs when 1, else 0"]
pub type WdtActiveR = crate::BitReader;
#[doc = "Field `WDT_ACTIVE` writer - Watchdog runs when 1, else 0"]
pub type WdtActiveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - Interrupt assert when 1"]
#[inline(always)]
pub fn int_assert(&self) -> IntAssertR {
IntAssertR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Watchdog runs when 1, else 0"]
#[inline(always)]
pub fn wdt_active(&self) -> WdtActiveR {
WdtActiveR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Interrupt assert when 1"]
#[inline(always)]
#[must_use]
pub fn int_assert(&mut self) -> IntAssertW<WdtSrSpec> {
IntAssertW::new(self, 0)
}
#[doc = "Bit 1 - Watchdog runs when 1, else 0"]
#[inline(always)]
#[must_use]
pub fn wdt_active(&mut self) -> WdtActiveW<WdtSrSpec> {
WdtActiveW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtSrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "WatchDog Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtSrSpec;
impl crate::RegisterSpec for WdtSrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_sr::R`](R) reader structure"]
impl crate::Readable for WdtSrSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_sr::W`](W) writer structure"]
impl crate::Writable for WdtSrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_SR to value 0"]
impl crate::Resettable for WdtSrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_WP (rw) register accessor: WatchDog Write Protect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_wp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_wp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_wp`]
module"]
#[doc(alias = "WDT_WP")]
pub type WdtWp = crate::Reg<wdt_wp::WdtWpSpec>;
#[doc = "WatchDog Write Protect Register"]
pub mod wdt_wp {
#[doc = "Register `WDT_WP` reader"]
pub type R = crate::R<WdtWpSpec>;
#[doc = "Register `WDT_WP` writer"]
pub type W = crate::W<WdtWpSpec>;
#[doc = "Field `WRPT` reader - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
pub type WrptR = crate::FieldReader<u32>;
#[doc = "Field `WRPT` writer - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
pub type WrptW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
#[doc = "Field `WRPT_ST` reader - 1 indicates write protect is active"]
pub type WrptStR = crate::BitReader;
#[doc = "Field `WRPT_ST` writer - 1 indicates write protect is active"]
pub type WrptStW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:30 - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
#[inline(always)]
pub fn wrpt(&self) -> WrptR {
WrptR::new(self.bits & 0x7fff_ffff)
}
#[doc = "Bit 31 - 1 indicates write protect is active"]
#[inline(always)]
pub fn wrpt_st(&self) -> WrptStR {
WrptStR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:30 - write 0x58ab99fc generate write_protect, write 0x51ff8621 to release"]
#[inline(always)]
#[must_use]
pub fn wrpt(&mut self) -> WrptW<WdtWpSpec> {
WrptW::new(self, 0)
}
#[doc = "Bit 31 - 1 indicates write protect is active"]
#[inline(always)]
#[must_use]
pub fn wrpt_st(&mut self) -> WrptStW<WdtWpSpec> {
WrptStW::new(self, 31)
}
}
#[doc = "WatchDog Write Protect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_wp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_wp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtWpSpec;
impl crate::RegisterSpec for WdtWpSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_wp::R`](R) reader structure"]
impl crate::Readable for WdtWpSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_wp::W`](W) writer structure"]
impl crate::Writable for WdtWpSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_WP to value 0"]
impl crate::Resettable for WdtWpSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "WDT_FG (rw) register accessor: WatchDog Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_fg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_fg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_fg`]
module"]
#[doc(alias = "WDT_FG")]
pub type WdtFg = crate::Reg<wdt_fg::WdtFgSpec>;
#[doc = "WatchDog Flag Register"]
pub mod wdt_fg {
#[doc = "Register `WDT_FG` reader"]
pub type R = crate::R<WdtFgSpec>;
#[doc = "Register `WDT_FG` writer"]
pub type W = crate::W<WdtFgSpec>;
#[doc = "Field `RST_FG_CLR` reader - SinglePulse/A pulse to clear reset flag"]
pub type RstFgClrR = crate::BitReader;
#[doc = "Field `RST_FG_CLR` writer - SinglePulse/A pulse to clear reset flag"]
pub type RstFgClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RST_FG` reader - 1 indicates wdt has already reset system"]
pub type RstFgR = crate::BitReader;
#[doc = "Field `RST_FG` writer - 1 indicates wdt has already reset system"]
pub type RstFgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYNC_FG_CLR` reader - SinglePulse/A pulse to clear sync flag"]
pub type SyncFgClrR = crate::BitReader;
#[doc = "Field `SYNC_FG_CLR` writer - SinglePulse/A pulse to clear sync flag"]
pub type SyncFgClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYNC_FG` reader - 1 indicates one transition from system clk to wdt clk has complicated"]
pub type SyncFgR = crate::BitReader;
#[doc = "Field `SYNC_FG` writer - 1 indicates one transition from system clk to wdt clk has complicated"]
pub type SyncFgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - SinglePulse/A pulse to clear reset flag"]
#[inline(always)]
pub fn rst_fg_clr(&self) -> RstFgClrR {
RstFgClrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1 indicates wdt has already reset system"]
#[inline(always)]
pub fn rst_fg(&self) -> RstFgR {
RstFgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SinglePulse/A pulse to clear sync flag"]
#[inline(always)]
pub fn sync_fg_clr(&self) -> SyncFgClrR {
SyncFgClrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 1 indicates one transition from system clk to wdt clk has complicated"]
#[inline(always)]
pub fn sync_fg(&self) -> SyncFgR {
SyncFgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - SinglePulse/A pulse to clear reset flag"]
#[inline(always)]
#[must_use]
pub fn rst_fg_clr(&mut self) -> RstFgClrW<WdtFgSpec> {
RstFgClrW::new(self, 0)
}
#[doc = "Bit 1 - 1 indicates wdt has already reset system"]
#[inline(always)]
#[must_use]
pub fn rst_fg(&mut self) -> RstFgW<WdtFgSpec> {
RstFgW::new(self, 1)
}
#[doc = "Bit 2 - SinglePulse/A pulse to clear sync flag"]
#[inline(always)]
#[must_use]
pub fn sync_fg_clr(&mut self) -> SyncFgClrW<WdtFgSpec> {
SyncFgClrW::new(self, 2)
}
#[doc = "Bit 3 - 1 indicates one transition from system clk to wdt clk has complicated"]
#[inline(always)]
#[must_use]
pub fn sync_fg(&mut self) -> SyncFgW<WdtFgSpec> {
SyncFgW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<WdtFgSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "WatchDog Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_fg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_fg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtFgSpec;
impl crate::RegisterSpec for WdtFgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdt_fg::R`](R) reader structure"]
impl crate::Readable for WdtFgSpec {}
#[doc = "`write(|w| ..)` method takes [`wdt_fg::W`](W) writer structure"]
impl crate::Writable for WdtFgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDT_FG to value 0"]
impl crate::Resettable for WdtFgSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "LPTIM3"]
pub struct Lptim3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Lptim3 {}
impl Lptim3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const lptim3::RegisterBlock = 0x4004_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const lptim3::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Lptim3 {
type Target = lptim3::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Lptim3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Lptim3").finish()
}
}
#[doc = "LPTIM3"]
pub mod lptim3 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
isr: Isr,
icr: Icr,
ier: Ier,
cfgr: Cfgr,
cr: Cr,
cmp: Cmp,
arr: Arr,
cnt: Cnt,
rcr: Rcr,
}
impl RegisterBlock {
#[doc = "0x00 - LPTIM interrupt and status register"]
#[inline(always)]
pub const fn isr(&self) -> &Isr {
&self.isr
}
#[doc = "0x04 - LPTIM interrupt and status clear register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x08 - LPTIM interrupt and wakeup enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x0c - LPTIM configuration register"]
#[inline(always)]
pub const fn cfgr(&self) -> &Cfgr {
&self.cfgr
}
#[doc = "0x10 - LPTIM control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x14 - LPTIM compare register"]
#[inline(always)]
pub const fn cmp(&self) -> &Cmp {
&self.cmp
}
#[doc = "0x18 - LPTIM autoreload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
#[doc = "0x1c - LPTIM counter register"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x20 - LPTIM repetition register"]
#[inline(always)]
pub const fn rcr(&self) -> &Rcr {
&self.rcr
}
}
#[doc = "ISR (rw) register accessor: LPTIM interrupt and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`]
module"]
#[doc(alias = "ISR")]
pub type Isr = crate::Reg<isr::IsrSpec>;
#[doc = "LPTIM interrupt and status register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub type R = crate::R<IsrSpec>;
#[doc = "Register `ISR` writer"]
pub type W = crate::W<IsrSpec>;
#[doc = "Field `UE` reader - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OF` reader - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
pub type OfR = crate::BitReader;
#[doc = "Field `OF` writer - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC` reader - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
pub type OcR = crate::BitReader;
#[doc = "Field `OC` writer - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
pub type OcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ET` reader - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
pub type EtR = crate::BitReader;
#[doc = "Field `ET` writer - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
pub type EtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `UEWKUP` reader - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type UewkupR = crate::BitReader;
#[doc = "Field `UEWKUP` writer - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type UewkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFWKUP` reader - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OfwkupR = crate::BitReader;
#[doc = "Field `OFWKUP` writer - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OfwkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCWKUP` reader - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OcwkupR = crate::BitReader;
#[doc = "Field `OCWKUP` writer - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
pub type OcwkupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0 - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn of(&self) -> OfR {
OfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn oc(&self) -> OcR {
OcR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn et(&self) -> EtR {
EtR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn uewkup(&self) -> UewkupR {
UewkupR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ofwkup(&self) -> OfwkupR {
OfwkupR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
pub fn ocwkup(&self) -> OcwkupR {
OcwkupR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0 - LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ue(&mut self) -> UeW<IsrSpec> {
UeW::new(self, 0)
}
#[doc = "Bit 1 - Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn of(&mut self) -> OfW<IsrSpec> {
OfW::new(self, 1)
}
#[doc = "Bit 2 - Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn oc(&mut self) -> OcW<IsrSpec> {
OcW::new(self, 2)
}
#[doc = "Bit 3 - External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn et(&mut self) -> EtW<IsrSpec> {
EtW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IsrSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn uewkup(&mut self) -> UewkupW<IsrSpec> {
UewkupW::new(self, 8)
}
#[doc = "Bit 9 - Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ofwkup(&mut self) -> OfwkupW<IsrSpec> {
OfwkupW::new(self, 9)
}
#[doc = "Bit 10 - Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register."]
#[inline(always)]
#[must_use]
pub fn ocwkup(&mut self) -> OcwkupW<IsrSpec> {
OcwkupW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IsrSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "LPTIM interrupt and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsrSpec;
impl crate::RegisterSpec for IsrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`isr::R`](R) reader structure"]
impl crate::Readable for IsrSpec {}
#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"]
impl crate::Writable for IsrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for IsrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ICR (rw) register accessor: LPTIM interrupt and status clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`]
module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "LPTIM interrupt and status clear register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `UECLR` reader - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
pub type UeclrR = crate::BitReader;
#[doc = "Field `UECLR` writer - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
pub type UeclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFCLR` reader - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
pub type OfclrR = crate::BitReader;
#[doc = "Field `OFCLR` writer - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
pub type OfclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCCLR` reader - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
pub type OcclrR = crate::BitReader;
#[doc = "Field `OCCLR` writer - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
pub type OcclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETCLR` reader - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
pub type EtclrR = crate::BitReader;
#[doc = "Field `ETCLR` writer - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
pub type EtclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `WKUPCLR` reader - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
pub type WkupclrR = crate::BitReader;
#[doc = "Field `WKUPCLR` writer - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
pub type WkupclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
impl R {
#[doc = "Bit 0 - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
#[inline(always)]
pub fn ueclr(&self) -> UeclrR {
UeclrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn ofclr(&self) -> OfclrR {
OfclrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn occlr(&self) -> OcclrR {
OcclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
#[inline(always)]
pub fn etclr(&self) -> EtclrR {
EtclrR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
#[inline(always)]
pub fn wkupclr(&self) -> WkupclrR {
WkupclrR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 9) & 0x007f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register."]
#[inline(always)]
#[must_use]
pub fn ueclr(&mut self) -> UeclrW<IcrSpec> {
UeclrW::new(self, 0)
}
#[doc = "Bit 1 - Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn ofclr(&mut self) -> OfclrW<IcrSpec> {
OfclrW::new(self, 1)
}
#[doc = "Bit 2 - Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn occlr(&mut self) -> OcclrW<IcrSpec> {
OcclrW::new(self, 2)
}
#[doc = "Bit 3 - External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register"]
#[inline(always)]
#[must_use]
pub fn etclr(&mut self) -> EtclrW<IcrSpec> {
EtclrW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IcrSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register."]
#[inline(always)]
#[must_use]
pub fn wkupclr(&mut self) -> WkupclrW<IcrSpec> {
WkupclrW::new(self, 8)
}
#[doc = "Bits 9:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IcrSpec> {
RsvdW::new(self, 9)
}
}
#[doc = "LPTIM interrupt and status clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IER (rw) register accessor: LPTIM interrupt and wakeup enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "LPTIM interrupt and wakeup enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `UEIE` reader - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
pub type UeieR = crate::BitReader;
#[doc = "Field `UEIE` writer - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
pub type UeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCIE` reader - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
pub type OcieR = crate::BitReader;
#[doc = "Field `OCIE` writer - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
pub type OcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETIE` reader - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
pub type EtieR = crate::BitReader;
#[doc = "Field `ETIE` writer - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
pub type EtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::FieldReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `UEWE` reader - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
pub type UeweR = crate::BitReader;
#[doc = "Field `UEWE` writer - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
pub type UeweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFWE` reader - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
pub type OfweR = crate::BitReader;
#[doc = "Field `OFWE` writer - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
pub type OfweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCWE` reader - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
pub type OcweR = crate::BitReader;
#[doc = "Field `OCWE` writer - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
pub type OcweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
impl R {
#[doc = "Bit 0 - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
#[inline(always)]
pub fn ueie(&self) -> UeieR {
UeieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
#[inline(always)]
pub fn ocie(&self) -> OcieR {
OcieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
#[inline(always)]
pub fn etie(&self) -> EtieR {
EtieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
#[inline(always)]
pub fn uewe(&self) -> UeweR {
UeweR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
#[inline(always)]
pub fn ofwe(&self) -> OfweR {
OfweR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
#[inline(always)]
pub fn ocwe(&self) -> OcweR {
OcweR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 11:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 11) & 0x001f_ffff)
}
}
impl W {
#[doc = "Bit 0 - Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ueie(&mut self) -> UeieW<IerSpec> {
UeieW::new(self, 0)
}
#[doc = "Bit 1 - Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ofie(&mut self) -> OfieW<IerSpec> {
OfieW::new(self, 1)
}
#[doc = "Bit 2 - Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn ocie(&mut self) -> OcieW<IerSpec> {
OcieW::new(self, 2)
}
#[doc = "Bit 3 - External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled"]
#[inline(always)]
#[must_use]
pub fn etie(&mut self) -> EtieW<IerSpec> {
EtieW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<IerSpec> {
Rsvd2W::new(self, 4)
}
#[doc = "Bit 8 - Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn uewe(&mut self) -> UeweW<IerSpec> {
UeweW::new(self, 8)
}
#[doc = "Bit 9 - Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn ofwe(&mut self) -> OfweW<IerSpec> {
OfweW::new(self, 9)
}
#[doc = "Bit 10 - Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled"]
#[inline(always)]
#[must_use]
pub fn ocwe(&mut self) -> OcweW<IerSpec> {
OcweW::new(self, 10)
}
#[doc = "Bits 11:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<IerSpec> {
RsvdW::new(self, 11)
}
}
#[doc = "LPTIM interrupt and wakeup enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CFGR (rw) register accessor: LPTIM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgr`]
module"]
#[doc(alias = "CFGR")]
pub type Cfgr = crate::Reg<cfgr::CfgrSpec>;
#[doc = "LPTIM configuration register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub type R = crate::R<CfgrSpec>;
#[doc = "Register `CFGR` writer"]
pub type W = crate::W<CfgrSpec>;
#[doc = "Field `CKSEL` reader - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
pub type CkselR = crate::BitReader;
#[doc = "Field `CKSEL` writer - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
pub type CkselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CKPOL` reader - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
pub type CkpolR = crate::FieldReader;
#[doc = "Field `CKPOL` writer - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
pub type CkpolW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CKFLT` reader - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
pub type CkfltR = crate::FieldReader;
#[doc = "Field `CKFLT` writer - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
pub type CkfltW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `INTCKSEL` reader - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
pub type IntckselR = crate::BitReader;
#[doc = "Field `INTCKSEL` writer - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
pub type IntckselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRGFLT` reader - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
pub type TrgfltR = crate::FieldReader;
#[doc = "Field `TRGFLT` writer - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
pub type TrgfltW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `EXTCKSEL` reader - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
pub type ExtckselR = crate::BitReader;
#[doc = "Field `EXTCKSEL` writer - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
pub type ExtckselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRESC` reader - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
pub type PrescR = crate::FieldReader;
#[doc = "Field `PRESC` writer - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
pub type PrescW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD4` reader - "]
pub type Rsvd4R = crate::BitReader;
#[doc = "Field `RSVD4` writer - "]
pub type Rsvd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRIGSEL` reader - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
pub type TrigselR = crate::FieldReader;
#[doc = "Field `TRIGSEL` writer - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
pub type TrigselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `RSVD3` reader - "]
pub type Rsvd3R = crate::BitReader;
#[doc = "Field `RSVD3` writer - "]
pub type Rsvd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRIGEN` reader - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
pub type TrigenR = crate::FieldReader;
#[doc = "Field `TRIGEN` writer - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
pub type TrigenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `TIMOUT` reader - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
pub type TimoutR = crate::BitReader;
#[doc = "Field `TIMOUT` writer - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
pub type TimoutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WAVE` reader - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
pub type WaveR = crate::BitReader;
#[doc = "Field `WAVE` writer - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
pub type WaveW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WAVPOL` reader - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
pub type WavpolR = crate::BitReader;
#[doc = "Field `WAVPOL` writer - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
pub type WavpolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD2` reader - "]
pub type Rsvd2R = crate::BitReader;
#[doc = "Field `RSVD2` writer - "]
pub type Rsvd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COUNTMODE` reader - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
pub type CountmodeR = crate::BitReader;
#[doc = "Field `COUNTMODE` writer - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
pub type CountmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bit 0 - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
#[inline(always)]
pub fn cksel(&self) -> CkselR {
CkselR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
#[inline(always)]
pub fn ckpol(&self) -> CkpolR {
CkpolR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
#[inline(always)]
pub fn ckflt(&self) -> CkfltR {
CkfltR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
#[inline(always)]
pub fn intcksel(&self) -> IntckselR {
IntckselR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
#[inline(always)]
pub fn trgflt(&self) -> TrgfltR {
TrgfltR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8 - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
#[inline(always)]
pub fn extcksel(&self) -> ExtckselR {
ExtckselR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:11 - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
#[inline(always)]
pub fn presc(&self) -> PrescR {
PrescR::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn rsvd4(&self) -> Rsvd4R {
Rsvd4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 13:15 - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
#[inline(always)]
pub fn trigsel(&self) -> TrigselR {
TrigselR::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rsvd3(&self) -> Rsvd3R {
Rsvd3R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18 - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
#[inline(always)]
pub fn trigen(&self) -> TrigenR {
TrigenR::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bit 19 - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
#[inline(always)]
pub fn timout(&self) -> TimoutR {
TimoutR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
#[inline(always)]
pub fn wave(&self) -> WaveR {
WaveR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
pub fn wavpol(&self) -> WavpolR {
WavpolR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn rsvd2(&self) -> Rsvd2R {
Rsvd2R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
#[inline(always)]
pub fn countmode(&self) -> CountmodeR {
CountmodeR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0 - Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL"]
#[inline(always)]
#[must_use]
pub fn cksel(&mut self) -> CkselW<CfgrSpec> {
CkselW::new(self, 0)
}
#[doc = "Bits 1:2 - Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed"]
#[inline(always)]
#[must_use]
pub fn ckpol(&mut self) -> CkpolW<CfgrSpec> {
CkpolW::new(self, 1)
}
#[doc = "Bits 3:4 - Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition."]
#[inline(always)]
#[must_use]
pub fn ckflt(&mut self) -> CkfltW<CfgrSpec> {
CkfltW::new(self, 3)
}
#[doc = "Bit 5 - Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2"]
#[inline(always)]
#[must_use]
pub fn intcksel(&mut self) -> IntckselW<CfgrSpec> {
IntckselW::new(self, 5)
}
#[doc = "Bits 6:7 - Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger."]
#[inline(always)]
#[must_use]
pub fn trgflt(&mut self) -> TrgfltW<CfgrSpec> {
TrgfltW::new(self, 6)
}
#[doc = "Bit 8 - External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated)"]
#[inline(always)]
#[must_use]
pub fn extcksel(&mut self) -> ExtckselW<CfgrSpec> {
ExtckselW::new(self, 8)
}
#[doc = "Bits 9:11 - Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128"]
#[inline(always)]
#[must_use]
pub fn presc(&mut self) -> PrescW<CfgrSpec> {
PrescW::new(self, 9)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn rsvd4(&mut self) -> Rsvd4W<CfgrSpec> {
Rsvd4W::new(self, 12)
}
#[doc = "Bits 13:15 - Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7"]
#[inline(always)]
#[must_use]
pub fn trigsel(&mut self) -> TrigselW<CfgrSpec> {
TrigselW::new(self, 13)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rsvd3(&mut self) -> Rsvd3W<CfgrSpec> {
Rsvd3W::new(self, 16)
}
#[doc = "Bits 17:18 - Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges"]
#[inline(always)]
#[must_use]
pub fn trigen(&mut self) -> TrigenW<CfgrSpec> {
TrigenW::new(self, 17)
}
#[doc = "Bit 19 - Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter"]
#[inline(always)]
#[must_use]
pub fn timout(&mut self) -> TimoutW<CfgrSpec> {
TimoutW::new(self, 19)
}
#[doc = "Bit 20 - Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode"]
#[inline(always)]
#[must_use]
pub fn wave(&mut self) -> WaveW<CfgrSpec> {
WaveW::new(self, 20)
}
#[doc = "Bit 21 - Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"]
#[inline(always)]
#[must_use]
pub fn wavpol(&mut self) -> WavpolW<CfgrSpec> {
WavpolW::new(self, 21)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn rsvd2(&mut self) -> Rsvd2W<CfgrSpec> {
Rsvd2W::new(self, 22)
}
#[doc = "Bit 23 - counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock"]
#[inline(always)]
#[must_use]
pub fn countmode(&mut self) -> CountmodeW<CfgrSpec> {
CountmodeW::new(self, 23)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CfgrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CfgrSpec;
impl crate::RegisterSpec for CfgrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cfgr::R`](R) reader structure"]
impl crate::Readable for CfgrSpec {}
#[doc = "`write(|w| ..)` method takes [`cfgr::W`](W) writer structure"]
impl crate::Writable for CfgrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CFGR to value 0"]
impl crate::Resettable for CfgrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR (rw) register accessor: LPTIM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "LPTIM control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `ENABLE` reader - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
pub type EnableR = crate::BitReader;
#[doc = "Field `ENABLE` writer - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SNGSTRT` reader - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
pub type SngstrtR = crate::BitReader;
#[doc = "Field `SNGSTRT` writer - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
pub type SngstrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CNTSTRT` reader - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
pub type CntstrtR = crate::BitReader;
#[doc = "Field `CNTSTRT` writer - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
pub type CntstrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COUNTRST` reader - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
pub type CountrstR = crate::BitReader;
#[doc = "Field `COUNTRST` writer - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
pub type CountrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
impl R {
#[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
#[inline(always)]
pub fn enable(&self) -> EnableR {
EnableR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
#[inline(always)]
pub fn sngstrt(&self) -> SngstrtR {
SngstrtR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
#[inline(always)]
pub fn cntstrt(&self) -> CntstrtR {
CntstrtR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
#[inline(always)]
pub fn countrst(&self) -> CountrstR {
CountrstR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 4) & 0x0fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<CrSpec> {
EnableW::new(self, 0)
}
#[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode."]
#[inline(always)]
#[must_use]
pub fn sngstrt(&mut self) -> SngstrtW<CrSpec> {
SngstrtW::new(self, 1)
}
#[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
= 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode."]
#[inline(always)]
#[must_use]
pub fn cntstrt(&mut self) -> CntstrtW<CrSpec> {
CntstrtW::new(self, 2)
}
#[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1."]
#[inline(always)]
#[must_use]
pub fn countrst(&mut self) -> CountrstW<CrSpec> {
CountrstW::new(self, 3)
}
#[doc = "Bits 4:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 4)
}
}
#[doc = "LPTIM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CMP (rw) register accessor: LPTIM compare register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp`]
module"]
#[doc(alias = "CMP")]
pub type Cmp = crate::Reg<cmp::CmpSpec>;
#[doc = "LPTIM compare register"]
pub mod cmp {
#[doc = "Register `CMP` reader"]
pub type R = crate::R<CmpSpec>;
#[doc = "Register `CMP` writer"]
pub type W = crate::W<CmpSpec>;
#[doc = "Field `CMP` reader - Compare value CMP is the compare value used by the LPTIM."]
pub type CmpR = crate::FieldReader<u32>;
#[doc = "Field `CMP` writer - Compare value CMP is the compare value used by the LPTIM."]
pub type CmpW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Compare value CMP is the compare value used by the LPTIM."]
#[inline(always)]
pub fn cmp(&self) -> CmpR {
CmpR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Compare value CMP is the compare value used by the LPTIM."]
#[inline(always)]
#[must_use]
pub fn cmp(&mut self) -> CmpW<CmpSpec> {
CmpW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CmpSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM compare register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmpSpec;
impl crate::RegisterSpec for CmpSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cmp::R`](R) reader structure"]
impl crate::Readable for CmpSpec {}
#[doc = "`write(|w| ..)` method takes [`cmp::W`](W) writer structure"]
impl crate::Writable for CmpSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CMP to value 0"]
impl crate::Resettable for CmpSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ARR (rw) register accessor: LPTIM autoreload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`]
module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "LPTIM autoreload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP\\[15:0\\]
value."]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<ArrSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM autoreload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CNT (rw) register accessor: LPTIM counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "LPTIM counter register"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:23 - Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical."]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CntSpec> {
RsvdW::new(self, 24)
}
}
#[doc = "LPTIM counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RCR (rw) register accessor: LPTIM repetition register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcr`]
module"]
#[doc(alias = "RCR")]
pub type Rcr = crate::Reg<rcr::RcrSpec>;
#[doc = "LPTIM repetition register"]
pub mod rcr {
#[doc = "Register `RCR` reader"]
pub type R = crate::R<RcrSpec>;
#[doc = "Register `RCR` writer"]
pub type W = crate::W<RcrSpec>;
#[doc = "Field `REP` reader - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
pub type RepR = crate::FieldReader;
#[doc = "Field `REP` writer - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
pub type RepW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:7 - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
#[inline(always)]
pub fn rep(&self) -> RepR {
RepR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:7 - Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."]
#[inline(always)]
#[must_use]
pub fn rep(&mut self) -> RepW<RcrSpec> {
RepW::new(self, 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<RcrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "LPTIM repetition register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RcrSpec;
impl crate::RegisterSpec for RcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rcr::R`](R) reader structure"]
impl crate::Readable for RcrSpec {}
#[doc = "`write(|w| ..)` method takes [`rcr::W`](W) writer structure"]
impl crate::Writable for RcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RCR to value 0"]
impl crate::Resettable for RcrSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "CRC2"]
pub struct Crc2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for Crc2 {}
impl Crc2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const crc2::RegisterBlock = 0x4008_5000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const crc2::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for Crc2 {
type Target = crc2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for Crc2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crc2").finish()
}
}
#[doc = "CRC2"]
pub mod crc2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
dr: Dr,
sr: Sr,
cr: Cr,
rsvd1: Rsvd1,
init: Init,
pol: Pol,
}
impl RegisterBlock {
#[doc = "0x00 - Data register"]
#[inline(always)]
pub const fn dr(&self) -> &Dr {
&self.dr
}
#[doc = "0x04 - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x08 - Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x0c - "]
#[inline(always)]
pub const fn rsvd1(&self) -> &Rsvd1 {
&self.rsvd1
}
#[doc = "0x10 - Initial CRC value"]
#[inline(always)]
pub const fn init(&self) -> &Init {
&self.init
}
#[doc = "0x14 - CRC polynomial"]
#[inline(always)]
pub const fn pol(&self) -> &Pol {
&self.pol
}
}
#[doc = "DR (rw) register accessor: Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`]
module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "Data register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `DR` reader - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
pub type DrR = crate::FieldReader<u32>;
#[doc = "Field `DR` writer - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
pub type DrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
#[inline(always)]
pub fn dr(&self) -> DrR {
DrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value."]
#[inline(always)]
#[must_use]
pub fn dr(&mut self) -> DrW<DrSpec> {
DrW::new(self, 0)
}
}
#[doc = "Data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `DONE` reader - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
pub type DoneR = crate::BitReader;
#[doc = "Field `DONE` writer - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVERFLOW` reader - Overflow when new data arrive while last calculation not done yet"]
pub type OverflowR = crate::BitReader;
#[doc = "Field `OVERFLOW` writer - Overflow when new data arrive while last calculation not done yet"]
pub type OverflowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
impl R {
#[doc = "Bit 0 - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
#[inline(always)]
pub fn done(&self) -> DoneR {
DoneR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Overflow when new data arrive while last calculation not done yet"]
#[inline(always)]
pub fn overflow(&self) -> OverflowR {
OverflowR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bit 0 - Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished."]
#[inline(always)]
#[must_use]
pub fn done(&mut self) -> DoneW<SrSpec> {
DoneW::new(self, 0)
}
#[doc = "Bit 1 - Overflow when new data arrive while last calculation not done yet"]
#[inline(always)]
#[must_use]
pub fn overflow(&mut self) -> OverflowW<SrSpec> {
OverflowW::new(self, 1)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<SrSpec> {
RsvdW::new(self, 2)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "CR (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `RESET` reader - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
pub type ResetR = crate::BitReader;
#[doc = "Field `RESET` writer - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATASIZE` reader - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
pub type DatasizeR = crate::FieldReader;
#[doc = "Field `DATASIZE` writer - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
pub type DatasizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `POLYSIZE` reader - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
pub type PolysizeR = crate::FieldReader;
#[doc = "Field `POLYSIZE` writer - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
pub type PolysizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `REV_IN` reader - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
pub type RevInR = crate::FieldReader;
#[doc = "Field `REV_IN` writer - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
pub type RevInW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `REV_OUT` reader - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
pub type RevOutR = crate::BitReader;
#[doc = "Field `REV_OUT` writer - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
pub type RevOutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSVD` reader - "]
pub type RsvdR = crate::FieldReader<u32>;
#[doc = "Field `RSVD` writer - "]
pub type RsvdW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bit 0 - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
#[inline(always)]
pub fn reset(&self) -> ResetR {
ResetR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
#[inline(always)]
pub fn datasize(&self) -> DatasizeR {
DatasizeR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:4 - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
#[inline(always)]
pub fn polysize(&self) -> PolysizeR {
PolysizeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bits 5:6 - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
#[inline(always)]
pub fn rev_in(&self) -> RevInR {
RevInR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
#[inline(always)]
pub fn rev_out(&self) -> RevOutR {
RevOutR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:31"]
#[inline(always)]
pub fn rsvd(&self) -> RsvdR {
RsvdR::new((self.bits >> 8) & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bit 0 - This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware"]
#[inline(always)]
#[must_use]
pub fn reset(&mut self) -> ResetW<CrSpec> {
ResetW::new(self, 0)
}
#[doc = "Bits 1:2 - Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit"]
#[inline(always)]
#[must_use]
pub fn datasize(&mut self) -> DatasizeW<CrSpec> {
DatasizeW::new(self, 1)
}
#[doc = "Bits 3:4 - Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial"]
#[inline(always)]
#[must_use]
pub fn polysize(&mut self) -> PolysizeW<CrSpec> {
PolysizeW::new(self, 3)
}
#[doc = "Bits 5:6 - Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word"]
#[inline(always)]
#[must_use]
pub fn rev_in(&mut self) -> RevInW<CrSpec> {
RevInW::new(self, 5)
}
#[doc = "Bit 7 - Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format"]
#[inline(always)]
#[must_use]
pub fn rev_out(&mut self) -> RevOutW<CrSpec> {
RevOutW::new(self, 7)
}
#[doc = "Bits 8:31"]
#[inline(always)]
#[must_use]
pub fn rsvd(&mut self) -> RsvdW<CrSpec> {
RsvdW::new(self, 8)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "RSVD1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsvd1`]
module"]
#[doc(alias = "RSVD1")]
pub type Rsvd1 = crate::Reg<rsvd1::Rsvd1Spec>;
#[doc = ""]
pub mod rsvd1 {
#[doc = "Register `RSVD1` reader"]
pub type R = crate::R<Rsvd1Spec>;
#[doc = "Register `RSVD1` writer"]
pub type W = crate::W<Rsvd1Spec>;
impl W {}
#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsvd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsvd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rsvd1Spec;
impl crate::RegisterSpec for Rsvd1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsvd1::R`](R) reader structure"]
impl crate::Readable for Rsvd1Spec {}
#[doc = "`write(|w| ..)` method takes [`rsvd1::W`](W) writer structure"]
impl crate::Writable for Rsvd1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RSVD1 to value 0"]
impl crate::Resettable for Rsvd1Spec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INIT (rw) register accessor: Initial CRC value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`init::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`init::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@init`]
module"]
#[doc(alias = "INIT")]
pub type Init = crate::Reg<init::InitSpec>;
#[doc = "Initial CRC value"]
pub mod init {
#[doc = "Register `INIT` reader"]
pub type R = crate::R<InitSpec>;
#[doc = "Register `INIT` writer"]
pub type W = crate::W<InitSpec>;
#[doc = "Field `INIT` reader - Programmable initial CRC value"]
pub type InitR = crate::FieldReader<u32>;
#[doc = "Field `INIT` writer - Programmable initial CRC value"]
pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Programmable initial CRC value"]
#[inline(always)]
pub fn init(&self) -> InitR {
InitR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Programmable initial CRC value"]
#[inline(always)]
#[must_use]
pub fn init(&mut self) -> InitW<InitSpec> {
InitW::new(self, 0)
}
}
#[doc = "Initial CRC value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`init::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`init::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct InitSpec;
impl crate::RegisterSpec for InitSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`init::R`](R) reader structure"]
impl crate::Readable for InitSpec {}
#[doc = "`write(|w| ..)` method takes [`init::W`](W) writer structure"]
impl crate::Writable for InitSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INIT to value 0"]
impl crate::Resettable for InitSpec {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "POL (rw) register accessor: CRC polynomial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pol::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pol::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pol`]
module"]
#[doc(alias = "POL")]
pub type Pol = crate::Reg<pol::PolSpec>;
#[doc = "CRC polynomial"]
pub mod pol {
#[doc = "Register `POL` reader"]
pub type R = crate::R<PolSpec>;
#[doc = "Register `POL` writer"]
pub type W = crate::W<PolSpec>;
#[doc = "Field `POL` reader - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
pub type PolR = crate::FieldReader<u32>;
#[doc = "Field `POL` writer - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
pub type PolW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
#[inline(always)]
pub fn pol(&self) -> PolR {
PolR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value."]
#[inline(always)]
#[must_use]
pub fn pol(&mut self) -> PolW<PolSpec> {
PolW::new(self, 0)
}
}
#[doc = "CRC polynomial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pol::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PolSpec;
impl crate::RegisterSpec for PolSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pol::R`](R) reader structure"]
impl crate::Readable for PolSpec {}
#[doc = "`write(|w| ..)` method takes [`pol::W`](W) writer structure"]
impl crate::Writable for PolSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets POL to value 0"]
impl crate::Resettable for PolSpec {
const RESET_VALUE: u32 = 0;
}
}
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "HPSYS_RCC"]
pub hpsys_rcc: HpsysRcc,
#[doc = "ATIM1"]
pub atim1: Atim1,
#[doc = "I2S1"]
pub i2s1: I2s1,
#[doc = "HPSYS_CFG"]
pub hpsys_cfg: HpsysCfg,
#[doc = "MPI1"]
pub mpi1: Mpi1,
#[doc = "MPI2"]
pub mpi2: Mpi2,
#[doc = "CRC1"]
pub crc1: Crc1,
#[doc = "DMAC1"]
pub dmac1: Dmac1,
#[doc = "USART1"]
pub usart1: Usart1,
#[doc = "USART2"]
pub usart2: Usart2,
#[doc = "USART3"]
pub usart3: Usart3,
#[doc = "BTIM1"]
pub btim1: Btim1,
#[doc = "WDT1"]
pub wdt1: Wdt1,
#[doc = "SPI1"]
pub spi1: Spi1,
#[doc = "SPI2"]
pub spi2: Spi2,
#[doc = "PDM1"]
pub pdm1: Pdm1,
#[doc = "I2C1"]
pub i2c1: I2c1,
#[doc = "I2C2"]
pub i2c2: I2c2,
#[doc = "I2C3"]
pub i2c3: I2c3,
#[doc = "I2C4"]
pub i2c4: I2c4,
#[doc = "HPSYS_GPIO"]
pub hpsys_gpio: HpsysGpio,
#[doc = "BTIM2"]
pub btim2: Btim2,
#[doc = "HPSYS_AON"]
pub hpsys_aon: HpsysAon,
#[doc = "LPTIM1"]
pub lptim1: Lptim1,
#[doc = "LPTIM2"]
pub lptim2: Lptim2,
#[doc = "RTC"]
pub rtc: Rtc,
#[doc = "IWDT"]
pub iwdt: Iwdt,
#[doc = "DMAC2"]
pub dmac2: Dmac2,
#[doc = "USART4"]
pub usart4: Usart4,
#[doc = "USART5"]
pub usart5: Usart5,
#[doc = "BTIM3"]
pub btim3: Btim3,
#[doc = "BTIM4"]
pub btim4: Btim4,
#[doc = "WDT2"]
pub wdt2: Wdt2,
#[doc = "LPTIM3"]
pub lptim3: Lptim3,
#[doc = "CRC2"]
pub crc2: Crc2,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
hpsys_rcc: HpsysRcc {
_marker: PhantomData,
},
atim1: Atim1 {
_marker: PhantomData,
},
i2s1: I2s1 {
_marker: PhantomData,
},
hpsys_cfg: HpsysCfg {
_marker: PhantomData,
},
mpi1: Mpi1 {
_marker: PhantomData,
},
mpi2: Mpi2 {
_marker: PhantomData,
},
crc1: Crc1 {
_marker: PhantomData,
},
dmac1: Dmac1 {
_marker: PhantomData,
},
usart1: Usart1 {
_marker: PhantomData,
},
usart2: Usart2 {
_marker: PhantomData,
},
usart3: Usart3 {
_marker: PhantomData,
},
btim1: Btim1 {
_marker: PhantomData,
},
wdt1: Wdt1 {
_marker: PhantomData,
},
spi1: Spi1 {
_marker: PhantomData,
},
spi2: Spi2 {
_marker: PhantomData,
},
pdm1: Pdm1 {
_marker: PhantomData,
},
i2c1: I2c1 {
_marker: PhantomData,
},
i2c2: I2c2 {
_marker: PhantomData,
},
i2c3: I2c3 {
_marker: PhantomData,
},
i2c4: I2c4 {
_marker: PhantomData,
},
hpsys_gpio: HpsysGpio {
_marker: PhantomData,
},
btim2: Btim2 {
_marker: PhantomData,
},
hpsys_aon: HpsysAon {
_marker: PhantomData,
},
lptim1: Lptim1 {
_marker: PhantomData,
},
lptim2: Lptim2 {
_marker: PhantomData,
},
rtc: Rtc {
_marker: PhantomData,
},
iwdt: Iwdt {
_marker: PhantomData,
},
dmac2: Dmac2 {
_marker: PhantomData,
},
usart4: Usart4 {
_marker: PhantomData,
},
usart5: Usart5 {
_marker: PhantomData,
},
btim3: Btim3 {
_marker: PhantomData,
},
btim4: Btim4 {
_marker: PhantomData,
},
wdt2: Wdt2 {
_marker: PhantomData,
},
lptim3: Lptim3 {
_marker: PhantomData,
},
crc2: Crc2 {
_marker: PhantomData,
},
}
}
}