use core::sync::atomic::{self, Ordering};
use super::barrier;
#[inline(always)]
pub(crate) fn arch_set_my_processor_id(_: usize) {}
#[inline(always)]
pub(crate) fn arch_my_processor_id() -> usize {
unreachable!()
}
#[inline(always)]
pub(crate) fn arch_cpu_relax() {
unreachable!()
}
#[inline(always)]
pub(crate) fn arch_cpu_wfe() {
unreachable!()
}
#[inline(always)]
pub(crate) fn arch_smp_mb_acquire() {
barrier();
atomic::fence(Ordering::Acquire);
}
#[inline(always)]
pub(crate) fn arch_smp_mb_release() {
barrier();
atomic::fence(Ordering::Release);
}
#[inline(always)]
pub(crate) fn arch_smp_mb() {
barrier();
atomic::fence(Ordering::SeqCst);
}
#[inline(always)]
pub(crate) fn arch_isb() {
barrier();
}