sel4-sys 0.0.28

Rust interface to the seL4 kernel
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#
# Copyright 2014, General Dynamics C4 Systems
#
# This software may be distributed and modified according to the terms of
# the GNU General Public License version 2. Note that NO WARRANTY is provided.
# See "LICENSE_GPLv2.txt" for details.
#
# @TAG(GD_GPL)
#

config HAVE_ARCH_TIMER
    bool
    default y
    depends on ARM_CORTEX_A15

config ENABLE_A9_PREFETCHER
    bool "Enable Cortex-A9 prefetcher"
    default n
    depends on ARM_CORTEX_A9
    help
        Cortex-A9 has an L1 and L2 prefetcher. By default
        they are disabled. This config options allows
        them to be turned on. Enabling the prefetchers
        requires that the kernel be in secure mode. ARM
        documents indicate that as of r4p1 version of
        Cortex-A9 the bits used to enable the prefetchers
        no longer exist, it is not clear if this is just
        a document error or not.

config EXPORT_PMU_USER
    bool "PL0 access to PMU"
    default n
    depends on ARCH_ARM_V7A || ARCH_ARM_V8A
    help
        Grant user access to Performance Monitoring Unit.
        WARNING: While useful for evaluating performance,
        this option opens timing and covert channels.

config EXPORT_PCNT_USER
    bool "PL0 access to generic timer CNTPCT and CNTFRQ"
    default y
    depends on HAVE_ARCH_TIMER
    help
        Grant user access to physical counter and counter
        frequency registers of the generic timer.
        WARNING: selecting this option opens a timing
        channel

config EXPORT_VCNT_USER
    bool "PL0 access to generic timer CNTVCT and CNTFRQ"
    default y
    depends on HAVE_ARCH_TIMER
    help
        Grant user access to virtual counter and counter
        frequency registers of the generic timer.
        WARNING: selecting this option opens a timing
        channel

choice
    prompt "IPC Buffer location"
    default IPC_BUF_TPIDRURW if !ARCH_ARM_V6
    default IPC_BUF_GLOBALS_FRAME if ARCH_ARM_V6
    depends on ARCH_ARM
    help
        Controls how the location of the IPC buffer is
        provided to the user

    config IPC_BUF_GLOBALS_FRAME
        bool "Globals frame"
        depends on ARCH_AARCH32
        help
            Put the address of the IPC buffer in a dedicated
            frame that is read only at user level. This works
            on all ARM platforms
    config IPC_BUF_TPIDRURW
        bool "ThreadID register"
        depends on !ARCH_ARM_V6
        help
            Put the address of the IPC buffer in the user
            readable/writeable ThreadID register. When enabled
            this has the result of the kernel overwriting
            any value the user writes to this register.
endchoice

config SMMU_INTERRUPT_ENABLE
    bool "Enable SMMU interrupts"
    default y if DEBUG_BUILD
    default n if !DEBUG_BUILD
    depends on ARM_SMMU
    help
        SMMU interrupts currently only serve a debug purpose as
        they are not forwarded to user level. Enabling this will
        cause some fault types to print out a message in the kernel.
        WARNING: Printing fault information is slow and rapid faults
        can result in all time spent in the kernel printing fault
        messages