sdmmc_core/register/ext_csd/
wr_rel_param.rs

1use crate::lib_bitfield;
2use crate::result::Result;
3
4use super::{ExtCsd, ExtCsdIndex};
5
6mod en_rel_wr;
7mod en_rpmb_rel_wr;
8mod hs_ctrl_rel;
9
10pub use en_rel_wr::*;
11pub use en_rpmb_rel_wr::*;
12pub use hs_ctrl_rel::*;
13
14lib_bitfield! {
15    /// Represents the `WR_REL_PARAM` field of the [ExtCsd] register.
16    WriteReliabilityParameter: u8,
17    mask: 0b10101,
18    default: 0,
19    {
20        /// Indicates support for enhanced RPMB reliable write.
21        en_rpmb_rel_wr: EnhancedRpmbReliableWrite, 4;
22        /// Indicates support for enhanced reliable write.
23        en_rel_wr: EnhancedReliableWrite, 2;
24        /// Indicates support for host controlled data reliability.
25        hs_ctrl_rel: HostControlledDataReliability, 0;
26    }
27}
28
29impl WriteReliabilityParameter {
30    /// Converts an inner representation into a [WriteReliabilityParameter].
31    pub const fn from_inner(val: u8) -> Self {
32        Self(val & Self::MASK)
33    }
34}
35
36impl ExtCsd {
37    /// Gets the `WR_REL_PARAM` field of the [ExtCsd] register.
38    pub const fn wr_rel_param(&self) -> WriteReliabilityParameter {
39        WriteReliabilityParameter::from_inner(self.0[ExtCsdIndex::WrRelParam.into_inner()])
40    }
41
42    /// Sets the `WR_REL_PARAM` field of the [ExtCsd] register.
43    pub fn set_wr_rel_param(&mut self, val: WriteReliabilityParameter) {
44        self.0[ExtCsdIndex::WrRelParam.into_inner()] = val.into_inner();
45    }
46}
47
48#[cfg(test)]
49mod tests {
50    use super::*;
51
52    #[test]
53    fn test_wr_rel_param() {
54        let mut ext_csd = ExtCsd::new();
55
56        assert_eq!(ext_csd.wr_rel_param(), WriteReliabilityParameter::new());
57
58        (0..=u8::MAX)
59            .map(WriteReliabilityParameter::from_inner)
60            .for_each(|wr_rel_param| {
61                ext_csd.set_wr_rel_param(wr_rel_param);
62                assert_eq!(ext_csd.wr_rel_param(), wr_rel_param);
63            });
64    }
65}