sdmmc-core 0.5.0

SD/MMC core data structures and algorithms
Documentation
use crate::lib_enum;
use crate::result::{Error, Result};

lib_enum! {
    /// Represents the `MIN_PERF_*` field read-write access values.
    AccessPerformance: u8 {
        default: LowSpeed,
        error: Error,
        /// Represents devices below 2.4MB/s (SDR) or 4.8MB/s (DDR).
        LowSpeed = 0x00,
        /// Represents devices at 2.4MB/s (SDR) or 4.8MB/s (DDR).
        ClassA = 0x08,
        /// Represents devices at 3.0MB/s (SDR) or 6.0MB/s (DDR).
        ClassB = 0x0a,
        /// Represents devices at 4.5MB/s (SDR) or 9.0MB/s (DDR).
        ClassC = 0x0f,
        /// Represents devices at 6.0MB/s (SDR) or 12.0MB/s (DDR).
        ClassD = 0x14,
        /// Represents devices at 9.0MB/s (SDR) or 18.0MB/s (DDR).
        ClassE = 0x1e,
        /// Represents devices at 12.0MB/s (SDR) or 24.0MB/s (DDR).
        ClassF = 0x28,
        /// Represents devices at 15.0MB/s (SDR) or 30.0MB/s (DDR).
        ClassG = 0x32,
        /// Represents devices at 18.0MB/s (SDR) or 36.0MB/s (DDR).
        ClassH = 0x3c,
        /// Represents devices at 21.0MB/s (SDR) or 42.0MB/s (DDR).
        ClassJ = 0x46,
        /// Represents devices at 24.0MB/s (SDR) or 48.0MB/s (DDR).
        ClassK = 0x50,
        /// Represents devices at 30.0MB/s (SDR) or 60.0MB/s (DDR).
        ClassM = 0x64,
        /// Represents devices at 36.0MB/s (SDR) or 72.0MB/s (DDR).
        ClassO = 0x78,
        /// Represents devices at 42.0MB/s (SDR) or 84.0MB/s (DDR).
        ClassR = 0x8c,
        /// Represents devices at 48.0MB/s (SDR) or 96.0MB/s (DDR).
        ClassT = 0xa0,
    }
}

impl AccessPerformance {
    /// Attempts to convert an inner representation into a [AccessPerformance].
    pub const fn try_from_inner(val: u8) -> Result<Self> {
        Self::from_raw(val)
    }

    /// Converts a [AccessPerformance] into an inner representation.
    pub const fn into_inner(self) -> u8 {
        self.into_raw()
    }
}