sdmmc-core 0.5.0

SD/MMC core data structures and algorithms
Documentation 
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use crate::lib_bitfield;
use crate::register::ext_csd::{ExtCsd, ExtCsdIndex};

lib_bitfield! {
    /// Represents the `CMDQ_SUPPORT` field of the [ExtCsd] register.
    CommandQueueSupport: u8,
    mask: 0x1,
    default: 0,
    {
        /// Indicates whether the command queue is supported.
        cmdq_support: 0;
    }
}

impl ExtCsd {
    /// Gets the `CMDQ_SUPPORT` field of the [ExtCsd] register.
    pub const fn cmdq_support(&self) -> CommandQueueSupport {
        CommandQueueSupport::from_inner(self.0[ExtCsdIndex::CmdqSupport.into_inner()])
    }

    /// Sets the `CMDQ_SUPPORT` field of the [ExtCsd] register.
    pub(crate) fn set_cmdq_support(&mut self, val: CommandQueueSupport) {
        self.0[ExtCsdIndex::CmdqSupport.into_inner()] = val.into_inner();
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_cmdq_support() {
        let mut ext_csd = ExtCsd::new();

        assert_eq!(ext_csd.cmdq_support(), CommandQueueSupport::new());

        (0..u8::MAX)
            .map(CommandQueueSupport::from_inner)
            .for_each(|support| {
                ext_csd.set_cmdq_support(support);
                assert_eq!(ext_csd.cmdq_support(), support);
                assert_eq!(support.cmdq_support(), (support.into_inner() & 0x1) != 0);
            });
    }
}