scirs2-neural 0.2.0

Neural network building blocks module for SciRS2 (scirs2-neural) - Minimal Version
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

//! Recurrent layer implementations

pub mod bidirectional;
pub mod gru;
pub mod lstm;
pub mod rnn;

// Re-export main types
pub use bidirectional::Bidirectional;
pub use gru::GRU;
pub use lstm::LSTM;
pub use rnn::RNN;

// Type aliases for compatibility
use scirs2_core::ndarray::{Array, IxDyn};
use std::sync::{Arc, RwLock};

/// Type alias for LSTM state cache (hidden, cell)
pub type LstmStateCache<F> = Arc<RwLock<Option<(Array<F, IxDyn>, Array<F, IxDyn>)>>>;

/// Type alias for LSTM gate cache (input, forget, output, cell gates)
pub type LstmGateCache<F> = Arc<
    RwLock<
        Option<(
            Array<F, IxDyn>,
            Array<F, IxDyn>,
            Array<F, IxDyn>,
            Array<F, IxDyn>,
        )>,
    >,
>;

/// Type alias for GRU state cache
pub type GruStateCache<F> = Arc<RwLock<Option<Array<F, IxDyn>>>>;

/// Type alias for GRU gate cache (reset, update, new gates)
pub type GruGateCache<F> = Arc<RwLock<Option<(Array<F, IxDyn>, Array<F, IxDyn>, Array<F, IxDyn>)>>>;

/// Type alias for RNN state cache
pub type RnnStateCache<F> = Arc<RwLock<Option<Array<F, IxDyn>>>>;

/// Type alias for LSTM step output (new_h, new_c, (input_gate, forget_gate, cell_gate, output_gate))
pub type LstmStepOutput<F> = (
    Array<F, IxDyn>,
    Array<F, IxDyn>,
    (
        Array<F, IxDyn>,
        Array<F, IxDyn>,
        Array<F, IxDyn>,
        Array<F, IxDyn>,
    ),
);

/// Type alias for GRU forward output (new_h, (reset_gate, update_gate, new_gate))
pub type GruForwardOutput<F> = (
    Array<F, IxDyn>,
    (Array<F, IxDyn>, Array<F, IxDyn>, Array<F, IxDyn>),
);