© 1998–2026 Miroslav Šotek. All rights reserved. Contact: www.anulum.li | protoscience@anulum.li ORCID: https://orcid.org/0009-0009-3560-0851 License: GNU AFFERO GENERAL PUBLIC LICENSE v3 Commercial Licensing: Available
SC-NeuroCore
Stochastic computing and neuromorphic hardware co-design toolkit
Version: 3.15.32
SC-NeuroCore is a research-to-hardware software stack for designing spiking and stochastic neural systems, validating their numerical behaviour, and moving selected models toward FPGA, ASIC, and embedded neuromorphic deployment. It combines a Python public API, an optional Rust acceleration engine, SystemVerilog generation paths, benchmark evidence, and polyglot research mirrors for selected kernels.
It is useful when a team needs to answer practical questions such as:
- Can a stochastic bitstream representation approximate this neural computation within a bounded error budget?
- Which neuron, synapse, encoder, or network path is numerically appropriate for a target workload?
- Can a model be converted into auditable hardware artefacts rather than remaining only a Python simulation?
- Which evidence is available for speed, parity, synthesis, safety-case readiness, or cross-framework comparison?
- Which capabilities are stable package surfaces and which remain source-checkout research surfaces?
Who It Is For
| Audience | Primary value |
|---|---|
| Neuroscience and SNN researchers | Reproducible neuron and network experiments with explicit numerical guardrails. |
| Hardware and FPGA engineers | Bitstream arithmetic, fixed-point export, RTL generation, and synthesis evidence workflows. |
| ML and edge-computing teams | SNN training, ANN-to-SNN conversion, acceleration options, and deployment trade-off studies. |
| Safety, verification, and industrial teams | Evidence bags, fail-closed readiness checks, formal-verification collateral, and documentation boundaries. |
| Commercial evaluators | A mapped path from modelling to hardware-oriented evidence, with clear gaps before field deployment. |
What Makes It Distinct
- Stochastic computing first: bitstream encoders, probabilistic arithmetic, Sobol/LFSR sources, and bounded error reasoning are first-class components.
- Neuromorphic breadth with guardrails: the repository contains a wide neuron/model catalogue, but public docs separate stable package surfaces from opt-in research paths.
- Hardware-oriented output: selected workflows generate Verilog/SystemVerilog artefacts, synthesis reports, and hardware-readiness evidence instead of stopping at simulation.
- Evidence-indexed benchmarking: public benchmark claims are tied to committed artefacts under
benchmarks/results/or hardware reports underhdl/reports/. - Polyglot parity research: Julia, Go, Mojo, Rust, and Python counterparts exist for selected kernels to test implementation fidelity and performance trade-offs, while the default install remains Python-first.
Application Areas
SC-NeuroCore is positioned for neuromorphic R&D, stochastic accelerator design, edge inference studies, BCI and spike-codec prototyping, safety-case tooling, and hardware/software co-design. It is not a certified medical, automotive, aerospace, or rail product by itself. Domain profiles in the documentation state required evidence and missing evidence explicitly so commercial or regulated deployment work can start from an auditable gap list.
Current Evidence Boundary
| Surface | Current status |
|---|---|
| Public Python package | Version 3.15.32 package surface with base NumPy/SciPy dependency boundary. |
| Optional acceleration | Rust engine and optional heavy backends are opt-in; Python fallbacks remain available. |
| Hardware evidence | Committed synthesis and report artefacts exist for selected flows; power/energy claims require matching committed reports. |
| Benchmarks | Only committed JSON/CSV/report artefacts are public evidence. Local exploratory runs must not be promoted without raw artefacts. |
| Polyglot surfaces | Source-checkout research and parity surfaces, not default user install requirements. |
| Regulated deployment | Readiness tooling and evidence categories only; no certification or field approval claim. |
Version and Capability Snapshot
SC-NeuroCore Capability Inventory
| Surface | Current inventory |
|---|---|
| Package version | 3.15.32 |
| Public API exports | 44 |
| Python model source modules | 151 |
| Python model classes | 157 |
| Model documentation pages | 174 |
| Rust PyO3 model wrappers | 175 |
| Optional extras | 24 |
| Python test files | 762 |
| Public documentation pages | 543 |
| GitHub Actions workflows | 14 |
Evidence boundary: this snapshot is a static inventory. Performance, coverage, hardware, and scientific-fidelity claims require their own committed evidence artefacts.
Quick Start
For biological closed-loop BCI implementations (experimental), install the bioware optional dependencies:
=
=
Zenith Quickstart
Train biologically plausible rules using PyTorch surrogate autograd, then export the exact layer to hardware:
Bio-hybrid Closed-Loop with ArcaneZenith (Experimental)
The bioware module securely bridges biological real-world MEA setups into Stochastic Computing and Optogenetic laser outputs natively. It supports PCA/K-Means spike sorting, runtime health tracking, pharmacological wash simulations, and ArcaneZenithCognitiveCore bridged bindings.
# 1. Train entirely in standard DL execution architectures
=
# ... standard cross-entropy loss.backward() loop
# 2. Deploy natively to SC-NeuroCore hardware limits
=
See the full end-to-end integration demo in examples/zenith_hybrid_resnet.py.
# Add only the extras needed for the current workflow.
See Install Profiles for the full optional dependency matrix and research-only boundaries.
Rust Engine (39–202× faster)
The optional Rust engine provides SIMD-accelerated simulation, 174 neuron models via PyO3, and fused E-I network simulation. Pre-built wheels are available through repository release assets or source builds when present in the local environment.
When installed, SC-NeuroCore automatically uses the Rust engine for:
- NetworkRunner: 161-model fused Rayon-parallel simulation loop
- E-I network: single Rust call for connectivity + Poisson + Euler + spike detection
- Batch simulate: model dispatch loop in compiled Rust
- SIMD bitstream ops: 190 Gbit/s popcount (AVX-512)
The pure Python package works without the engine — NumPy fallbacks are used for all operations. Install or build the engine only when you need the performance advantage. See Install Profiles for the base install, optional extras, and source-build path.
pip install sc-neurocore publishes the Python suite under the public
sc-neurocore package name. The optional Rust engine remains part of the
repository / release-asset / source-build flow rather than a separate PyPI
runtime dependency. Source-only extended modules such as analysis, viz,
audio, dashboard, and swarm still require a source checkout.
Development Setup
If you are changing the Rust bridge locally, install bridge/ in the same
environment or run source-tree commands with PYTHONPATH=src:bridge.
Visual SNN Design Studio (Experimental)
Status: Development preview. The Studio is functional but under active development. API and UI may change between releases until the v4.0 stable API freeze.
A web-based IDE for designing, training, compiling, and deploying spiking neural networks — from ODE equations to FPGA bitstream in a single browser tab.
| Feature | What it does |
|---|---|
| 118 Model Browser | Browse all neuron models by category, simulate with parameter sliders |
| 18+ Analysis Views | Trace, phase portrait, ISI, f-I curve, bifurcation, heatmap, STA, frequency response, characterisation dashboard |
| Compiler Inspector | Build SC IR from equations, verify, emit SystemVerilog |
| Synthesis Dashboard | One-click Yosys synthesis to ice40/ECP5/Gowin/Xilinx, multi-target comparison, resource bars |
| Training Monitor | Live loss/accuracy curves via SSE, 6 surrogate gradients, per-layer spike rates |
| Network Canvas | Drag-and-drop populations and projections (React Flow), NIR export/import |
| Full Pipeline | Network → simulate → compile → synthesise in one click |
| Project Save/Load | Persistent workspaces as JSON, server-side storage |
No other SNN framework provides a visual design-to-hardware pipeline. snnTorch has Jupyter notebooks. Brian2 has a basic GUI. Neither goes from visual network design to FPGA resource estimation.
| Feature | SC-NeuroCore Studio | Brian2 GUI | snnTorch | Nengo GUI |
|---|---|---|---|---|
| Visual network design | Yes | Basic | No | Yes |
| ODE equation editor | Yes | No | No | No |
| Live training curves | Yes | No | TensorBoard | No |
| Verilog output viewer | Yes | No | No | No |
| FPGA synthesis | Yes | No | No | No |
| Co-simulation view | Yes | No | No | No |
Full documentation: Studio Guide
Docker
The Docker image ships with the full Rust engine (39–202× faster than Brian2):
# Build
# or: docker build -f deploy/Dockerfile -t sc-neurocore:latest .
# Build the offline HDL shipping profile with packaged baseline RTL primitives
# and the hash-locked HDL dependency set. Vivado is not required for this image.
# Run interactive Python shell
# or: docker run --rm -it sc-neurocore:latest
# Smoke test via docker compose
Pre-built images are published to GHCR on every release:
Architecture
Module Tiers
pip install sc-neurocore ships Core + Simulation + Domain bridges only.
Research and extended modules are available from source (pip install -e ".[dev]").
| Tier | Modules | Ships in wheel | Status |
|---|---|---|---|
| Core | neurons, synapses, layers, sources, utils, recorders, accel, compiler, hdl_gen, hardware, cli, exceptions | Yes | Production path; current CI coverage gate is 96%, with 100% retained as the target. |
| Simulation | hdc, solvers, transformers, learning, graphs, ensembles, export, pipeline, profiling, models, math, spatial, verification, security | Yes | Stable. Import explicitly. |
| Industrial | safety_cert, asic_flow, fault_injection, uvm_gen, hypervisor, digital_twin, chiplet, spintronic, memristor, analog_bridge | No | 1,173 tests. Available from source. |
| Extended research | evo_substrate, meta_plasticity, bioware, federated, bci_studio, explainability, neuro_symbolic, stochastic_doctor, model_zoo | No | 1,173 tests. Available from source. |
| Domain bridges | quantum (Qiskit/PennyLane), adapters/holonomic (JAX), scpn (Petri nets) | Yes | Requires pip install sc-neurocore[quantum] or [jax] |
| Research | robotics, physics, bio, optics, chaos, sleep, interfaces | No | Tested. Available from source. |
| Speculative | research/ (eschaton, exotic, meta, post_silicon, transcendent) |
No | Theoretical. See research/README.md. |
Architecture Diagram
graph TD
subgraph "Python API (pip install sc-neurocore)"
A[BitstreamEncoder] --> B[SCDenseLayer / SCConv2DLayer]
B --> C[173 Neuron Models<br/>LIF · HH · AdEx · Izhikevich · ArcaneNeuron · ...]
C --> NET[Network Engine<br/>Population · Projection · 3 Backends]
C --> ID[Identity Substrate<br/>Persistent SNN · Checkpoint · Director]
C --> D[STDP / R-STDP Synapses]
D --> E[BitstreamSpikeRecorder]
end
subgraph "Acceleration"
B --> F{Backend?}
F -->|CPU| G[NumPy / Numba SIMD]
F -->|GPU| H[CuPy CUDA]
F -->|Rust| I[sc_neurocore_engine<br/>39–202× vs Brian2 · 174 neuron models<br/>161-model NetworkRunner]
F -->|MPI| MPI[mpi4py distributed<br/>billion-neuron scale]
end
subgraph "Hardware Target"
I --> J[IR Compiler]
J --> K[SystemVerilog Emitter]
J --> K2[MLIR/CIRCT Emitter]
K --> L[Verilog RTL<br/>AXI-Lite + LIF Core]
K2 --> L
L --> M[FPGA Bitstream<br/>Xilinx / Intel]
L --> V[Formal Verification<br/>SymbiYosys · 7 modules]
end
subgraph "Domain Bridges (optional)"
B --> N[SCPN Petri Nets]
B --> O[Quantum Hybrid<br/>Qiskit / PennyLane]
B --> P[HDC/VSA Symbolic Memory]
end
style A fill:#2d6a4f,color:#fff
style I fill:#b5651d,color:#fff
style L fill:#1a237e,color:#fff
style M fill:#4a148c,color:#fff
style O fill:#6a1b9a,color:#fff
style V fill:#004d40,color:#fff
Core API (28 symbols)
Hardware (Verilog RTL)
hdl/
sc_bitstream_encoder.v -- LFSR-based stochastic encoder (SEED_INIT param)
sc_bitstream_synapse.v -- AND-gate SC multiplier
sc_mux_add.v -- 2-input MUX (scaled addition)
sc_cordiv.v -- CORDIV stochastic divider (Li et al. 2014)
sc_dotproduct_to_current.v -- Popcount -> fixed-point current
sc_lif_neuron.v -- Q8.8 leaky integrate-and-fire
sc_firing_rate_bank.v -- Spike rate estimator
sc_dense_layer_core.v -- Full dense layer pipeline (decorrelated seeds)
sc_dense_matrix_layer.v -- N×M weight matrix layer
sc_axil_cfg.v -- AXI-Lite register file
sc_axil_cfg_param.v -- Parameterized AXI-Lite register file
sc_axis_interface.v -- AXI-Stream bulk bitstream I/O
sc_dma_controller.v -- DMA for weight upload and output readback
sc_cdc_primitives.v -- Clock domain crossing (2-FF sync, Gray, async FIFO)
sc_dense_layer_top.v -- Dense layer top wrapper
sc_neurocore_top.v -- System top (DMA + AXI + layers)
sc_aer_encoder.v -- AER spike encoder (event-driven output)
sc_event_neuron.v -- Event-triggered LIF (power ∝ spike rate)
sc_aer_router.v -- AER event distribution to target neurons
tb_sc_*.v (7 testbenches) -- Self-checking simulation testbenches
formal/ (7 modules) -- SymbiYosys formal verification properties
GPU Acceleration
# VectorizedSCLayer auto-detects GPU
=
= # GPU if CuPy available, else CPU
Hardware-Software Co-Simulation
The co-sim flow verifies bit-exact equivalence between the Python model and Verilog RTL:
# 1. Generate stimuli + expected results (Python golden model)
# 2. Run Verilog simulation (requires Icarus Verilog)
# 3. Compare results
Reproducibility
Every GitHub Release includes:
- wheel + sdist — Python distribution artifacts (
dist/sc_neurocore-*) - SBOM — CycloneDX software bill of materials (
sbom.json) - Changelog extract — release notes from
CHANGELOG.md
Co-simulation traces are generated deterministically from fixed LFSR seeds. To reproduce a published benchmark:
For Verilog co-sim trace reproduction, see scripts/cosim_gen_and_check.py
and the seed constants in hdl/sc_bitstream_encoder.v.
Key Technical Details
- LFSR: 16-bit maximal-length, polynomial x16+x14+x13+x11+1, period 65535
- Seed strategy: Input encoders
0xACE1 + i*7, weight encoders0xBEEF + i*13 - Fixed-point: Q8.8 (DATA_WIDTH=16, FRACTION=8), signed two's complement
- Overflow: Explicit bit-width masking via
_mask()function
Examples
Runnable scripts in examples/:
| Script | Description |
|---|---|
01_basic_sc_encoding.py |
Bernoulli & Sobol bitstream encoding/decoding |
02_sc_neuron_layer.py |
SCDenseLayer construction, spike trains, and firing-rate summary |
03_ir_compile_demo.py |
IR graph building, verification, SystemVerilog emission (v3 Rust engine) |
04_vectorized_layer.py |
VectorizedSCLayer throughput benchmarking |
05_scpn_stack.py |
Full 7-layer SCPN consciousness stack with inter-layer coupling |
06_hdl_generation.py |
Verilog top-level generation from a network description |
07_ensemble_consensus.py |
Multi-agent ensemble orchestration and voting |
08_hdc_symbolic_query.py |
Hyper-Dimensional Computing symbolic memory (v3 Rust engine) |
09_safety_critical_logic.py |
Fault-tolerant Boolean logic with stochastic redundancy (v3 Rust engine) |
10_benchmark_report.py |
Head-to-head v2/v3 benchmark suite (v3 Rust engine) |
11_sc_training_demo.py |
Surrogate-gradient training of an SC dense layer (v3 Rust engine) |
12_load_pretrained_model.py |
Load pretrained ConvSpikingNet and classify MNIST digits |
zenith_hybrid_resnet.py |
Train hybrid network with PyTorch autograd → save via Zenith exascale persistence |
jax_training_demo.py |
JAX JIT surrogate-gradient SNN training on synthetic data |
mnist_fpga/demo.py |
MNIST classifier: train → quantise Q8.8 → SC simulate → Verilog export |
mnist_conv_train.py |
ConvSpikingNet: 99.49% MNIST (learnable beta/threshold, cosine LR; evidence in benchmarks/results/mnist_conv_accuracy_reproducibility.json) |
mnist_surrogate/train.py |
Surrogate gradient SNN training (FastSigmoid/SuperSpike/ATan, ~95% MNIST) |
nir_roundtrip_demo.py |
NIR roundtrip: CubaLIF + recurrent connections, build → import → run → export |
norse_nir_roundtrip.py |
Norse → NIR → SC-NeuroCore roundtrip with real Norse weights |
snntorch_nir_roundtrip.py |
snnTorch RSynaptic → NIR → SC-NeuroCore roundtrip (CubaLIF + recurrent) |
spikingjelly_nir_roundtrip.py |
SpikingJelly → NIR → SC-NeuroCore roundtrip |
ann_to_snn_demo.py |
Convert trained PyTorch ANN to rate-coded SNN |
delay_training_demo.py |
Train spiking network with learnable per-synapse delays |
PYTHONPATH=src:bridge
Examples marked (v3 Rust engine) require an available sc_neurocore_engine
bridge install. For source-tree runs against local bridge code, use
PYTHONPATH=src:bridge or install bridge/ in the same environment.
CI/CD
14 GitHub Actions workflows (.github/workflows/), all SHA-pinned:
| Workflow | Purpose |
|---|---|
| ci.yml | Lint (ruff format + ruff check + bandit) + Test (Python 3.10-3.14, coverage gate enforced in CI) + Build |
| v3-engine.yml | Rust engine cargo test + cargo clippy |
| v3-wheels.yml | Cross-platform wheels (Linux, macOS, Windows × Python 3.10–3.14) |
| docker.yml | Build & push Docker image to GHCR on release tags |
| docs.yml | MkDocs → GitHub Pages |
| publish.yml | Publish sc-neurocore to PyPI and engine/ to crates.io on release tags |
| release.yml | Python wheel + sdist + changelog extraction → GitHub Release |
| benchmark.yml | Performance regression tracking |
| codeql.yml | CodeQL security analysis (weekly + on push) |
| scorecard.yml | OpenSSF Scorecard |
| pre-commit.yml | Pre-commit hook validation |
| yosys-synth.yml | Yosys HDL synthesis verification |
| stale.yml | Auto-label and close stale issues |
Benchmarks
Run the benchmark suite:
Sample results (CPU, quick mode):
| Operation | Throughput |
|---|---|
| LFSR step | 2.25 Mstep/s |
| Bitstream encoder | 1.88 Mstep/s |
| LIF neuron step | 1.15 Mstep/s |
| vec_and (1024 words) | 45.67 Gbit/s |
| gpu_vec_mac (64x32x16w) | 6.15 GOP/s |
Documentation
Live site: anulum.github.io/sc-neurocore
- Getting Started — Installation & quickstart
- Install Profiles — Base install, optional extras, and research-only polyglot boundary
- FPGA Deploy Cookbook — Five-minute scaffold, optional synthesis, report-to-optimiser handoff
- Tutorials — 88 tracked guides and tutorials (SC fundamentals → MNIST → FPGA → quantum → formal verification)
- API Reference — Python package API
- Rust Engine API — Rust engine docs
- Hardware Guide — FPGA deployment workflow
- Architecture — Package architecture
- Benchmarks — Performance measurements
- CHANGELOG.md — Version history
Build docs locally:
Install Extras
Start with the base package. It installs the Python package plus numpy and
scipy; it does not install PyTorch, JAX, Qiskit, PennyLane, Lava, FastAPI, or
hardware toolchains.
Acceleration and research extras are intentionally opt-in:
See Install Profiles before using full.
The default package and FPGA scaffold flow do not require those heavy extras.
For development (includes all modules and source-only research code):
Pinned dependency files for reproducible environments:
Rust Engine (174 Neuron Models, 1 720 Tests across 6 Crates)
The sc_neurocore_engine crate provides 174 Rust neuron models callable
from Python via PyO3 bindings (including ArcaneNeuron), a 161-model
NetworkRunner with Rayon-parallel population simulation (100K+ neurons),
and SIMD-accelerated primitives with dispatch across five ISAs (AVX-512,
AVX2, NEON, SVE, RISC-V V).
1 720 Rust tests across 6 workspace crates:
| Crate | Tests | Purpose |
|---|---|---|
sc_neurocore_engine |
1,552 | PyO3 SIMD engine, 174 neuron models, NetworkRunner |
tinysc_riscv |
83 | RISC-V SC instruction set simulator |
core_engine |
22 | SC arithmetic core (standalone) |
autonomous_learning |
12 | Self-modifying plasticity rules |
neuro_symbolic |
28 | Hyperdimensional computing + predictive coding |
stochastic_doctor_core |
23 | Bitstream diagnostics engine |
| Category | Scope |
|---|---|
| Primitives | Bernoulli + Sobol bitstream, pack/unpack, popcount, SIMD (5 ISAs) |
| Neurons | 174 models: LIF variants, HH-type, maps, hardware emulators, population, ArcaneNeuron |
| NetworkRunner | 161-model fused simulation loop with CSR projections and Rayon parallelism |
| Synapses | Static, STDP, Reward-STDP |
| Layers | Dense, Conv2D, Recurrent, Learning, Fusion, Memristive, Attention |
| Networks | Brunel, GNN, Spike recorder, Connectome, Fault injection |
| Compiler | IR builder/parser/verifier, SystemVerilog + MLIR emitters, IR bridge |
| Domain | HDC, Kuramoto, SSGF geometry |
| Training | 6 surrogate gradient functions + property tests |
Community
- GitHub Discussions — questions, ideas, show & tell
- Issue Tracker — bug reports and feature requests
- Contributing Guide — how to set up, test, and submit PRs
Citation
If you use SC-NeuroCore in your research, please cite:
See also CITATION.cff for the machine-readable citation metadata.
AI Disclosure
This project uses LLMs for advanced control mechanisms and GitHub handling. All output is reviewed, tested, and verified by the project author.
License
SC-NeuroCore is dual-licensed:
- Open Source: GNU Affero General Public License v3.0 (AGPLv3)
- Commercial: Proprietary license available for integration into closed-source products
For commercial licensing enquiries, contact protoscience@anulum.li.