1use num_derive::FromPrimitive;
2
3#[derive(Debug, Clone, Copy, PartialEq, FromPrimitive)]
4#[repr(u8)]
5pub enum Opcode {
6 Lddw,
7 Ldxb,
8 Ldxh,
9 Ldxw,
10 Ldxdw,
11 Stb,
12 Sth,
13 Stw,
14 Stdw,
15 Stxb,
16 Stxh,
17 Stxw,
18 Stxdw,
19 Add32,
20 Add32Imm,
21 Add32Reg,
22 Sub32,
23 Sub32Imm,
24 Sub32Reg,
25 Mul32,
26 Mul32Imm,
27 Mul32Reg,
28 Div32,
29 Div32Imm,
30 Div32Reg,
31 Or32,
32 Or32Imm,
33 Or32Reg,
34 And32,
35 And32Imm,
36 And32Reg,
37 Lsh32,
38 Lsh32Imm,
39 Lsh32Reg,
40 Rsh32,
41 Rsh32Imm,
42 Rsh32Reg,
43 Mod32,
44 Mod32Imm,
45 Mod32Reg,
46 Xor32,
47 Xor32Imm,
48 Xor32Reg,
49 Mov32,
50 Mov32Imm,
51 Mov32Reg,
52 Arsh32,
53 Arsh32Imm,
54 Arsh32Reg,
55 Lmul32,
56 Lmul32Imm,
57 Lmul32Reg,
58 Udiv32,
59 Udiv32Imm,
60 Udiv32Reg,
61 Urem32,
62 Urem32Imm,
63 Urem32Reg,
64 Sdiv32,
65 Sdiv32Imm,
66 Sdiv32Reg,
67 Srem32,
68 Srem32Imm,
69 Srem32Reg,
70 Le,
71 Be,
72 Add64,
73 Add64Imm,
74 Add64Reg,
75 Sub64,
76 Sub64Imm,
77 Sub64Reg,
78 Mul64,
79 Mul64Imm,
80 Mul64Reg,
81 Div64,
82 Div64Imm,
83 Div64Reg,
84 Or64,
85 Or64Imm,
86 Or64Reg,
87 And64,
88 And64Imm,
89 And64Reg,
90 Lsh64,
91 Lsh64Imm,
92 Lsh64Reg,
93 Rsh64,
94 Rsh64Imm,
95 Rsh64Reg,
96 Mod64,
97 Mod64Imm,
98 Mod64Reg,
99 Xor64,
100 Xor64Imm,
101 Xor64Reg,
102 Mov64,
103 Mov64Imm,
104 Mov64Reg,
105 Arsh64,
106 Arsh64Imm,
107 Arsh64Reg,
108 Hor64Imm,
109 Lmul64,
110 Lmul64Imm,
111 Lmul64Reg,
112 Uhmul64,
113 Uhmul64Imm,
114 Uhmul64Reg,
115 Udiv64,
116 Udiv64Imm,
117 Udiv64Reg,
118 Urem64,
119 Urem64Imm,
120 Urem64Reg,
121 Shmul64,
122 Shmul64Imm,
123 Shmul64Reg,
124 Sdiv64,
125 Sdiv64Imm,
126 Sdiv64Reg,
127 Srem64,
128 Srem64Imm,
129 Srem64Reg,
130 Neg32,
131 Neg64,
132 Ja,
133 Jeq,
134 JeqImm,
135 JeqReg,
136 Jgt,
137 JgtImm,
138 JgtReg,
139 Jge,
140 JgeImm,
141 JgeReg,
142 Jlt,
143 JltImm,
144 JltReg,
145 Jle,
146 JleImm,
147 JleReg,
148 Jset,
149 JsetImm,
150 JsetReg,
151 Jne,
152 JneImm,
153 JneReg,
154 Jsgt,
155 JsgtImm,
156 JsgtReg,
157 Jsge,
158 JsgeImm,
159 JsgeReg,
160 Jslt,
161 JsltImm,
162 JsltReg,
163 Jsle,
164 JsleImm,
165 JsleReg,
166 Call,
167 Callx,
168 Exit,
169}
170
171impl Opcode {
172 pub fn from_str(s: &str) -> Result<Self, &'static str> {
173 match s.to_lowercase().as_str() {
174 "lddw" => Ok(Opcode::Lddw),
175 "ldxb" => Ok(Opcode::Ldxb),
176 "ldxh" => Ok(Opcode::Ldxh),
177 "ldxw" => Ok(Opcode::Ldxw),
178 "ldxdw" => Ok(Opcode::Ldxdw),
179 "stb" => Ok(Opcode::Stb),
180 "sth" => Ok(Opcode::Sth),
181 "stw" => Ok(Opcode::Stw),
182 "stdw" => Ok(Opcode::Stdw),
183 "stxb" => Ok(Opcode::Stxb),
184 "stxh" => Ok(Opcode::Stxh),
185 "stxw" => Ok(Opcode::Stxw),
186 "stxdw" => Ok(Opcode::Stxdw),
187 "add32" => Ok(Opcode::Add32),
188 "sub32" => Ok(Opcode::Sub32),
189 "mul32" => Ok(Opcode::Mul32),
190 "div32" => Ok(Opcode::Div32),
191 "or32" => Ok(Opcode::Or32),
192 "and32" => Ok(Opcode::And32),
193 "lsh32" => Ok(Opcode::Lsh32),
194 "rsh32" => Ok(Opcode::Rsh32),
195 "neg32" => Ok(Opcode::Neg32),
196 "mod32" => Ok(Opcode::Mod32),
197 "xor32" => Ok(Opcode::Xor32),
198 "mov32" => Ok(Opcode::Mov32),
199 "arsh32" => Ok(Opcode::Arsh32),
200 "lmul32" => Ok(Opcode::Lmul32),
201 "udiv32" => Ok(Opcode::Udiv32),
202 "urem32" => Ok(Opcode::Urem32),
203 "sdiv32" => Ok(Opcode::Sdiv32),
204 "srem32" => Ok(Opcode::Srem32),
205 "le" => Ok(Opcode::Le),
206 "be" => Ok(Opcode::Be),
207 "add64" => Ok(Opcode::Add64),
208 "sub64" => Ok(Opcode::Sub64),
209 "mul64" => Ok(Opcode::Mul64),
210 "div64" => Ok(Opcode::Div64),
211 "or64" => Ok(Opcode::Or64),
212 "and64" => Ok(Opcode::And64),
213 "lsh64" => Ok(Opcode::Lsh64),
214 "rsh64" => Ok(Opcode::Rsh64),
215 "neg64" => Ok(Opcode::Neg64),
216 "mod64" => Ok(Opcode::Mod64),
217 "xor64" => Ok(Opcode::Xor64),
218 "mov64" => Ok(Opcode::Mov64),
219 "arsh64" => Ok(Opcode::Arsh64),
220 "hor64" => Ok(Opcode::Hor64Imm),
221 "lmul64" => Ok(Opcode::Lmul64),
222 "uhmul64" => Ok(Opcode::Uhmul64),
223 "udiv64" => Ok(Opcode::Udiv64),
224 "urem64" => Ok(Opcode::Urem64),
225 "shmul64" => Ok(Opcode::Shmul64),
226 "sdiv64" => Ok(Opcode::Sdiv64),
227 "srem64" => Ok(Opcode::Srem64),
228 "ja" => Ok(Opcode::Ja),
229 "jeq" => Ok(Opcode::Jeq),
230 "jgt" => Ok(Opcode::Jgt),
231 "jge" => Ok(Opcode::Jge),
232 "jlt" => Ok(Opcode::Jlt),
233 "jle" => Ok(Opcode::Jle),
234 "jset" => Ok(Opcode::Jset),
235 "jne" => Ok(Opcode::Jne),
236 "jsgt" => Ok(Opcode::Jsgt),
237 "jsge" => Ok(Opcode::Jsge),
238 "jslt" => Ok(Opcode::Jslt),
239 "jsle" => Ok(Opcode::Jsle),
240 "call" => Ok(Opcode::Call),
241 "callx" => Ok(Opcode::Callx),
242 "exit" => Ok(Opcode::Exit),
243 _ => Err("Invalid opcode"),
244 }
245 }
246
247 pub fn from_u8(u: u8) -> Option<Self> {
248 match u {
249 0x18 => Some(Opcode::Lddw),
250 0x71 => Some(Opcode::Ldxb),
251 0x69 => Some(Opcode::Ldxh),
252 0x61 => Some(Opcode::Ldxw),
253 0x79 => Some(Opcode::Ldxdw),
254 0x72 => Some(Opcode::Stb),
255 0x6a => Some(Opcode::Sth),
256 0x62 => Some(Opcode::Stw),
257 0x7a => Some(Opcode::Stdw),
258 0x73 => Some(Opcode::Stxb),
259 0x6b => Some(Opcode::Stxh),
260 0x63 => Some(Opcode::Stxw),
261 0x7b => Some(Opcode::Stxdw),
262 0x04 => Some(Opcode::Add32Imm),
263 0x0c => Some(Opcode::Add32Reg),
264 0x14 => Some(Opcode::Sub32Imm),
265 0x1c => Some(Opcode::Sub32Reg),
266 0x24 => Some(Opcode::Mul32Imm),
267 0x2c => Some(Opcode::Mul32Reg),
268 0x34 => Some(Opcode::Div32Imm),
269 0x3c => Some(Opcode::Div32Reg),
270 0x44 => Some(Opcode::Or32Imm),
271 0x4c => Some(Opcode::Or32Reg),
272 0x54 => Some(Opcode::And32Imm),
273 0x5c => Some(Opcode::And32Reg),
274 0x64 => Some(Opcode::Lsh32Imm),
275 0x6c => Some(Opcode::Lsh32Reg),
276 0x74 => Some(Opcode::Rsh32Imm),
277 0x7c => Some(Opcode::Rsh32Reg),
278 0x94 => Some(Opcode::Mod32Imm),
279 0x9c => Some(Opcode::Mod32Reg),
280 0xa4 => Some(Opcode::Xor32Imm),
281 0xac => Some(Opcode::Xor32Reg),
282 0xb4 => Some(Opcode::Mov32Imm),
283 0xbc => Some(Opcode::Mov32Reg),
284 0xc4 => Some(Opcode::Arsh32Imm),
285 0xcc => Some(Opcode::Arsh32Reg),
286 0x86 => Some(Opcode::Lmul32Imm),
287 0x8e => Some(Opcode::Lmul32Reg),
288 0x46 => Some(Opcode::Udiv32Imm),
289 0x4e => Some(Opcode::Udiv32Reg),
290 0x66 => Some(Opcode::Urem32Imm),
291 0x6e => Some(Opcode::Urem32Reg),
292 0xc6 => Some(Opcode::Sdiv32Imm),
293 0xce => Some(Opcode::Sdiv32Reg),
294 0xe6 => Some(Opcode::Srem32Imm),
295 0xee => Some(Opcode::Srem32Reg),
296 0xd4 => Some(Opcode::Le),
297 0xdc => Some(Opcode::Be),
298 0x07 => Some(Opcode::Add64Imm),
299 0x0f => Some(Opcode::Add64Reg),
300 0x17 => Some(Opcode::Sub64Imm),
301 0x1f => Some(Opcode::Sub64Reg),
302 0x27 => Some(Opcode::Mul64Imm),
303 0x2f => Some(Opcode::Mul64Reg),
304 0x37 => Some(Opcode::Div64Imm),
305 0x3f => Some(Opcode::Div64Reg),
306 0x47 => Some(Opcode::Or64Imm),
307 0x4f => Some(Opcode::Or64Reg),
308 0x57 => Some(Opcode::And64Imm),
309 0x5f => Some(Opcode::And64Reg),
310 0x67 => Some(Opcode::Lsh64Imm),
311 0x6f => Some(Opcode::Lsh64Reg),
312 0x77 => Some(Opcode::Rsh64Imm),
313 0x7f => Some(Opcode::Rsh64Reg),
314 0x97 => Some(Opcode::Mod64Imm),
315 0x9f => Some(Opcode::Mod64Reg),
316 0xa7 => Some(Opcode::Xor64Imm),
317 0xaf => Some(Opcode::Xor64Reg),
318 0xb7 => Some(Opcode::Mov64Imm),
319 0xbf => Some(Opcode::Mov64Reg),
320 0xc7 => Some(Opcode::Arsh64Imm),
321 0xcf => Some(Opcode::Arsh64Reg),
322 0xf7 => Some(Opcode::Hor64Imm),
323 0x96 => Some(Opcode::Lmul64Imm),
324 0x9e => Some(Opcode::Lmul64Reg),
325 0x36 => Some(Opcode::Uhmul64Imm),
326 0x3e => Some(Opcode::Uhmul64Reg),
327 0x56 => Some(Opcode::Udiv64Imm),
328 0x5e => Some(Opcode::Udiv64Reg),
329 0x76 => Some(Opcode::Urem64Imm),
330 0x7e => Some(Opcode::Urem64Reg),
331 0xb6 => Some(Opcode::Shmul64Imm),
332 0xbe => Some(Opcode::Shmul64Reg),
333 0xd6 => Some(Opcode::Sdiv64Imm),
334 0xde => Some(Opcode::Sdiv64Reg),
335 0xf6 => Some(Opcode::Srem64Imm),
336 0xfe => Some(Opcode::Srem64Reg),
337 0x84 => Some(Opcode::Neg32),
338 0x87 => Some(Opcode::Neg64),
339 0x05 => Some(Opcode::Ja),
340 0x15 => Some(Opcode::JeqImm),
341 0x1d => Some(Opcode::JeqReg),
342 0x25 => Some(Opcode::JgtImm),
343 0x2d => Some(Opcode::JgtReg),
344 0x35 => Some(Opcode::JgeImm),
345 0x3d => Some(Opcode::JgeReg),
346 0xa5 => Some(Opcode::JltImm),
347 0xad => Some(Opcode::JltReg),
348 0xb5 => Some(Opcode::JleImm),
349 0xbd => Some(Opcode::JleReg),
350 0x45 => Some(Opcode::JsetImm),
351 0x4d => Some(Opcode::JsetReg),
352 0x55 => Some(Opcode::JneImm),
353 0x5d => Some(Opcode::JneReg),
354 0x65 => Some(Opcode::JsgtImm),
355 0x6d => Some(Opcode::JsgtReg),
356 0x75 => Some(Opcode::JsgeImm),
357 0x7d => Some(Opcode::JsgeReg),
358 0xc5 => Some(Opcode::JsltImm),
359 0xcd => Some(Opcode::JsltReg),
360 0xd5 => Some(Opcode::JsleImm),
361 0xdd => Some(Opcode::JsleReg),
362 0x85 => Some(Opcode::Call),
363 0x8d => Some(Opcode::Callx),
364 0x95 => Some(Opcode::Exit),
365 _ => None,
366 }
367 }
368
369 pub fn to_bytecode(&self) -> u8 {
370 match self {
371 Opcode::Lddw => 0x18,
372 Opcode::Ldxb => 0x71,
373 Opcode::Ldxh => 0x69,
374 Opcode::Ldxw => 0x61,
375 Opcode::Ldxdw => 0x79,
376 Opcode::Stb => 0x72,
377 Opcode::Sth => 0x6a,
378 Opcode::Stw => 0x62,
379 Opcode::Stdw => 0x7a,
380 Opcode::Stxb => 0x73,
381 Opcode::Stxh => 0x6b,
382 Opcode::Stxw => 0x63,
383 Opcode::Stxdw => 0x7b,
384 Opcode::Add32Imm => 0x04,
386 Opcode::Add32Reg => 0x0c,
387 Opcode::Sub32Imm => 0x14,
389 Opcode::Sub32Reg => 0x1c,
390 Opcode::Mul32Imm => 0x24,
392 Opcode::Mul32Reg => 0x2c,
393 Opcode::Div32Imm => 0x34,
395 Opcode::Div32Reg => 0x3c,
396 Opcode::Or32Imm => 0x44,
398 Opcode::Or32Reg => 0x4c,
399 Opcode::And32Imm => 0x54,
401 Opcode::And32Reg => 0x5c,
402 Opcode::Lsh32Imm => 0x64,
404 Opcode::Lsh32Reg => 0x6c,
405 Opcode::Rsh32Imm => 0x74,
407 Opcode::Rsh32Reg => 0x7c,
408 Opcode::Mod32Imm => 0x94,
410 Opcode::Mod32Reg => 0x9c,
411 Opcode::Xor32Imm => 0xa4,
413 Opcode::Xor32Reg => 0xac,
414 Opcode::Mov32Imm => 0xb4,
416 Opcode::Mov32Reg => 0xbc,
417 Opcode::Arsh32Imm => 0xc4,
419 Opcode::Arsh32Reg => 0xcc,
420 Opcode::Lmul32Imm => 0x86,
422 Opcode::Lmul32Reg => 0x8e,
423 Opcode::Udiv32Imm => 0x46,
425 Opcode::Udiv32Reg => 0x4e,
426 Opcode::Urem32Imm => 0x66,
428 Opcode::Urem32Reg => 0x6e,
429 Opcode::Sdiv32Imm => 0xc6,
431 Opcode::Sdiv32Reg => 0xce,
432 Opcode::Srem32Imm => 0xe6,
434 Opcode::Srem32Reg => 0xee,
435 Opcode::Le => 0xd4,
436 Opcode::Be => 0xdc,
437 Opcode::Add64Imm => 0x07,
439 Opcode::Add64Reg => 0x0f,
440 Opcode::Sub64Imm => 0x17,
442 Opcode::Sub64Reg => 0x1f,
443 Opcode::Mul64Imm => 0x27,
445 Opcode::Mul64Reg => 0x2f,
446 Opcode::Div64Imm => 0x37,
448 Opcode::Div64Reg => 0x3f,
449 Opcode::Or64Imm => 0x47,
451 Opcode::Or64Reg => 0x4f,
452 Opcode::And64Imm => 0x57,
454 Opcode::And64Reg => 0x5f,
455 Opcode::Lsh64Imm => 0x67,
457 Opcode::Lsh64Reg => 0x6f,
458 Opcode::Rsh64Imm => 0x77,
460 Opcode::Rsh64Reg => 0x7f,
461 Opcode::Mod64Imm => 0x97,
463 Opcode::Mod64Reg => 0x9f,
464 Opcode::Xor64Imm => 0xa7,
466 Opcode::Xor64Reg => 0xaf,
467 Opcode::Mov64Imm => 0xb7,
469 Opcode::Mov64Reg => 0xbf,
470 Opcode::Arsh64Imm => 0xc7,
472 Opcode::Arsh64Reg => 0xcf,
473 Opcode::Hor64Imm => 0xf7,
474 Opcode::Lmul64Imm => 0x96,
476 Opcode::Lmul64Reg => 0x9e,
477 Opcode::Uhmul64Imm => 0x36,
479 Opcode::Uhmul64Reg => 0x3e,
480 Opcode::Udiv64Imm => 0x56,
482 Opcode::Udiv64Reg => 0x5e,
483 Opcode::Urem64Imm => 0x76,
485 Opcode::Urem64Reg => 0x7e,
486 Opcode::Shmul64Imm => 0xb6,
488 Opcode::Shmul64Reg => 0xbe,
489 Opcode::Sdiv64Imm => 0xd6,
491 Opcode::Sdiv64Reg => 0xde,
492 Opcode::Srem64Imm => 0xf6,
494 Opcode::Srem64Reg => 0xfe,
495 Opcode::Neg32 => 0x84,
496 Opcode::Neg64 => 0x87,
497 Opcode::Ja => 0x05,
498 Opcode::JeqImm => 0x15,
500 Opcode::JeqReg => 0x1d,
501 Opcode::JgtImm => 0x25,
503 Opcode::JgtReg => 0x2d,
504 Opcode::JgeImm => 0x35,
506 Opcode::JgeReg => 0x3d,
507 Opcode::JltImm => 0xa5,
509 Opcode::JltReg => 0xad,
510 Opcode::JleImm => 0xb5,
512 Opcode::JleReg => 0xbd,
513 Opcode::JsetImm => 0x45,
515 Opcode::JsetReg => 0x4d,
516 Opcode::JneImm => 0x55,
518 Opcode::JneReg => 0x5d,
519 Opcode::JsgtImm => 0x65,
521 Opcode::JsgtReg => 0x6d,
522 Opcode::JsgeImm => 0x75,
524 Opcode::JsgeReg => 0x7d,
525 Opcode::JsltImm => 0xc5,
527 Opcode::JsltReg => 0xcd,
528 Opcode::JsleImm => 0xd5,
530 Opcode::JsleReg => 0xdd,
531 Opcode::Call => 0x85,
532 Opcode::Callx => 0x8d,
533 Opcode::Exit => 0x95,
534
535 _ => 0x00,
536
537 }
538 }
539
540 pub fn to_str(&self) -> &'static str {
541 match self {
542 Opcode::Lddw => "lddw",
543 Opcode::Ldxb => "ldxb",
544 Opcode::Ldxh => "ldxh",
545 Opcode::Ldxw => "ldxw",
546 Opcode::Ldxdw => "ldxdw",
547 Opcode::Stb => "stb",
548 Opcode::Sth => "sth",
549 Opcode::Stw => "stw",
550 Opcode::Stdw => "stdw",
551 Opcode::Stxb => "stxb",
552 Opcode::Stxh => "stxh",
553 Opcode::Stxw => "stxw",
554 Opcode::Stxdw => "stxdw",
555 Opcode::Add32 | Opcode::Add32Imm | Opcode::Add32Reg => "add32",
556 Opcode::Sub32 | Opcode::Sub32Imm | Opcode::Sub32Reg => "sub32",
557 Opcode::Mul32 | Opcode::Mul32Imm | Opcode::Mul32Reg => "mul32",
558 Opcode::Div32 | Opcode::Div32Imm | Opcode::Div32Reg => "div32",
559 Opcode::Or32 | Opcode::Or32Imm | Opcode::Or32Reg => "or32",
560 Opcode::And32 | Opcode::And32Imm | Opcode::And32Reg => "and32",
561 Opcode::Lsh32 | Opcode::Lsh32Imm | Opcode::Lsh32Reg => "lsh32",
562 Opcode::Rsh32 | Opcode::Rsh32Imm | Opcode::Rsh32Reg => "rsh32",
563 Opcode::Neg32 => "neg32",
564 Opcode::Mod32 | Opcode::Mod32Imm | Opcode::Mod32Reg => "mod32",
565 Opcode::Xor32 | Opcode::Xor32Imm | Opcode::Xor32Reg => "xor32",
566 Opcode::Mov32 | Opcode::Mov32Imm | Opcode::Mov32Reg => "mov32",
567 Opcode::Arsh32 | Opcode::Arsh32Imm | Opcode::Arsh32Reg => "arsh32",
568 Opcode::Lmul32 | Opcode::Lmul32Imm | Opcode::Lmul32Reg => "lmul32",
569 Opcode::Udiv32 | Opcode::Udiv32Imm | Opcode::Udiv32Reg => "udiv32",
570 Opcode::Urem32 | Opcode::Urem32Imm | Opcode::Urem32Reg => "urem32",
571 Opcode::Sdiv32 | Opcode::Sdiv32Imm | Opcode::Sdiv32Reg => "sdiv32",
572 Opcode::Srem32 | Opcode::Srem32Imm | Opcode::Srem32Reg => "srem32",
573 Opcode::Le => "le",
574 Opcode::Be => "be",
575 Opcode::Add64 | Opcode::Add64Imm | Opcode::Add64Reg => "add64",
576 Opcode::Sub64 | Opcode::Sub64Imm | Opcode::Sub64Reg => "sub64",
577 Opcode::Mul64 | Opcode::Mul64Imm | Opcode::Mul64Reg => "mul64",
578 Opcode::Div64 | Opcode::Div64Imm | Opcode::Div64Reg => "div64",
579 Opcode::Or64 | Opcode::Or64Imm | Opcode::Or64Reg => "or64",
580 Opcode::And64 | Opcode::And64Imm | Opcode::And64Reg => "and64",
581 Opcode::Lsh64 | Opcode::Lsh64Imm | Opcode::Lsh64Reg => "lsh64",
582 Opcode::Rsh64 | Opcode::Rsh64Imm | Opcode::Rsh64Reg => "rsh64",
583 Opcode::Neg64 => "neg64",
584 Opcode::Mod64 | Opcode::Mod64Imm | Opcode::Mod64Reg => "mod64",
585 Opcode::Xor64 | Opcode::Xor64Imm | Opcode::Xor64Reg => "xor64",
586 Opcode::Mov64 | Opcode::Mov64Imm | Opcode::Mov64Reg => "mov64",
587 Opcode::Arsh64 | Opcode::Arsh64Imm | Opcode::Arsh64Reg => "arsh64",
588 Opcode::Hor64Imm => "hor64",
589 Opcode::Lmul64 | Opcode::Lmul64Imm | Opcode::Lmul64Reg => "lmul64",
590 Opcode::Uhmul64 | Opcode::Uhmul64Imm | Opcode::Uhmul64Reg => "uhmul64",
591 Opcode::Udiv64 | Opcode::Udiv64Imm | Opcode::Udiv64Reg => "udiv64",
592 Opcode::Urem64 | Opcode::Urem64Imm | Opcode::Urem64Reg => "urem64",
593 Opcode::Shmul64 | Opcode::Shmul64Imm | Opcode::Shmul64Reg => "shmul64",
594 Opcode::Sdiv64 | Opcode::Sdiv64Imm | Opcode::Sdiv64Reg => "sdiv64",
595 Opcode::Srem64 | Opcode::Srem64Imm | Opcode::Srem64Reg => "srem64",
596 Opcode::Ja | Opcode::Jeq | Opcode::JeqImm | Opcode::JeqReg => "jeq",
597 Opcode::Jgt | Opcode::JgtImm | Opcode::JgtReg => "jgt",
598 Opcode::Jge | Opcode::JgeImm | Opcode::JgeReg => "jge",
599 Opcode::Jlt | Opcode::JltImm | Opcode::JltReg => "jlt",
600 Opcode::Jle | Opcode::JleImm | Opcode::JleReg => "jle",
601 Opcode::Jset | Opcode::JsetImm | Opcode::JsetReg => "jset",
602 Opcode::Jne | Opcode::JneImm | Opcode::JneReg => "jne",
603 Opcode::Jsgt | Opcode::JsgtImm | Opcode::JsgtReg => "jsgt",
604 Opcode::Jsge | Opcode::JsgeImm | Opcode::JsgeReg => "jsge",
605 Opcode::Jslt | Opcode::JsltImm | Opcode::JsltReg => "jslt",
606 Opcode::Jsle | Opcode::JsleImm | Opcode::JsleReg => "jsle",
607 Opcode::Call | Opcode::Callx => "call",
608 Opcode::Exit => "exit",
609 }
610 }
611 pub fn to_string(&self) -> String {
612 self.to_str().to_string()
613 }
614}