saml10e16a/gclk/
pchctrl.rs1#[doc = "Reader of register PCHCTRL[%s]"]
2pub type R = crate::R<u32, super::PCHCTRL>;
3#[doc = "Writer for register PCHCTRL[%s]"]
4pub type W = crate::W<u32, super::PCHCTRL>;
5#[doc = "Register PCHCTRL[%s] `reset()`'s with value 0"]
6impl crate::ResetValue for super::PCHCTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Possible values of the field `GEN`"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum GEN_A {
16 #[doc = "Generic clock generator 0"]
17 GCLK0,
18 #[doc = "Generic clock generator 1"]
19 GCLK1,
20 #[doc = "Generic clock generator 2"]
21 GCLK2,
22 #[doc = "Generic clock generator 3"]
23 GCLK3,
24 #[doc = "Generic clock generator 4"]
25 GCLK4,
26}
27impl crate::ToBits<u8> for GEN_A {
28 #[inline(always)]
29 fn _bits(&self) -> u8 {
30 match *self {
31 GEN_A::GCLK0 => 0,
32 GEN_A::GCLK1 => 1,
33 GEN_A::GCLK2 => 2,
34 GEN_A::GCLK3 => 3,
35 GEN_A::GCLK4 => 4,
36 }
37 }
38}
39#[doc = "Reader of field `GEN`"]
40pub type GEN_R = crate::R<u8, GEN_A>;
41impl GEN_R {
42 #[doc = r"Get enumerated values variant"]
43 #[inline(always)]
44 pub fn variant(&self) -> crate::Variant<u8, GEN_A> {
45 use crate::Variant::*;
46 match self.bits {
47 0 => Val(GEN_A::GCLK0),
48 1 => Val(GEN_A::GCLK1),
49 2 => Val(GEN_A::GCLK2),
50 3 => Val(GEN_A::GCLK3),
51 4 => Val(GEN_A::GCLK4),
52 i => Res(i),
53 }
54 }
55 #[doc = "Checks if the value of the field is `GCLK0`"]
56 #[inline(always)]
57 pub fn is_gclk0(&self) -> bool {
58 *self == GEN_A::GCLK0
59 }
60 #[doc = "Checks if the value of the field is `GCLK1`"]
61 #[inline(always)]
62 pub fn is_gclk1(&self) -> bool {
63 *self == GEN_A::GCLK1
64 }
65 #[doc = "Checks if the value of the field is `GCLK2`"]
66 #[inline(always)]
67 pub fn is_gclk2(&self) -> bool {
68 *self == GEN_A::GCLK2
69 }
70 #[doc = "Checks if the value of the field is `GCLK3`"]
71 #[inline(always)]
72 pub fn is_gclk3(&self) -> bool {
73 *self == GEN_A::GCLK3
74 }
75 #[doc = "Checks if the value of the field is `GCLK4`"]
76 #[inline(always)]
77 pub fn is_gclk4(&self) -> bool {
78 *self == GEN_A::GCLK4
79 }
80}
81#[doc = "Write proxy for field `GEN`"]
82pub struct GEN_W<'a> {
83 w: &'a mut W,
84}
85impl<'a> GEN_W<'a> {
86 #[doc = r"Writes `variant` to the field"]
87 #[inline(always)]
88 pub fn variant(self, variant: GEN_A) -> &'a mut W {
89 use crate::ToBits;
90 unsafe { self.bits(variant._bits()) }
91 }
92 #[doc = "Generic clock generator 0"]
93 #[inline(always)]
94 pub fn gclk0(self) -> &'a mut W {
95 self.variant(GEN_A::GCLK0)
96 }
97 #[doc = "Generic clock generator 1"]
98 #[inline(always)]
99 pub fn gclk1(self) -> &'a mut W {
100 self.variant(GEN_A::GCLK1)
101 }
102 #[doc = "Generic clock generator 2"]
103 #[inline(always)]
104 pub fn gclk2(self) -> &'a mut W {
105 self.variant(GEN_A::GCLK2)
106 }
107 #[doc = "Generic clock generator 3"]
108 #[inline(always)]
109 pub fn gclk3(self) -> &'a mut W {
110 self.variant(GEN_A::GCLK3)
111 }
112 #[doc = "Generic clock generator 4"]
113 #[inline(always)]
114 pub fn gclk4(self) -> &'a mut W {
115 self.variant(GEN_A::GCLK4)
116 }
117 #[doc = r"Writes raw bits to the field"]
118 #[inline(always)]
119 pub unsafe fn bits(self, value: u8) -> &'a mut W {
120 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
121 self.w
122 }
123}
124#[doc = "Reader of field `CHEN`"]
125pub type CHEN_R = crate::R<bool, bool>;
126#[doc = "Write proxy for field `CHEN`"]
127pub struct CHEN_W<'a> {
128 w: &'a mut W,
129}
130impl<'a> CHEN_W<'a> {
131 #[doc = r"Sets the field bit"]
132 #[inline(always)]
133 pub fn set_bit(self) -> &'a mut W {
134 self.bit(true)
135 }
136 #[doc = r"Clears the field bit"]
137 #[inline(always)]
138 pub fn clear_bit(self) -> &'a mut W {
139 self.bit(false)
140 }
141 #[doc = r"Writes raw bits to the field"]
142 #[inline(always)]
143 pub fn bit(self, value: bool) -> &'a mut W {
144 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
145 self.w
146 }
147}
148#[doc = "Reader of field `WRTLOCK`"]
149pub type WRTLOCK_R = crate::R<bool, bool>;
150#[doc = "Write proxy for field `WRTLOCK`"]
151pub struct WRTLOCK_W<'a> {
152 w: &'a mut W,
153}
154impl<'a> WRTLOCK_W<'a> {
155 #[doc = r"Sets the field bit"]
156 #[inline(always)]
157 pub fn set_bit(self) -> &'a mut W {
158 self.bit(true)
159 }
160 #[doc = r"Clears the field bit"]
161 #[inline(always)]
162 pub fn clear_bit(self) -> &'a mut W {
163 self.bit(false)
164 }
165 #[doc = r"Writes raw bits to the field"]
166 #[inline(always)]
167 pub fn bit(self, value: bool) -> &'a mut W {
168 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
169 self.w
170 }
171}
172impl R {
173 #[doc = "Bits 0:2 - Generic Clock Generator"]
174 #[inline(always)]
175 pub fn gen(&self) -> GEN_R {
176 GEN_R::new((self.bits & 0x07) as u8)
177 }
178 #[doc = "Bit 6 - Channel Enable"]
179 #[inline(always)]
180 pub fn chen(&self) -> CHEN_R {
181 CHEN_R::new(((self.bits >> 6) & 0x01) != 0)
182 }
183 #[doc = "Bit 7 - Write Lock"]
184 #[inline(always)]
185 pub fn wrtlock(&self) -> WRTLOCK_R {
186 WRTLOCK_R::new(((self.bits >> 7) & 0x01) != 0)
187 }
188}
189impl W {
190 #[doc = "Bits 0:2 - Generic Clock Generator"]
191 #[inline(always)]
192 pub fn gen(&mut self) -> GEN_W {
193 GEN_W { w: self }
194 }
195 #[doc = "Bit 6 - Channel Enable"]
196 #[inline(always)]
197 pub fn chen(&mut self) -> CHEN_W {
198 CHEN_W { w: self }
199 }
200 #[doc = "Bit 7 - Write Lock"]
201 #[inline(always)]
202 pub fn wrtlock(&mut self) -> WRTLOCK_W {
203 WRTLOCK_W { w: self }
204 }
205}