saml10d16a/nvmctrl/
ctrlb.rs

1#[doc = "Reader of register CTRLB"]
2pub type R = crate::R<u32, super::CTRLB>;
3#[doc = "Writer for register CTRLB"]
4pub type W = crate::W<u32, super::CTRLB>;
5#[doc = "Register CTRLB `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRLB {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `RWS`"]
14pub type RWS_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `RWS`"]
16pub struct RWS_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RWS_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x0f << 1)) | (((value as u32) & 0x0f) << 1);
24        self.w
25    }
26}
27#[doc = "Possible values of the field `SLEEPPRM`"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29pub enum SLEEPPRM_A {
30    #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."]
31    WAKEONACCESS,
32    #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."]
33    WAKEUPINSTANT,
34    #[doc = "Auto power reduction disabled."]
35    DISABLED,
36}
37impl crate::ToBits<u8> for SLEEPPRM_A {
38    #[inline(always)]
39    fn _bits(&self) -> u8 {
40        match *self {
41            SLEEPPRM_A::WAKEONACCESS => 0,
42            SLEEPPRM_A::WAKEUPINSTANT => 1,
43            SLEEPPRM_A::DISABLED => 3,
44        }
45    }
46}
47#[doc = "Reader of field `SLEEPPRM`"]
48pub type SLEEPPRM_R = crate::R<u8, SLEEPPRM_A>;
49impl SLEEPPRM_R {
50    #[doc = r"Get enumerated values variant"]
51    #[inline(always)]
52    pub fn variant(&self) -> crate::Variant<u8, SLEEPPRM_A> {
53        use crate::Variant::*;
54        match self.bits {
55            0 => Val(SLEEPPRM_A::WAKEONACCESS),
56            1 => Val(SLEEPPRM_A::WAKEUPINSTANT),
57            3 => Val(SLEEPPRM_A::DISABLED),
58            i => Res(i),
59        }
60    }
61    #[doc = "Checks if the value of the field is `WAKEONACCESS`"]
62    #[inline(always)]
63    pub fn is_wakeonaccess(&self) -> bool {
64        *self == SLEEPPRM_A::WAKEONACCESS
65    }
66    #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"]
67    #[inline(always)]
68    pub fn is_wakeupinstant(&self) -> bool {
69        *self == SLEEPPRM_A::WAKEUPINSTANT
70    }
71    #[doc = "Checks if the value of the field is `DISABLED`"]
72    #[inline(always)]
73    pub fn is_disabled(&self) -> bool {
74        *self == SLEEPPRM_A::DISABLED
75    }
76}
77#[doc = "Write proxy for field `SLEEPPRM`"]
78pub struct SLEEPPRM_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> SLEEPPRM_W<'a> {
82    #[doc = r"Writes `variant` to the field"]
83    #[inline(always)]
84    pub fn variant(self, variant: SLEEPPRM_A) -> &'a mut W {
85        use crate::ToBits;
86        unsafe { self.bits(variant._bits()) }
87    }
88    #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."]
89    #[inline(always)]
90    pub fn wakeonaccess(self) -> &'a mut W {
91        self.variant(SLEEPPRM_A::WAKEONACCESS)
92    }
93    #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."]
94    #[inline(always)]
95    pub fn wakeupinstant(self) -> &'a mut W {
96        self.variant(SLEEPPRM_A::WAKEUPINSTANT)
97    }
98    #[doc = "Auto power reduction disabled."]
99    #[inline(always)]
100    pub fn disabled(self) -> &'a mut W {
101        self.variant(SLEEPPRM_A::DISABLED)
102    }
103    #[doc = r"Writes raw bits to the field"]
104    #[inline(always)]
105    pub unsafe fn bits(self, value: u8) -> &'a mut W {
106        self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
107        self.w
108    }
109}
110#[doc = "Reader of field `FWUP`"]
111pub type FWUP_R = crate::R<bool, bool>;
112#[doc = "Write proxy for field `FWUP`"]
113pub struct FWUP_W<'a> {
114    w: &'a mut W,
115}
116impl<'a> FWUP_W<'a> {
117    #[doc = r"Sets the field bit"]
118    #[inline(always)]
119    pub fn set_bit(self) -> &'a mut W {
120        self.bit(true)
121    }
122    #[doc = r"Clears the field bit"]
123    #[inline(always)]
124    pub fn clear_bit(self) -> &'a mut W {
125        self.bit(false)
126    }
127    #[doc = r"Writes raw bits to the field"]
128    #[inline(always)]
129    pub fn bit(self, value: bool) -> &'a mut W {
130        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
131        self.w
132    }
133}
134#[doc = "Possible values of the field `READMODE`"]
135#[derive(Clone, Copy, Debug, PartialEq)]
136pub enum READMODE_A {
137    #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."]
138    NO_MISS_PENALTY,
139    #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."]
140    LOW_POWER,
141    #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."]
142    DETERMINISTIC,
143}
144impl crate::ToBits<u8> for READMODE_A {
145    #[inline(always)]
146    fn _bits(&self) -> u8 {
147        match *self {
148            READMODE_A::NO_MISS_PENALTY => 0,
149            READMODE_A::LOW_POWER => 1,
150            READMODE_A::DETERMINISTIC => 2,
151        }
152    }
153}
154#[doc = "Reader of field `READMODE`"]
155pub type READMODE_R = crate::R<u8, READMODE_A>;
156impl READMODE_R {
157    #[doc = r"Get enumerated values variant"]
158    #[inline(always)]
159    pub fn variant(&self) -> crate::Variant<u8, READMODE_A> {
160        use crate::Variant::*;
161        match self.bits {
162            0 => Val(READMODE_A::NO_MISS_PENALTY),
163            1 => Val(READMODE_A::LOW_POWER),
164            2 => Val(READMODE_A::DETERMINISTIC),
165            i => Res(i),
166        }
167    }
168    #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"]
169    #[inline(always)]
170    pub fn is_no_miss_penalty(&self) -> bool {
171        *self == READMODE_A::NO_MISS_PENALTY
172    }
173    #[doc = "Checks if the value of the field is `LOW_POWER`"]
174    #[inline(always)]
175    pub fn is_low_power(&self) -> bool {
176        *self == READMODE_A::LOW_POWER
177    }
178    #[doc = "Checks if the value of the field is `DETERMINISTIC`"]
179    #[inline(always)]
180    pub fn is_deterministic(&self) -> bool {
181        *self == READMODE_A::DETERMINISTIC
182    }
183}
184#[doc = "Write proxy for field `READMODE`"]
185pub struct READMODE_W<'a> {
186    w: &'a mut W,
187}
188impl<'a> READMODE_W<'a> {
189    #[doc = r"Writes `variant` to the field"]
190    #[inline(always)]
191    pub fn variant(self, variant: READMODE_A) -> &'a mut W {
192        use crate::ToBits;
193        unsafe { self.bits(variant._bits()) }
194    }
195    #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."]
196    #[inline(always)]
197    pub fn no_miss_penalty(self) -> &'a mut W {
198        self.variant(READMODE_A::NO_MISS_PENALTY)
199    }
200    #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."]
201    #[inline(always)]
202    pub fn low_power(self) -> &'a mut W {
203        self.variant(READMODE_A::LOW_POWER)
204    }
205    #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."]
206    #[inline(always)]
207    pub fn deterministic(self) -> &'a mut W {
208        self.variant(READMODE_A::DETERMINISTIC)
209    }
210    #[doc = r"Writes raw bits to the field"]
211    #[inline(always)]
212    pub unsafe fn bits(self, value: u8) -> &'a mut W {
213        self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
214        self.w
215    }
216}
217#[doc = "Reader of field `CACHEDIS`"]
218pub type CACHEDIS_R = crate::R<bool, bool>;
219#[doc = "Write proxy for field `CACHEDIS`"]
220pub struct CACHEDIS_W<'a> {
221    w: &'a mut W,
222}
223impl<'a> CACHEDIS_W<'a> {
224    #[doc = r"Sets the field bit"]
225    #[inline(always)]
226    pub fn set_bit(self) -> &'a mut W {
227        self.bit(true)
228    }
229    #[doc = r"Clears the field bit"]
230    #[inline(always)]
231    pub fn clear_bit(self) -> &'a mut W {
232        self.bit(false)
233    }
234    #[doc = r"Writes raw bits to the field"]
235    #[inline(always)]
236    pub fn bit(self, value: bool) -> &'a mut W {
237        self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
238        self.w
239    }
240}
241#[doc = "Reader of field `QWEN`"]
242pub type QWEN_R = crate::R<bool, bool>;
243#[doc = "Write proxy for field `QWEN`"]
244pub struct QWEN_W<'a> {
245    w: &'a mut W,
246}
247impl<'a> QWEN_W<'a> {
248    #[doc = r"Sets the field bit"]
249    #[inline(always)]
250    pub fn set_bit(self) -> &'a mut W {
251        self.bit(true)
252    }
253    #[doc = r"Clears the field bit"]
254    #[inline(always)]
255    pub fn clear_bit(self) -> &'a mut W {
256        self.bit(false)
257    }
258    #[doc = r"Writes raw bits to the field"]
259    #[inline(always)]
260    pub fn bit(self, value: bool) -> &'a mut W {
261        self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
262        self.w
263    }
264}
265impl R {
266    #[doc = "Bits 1:4 - NVM Read Wait States"]
267    #[inline(always)]
268    pub fn rws(&self) -> RWS_R {
269        RWS_R::new(((self.bits >> 1) & 0x0f) as u8)
270    }
271    #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"]
272    #[inline(always)]
273    pub fn sleepprm(&self) -> SLEEPPRM_R {
274        SLEEPPRM_R::new(((self.bits >> 8) & 0x03) as u8)
275    }
276    #[doc = "Bit 11 - fast wake-up"]
277    #[inline(always)]
278    pub fn fwup(&self) -> FWUP_R {
279        FWUP_R::new(((self.bits >> 11) & 0x01) != 0)
280    }
281    #[doc = "Bits 16:17 - NVMCTRL Read Mode"]
282    #[inline(always)]
283    pub fn readmode(&self) -> READMODE_R {
284        READMODE_R::new(((self.bits >> 16) & 0x03) as u8)
285    }
286    #[doc = "Bit 18 - Cache Disable"]
287    #[inline(always)]
288    pub fn cachedis(&self) -> CACHEDIS_R {
289        CACHEDIS_R::new(((self.bits >> 18) & 0x01) != 0)
290    }
291    #[doc = "Bit 19 - Quick Write Enable"]
292    #[inline(always)]
293    pub fn qwen(&self) -> QWEN_R {
294        QWEN_R::new(((self.bits >> 19) & 0x01) != 0)
295    }
296}
297impl W {
298    #[doc = "Bits 1:4 - NVM Read Wait States"]
299    #[inline(always)]
300    pub fn rws(&mut self) -> RWS_W {
301        RWS_W { w: self }
302    }
303    #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"]
304    #[inline(always)]
305    pub fn sleepprm(&mut self) -> SLEEPPRM_W {
306        SLEEPPRM_W { w: self }
307    }
308    #[doc = "Bit 11 - fast wake-up"]
309    #[inline(always)]
310    pub fn fwup(&mut self) -> FWUP_W {
311        FWUP_W { w: self }
312    }
313    #[doc = "Bits 16:17 - NVMCTRL Read Mode"]
314    #[inline(always)]
315    pub fn readmode(&mut self) -> READMODE_W {
316        READMODE_W { w: self }
317    }
318    #[doc = "Bit 18 - Cache Disable"]
319    #[inline(always)]
320    pub fn cachedis(&mut self) -> CACHEDIS_W {
321        CACHEDIS_W { w: self }
322    }
323    #[doc = "Bit 19 - Quick Write Enable"]
324    #[inline(always)]
325    pub fn qwen(&mut self) -> QWEN_W {
326        QWEN_W { w: self }
327    }
328}
saml10d16a/nvmctrl/ctrlb.rs

saml10d16a/nvmctrl/
ctrlb.rs
