1#[doc = "Reader of register LUTCTRL[%s]"]
2pub type R = crate::R<u32, super::LUTCTRL>;
3#[doc = "Writer for register LUTCTRL[%s]"]
4pub type W = crate::W<u32, super::LUTCTRL>;
5#[doc = "Register LUTCTRL[%s] `reset()`'s with value 0"]
6impl crate::ResetValue for super::LUTCTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `ENABLE`"]
14pub type ENABLE_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `ENABLE`"]
16pub struct ENABLE_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> ENABLE_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
34 self.w
35 }
36}
37#[doc = "Possible values of the field `FILTSEL`"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum FILTSEL_A {
40 #[doc = "Filter disabled"]
41 DISABLE,
42 #[doc = "Synchronizer enabled"]
43 SYNCH,
44 #[doc = "Filter enabled"]
45 FILTER,
46}
47impl crate::ToBits<u8> for FILTSEL_A {
48 #[inline(always)]
49 fn _bits(&self) -> u8 {
50 match *self {
51 FILTSEL_A::DISABLE => 0,
52 FILTSEL_A::SYNCH => 1,
53 FILTSEL_A::FILTER => 2,
54 }
55 }
56}
57#[doc = "Reader of field `FILTSEL`"]
58pub type FILTSEL_R = crate::R<u8, FILTSEL_A>;
59impl FILTSEL_R {
60 #[doc = r"Get enumerated values variant"]
61 #[inline(always)]
62 pub fn variant(&self) -> crate::Variant<u8, FILTSEL_A> {
63 use crate::Variant::*;
64 match self.bits {
65 0 => Val(FILTSEL_A::DISABLE),
66 1 => Val(FILTSEL_A::SYNCH),
67 2 => Val(FILTSEL_A::FILTER),
68 i => Res(i),
69 }
70 }
71 #[doc = "Checks if the value of the field is `DISABLE`"]
72 #[inline(always)]
73 pub fn is_disable(&self) -> bool {
74 *self == FILTSEL_A::DISABLE
75 }
76 #[doc = "Checks if the value of the field is `SYNCH`"]
77 #[inline(always)]
78 pub fn is_synch(&self) -> bool {
79 *self == FILTSEL_A::SYNCH
80 }
81 #[doc = "Checks if the value of the field is `FILTER`"]
82 #[inline(always)]
83 pub fn is_filter(&self) -> bool {
84 *self == FILTSEL_A::FILTER
85 }
86}
87#[doc = "Write proxy for field `FILTSEL`"]
88pub struct FILTSEL_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> FILTSEL_W<'a> {
92 #[doc = r"Writes `variant` to the field"]
93 #[inline(always)]
94 pub fn variant(self, variant: FILTSEL_A) -> &'a mut W {
95 use crate::ToBits;
96 unsafe { self.bits(variant._bits()) }
97 }
98 #[doc = "Filter disabled"]
99 #[inline(always)]
100 pub fn disable(self) -> &'a mut W {
101 self.variant(FILTSEL_A::DISABLE)
102 }
103 #[doc = "Synchronizer enabled"]
104 #[inline(always)]
105 pub fn synch(self) -> &'a mut W {
106 self.variant(FILTSEL_A::SYNCH)
107 }
108 #[doc = "Filter enabled"]
109 #[inline(always)]
110 pub fn filter(self) -> &'a mut W {
111 self.variant(FILTSEL_A::FILTER)
112 }
113 #[doc = r"Writes raw bits to the field"]
114 #[inline(always)]
115 pub unsafe fn bits(self, value: u8) -> &'a mut W {
116 self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
117 self.w
118 }
119}
120#[doc = "Reader of field `EDGESEL`"]
121pub type EDGESEL_R = crate::R<bool, bool>;
122#[doc = "Write proxy for field `EDGESEL`"]
123pub struct EDGESEL_W<'a> {
124 w: &'a mut W,
125}
126impl<'a> EDGESEL_W<'a> {
127 #[doc = r"Sets the field bit"]
128 #[inline(always)]
129 pub fn set_bit(self) -> &'a mut W {
130 self.bit(true)
131 }
132 #[doc = r"Clears the field bit"]
133 #[inline(always)]
134 pub fn clear_bit(self) -> &'a mut W {
135 self.bit(false)
136 }
137 #[doc = r"Writes raw bits to the field"]
138 #[inline(always)]
139 pub fn bit(self, value: bool) -> &'a mut W {
140 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
141 self.w
142 }
143}
144#[doc = "Possible values of the field `INSEL0`"]
145#[derive(Clone, Copy, Debug, PartialEq)]
146pub enum INSEL0_A {
147 #[doc = "Masked input"]
148 MASK,
149 #[doc = "Feedback input source"]
150 FEEDBACK,
151 #[doc = "Linked LUT input source"]
152 LINK,
153 #[doc = "Event input source"]
154 EVENT,
155 #[doc = "I/O pin input source"]
156 IO,
157 #[doc = "AC input source"]
158 AC,
159 #[doc = "TC input source"]
160 TC,
161 #[doc = "Alternate TC input source"]
162 ALTTC,
163 #[doc = "TCC input source"]
164 TCC,
165 #[doc = "SERCOM input source"]
166 SERCOM,
167 #[doc = "Alternate 2 TC input source"]
168 ALT2TC,
169 #[doc = "Asynchronous event input source. The EVENT input will bypass edge detection logic."]
170 ASYNCEVENT,
171}
172impl crate::ToBits<u8> for INSEL0_A {
173 #[inline(always)]
174 fn _bits(&self) -> u8 {
175 match *self {
176 INSEL0_A::MASK => 0,
177 INSEL0_A::FEEDBACK => 1,
178 INSEL0_A::LINK => 2,
179 INSEL0_A::EVENT => 3,
180 INSEL0_A::IO => 4,
181 INSEL0_A::AC => 5,
182 INSEL0_A::TC => 6,
183 INSEL0_A::ALTTC => 7,
184 INSEL0_A::TCC => 8,
185 INSEL0_A::SERCOM => 9,
186 INSEL0_A::ALT2TC => 10,
187 INSEL0_A::ASYNCEVENT => 11,
188 }
189 }
190}
191#[doc = "Reader of field `INSEL0`"]
192pub type INSEL0_R = crate::R<u8, INSEL0_A>;
193impl INSEL0_R {
194 #[doc = r"Get enumerated values variant"]
195 #[inline(always)]
196 pub fn variant(&self) -> crate::Variant<u8, INSEL0_A> {
197 use crate::Variant::*;
198 match self.bits {
199 0 => Val(INSEL0_A::MASK),
200 1 => Val(INSEL0_A::FEEDBACK),
201 2 => Val(INSEL0_A::LINK),
202 3 => Val(INSEL0_A::EVENT),
203 4 => Val(INSEL0_A::IO),
204 5 => Val(INSEL0_A::AC),
205 6 => Val(INSEL0_A::TC),
206 7 => Val(INSEL0_A::ALTTC),
207 8 => Val(INSEL0_A::TCC),
208 9 => Val(INSEL0_A::SERCOM),
209 10 => Val(INSEL0_A::ALT2TC),
210 11 => Val(INSEL0_A::ASYNCEVENT),
211 i => Res(i),
212 }
213 }
214 #[doc = "Checks if the value of the field is `MASK`"]
215 #[inline(always)]
216 pub fn is_mask(&self) -> bool {
217 *self == INSEL0_A::MASK
218 }
219 #[doc = "Checks if the value of the field is `FEEDBACK`"]
220 #[inline(always)]
221 pub fn is_feedback(&self) -> bool {
222 *self == INSEL0_A::FEEDBACK
223 }
224 #[doc = "Checks if the value of the field is `LINK`"]
225 #[inline(always)]
226 pub fn is_link(&self) -> bool {
227 *self == INSEL0_A::LINK
228 }
229 #[doc = "Checks if the value of the field is `EVENT`"]
230 #[inline(always)]
231 pub fn is_event(&self) -> bool {
232 *self == INSEL0_A::EVENT
233 }
234 #[doc = "Checks if the value of the field is `IO`"]
235 #[inline(always)]
236 pub fn is_io(&self) -> bool {
237 *self == INSEL0_A::IO
238 }
239 #[doc = "Checks if the value of the field is `AC`"]
240 #[inline(always)]
241 pub fn is_ac(&self) -> bool {
242 *self == INSEL0_A::AC
243 }
244 #[doc = "Checks if the value of the field is `TC`"]
245 #[inline(always)]
246 pub fn is_tc(&self) -> bool {
247 *self == INSEL0_A::TC
248 }
249 #[doc = "Checks if the value of the field is `ALTTC`"]
250 #[inline(always)]
251 pub fn is_alttc(&self) -> bool {
252 *self == INSEL0_A::ALTTC
253 }
254 #[doc = "Checks if the value of the field is `TCC`"]
255 #[inline(always)]
256 pub fn is_tcc(&self) -> bool {
257 *self == INSEL0_A::TCC
258 }
259 #[doc = "Checks if the value of the field is `SERCOM`"]
260 #[inline(always)]
261 pub fn is_sercom(&self) -> bool {
262 *self == INSEL0_A::SERCOM
263 }
264 #[doc = "Checks if the value of the field is `ALT2TC`"]
265 #[inline(always)]
266 pub fn is_alt2tc(&self) -> bool {
267 *self == INSEL0_A::ALT2TC
268 }
269 #[doc = "Checks if the value of the field is `ASYNCEVENT`"]
270 #[inline(always)]
271 pub fn is_asyncevent(&self) -> bool {
272 *self == INSEL0_A::ASYNCEVENT
273 }
274}
275#[doc = "Write proxy for field `INSEL0`"]
276pub struct INSEL0_W<'a> {
277 w: &'a mut W,
278}
279impl<'a> INSEL0_W<'a> {
280 #[doc = r"Writes `variant` to the field"]
281 #[inline(always)]
282 pub fn variant(self, variant: INSEL0_A) -> &'a mut W {
283 use crate::ToBits;
284 unsafe { self.bits(variant._bits()) }
285 }
286 #[doc = "Masked input"]
287 #[inline(always)]
288 pub fn mask(self) -> &'a mut W {
289 self.variant(INSEL0_A::MASK)
290 }
291 #[doc = "Feedback input source"]
292 #[inline(always)]
293 pub fn feedback(self) -> &'a mut W {
294 self.variant(INSEL0_A::FEEDBACK)
295 }
296 #[doc = "Linked LUT input source"]
297 #[inline(always)]
298 pub fn link(self) -> &'a mut W {
299 self.variant(INSEL0_A::LINK)
300 }
301 #[doc = "Event input source"]
302 #[inline(always)]
303 pub fn event(self) -> &'a mut W {
304 self.variant(INSEL0_A::EVENT)
305 }
306 #[doc = "I/O pin input source"]
307 #[inline(always)]
308 pub fn io(self) -> &'a mut W {
309 self.variant(INSEL0_A::IO)
310 }
311 #[doc = "AC input source"]
312 #[inline(always)]
313 pub fn ac(self) -> &'a mut W {
314 self.variant(INSEL0_A::AC)
315 }
316 #[doc = "TC input source"]
317 #[inline(always)]
318 pub fn tc(self) -> &'a mut W {
319 self.variant(INSEL0_A::TC)
320 }
321 #[doc = "Alternate TC input source"]
322 #[inline(always)]
323 pub fn alttc(self) -> &'a mut W {
324 self.variant(INSEL0_A::ALTTC)
325 }
326 #[doc = "TCC input source"]
327 #[inline(always)]
328 pub fn tcc(self) -> &'a mut W {
329 self.variant(INSEL0_A::TCC)
330 }
331 #[doc = "SERCOM input source"]
332 #[inline(always)]
333 pub fn sercom(self) -> &'a mut W {
334 self.variant(INSEL0_A::SERCOM)
335 }
336 #[doc = "Alternate 2 TC input source"]
337 #[inline(always)]
338 pub fn alt2tc(self) -> &'a mut W {
339 self.variant(INSEL0_A::ALT2TC)
340 }
341 #[doc = "Asynchronous event input source. The EVENT input will bypass edge detection logic."]
342 #[inline(always)]
343 pub fn asyncevent(self) -> &'a mut W {
344 self.variant(INSEL0_A::ASYNCEVENT)
345 }
346 #[doc = r"Writes raw bits to the field"]
347 #[inline(always)]
348 pub unsafe fn bits(self, value: u8) -> &'a mut W {
349 self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
350 self.w
351 }
352}
353#[doc = "Possible values of the field `INSEL1`"]
354#[derive(Clone, Copy, Debug, PartialEq)]
355pub enum INSEL1_A {
356 #[doc = "Masked input"]
357 MASK,
358 #[doc = "Feedback input source"]
359 FEEDBACK,
360 #[doc = "Linked LUT input source"]
361 LINK,
362 #[doc = "Event input source"]
363 EVENT,
364 #[doc = "I/O pin input source"]
365 IO,
366 #[doc = "AC input source"]
367 AC,
368 #[doc = "TC input source"]
369 TC,
370 #[doc = "Alternate TC input source"]
371 ALTTC,
372 #[doc = "TCC input source"]
373 TCC,
374 #[doc = "SERCOM input source"]
375 SERCOM,
376 #[doc = "Alternate 2 TC input source"]
377 ALT2TC,
378 #[doc = "Asynchronous event input source. The EVENT input will bypass edge detection logic."]
379 ASYNCEVENT,
380}
381impl crate::ToBits<u8> for INSEL1_A {
382 #[inline(always)]
383 fn _bits(&self) -> u8 {
384 match *self {
385 INSEL1_A::MASK => 0,
386 INSEL1_A::FEEDBACK => 1,
387 INSEL1_A::LINK => 2,
388 INSEL1_A::EVENT => 3,
389 INSEL1_A::IO => 4,
390 INSEL1_A::AC => 5,
391 INSEL1_A::TC => 6,
392 INSEL1_A::ALTTC => 7,
393 INSEL1_A::TCC => 8,
394 INSEL1_A::SERCOM => 9,
395 INSEL1_A::ALT2TC => 10,
396 INSEL1_A::ASYNCEVENT => 11,
397 }
398 }
399}
400#[doc = "Reader of field `INSEL1`"]
401pub type INSEL1_R = crate::R<u8, INSEL1_A>;
402impl INSEL1_R {
403 #[doc = r"Get enumerated values variant"]
404 #[inline(always)]
405 pub fn variant(&self) -> crate::Variant<u8, INSEL1_A> {
406 use crate::Variant::*;
407 match self.bits {
408 0 => Val(INSEL1_A::MASK),
409 1 => Val(INSEL1_A::FEEDBACK),
410 2 => Val(INSEL1_A::LINK),
411 3 => Val(INSEL1_A::EVENT),
412 4 => Val(INSEL1_A::IO),
413 5 => Val(INSEL1_A::AC),
414 6 => Val(INSEL1_A::TC),
415 7 => Val(INSEL1_A::ALTTC),
416 8 => Val(INSEL1_A::TCC),
417 9 => Val(INSEL1_A::SERCOM),
418 10 => Val(INSEL1_A::ALT2TC),
419 11 => Val(INSEL1_A::ASYNCEVENT),
420 i => Res(i),
421 }
422 }
423 #[doc = "Checks if the value of the field is `MASK`"]
424 #[inline(always)]
425 pub fn is_mask(&self) -> bool {
426 *self == INSEL1_A::MASK
427 }
428 #[doc = "Checks if the value of the field is `FEEDBACK`"]
429 #[inline(always)]
430 pub fn is_feedback(&self) -> bool {
431 *self == INSEL1_A::FEEDBACK
432 }
433 #[doc = "Checks if the value of the field is `LINK`"]
434 #[inline(always)]
435 pub fn is_link(&self) -> bool {
436 *self == INSEL1_A::LINK
437 }
438 #[doc = "Checks if the value of the field is `EVENT`"]
439 #[inline(always)]
440 pub fn is_event(&self) -> bool {
441 *self == INSEL1_A::EVENT
442 }
443 #[doc = "Checks if the value of the field is `IO`"]
444 #[inline(always)]
445 pub fn is_io(&self) -> bool {
446 *self == INSEL1_A::IO
447 }
448 #[doc = "Checks if the value of the field is `AC`"]
449 #[inline(always)]
450 pub fn is_ac(&self) -> bool {
451 *self == INSEL1_A::AC
452 }
453 #[doc = "Checks if the value of the field is `TC`"]
454 #[inline(always)]
455 pub fn is_tc(&self) -> bool {
456 *self == INSEL1_A::TC
457 }
458 #[doc = "Checks if the value of the field is `ALTTC`"]
459 #[inline(always)]
460 pub fn is_alttc(&self) -> bool {
461 *self == INSEL1_A::ALTTC
462 }
463 #[doc = "Checks if the value of the field is `TCC`"]
464 #[inline(always)]
465 pub fn is_tcc(&self) -> bool {
466 *self == INSEL1_A::TCC
467 }
468 #[doc = "Checks if the value of the field is `SERCOM`"]
469 #[inline(always)]
470 pub fn is_sercom(&self) -> bool {
471 *self == INSEL1_A::SERCOM
472 }
473 #[doc = "Checks if the value of the field is `ALT2TC`"]
474 #[inline(always)]
475 pub fn is_alt2tc(&self) -> bool {
476 *self == INSEL1_A::ALT2TC
477 }
478 #[doc = "Checks if the value of the field is `ASYNCEVENT`"]
479 #[inline(always)]
480 pub fn is_asyncevent(&self) -> bool {
481 *self == INSEL1_A::ASYNCEVENT
482 }
483}
484#[doc = "Write proxy for field `INSEL1`"]
485pub struct INSEL1_W<'a> {
486 w: &'a mut W,
487}
488impl<'a> INSEL1_W<'a> {
489 #[doc = r"Writes `variant` to the field"]
490 #[inline(always)]
491 pub fn variant(self, variant: INSEL1_A) -> &'a mut W {
492 use crate::ToBits;
493 unsafe { self.bits(variant._bits()) }
494 }
495 #[doc = "Masked input"]
496 #[inline(always)]
497 pub fn mask(self) -> &'a mut W {
498 self.variant(INSEL1_A::MASK)
499 }
500 #[doc = "Feedback input source"]
501 #[inline(always)]
502 pub fn feedback(self) -> &'a mut W {
503 self.variant(INSEL1_A::FEEDBACK)
504 }
505 #[doc = "Linked LUT input source"]
506 #[inline(always)]
507 pub fn link(self) -> &'a mut W {
508 self.variant(INSEL1_A::LINK)
509 }
510 #[doc = "Event input source"]
511 #[inline(always)]
512 pub fn event(self) -> &'a mut W {
513 self.variant(INSEL1_A::EVENT)
514 }
515 #[doc = "I/O pin input source"]
516 #[inline(always)]
517 pub fn io(self) -> &'a mut W {
518 self.variant(INSEL1_A::IO)
519 }
520 #[doc = "AC input source"]
521 #[inline(always)]
522 pub fn ac(self) -> &'a mut W {
523 self.variant(INSEL1_A::AC)
524 }
525 #[doc = "TC input source"]
526 #[inline(always)]
527 pub fn tc(self) -> &'a mut W {
528 self.variant(INSEL1_A::TC)
529 }
530 #[doc = "Alternate TC input source"]
531 #[inline(always)]
532 pub fn alttc(self) -> &'a mut W {
533 self.variant(INSEL1_A::ALTTC)
534 }
535 #[doc = "TCC input source"]
536 #[inline(always)]
537 pub fn tcc(self) -> &'a mut W {
538 self.variant(INSEL1_A::TCC)
539 }
540 #[doc = "SERCOM input source"]
541 #[inline(always)]
542 pub fn sercom(self) -> &'a mut W {
543 self.variant(INSEL1_A::SERCOM)
544 }
545 #[doc = "Alternate 2 TC input source"]
546 #[inline(always)]
547 pub fn alt2tc(self) -> &'a mut W {
548 self.variant(INSEL1_A::ALT2TC)
549 }
550 #[doc = "Asynchronous event input source. The EVENT input will bypass edge detection logic."]
551 #[inline(always)]
552 pub fn asyncevent(self) -> &'a mut W {
553 self.variant(INSEL1_A::ASYNCEVENT)
554 }
555 #[doc = r"Writes raw bits to the field"]
556 #[inline(always)]
557 pub unsafe fn bits(self, value: u8) -> &'a mut W {
558 self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
559 self.w
560 }
561}
562#[doc = "Possible values of the field `INSEL2`"]
563#[derive(Clone, Copy, Debug, PartialEq)]
564pub enum INSEL2_A {
565 #[doc = "Masked input"]
566 MASK,
567 #[doc = "Feedback input source"]
568 FEEDBACK,
569 #[doc = "Linked LUT input source"]
570 LINK,
571 #[doc = "Event input source"]
572 EVENT,
573 #[doc = "I/O pin input source"]
574 IO,
575 #[doc = "AC input source"]
576 AC,
577 #[doc = "TC input source"]
578 TC,
579 #[doc = "Alternate TC input source"]
580 ALTTC,
581 #[doc = "TCC input source"]
582 TCC,
583 #[doc = "SERCOM input source"]
584 SERCOM,
585 #[doc = "Alternate 2 TC input source"]
586 ALT2TC,
587 #[doc = "Asynchronous event input source. The EVENT input will bypass edge detection logic."]
588 ASYNCEVENT,
589}
590impl crate::ToBits<u8> for INSEL2_A {
591 #[inline(always)]
592 fn _bits(&self) -> u8 {
593 match *self {
594 INSEL2_A::MASK => 0,
595 INSEL2_A::FEEDBACK => 1,
596 INSEL2_A::LINK => 2,
597 INSEL2_A::EVENT => 3,
598 INSEL2_A::IO => 4,
599 INSEL2_A::AC => 5,
600 INSEL2_A::TC => 6,
601 INSEL2_A::ALTTC => 7,
602 INSEL2_A::TCC => 8,
603 INSEL2_A::SERCOM => 9,
604 INSEL2_A::ALT2TC => 10,
605 INSEL2_A::ASYNCEVENT => 11,
606 }
607 }
608}
609#[doc = "Reader of field `INSEL2`"]
610pub type INSEL2_R = crate::R<u8, INSEL2_A>;
611impl INSEL2_R {
612 #[doc = r"Get enumerated values variant"]
613 #[inline(always)]
614 pub fn variant(&self) -> crate::Variant<u8, INSEL2_A> {
615 use crate::Variant::*;
616 match self.bits {
617 0 => Val(INSEL2_A::MASK),
618 1 => Val(INSEL2_A::FEEDBACK),
619 2 => Val(INSEL2_A::LINK),
620 3 => Val(INSEL2_A::EVENT),
621 4 => Val(INSEL2_A::IO),
622 5 => Val(INSEL2_A::AC),
623 6 => Val(INSEL2_A::TC),
624 7 => Val(INSEL2_A::ALTTC),
625 8 => Val(INSEL2_A::TCC),
626 9 => Val(INSEL2_A::SERCOM),
627 10 => Val(INSEL2_A::ALT2TC),
628 11 => Val(INSEL2_A::ASYNCEVENT),
629 i => Res(i),
630 }
631 }
632 #[doc = "Checks if the value of the field is `MASK`"]
633 #[inline(always)]
634 pub fn is_mask(&self) -> bool {
635 *self == INSEL2_A::MASK
636 }
637 #[doc = "Checks if the value of the field is `FEEDBACK`"]
638 #[inline(always)]
639 pub fn is_feedback(&self) -> bool {
640 *self == INSEL2_A::FEEDBACK
641 }
642 #[doc = "Checks if the value of the field is `LINK`"]
643 #[inline(always)]
644 pub fn is_link(&self) -> bool {
645 *self == INSEL2_A::LINK
646 }
647 #[doc = "Checks if the value of the field is `EVENT`"]
648 #[inline(always)]
649 pub fn is_event(&self) -> bool {
650 *self == INSEL2_A::EVENT
651 }
652 #[doc = "Checks if the value of the field is `IO`"]
653 #[inline(always)]
654 pub fn is_io(&self) -> bool {
655 *self == INSEL2_A::IO
656 }
657 #[doc = "Checks if the value of the field is `AC`"]
658 #[inline(always)]
659 pub fn is_ac(&self) -> bool {
660 *self == INSEL2_A::AC
661 }
662 #[doc = "Checks if the value of the field is `TC`"]
663 #[inline(always)]
664 pub fn is_tc(&self) -> bool {
665 *self == INSEL2_A::TC
666 }
667 #[doc = "Checks if the value of the field is `ALTTC`"]
668 #[inline(always)]
669 pub fn is_alttc(&self) -> bool {
670 *self == INSEL2_A::ALTTC
671 }
672 #[doc = "Checks if the value of the field is `TCC`"]
673 #[inline(always)]
674 pub fn is_tcc(&self) -> bool {
675 *self == INSEL2_A::TCC
676 }
677 #[doc = "Checks if the value of the field is `SERCOM`"]
678 #[inline(always)]
679 pub fn is_sercom(&self) -> bool {
680 *self == INSEL2_A::SERCOM
681 }
682 #[doc = "Checks if the value of the field is `ALT2TC`"]
683 #[inline(always)]
684 pub fn is_alt2tc(&self) -> bool {
685 *self == INSEL2_A::ALT2TC
686 }
687 #[doc = "Checks if the value of the field is `ASYNCEVENT`"]
688 #[inline(always)]
689 pub fn is_asyncevent(&self) -> bool {
690 *self == INSEL2_A::ASYNCEVENT
691 }
692}
693#[doc = "Write proxy for field `INSEL2`"]
694pub struct INSEL2_W<'a> {
695 w: &'a mut W,
696}
697impl<'a> INSEL2_W<'a> {
698 #[doc = r"Writes `variant` to the field"]
699 #[inline(always)]
700 pub fn variant(self, variant: INSEL2_A) -> &'a mut W {
701 use crate::ToBits;
702 unsafe { self.bits(variant._bits()) }
703 }
704 #[doc = "Masked input"]
705 #[inline(always)]
706 pub fn mask(self) -> &'a mut W {
707 self.variant(INSEL2_A::MASK)
708 }
709 #[doc = "Feedback input source"]
710 #[inline(always)]
711 pub fn feedback(self) -> &'a mut W {
712 self.variant(INSEL2_A::FEEDBACK)
713 }
714 #[doc = "Linked LUT input source"]
715 #[inline(always)]
716 pub fn link(self) -> &'a mut W {
717 self.variant(INSEL2_A::LINK)
718 }
719 #[doc = "Event input source"]
720 #[inline(always)]
721 pub fn event(self) -> &'a mut W {
722 self.variant(INSEL2_A::EVENT)
723 }
724 #[doc = "I/O pin input source"]
725 #[inline(always)]
726 pub fn io(self) -> &'a mut W {
727 self.variant(INSEL2_A::IO)
728 }
729 #[doc = "AC input source"]
730 #[inline(always)]
731 pub fn ac(self) -> &'a mut W {
732 self.variant(INSEL2_A::AC)
733 }
734 #[doc = "TC input source"]
735 #[inline(always)]
736 pub fn tc(self) -> &'a mut W {
737 self.variant(INSEL2_A::TC)
738 }
739 #[doc = "Alternate TC input source"]
740 #[inline(always)]
741 pub fn alttc(self) -> &'a mut W {
742 self.variant(INSEL2_A::ALTTC)
743 }
744 #[doc = "TCC input source"]
745 #[inline(always)]
746 pub fn tcc(self) -> &'a mut W {
747 self.variant(INSEL2_A::TCC)
748 }
749 #[doc = "SERCOM input source"]
750 #[inline(always)]
751 pub fn sercom(self) -> &'a mut W {
752 self.variant(INSEL2_A::SERCOM)
753 }
754 #[doc = "Alternate 2 TC input source"]
755 #[inline(always)]
756 pub fn alt2tc(self) -> &'a mut W {
757 self.variant(INSEL2_A::ALT2TC)
758 }
759 #[doc = "Asynchronous event input source. The EVENT input will bypass edge detection logic."]
760 #[inline(always)]
761 pub fn asyncevent(self) -> &'a mut W {
762 self.variant(INSEL2_A::ASYNCEVENT)
763 }
764 #[doc = r"Writes raw bits to the field"]
765 #[inline(always)]
766 pub unsafe fn bits(self, value: u8) -> &'a mut W {
767 self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
768 self.w
769 }
770}
771#[doc = "Reader of field `INVEI`"]
772pub type INVEI_R = crate::R<bool, bool>;
773#[doc = "Write proxy for field `INVEI`"]
774pub struct INVEI_W<'a> {
775 w: &'a mut W,
776}
777impl<'a> INVEI_W<'a> {
778 #[doc = r"Sets the field bit"]
779 #[inline(always)]
780 pub fn set_bit(self) -> &'a mut W {
781 self.bit(true)
782 }
783 #[doc = r"Clears the field bit"]
784 #[inline(always)]
785 pub fn clear_bit(self) -> &'a mut W {
786 self.bit(false)
787 }
788 #[doc = r"Writes raw bits to the field"]
789 #[inline(always)]
790 pub fn bit(self, value: bool) -> &'a mut W {
791 self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
792 self.w
793 }
794}
795#[doc = "Reader of field `LUTEI`"]
796pub type LUTEI_R = crate::R<bool, bool>;
797#[doc = "Write proxy for field `LUTEI`"]
798pub struct LUTEI_W<'a> {
799 w: &'a mut W,
800}
801impl<'a> LUTEI_W<'a> {
802 #[doc = r"Sets the field bit"]
803 #[inline(always)]
804 pub fn set_bit(self) -> &'a mut W {
805 self.bit(true)
806 }
807 #[doc = r"Clears the field bit"]
808 #[inline(always)]
809 pub fn clear_bit(self) -> &'a mut W {
810 self.bit(false)
811 }
812 #[doc = r"Writes raw bits to the field"]
813 #[inline(always)]
814 pub fn bit(self, value: bool) -> &'a mut W {
815 self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
816 self.w
817 }
818}
819#[doc = "Reader of field `LUTEO`"]
820pub type LUTEO_R = crate::R<bool, bool>;
821#[doc = "Write proxy for field `LUTEO`"]
822pub struct LUTEO_W<'a> {
823 w: &'a mut W,
824}
825impl<'a> LUTEO_W<'a> {
826 #[doc = r"Sets the field bit"]
827 #[inline(always)]
828 pub fn set_bit(self) -> &'a mut W {
829 self.bit(true)
830 }
831 #[doc = r"Clears the field bit"]
832 #[inline(always)]
833 pub fn clear_bit(self) -> &'a mut W {
834 self.bit(false)
835 }
836 #[doc = r"Writes raw bits to the field"]
837 #[inline(always)]
838 pub fn bit(self, value: bool) -> &'a mut W {
839 self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
840 self.w
841 }
842}
843#[doc = "Reader of field `TRUTH`"]
844pub type TRUTH_R = crate::R<u8, u8>;
845#[doc = "Write proxy for field `TRUTH`"]
846pub struct TRUTH_W<'a> {
847 w: &'a mut W,
848}
849impl<'a> TRUTH_W<'a> {
850 #[doc = r"Writes raw bits to the field"]
851 #[inline(always)]
852 pub unsafe fn bits(self, value: u8) -> &'a mut W {
853 self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
854 self.w
855 }
856}
857impl R {
858 #[doc = "Bit 1 - LUT Enable"]
859 #[inline(always)]
860 pub fn enable(&self) -> ENABLE_R {
861 ENABLE_R::new(((self.bits >> 1) & 0x01) != 0)
862 }
863 #[doc = "Bits 4:5 - Filter Selection"]
864 #[inline(always)]
865 pub fn filtsel(&self) -> FILTSEL_R {
866 FILTSEL_R::new(((self.bits >> 4) & 0x03) as u8)
867 }
868 #[doc = "Bit 7 - Edge Selection"]
869 #[inline(always)]
870 pub fn edgesel(&self) -> EDGESEL_R {
871 EDGESEL_R::new(((self.bits >> 7) & 0x01) != 0)
872 }
873 #[doc = "Bits 8:11 - Input Selection 0"]
874 #[inline(always)]
875 pub fn insel0(&self) -> INSEL0_R {
876 INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8)
877 }
878 #[doc = "Bits 12:15 - Input Selection 1"]
879 #[inline(always)]
880 pub fn insel1(&self) -> INSEL1_R {
881 INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8)
882 }
883 #[doc = "Bits 16:19 - Input Selection 2"]
884 #[inline(always)]
885 pub fn insel2(&self) -> INSEL2_R {
886 INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8)
887 }
888 #[doc = "Bit 20 - Inverted Event Input Enable"]
889 #[inline(always)]
890 pub fn invei(&self) -> INVEI_R {
891 INVEI_R::new(((self.bits >> 20) & 0x01) != 0)
892 }
893 #[doc = "Bit 21 - LUT Event Input Enable"]
894 #[inline(always)]
895 pub fn lutei(&self) -> LUTEI_R {
896 LUTEI_R::new(((self.bits >> 21) & 0x01) != 0)
897 }
898 #[doc = "Bit 22 - LUT Event Output Enable"]
899 #[inline(always)]
900 pub fn luteo(&self) -> LUTEO_R {
901 LUTEO_R::new(((self.bits >> 22) & 0x01) != 0)
902 }
903 #[doc = "Bits 24:31 - Truth Value"]
904 #[inline(always)]
905 pub fn truth(&self) -> TRUTH_R {
906 TRUTH_R::new(((self.bits >> 24) & 0xff) as u8)
907 }
908}
909impl W {
910 #[doc = "Bit 1 - LUT Enable"]
911 #[inline(always)]
912 pub fn enable(&mut self) -> ENABLE_W {
913 ENABLE_W { w: self }
914 }
915 #[doc = "Bits 4:5 - Filter Selection"]
916 #[inline(always)]
917 pub fn filtsel(&mut self) -> FILTSEL_W {
918 FILTSEL_W { w: self }
919 }
920 #[doc = "Bit 7 - Edge Selection"]
921 #[inline(always)]
922 pub fn edgesel(&mut self) -> EDGESEL_W {
923 EDGESEL_W { w: self }
924 }
925 #[doc = "Bits 8:11 - Input Selection 0"]
926 #[inline(always)]
927 pub fn insel0(&mut self) -> INSEL0_W {
928 INSEL0_W { w: self }
929 }
930 #[doc = "Bits 12:15 - Input Selection 1"]
931 #[inline(always)]
932 pub fn insel1(&mut self) -> INSEL1_W {
933 INSEL1_W { w: self }
934 }
935 #[doc = "Bits 16:19 - Input Selection 2"]
936 #[inline(always)]
937 pub fn insel2(&mut self) -> INSEL2_W {
938 INSEL2_W { w: self }
939 }
940 #[doc = "Bit 20 - Inverted Event Input Enable"]
941 #[inline(always)]
942 pub fn invei(&mut self) -> INVEI_W {
943 INVEI_W { w: self }
944 }
945 #[doc = "Bit 21 - LUT Event Input Enable"]
946 #[inline(always)]
947 pub fn lutei(&mut self) -> LUTEI_W {
948 LUTEI_W { w: self }
949 }
950 #[doc = "Bit 22 - LUT Event Output Enable"]
951 #[inline(always)]
952 pub fn luteo(&mut self) -> LUTEO_W {
953 LUTEO_W { w: self }
954 }
955 #[doc = "Bits 24:31 - Truth Value"]
956 #[inline(always)]
957 pub fn truth(&mut self) -> TRUTH_W {
958 TRUTH_W { w: self }
959 }
960}