saml10d16a/port/group/
evctrl.rs

1#[doc = "Reader of register EVCTRL"]
2pub type R = crate::R<u32, super::EVCTRL>;
3#[doc = "Writer for register EVCTRL"]
4pub type W = crate::W<u32, super::EVCTRL>;
5#[doc = "Register EVCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::EVCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `PID0`"]
14pub type PID0_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `PID0`"]
16pub struct PID0_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> PID0_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
24        self.w
25    }
26}
27#[doc = "Possible values of the field `EVACT0`"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29pub enum EVACT0_A {
30    #[doc = "Event output to pin"]
31    OUT,
32    #[doc = "Set output register of pin on event"]
33    SET,
34    #[doc = "Clear output register of pin on event"]
35    CLR,
36    #[doc = "Toggle output register of pin on event"]
37    TGL,
38}
39impl crate::ToBits<u8> for EVACT0_A {
40    #[inline(always)]
41    fn _bits(&self) -> u8 {
42        match *self {
43            EVACT0_A::OUT => 0,
44            EVACT0_A::SET => 1,
45            EVACT0_A::CLR => 2,
46            EVACT0_A::TGL => 3,
47        }
48    }
49}
50#[doc = "Reader of field `EVACT0`"]
51pub type EVACT0_R = crate::R<u8, EVACT0_A>;
52impl EVACT0_R {
53    #[doc = r"Get enumerated values variant"]
54    #[inline(always)]
55    pub fn variant(&self) -> EVACT0_A {
56        match self.bits {
57            0 => EVACT0_A::OUT,
58            1 => EVACT0_A::SET,
59            2 => EVACT0_A::CLR,
60            3 => EVACT0_A::TGL,
61            _ => unreachable!(),
62        }
63    }
64    #[doc = "Checks if the value of the field is `OUT`"]
65    #[inline(always)]
66    pub fn is_out(&self) -> bool {
67        *self == EVACT0_A::OUT
68    }
69    #[doc = "Checks if the value of the field is `SET`"]
70    #[inline(always)]
71    pub fn is_set(&self) -> bool {
72        *self == EVACT0_A::SET
73    }
74    #[doc = "Checks if the value of the field is `CLR`"]
75    #[inline(always)]
76    pub fn is_clr(&self) -> bool {
77        *self == EVACT0_A::CLR
78    }
79    #[doc = "Checks if the value of the field is `TGL`"]
80    #[inline(always)]
81    pub fn is_tgl(&self) -> bool {
82        *self == EVACT0_A::TGL
83    }
84}
85#[doc = "Write proxy for field `EVACT0`"]
86pub struct EVACT0_W<'a> {
87    w: &'a mut W,
88}
89impl<'a> EVACT0_W<'a> {
90    #[doc = r"Writes `variant` to the field"]
91    #[inline(always)]
92    pub fn variant(self, variant: EVACT0_A) -> &'a mut W {
93        use crate::ToBits;
94        {
95            self.bits(variant._bits())
96        }
97    }
98    #[doc = "Event output to pin"]
99    #[inline(always)]
100    pub fn out(self) -> &'a mut W {
101        self.variant(EVACT0_A::OUT)
102    }
103    #[doc = "Set output register of pin on event"]
104    #[inline(always)]
105    pub fn set(self) -> &'a mut W {
106        self.variant(EVACT0_A::SET)
107    }
108    #[doc = "Clear output register of pin on event"]
109    #[inline(always)]
110    pub fn clr(self) -> &'a mut W {
111        self.variant(EVACT0_A::CLR)
112    }
113    #[doc = "Toggle output register of pin on event"]
114    #[inline(always)]
115    pub fn tgl(self) -> &'a mut W {
116        self.variant(EVACT0_A::TGL)
117    }
118    #[doc = r"Writes raw bits to the field"]
119    #[inline(always)]
120    pub fn bits(self, value: u8) -> &'a mut W {
121        self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
122        self.w
123    }
124}
125#[doc = "Reader of field `PORTEI0`"]
126pub type PORTEI0_R = crate::R<bool, bool>;
127#[doc = "Write proxy for field `PORTEI0`"]
128pub struct PORTEI0_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> PORTEI0_W<'a> {
132    #[doc = r"Sets the field bit"]
133    #[inline(always)]
134    pub fn set_bit(self) -> &'a mut W {
135        self.bit(true)
136    }
137    #[doc = r"Clears the field bit"]
138    #[inline(always)]
139    pub fn clear_bit(self) -> &'a mut W {
140        self.bit(false)
141    }
142    #[doc = r"Writes raw bits to the field"]
143    #[inline(always)]
144    pub fn bit(self, value: bool) -> &'a mut W {
145        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
146        self.w
147    }
148}
149#[doc = "Reader of field `PID1`"]
150pub type PID1_R = crate::R<u8, u8>;
151#[doc = "Write proxy for field `PID1`"]
152pub struct PID1_W<'a> {
153    w: &'a mut W,
154}
155impl<'a> PID1_W<'a> {
156    #[doc = r"Writes raw bits to the field"]
157    #[inline(always)]
158    pub unsafe fn bits(self, value: u8) -> &'a mut W {
159        self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8);
160        self.w
161    }
162}
163#[doc = "Reader of field `EVACT1`"]
164pub type EVACT1_R = crate::R<u8, u8>;
165#[doc = "Write proxy for field `EVACT1`"]
166pub struct EVACT1_W<'a> {
167    w: &'a mut W,
168}
169impl<'a> EVACT1_W<'a> {
170    #[doc = r"Writes raw bits to the field"]
171    #[inline(always)]
172    pub unsafe fn bits(self, value: u8) -> &'a mut W {
173        self.w.bits = (self.w.bits & !(0x03 << 13)) | (((value as u32) & 0x03) << 13);
174        self.w
175    }
176}
177#[doc = "Reader of field `PORTEI1`"]
178pub type PORTEI1_R = crate::R<bool, bool>;
179#[doc = "Write proxy for field `PORTEI1`"]
180pub struct PORTEI1_W<'a> {
181    w: &'a mut W,
182}
183impl<'a> PORTEI1_W<'a> {
184    #[doc = r"Sets the field bit"]
185    #[inline(always)]
186    pub fn set_bit(self) -> &'a mut W {
187        self.bit(true)
188    }
189    #[doc = r"Clears the field bit"]
190    #[inline(always)]
191    pub fn clear_bit(self) -> &'a mut W {
192        self.bit(false)
193    }
194    #[doc = r"Writes raw bits to the field"]
195    #[inline(always)]
196    pub fn bit(self, value: bool) -> &'a mut W {
197        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
198        self.w
199    }
200}
201#[doc = "Reader of field `PID2`"]
202pub type PID2_R = crate::R<u8, u8>;
203#[doc = "Write proxy for field `PID2`"]
204pub struct PID2_W<'a> {
205    w: &'a mut W,
206}
207impl<'a> PID2_W<'a> {
208    #[doc = r"Writes raw bits to the field"]
209    #[inline(always)]
210    pub unsafe fn bits(self, value: u8) -> &'a mut W {
211        self.w.bits = (self.w.bits & !(0x1f << 16)) | (((value as u32) & 0x1f) << 16);
212        self.w
213    }
214}
215#[doc = "Reader of field `EVACT2`"]
216pub type EVACT2_R = crate::R<u8, u8>;
217#[doc = "Write proxy for field `EVACT2`"]
218pub struct EVACT2_W<'a> {
219    w: &'a mut W,
220}
221impl<'a> EVACT2_W<'a> {
222    #[doc = r"Writes raw bits to the field"]
223    #[inline(always)]
224    pub unsafe fn bits(self, value: u8) -> &'a mut W {
225        self.w.bits = (self.w.bits & !(0x03 << 21)) | (((value as u32) & 0x03) << 21);
226        self.w
227    }
228}
229#[doc = "Reader of field `PORTEI2`"]
230pub type PORTEI2_R = crate::R<bool, bool>;
231#[doc = "Write proxy for field `PORTEI2`"]
232pub struct PORTEI2_W<'a> {
233    w: &'a mut W,
234}
235impl<'a> PORTEI2_W<'a> {
236    #[doc = r"Sets the field bit"]
237    #[inline(always)]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r"Clears the field bit"]
242    #[inline(always)]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r"Writes raw bits to the field"]
247    #[inline(always)]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
250        self.w
251    }
252}
253#[doc = "Reader of field `PID3`"]
254pub type PID3_R = crate::R<u8, u8>;
255#[doc = "Write proxy for field `PID3`"]
256pub struct PID3_W<'a> {
257    w: &'a mut W,
258}
259impl<'a> PID3_W<'a> {
260    #[doc = r"Writes raw bits to the field"]
261    #[inline(always)]
262    pub unsafe fn bits(self, value: u8) -> &'a mut W {
263        self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
264        self.w
265    }
266}
267#[doc = "Reader of field `EVACT3`"]
268pub type EVACT3_R = crate::R<u8, u8>;
269#[doc = "Write proxy for field `EVACT3`"]
270pub struct EVACT3_W<'a> {
271    w: &'a mut W,
272}
273impl<'a> EVACT3_W<'a> {
274    #[doc = r"Writes raw bits to the field"]
275    #[inline(always)]
276    pub unsafe fn bits(self, value: u8) -> &'a mut W {
277        self.w.bits = (self.w.bits & !(0x03 << 29)) | (((value as u32) & 0x03) << 29);
278        self.w
279    }
280}
281#[doc = "Reader of field `PORTEI3`"]
282pub type PORTEI3_R = crate::R<bool, bool>;
283#[doc = "Write proxy for field `PORTEI3`"]
284pub struct PORTEI3_W<'a> {
285    w: &'a mut W,
286}
287impl<'a> PORTEI3_W<'a> {
288    #[doc = r"Sets the field bit"]
289    #[inline(always)]
290    pub fn set_bit(self) -> &'a mut W {
291        self.bit(true)
292    }
293    #[doc = r"Clears the field bit"]
294    #[inline(always)]
295    pub fn clear_bit(self) -> &'a mut W {
296        self.bit(false)
297    }
298    #[doc = r"Writes raw bits to the field"]
299    #[inline(always)]
300    pub fn bit(self, value: bool) -> &'a mut W {
301        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
302        self.w
303    }
304}
305impl R {
306    #[doc = "Bits 0:4 - PORT Event Pin Identifier 0"]
307    #[inline(always)]
308    pub fn pid0(&self) -> PID0_R {
309        PID0_R::new((self.bits & 0x1f) as u8)
310    }
311    #[doc = "Bits 5:6 - PORT Event Action 0"]
312    #[inline(always)]
313    pub fn evact0(&self) -> EVACT0_R {
314        EVACT0_R::new(((self.bits >> 5) & 0x03) as u8)
315    }
316    #[doc = "Bit 7 - PORT Event Input Enable 0"]
317    #[inline(always)]
318    pub fn portei0(&self) -> PORTEI0_R {
319        PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0)
320    }
321    #[doc = "Bits 8:12 - PORT Event Pin Identifier 1"]
322    #[inline(always)]
323    pub fn pid1(&self) -> PID1_R {
324        PID1_R::new(((self.bits >> 8) & 0x1f) as u8)
325    }
326    #[doc = "Bits 13:14 - PORT Event Action 1"]
327    #[inline(always)]
328    pub fn evact1(&self) -> EVACT1_R {
329        EVACT1_R::new(((self.bits >> 13) & 0x03) as u8)
330    }
331    #[doc = "Bit 15 - PORT Event Input Enable 1"]
332    #[inline(always)]
333    pub fn portei1(&self) -> PORTEI1_R {
334        PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0)
335    }
336    #[doc = "Bits 16:20 - PORT Event Pin Identifier 2"]
337    #[inline(always)]
338    pub fn pid2(&self) -> PID2_R {
339        PID2_R::new(((self.bits >> 16) & 0x1f) as u8)
340    }
341    #[doc = "Bits 21:22 - PORT Event Action 2"]
342    #[inline(always)]
343    pub fn evact2(&self) -> EVACT2_R {
344        EVACT2_R::new(((self.bits >> 21) & 0x03) as u8)
345    }
346    #[doc = "Bit 23 - PORT Event Input Enable 2"]
347    #[inline(always)]
348    pub fn portei2(&self) -> PORTEI2_R {
349        PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0)
350    }
351    #[doc = "Bits 24:28 - PORT Event Pin Identifier 3"]
352    #[inline(always)]
353    pub fn pid3(&self) -> PID3_R {
354        PID3_R::new(((self.bits >> 24) & 0x1f) as u8)
355    }
356    #[doc = "Bits 29:30 - PORT Event Action 3"]
357    #[inline(always)]
358    pub fn evact3(&self) -> EVACT3_R {
359        EVACT3_R::new(((self.bits >> 29) & 0x03) as u8)
360    }
361    #[doc = "Bit 31 - PORT Event Input Enable 3"]
362    #[inline(always)]
363    pub fn portei3(&self) -> PORTEI3_R {
364        PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0)
365    }
366}
367impl W {
368    #[doc = "Bits 0:4 - PORT Event Pin Identifier 0"]
369    #[inline(always)]
370    pub fn pid0(&mut self) -> PID0_W {
371        PID0_W { w: self }
372    }
373    #[doc = "Bits 5:6 - PORT Event Action 0"]
374    #[inline(always)]
375    pub fn evact0(&mut self) -> EVACT0_W {
376        EVACT0_W { w: self }
377    }
378    #[doc = "Bit 7 - PORT Event Input Enable 0"]
379    #[inline(always)]
380    pub fn portei0(&mut self) -> PORTEI0_W {
381        PORTEI0_W { w: self }
382    }
383    #[doc = "Bits 8:12 - PORT Event Pin Identifier 1"]
384    #[inline(always)]
385    pub fn pid1(&mut self) -> PID1_W {
386        PID1_W { w: self }
387    }
388    #[doc = "Bits 13:14 - PORT Event Action 1"]
389    #[inline(always)]
390    pub fn evact1(&mut self) -> EVACT1_W {
391        EVACT1_W { w: self }
392    }
393    #[doc = "Bit 15 - PORT Event Input Enable 1"]
394    #[inline(always)]
395    pub fn portei1(&mut self) -> PORTEI1_W {
396        PORTEI1_W { w: self }
397    }
398    #[doc = "Bits 16:20 - PORT Event Pin Identifier 2"]
399    #[inline(always)]
400    pub fn pid2(&mut self) -> PID2_W {
401        PID2_W { w: self }
402    }
403    #[doc = "Bits 21:22 - PORT Event Action 2"]
404    #[inline(always)]
405    pub fn evact2(&mut self) -> EVACT2_W {
406        EVACT2_W { w: self }
407    }
408    #[doc = "Bit 23 - PORT Event Input Enable 2"]
409    #[inline(always)]
410    pub fn portei2(&mut self) -> PORTEI2_W {
411        PORTEI2_W { w: self }
412    }
413    #[doc = "Bits 24:28 - PORT Event Pin Identifier 3"]
414    #[inline(always)]
415    pub fn pid3(&mut self) -> PID3_W {
416        PID3_W { w: self }
417    }
418    #[doc = "Bits 29:30 - PORT Event Action 3"]
419    #[inline(always)]
420    pub fn evact3(&mut self) -> EVACT3_W {
421        EVACT3_W { w: self }
422    }
423    #[doc = "Bit 31 - PORT Event Input Enable 3"]
424    #[inline(always)]
425    pub fn portei3(&mut self) -> PORTEI3_W {
426        PORTEI3_W { w: self }
427    }
428}
saml10d16a/port/group/evctrl.rs

saml10d16a/port/group/
evctrl.rs
