#[doc = "Control Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "SPI Enable"]
#[must_use]
#[inline(always)]
pub const fn spien(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SPI Enable"]
#[inline(always)]
pub const fn set_spien(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "SPI Disable"]
#[must_use]
#[inline(always)]
pub const fn spidis(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SPI Disable"]
#[inline(always)]
pub const fn set_spidis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "SPI Software Reset"]
#[must_use]
#[inline(always)]
pub const fn swrst(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "SPI Software Reset"]
#[inline(always)]
pub const fn set_swrst(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "Last Transfer"]
#[must_use]
#[inline(always)]
pub const fn lastxfer(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Last Transfer"]
#[inline(always)]
pub const fn set_lastxfer(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
impl core::fmt::Debug for Cr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cr")
.field("spien", &self.spien())
.field("spidis", &self.spidis())
.field("swrst", &self.swrst())
.field("lastxfer", &self.lastxfer())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Cr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Cr {{ spien: {=bool:?}, spidis: {=bool:?}, swrst: {=bool:?}, lastxfer: {=bool:?} }}",
self.spien(),
self.spidis(),
self.swrst(),
self.lastxfer()
)
}
}
#[doc = "Chip Select Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Csr(pub u32);
impl Csr {
#[doc = "Clock Polarity"]
#[must_use]
#[inline(always)]
pub const fn cpol(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Clock Polarity"]
#[inline(always)]
pub const fn set_cpol(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Clock Phase"]
#[must_use]
#[inline(always)]
pub const fn ncpha(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Clock Phase"]
#[inline(always)]
pub const fn set_ncpha(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
#[must_use]
#[inline(always)]
pub const fn csnaat(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
#[inline(always)]
pub const fn set_csnaat(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Chip Select Active After Transfer"]
#[must_use]
#[inline(always)]
pub const fn csaat(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Chip Select Active After Transfer"]
#[inline(always)]
pub const fn set_csaat(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Bits Per Transfer"]
#[must_use]
#[inline(always)]
pub const fn bits(&self) -> super::vals::Bits {
let val = (self.0 >> 4usize) & 0x0f;
super::vals::Bits::from_bits(val as u8)
}
#[doc = "Bits Per Transfer"]
#[inline(always)]
pub const fn set_bits(&mut self, val: super::vals::Bits) {
self.0 = (self.0 & !(0x0f << 4usize)) | (((val.to_bits() as u32) & 0x0f) << 4usize);
}
#[doc = "Serial Clock Baud Rate"]
#[must_use]
#[inline(always)]
pub const fn scbr(&self) -> u8 {
let val = (self.0 >> 8usize) & 0xff;
val as u8
}
#[doc = "Serial Clock Baud Rate"]
#[inline(always)]
pub const fn set_scbr(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
}
#[doc = "Delay Before SPCK"]
#[must_use]
#[inline(always)]
pub const fn dlybs(&self) -> u8 {
let val = (self.0 >> 16usize) & 0xff;
val as u8
}
#[doc = "Delay Before SPCK"]
#[inline(always)]
pub const fn set_dlybs(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
}
#[doc = "Delay Between Consecutive Transfers"]
#[must_use]
#[inline(always)]
pub const fn dlybct(&self) -> u8 {
let val = (self.0 >> 24usize) & 0xff;
val as u8
}
#[doc = "Delay Between Consecutive Transfers"]
#[inline(always)]
pub const fn set_dlybct(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize);
}
}
impl Default for Csr {
#[inline(always)]
fn default() -> Csr {
Csr(0)
}
}
impl core::fmt::Debug for Csr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Csr")
.field("cpol", &self.cpol())
.field("ncpha", &self.ncpha())
.field("csnaat", &self.csnaat())
.field("csaat", &self.csaat())
.field("bits", &self.bits())
.field("scbr", &self.scbr())
.field("dlybs", &self.dlybs())
.field("dlybct", &self.dlybct())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Csr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Csr {{ cpol: {=bool:?}, ncpha: {=bool:?}, csnaat: {=bool:?}, csaat: {=bool:?}, bits: {:?}, scbr: {=u8:?}, dlybs: {=u8:?}, dlybct: {=u8:?} }}",
self.cpol(),
self.ncpha(),
self.csnaat(),
self.csaat(),
self.bits(),
self.scbr(),
self.dlybs(),
self.dlybct()
)
}
}
#[doc = "Interrupt Disable Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Idr(pub u32);
impl Idr {
#[doc = "Receive Data Register Full Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn rdrf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Receive Data Register Full Interrupt Disable"]
#[inline(always)]
pub const fn set_rdrf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "SPI Transmit Data Register Empty Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn tdre(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SPI Transmit Data Register Empty Interrupt Disable"]
#[inline(always)]
pub const fn set_tdre(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Mode Fault Error Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn modf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Mode Fault Error Interrupt Disable"]
#[inline(always)]
pub const fn set_modf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Overrun Error Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn ovres(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Overrun Error Interrupt Disable"]
#[inline(always)]
pub const fn set_ovres(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "NSS Rising Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn nssr(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "NSS Rising Interrupt Disable"]
#[inline(always)]
pub const fn set_nssr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Transmission Registers Empty Disable"]
#[must_use]
#[inline(always)]
pub const fn txempty(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "Transmission Registers Empty Disable"]
#[inline(always)]
pub const fn set_txempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Underrun Error Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn undes(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Underrun Error Interrupt Disable"]
#[inline(always)]
pub const fn set_undes(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
}
impl Default for Idr {
#[inline(always)]
fn default() -> Idr {
Idr(0)
}
}
impl core::fmt::Debug for Idr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Idr")
.field("rdrf", &self.rdrf())
.field("tdre", &self.tdre())
.field("modf", &self.modf())
.field("ovres", &self.ovres())
.field("nssr", &self.nssr())
.field("txempty", &self.txempty())
.field("undes", &self.undes())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Idr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Idr {{ rdrf: {=bool:?}, tdre: {=bool:?}, modf: {=bool:?}, ovres: {=bool:?}, nssr: {=bool:?}, txempty: {=bool:?}, undes: {=bool:?} }}",
self.rdrf(),
self.tdre(),
self.modf(),
self.ovres(),
self.nssr(),
self.txempty(),
self.undes()
)
}
}
#[doc = "Interrupt Enable Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ier(pub u32);
impl Ier {
#[doc = "Receive Data Register Full Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn rdrf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Receive Data Register Full Interrupt Enable"]
#[inline(always)]
pub const fn set_rdrf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "SPI Transmit Data Register Empty Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn tdre(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SPI Transmit Data Register Empty Interrupt Enable"]
#[inline(always)]
pub const fn set_tdre(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Mode Fault Error Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn modf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Mode Fault Error Interrupt Enable"]
#[inline(always)]
pub const fn set_modf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Overrun Error Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn ovres(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Overrun Error Interrupt Enable"]
#[inline(always)]
pub const fn set_ovres(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "NSS Rising Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn nssr(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "NSS Rising Interrupt Enable"]
#[inline(always)]
pub const fn set_nssr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Transmission Registers Empty Enable"]
#[must_use]
#[inline(always)]
pub const fn txempty(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "Transmission Registers Empty Enable"]
#[inline(always)]
pub const fn set_txempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Underrun Error Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn undes(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Underrun Error Interrupt Enable"]
#[inline(always)]
pub const fn set_undes(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
}
impl Default for Ier {
#[inline(always)]
fn default() -> Ier {
Ier(0)
}
}
impl core::fmt::Debug for Ier {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ier")
.field("rdrf", &self.rdrf())
.field("tdre", &self.tdre())
.field("modf", &self.modf())
.field("ovres", &self.ovres())
.field("nssr", &self.nssr())
.field("txempty", &self.txempty())
.field("undes", &self.undes())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ier {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ier {{ rdrf: {=bool:?}, tdre: {=bool:?}, modf: {=bool:?}, ovres: {=bool:?}, nssr: {=bool:?}, txempty: {=bool:?}, undes: {=bool:?} }}",
self.rdrf(),
self.tdre(),
self.modf(),
self.ovres(),
self.nssr(),
self.txempty(),
self.undes()
)
}
}
#[doc = "Interrupt Mask Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Imr(pub u32);
impl Imr {
#[doc = "Receive Data Register Full Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn rdrf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Receive Data Register Full Interrupt Mask"]
#[inline(always)]
pub const fn set_rdrf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "SPI Transmit Data Register Empty Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn tdre(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "SPI Transmit Data Register Empty Interrupt Mask"]
#[inline(always)]
pub const fn set_tdre(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Mode Fault Error Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn modf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Mode Fault Error Interrupt Mask"]
#[inline(always)]
pub const fn set_modf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Overrun Error Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn ovres(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Overrun Error Interrupt Mask"]
#[inline(always)]
pub const fn set_ovres(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "NSS Rising Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn nssr(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "NSS Rising Interrupt Mask"]
#[inline(always)]
pub const fn set_nssr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Transmission Registers Empty Mask"]
#[must_use]
#[inline(always)]
pub const fn txempty(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "Transmission Registers Empty Mask"]
#[inline(always)]
pub const fn set_txempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Underrun Error Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn undes(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Underrun Error Interrupt Mask"]
#[inline(always)]
pub const fn set_undes(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
}
impl Default for Imr {
#[inline(always)]
fn default() -> Imr {
Imr(0)
}
}
impl core::fmt::Debug for Imr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Imr")
.field("rdrf", &self.rdrf())
.field("tdre", &self.tdre())
.field("modf", &self.modf())
.field("ovres", &self.ovres())
.field("nssr", &self.nssr())
.field("txempty", &self.txempty())
.field("undes", &self.undes())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Imr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Imr {{ rdrf: {=bool:?}, tdre: {=bool:?}, modf: {=bool:?}, ovres: {=bool:?}, nssr: {=bool:?}, txempty: {=bool:?}, undes: {=bool:?} }}",
self.rdrf(),
self.tdre(),
self.modf(),
self.ovres(),
self.nssr(),
self.txempty(),
self.undes()
)
}
}
#[doc = "Mode Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Mr(pub u32);
impl Mr {
#[doc = "Master/Slave Mode"]
#[must_use]
#[inline(always)]
pub const fn mstr(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Master/Slave Mode"]
#[inline(always)]
pub const fn set_mstr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Peripheral Select"]
#[must_use]
#[inline(always)]
pub const fn ps(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Peripheral Select"]
#[inline(always)]
pub const fn set_ps(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Chip Select Decode"]
#[must_use]
#[inline(always)]
pub const fn pcsdec(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Chip Select Decode"]
#[inline(always)]
pub const fn set_pcsdec(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Mode Fault Detection"]
#[must_use]
#[inline(always)]
pub const fn modfdis(&self) -> bool {
let val = (self.0 >> 4usize) & 0x01;
val != 0
}
#[doc = "Mode Fault Detection"]
#[inline(always)]
pub const fn set_modfdis(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
}
#[doc = "Wait Data Read Before Transfer"]
#[must_use]
#[inline(always)]
pub const fn wdrbt(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Wait Data Read Before Transfer"]
#[inline(always)]
pub const fn set_wdrbt(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Local Loopback Enable"]
#[must_use]
#[inline(always)]
pub const fn llb(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Local Loopback Enable"]
#[inline(always)]
pub const fn set_llb(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "Peripheral Chip Select"]
#[must_use]
#[inline(always)]
pub const fn pcs(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[doc = "Peripheral Chip Select"]
#[inline(always)]
pub const fn set_pcs(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
#[doc = "Delay Between Chip Selects"]
#[must_use]
#[inline(always)]
pub const fn dlybcs(&self) -> u8 {
let val = (self.0 >> 24usize) & 0xff;
val as u8
}
#[doc = "Delay Between Chip Selects"]
#[inline(always)]
pub const fn set_dlybcs(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize);
}
}
impl Default for Mr {
#[inline(always)]
fn default() -> Mr {
Mr(0)
}
}
impl core::fmt::Debug for Mr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mr")
.field("mstr", &self.mstr())
.field("ps", &self.ps())
.field("pcsdec", &self.pcsdec())
.field("modfdis", &self.modfdis())
.field("wdrbt", &self.wdrbt())
.field("llb", &self.llb())
.field("pcs", &self.pcs())
.field("dlybcs", &self.dlybcs())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Mr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Mr {{ mstr: {=bool:?}, ps: {=bool:?}, pcsdec: {=bool:?}, modfdis: {=bool:?}, wdrbt: {=bool:?}, llb: {=bool:?}, pcs: {=u8:?}, dlybcs: {=u8:?} }}",
self.mstr(),
self.ps(),
self.pcsdec(),
self.modfdis(),
self.wdrbt(),
self.llb(),
self.pcs(),
self.dlybcs()
)
}
}
#[doc = "Receive Data Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Rdr(pub u32);
impl Rdr {
#[doc = "Receive Data"]
#[must_use]
#[inline(always)]
pub const fn rd(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "Receive Data"]
#[inline(always)]
pub const fn set_rd(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
#[doc = "Peripheral Chip Select"]
#[must_use]
#[inline(always)]
pub const fn pcs(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[doc = "Peripheral Chip Select"]
#[inline(always)]
pub const fn set_pcs(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
}
impl Default for Rdr {
#[inline(always)]
fn default() -> Rdr {
Rdr(0)
}
}
impl core::fmt::Debug for Rdr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rdr")
.field("rd", &self.rd())
.field("pcs", &self.pcs())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Rdr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Rdr {{ rd: {=u16:?}, pcs: {=u8:?} }}",
self.rd(),
self.pcs()
)
}
}
#[doc = "Status Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sr(pub u32);
impl Sr {
#[doc = "Receive Data Register Full"]
#[must_use]
#[inline(always)]
pub const fn rdrf(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Receive Data Register Full"]
#[inline(always)]
pub const fn set_rdrf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Transmit Data Register Empty"]
#[must_use]
#[inline(always)]
pub const fn tdre(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Transmit Data Register Empty"]
#[inline(always)]
pub const fn set_tdre(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Mode Fault Error"]
#[must_use]
#[inline(always)]
pub const fn modf(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Mode Fault Error"]
#[inline(always)]
pub const fn set_modf(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Overrun Error Status"]
#[must_use]
#[inline(always)]
pub const fn ovres(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Overrun Error Status"]
#[inline(always)]
pub const fn set_ovres(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "NSS Rising"]
#[must_use]
#[inline(always)]
pub const fn nssr(&self) -> bool {
let val = (self.0 >> 8usize) & 0x01;
val != 0
}
#[doc = "NSS Rising"]
#[inline(always)]
pub const fn set_nssr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
}
#[doc = "Transmission Registers Empty"]
#[must_use]
#[inline(always)]
pub const fn txempty(&self) -> bool {
let val = (self.0 >> 9usize) & 0x01;
val != 0
}
#[doc = "Transmission Registers Empty"]
#[inline(always)]
pub const fn set_txempty(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
}
#[doc = "Underrun Error Status (Slave Mode Only)"]
#[must_use]
#[inline(always)]
pub const fn undes(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "Underrun Error Status (Slave Mode Only)"]
#[inline(always)]
pub const fn set_undes(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "SPI Enable Status"]
#[must_use]
#[inline(always)]
pub const fn spiens(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "SPI Enable Status"]
#[inline(always)]
pub const fn set_spiens(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
}
impl Default for Sr {
#[inline(always)]
fn default() -> Sr {
Sr(0)
}
}
impl core::fmt::Debug for Sr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sr")
.field("rdrf", &self.rdrf())
.field("tdre", &self.tdre())
.field("modf", &self.modf())
.field("ovres", &self.ovres())
.field("nssr", &self.nssr())
.field("txempty", &self.txempty())
.field("undes", &self.undes())
.field("spiens", &self.spiens())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Sr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Sr {{ rdrf: {=bool:?}, tdre: {=bool:?}, modf: {=bool:?}, ovres: {=bool:?}, nssr: {=bool:?}, txempty: {=bool:?}, undes: {=bool:?}, spiens: {=bool:?} }}",
self.rdrf(),
self.tdre(),
self.modf(),
self.ovres(),
self.nssr(),
self.txempty(),
self.undes(),
self.spiens()
)
}
}
#[doc = "Transmit Data Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Tdr(pub u32);
impl Tdr {
#[doc = "Transmit Data"]
#[must_use]
#[inline(always)]
pub const fn td(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "Transmit Data"]
#[inline(always)]
pub const fn set_td(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
#[doc = "Peripheral Chip Select"]
#[must_use]
#[inline(always)]
pub const fn pcs(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x0f;
val as u8
}
#[doc = "Peripheral Chip Select"]
#[inline(always)]
pub const fn set_pcs(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize);
}
#[doc = "Last Transfer"]
#[must_use]
#[inline(always)]
pub const fn lastxfer(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Last Transfer"]
#[inline(always)]
pub const fn set_lastxfer(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
}
impl Default for Tdr {
#[inline(always)]
fn default() -> Tdr {
Tdr(0)
}
}
impl core::fmt::Debug for Tdr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tdr")
.field("td", &self.td())
.field("pcs", &self.pcs())
.field("lastxfer", &self.lastxfer())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Tdr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Tdr {{ td: {=u16:?}, pcs: {=u8:?}, lastxfer: {=bool:?} }}",
self.td(),
self.pcs(),
self.lastxfer()
)
}
}
#[doc = "Write Protection Control Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wpmr(pub u32);
impl Wpmr {
#[doc = "Write Protect Enable"]
#[must_use]
#[inline(always)]
pub const fn wpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Write Protect Enable"]
#[inline(always)]
pub const fn set_wpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Write Protect Key"]
#[must_use]
#[inline(always)]
pub const fn wpkey(&self) -> super::vals::Wpkey {
let val = (self.0 >> 8usize) & 0x00ff_ffff;
super::vals::Wpkey::from_bits(val as u32)
}
#[doc = "Write Protect Key"]
#[inline(always)]
pub const fn set_wpkey(&mut self, val: super::vals::Wpkey) {
self.0 = (self.0 & !(0x00ff_ffff << 8usize))
| (((val.to_bits() as u32) & 0x00ff_ffff) << 8usize);
}
}
impl Default for Wpmr {
#[inline(always)]
fn default() -> Wpmr {
Wpmr(0)
}
}
impl core::fmt::Debug for Wpmr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wpmr")
.field("wpen", &self.wpen())
.field("wpkey", &self.wpkey())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wpmr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wpmr {{ wpen: {=bool:?}, wpkey: {:?} }}",
self.wpen(),
self.wpkey()
)
}
}
#[doc = "Write Protection Status Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wpsr(pub u32);
impl Wpsr {
#[doc = "Write Protection Violation Status"]
#[must_use]
#[inline(always)]
pub const fn wpvs(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Write Protection Violation Status"]
#[inline(always)]
pub const fn set_wpvs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Write Protection Violation Source"]
#[must_use]
#[inline(always)]
pub const fn wpvsrc(&self) -> u8 {
let val = (self.0 >> 8usize) & 0xff;
val as u8
}
#[doc = "Write Protection Violation Source"]
#[inline(always)]
pub const fn set_wpvsrc(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
}
}
impl Default for Wpsr {
#[inline(always)]
fn default() -> Wpsr {
Wpsr(0)
}
}
impl core::fmt::Debug for Wpsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wpsr")
.field("wpvs", &self.wpvs())
.field("wpvsrc", &self.wpvsrc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wpsr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wpsr {{ wpvs: {=bool:?}, wpvsrc: {=u8:?} }}",
self.wpvs(),
self.wpvsrc()
)
}
}