#[doc = "Main Clock Frequency Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CkgrMcfr(pub u32);
impl CkgrMcfr {
#[doc = "Main Clock Frequency"]
#[must_use]
#[inline(always)]
pub const fn mainf(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "Main Clock Frequency"]
#[inline(always)]
pub const fn set_mainf(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
#[doc = "Main Clock Ready"]
#[must_use]
#[inline(always)]
pub const fn mainfrdy(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Main Clock Ready"]
#[inline(always)]
pub const fn set_mainfrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
}
impl Default for CkgrMcfr {
#[inline(always)]
fn default() -> CkgrMcfr {
CkgrMcfr(0)
}
}
impl core::fmt::Debug for CkgrMcfr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CkgrMcfr")
.field("mainf", &self.mainf())
.field("mainfrdy", &self.mainfrdy())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for CkgrMcfr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"CkgrMcfr {{ mainf: {=u16:?}, mainfrdy: {=bool:?} }}",
self.mainf(),
self.mainfrdy()
)
}
}
#[doc = "Main Oscillator Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CkgrMor(pub u32);
impl CkgrMor {
#[doc = "Main Crystal Oscillator Enable"]
#[must_use]
#[inline(always)]
pub const fn moscxten(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Main Crystal Oscillator Enable"]
#[inline(always)]
pub const fn set_moscxten(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Main Crystal Oscillator Bypass"]
#[must_use]
#[inline(always)]
pub const fn moscxtby(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Main Crystal Oscillator Bypass"]
#[inline(always)]
pub const fn set_moscxtby(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Main On-Chip RC Oscillator Enable"]
#[must_use]
#[inline(always)]
pub const fn moscrcen(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Main On-Chip RC Oscillator Enable"]
#[inline(always)]
pub const fn set_moscrcen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Main On-Chip RC Oscillator Frequency Selection"]
#[must_use]
#[inline(always)]
pub const fn moscrcf(&self) -> super::vals::Moscrcf {
let val = (self.0 >> 4usize) & 0x07;
super::vals::Moscrcf::from_bits(val as u8)
}
#[doc = "Main On-Chip RC Oscillator Frequency Selection"]
#[inline(always)]
pub const fn set_moscrcf(&mut self, val: super::vals::Moscrcf) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
#[doc = "Main Crystal Oscillator Start-up Time"]
#[must_use]
#[inline(always)]
pub const fn moscxtst(&self) -> u8 {
let val = (self.0 >> 8usize) & 0xff;
val as u8
}
#[doc = "Main Crystal Oscillator Start-up Time"]
#[inline(always)]
pub const fn set_moscxtst(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
}
#[doc = "Write Access Password"]
#[must_use]
#[inline(always)]
pub const fn key(&self) -> super::vals::Key {
let val = (self.0 >> 16usize) & 0xff;
super::vals::Key::from_bits(val as u8)
}
#[doc = "Write Access Password"]
#[inline(always)]
pub const fn set_key(&mut self, val: super::vals::Key) {
self.0 = (self.0 & !(0xff << 16usize)) | (((val.to_bits() as u32) & 0xff) << 16usize);
}
#[doc = "Main Oscillator Selection"]
#[must_use]
#[inline(always)]
pub const fn moscsel(&self) -> bool {
let val = (self.0 >> 24usize) & 0x01;
val != 0
}
#[doc = "Main Oscillator Selection"]
#[inline(always)]
pub const fn set_moscsel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
}
#[doc = "Clock Failure Detector Enable"]
#[must_use]
#[inline(always)]
pub const fn cfden(&self) -> bool {
let val = (self.0 >> 25usize) & 0x01;
val != 0
}
#[doc = "Clock Failure Detector Enable"]
#[inline(always)]
pub const fn set_cfden(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
}
}
impl Default for CkgrMor {
#[inline(always)]
fn default() -> CkgrMor {
CkgrMor(0)
}
}
impl core::fmt::Debug for CkgrMor {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CkgrMor")
.field("moscxten", &self.moscxten())
.field("moscxtby", &self.moscxtby())
.field("moscrcen", &self.moscrcen())
.field("moscrcf", &self.moscrcf())
.field("moscxtst", &self.moscxtst())
.field("key", &self.key())
.field("moscsel", &self.moscsel())
.field("cfden", &self.cfden())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for CkgrMor {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"CkgrMor {{ moscxten: {=bool:?}, moscxtby: {=bool:?}, moscrcen: {=bool:?}, moscrcf: {:?}, moscxtst: {=u8:?}, key: {:?}, moscsel: {=bool:?}, cfden: {=bool:?} }}",
self.moscxten(),
self.moscxtby(),
self.moscrcen(),
self.moscrcf(),
self.moscxtst(),
self.key(),
self.moscsel(),
self.cfden()
)
}
}
#[doc = "PLLA Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CkgrPllar(pub u32);
impl CkgrPllar {
#[doc = "Divider"]
#[must_use]
#[inline(always)]
pub const fn diva(&self) -> u8 {
let val = (self.0 >> 0usize) & 0xff;
val as u8
}
#[doc = "Divider"]
#[inline(always)]
pub const fn set_diva(&mut self, val: u8) {
self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
}
#[doc = "PLLA Counter"]
#[must_use]
#[inline(always)]
pub const fn pllacount(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x3f;
val as u8
}
#[doc = "PLLA Counter"]
#[inline(always)]
pub const fn set_pllacount(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
}
#[doc = "PLLA Multiplier"]
#[must_use]
#[inline(always)]
pub const fn mula(&self) -> u16 {
let val = (self.0 >> 16usize) & 0x07ff;
val as u16
}
#[doc = "PLLA Multiplier"]
#[inline(always)]
pub const fn set_mula(&mut self, val: u16) {
self.0 = (self.0 & !(0x07ff << 16usize)) | (((val as u32) & 0x07ff) << 16usize);
}
#[doc = "Must Be Set to 1"]
#[must_use]
#[inline(always)]
pub const fn one(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "Must Be Set to 1"]
#[inline(always)]
pub const fn set_one(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
}
impl Default for CkgrPllar {
#[inline(always)]
fn default() -> CkgrPllar {
CkgrPllar(0)
}
}
impl core::fmt::Debug for CkgrPllar {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CkgrPllar")
.field("diva", &self.diva())
.field("pllacount", &self.pllacount())
.field("mula", &self.mula())
.field("one", &self.one())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for CkgrPllar {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"CkgrPllar {{ diva: {=u8:?}, pllacount: {=u8:?}, mula: {=u16:?}, one: {=bool:?} }}",
self.diva(),
self.pllacount(),
self.mula(),
self.one()
)
}
}
#[doc = "UTMI Clock Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct CkgrUckr(pub u32);
impl CkgrUckr {
#[doc = "UTMI PLL Enable"]
#[must_use]
#[inline(always)]
pub const fn upllen(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "UTMI PLL Enable"]
#[inline(always)]
pub const fn set_upllen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "UTMI PLL Start-up Time"]
#[must_use]
#[inline(always)]
pub const fn upllcount(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x0f;
val as u8
}
#[doc = "UTMI PLL Start-up Time"]
#[inline(always)]
pub const fn set_upllcount(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize);
}
}
impl Default for CkgrUckr {
#[inline(always)]
fn default() -> CkgrUckr {
CkgrUckr(0)
}
}
impl core::fmt::Debug for CkgrUckr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CkgrUckr")
.field("upllen", &self.upllen())
.field("upllcount", &self.upllcount())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for CkgrUckr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"CkgrUckr {{ upllen: {=bool:?}, upllcount: {=u8:?} }}",
self.upllen(),
self.upllcount()
)
}
}
#[doc = "Fault Output Clear Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Focr(pub u32);
impl Focr {
#[doc = "Fault Output Clear"]
#[must_use]
#[inline(always)]
pub const fn foclr(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Fault Output Clear"]
#[inline(always)]
pub const fn set_foclr(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
}
impl Default for Focr {
#[inline(always)]
fn default() -> Focr {
Focr(0)
}
}
impl core::fmt::Debug for Focr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Focr")
.field("foclr", &self.foclr())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Focr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(f, "Focr {{ foclr: {=bool:?} }}", self.foclr())
}
}
#[doc = "Fast Start-up Mode Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fsmr(pub u32);
impl Fsmr {
#[doc = "Fast Start-up Input Enable 0"]
#[must_use]
#[inline(always)]
pub const fn fstt(&self, n: usize) -> bool {
assert!(n < 16usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Fast Start-up Input Enable 0"]
#[inline(always)]
pub const fn set_fstt(&mut self, n: usize, val: bool) {
assert!(n < 16usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "RTT Alarm Enable"]
#[must_use]
#[inline(always)]
pub const fn rttal(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "RTT Alarm Enable"]
#[inline(always)]
pub const fn set_rttal(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "RTC Alarm Enable"]
#[must_use]
#[inline(always)]
pub const fn rtcal(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "RTC Alarm Enable"]
#[inline(always)]
pub const fn set_rtcal(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "USB Alarm Enable"]
#[must_use]
#[inline(always)]
pub const fn usbal(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "USB Alarm Enable"]
#[inline(always)]
pub const fn set_usbal(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Low Power Mode"]
#[must_use]
#[inline(always)]
pub const fn lpm(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Low Power Mode"]
#[inline(always)]
pub const fn set_lpm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Fsmr {
#[inline(always)]
fn default() -> Fsmr {
Fsmr(0)
}
}
impl core::fmt::Debug for Fsmr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Fsmr")
.field("fstt[0]", &self.fstt(0usize))
.field("fstt[1]", &self.fstt(1usize))
.field("fstt[2]", &self.fstt(2usize))
.field("fstt[3]", &self.fstt(3usize))
.field("fstt[4]", &self.fstt(4usize))
.field("fstt[5]", &self.fstt(5usize))
.field("fstt[6]", &self.fstt(6usize))
.field("fstt[7]", &self.fstt(7usize))
.field("fstt[8]", &self.fstt(8usize))
.field("fstt[9]", &self.fstt(9usize))
.field("fstt[10]", &self.fstt(10usize))
.field("fstt[11]", &self.fstt(11usize))
.field("fstt[12]", &self.fstt(12usize))
.field("fstt[13]", &self.fstt(13usize))
.field("fstt[14]", &self.fstt(14usize))
.field("fstt[15]", &self.fstt(15usize))
.field("rttal", &self.rttal())
.field("rtcal", &self.rtcal())
.field("usbal", &self.usbal())
.field("lpm", &self.lpm())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Fsmr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Fsmr {{ fstt[0]: {=bool:?}, fstt[1]: {=bool:?}, fstt[2]: {=bool:?}, fstt[3]: {=bool:?}, fstt[4]: {=bool:?}, fstt[5]: {=bool:?}, fstt[6]: {=bool:?}, fstt[7]: {=bool:?}, fstt[8]: {=bool:?}, fstt[9]: {=bool:?}, fstt[10]: {=bool:?}, fstt[11]: {=bool:?}, fstt[12]: {=bool:?}, fstt[13]: {=bool:?}, fstt[14]: {=bool:?}, fstt[15]: {=bool:?}, rttal: {=bool:?}, rtcal: {=bool:?}, usbal: {=bool:?}, lpm: {=bool:?} }}",
self.fstt(0usize),
self.fstt(1usize),
self.fstt(2usize),
self.fstt(3usize),
self.fstt(4usize),
self.fstt(5usize),
self.fstt(6usize),
self.fstt(7usize),
self.fstt(8usize),
self.fstt(9usize),
self.fstt(10usize),
self.fstt(11usize),
self.fstt(12usize),
self.fstt(13usize),
self.fstt(14usize),
self.fstt(15usize),
self.rttal(),
self.rtcal(),
self.usbal(),
self.lpm()
)
}
}
#[doc = "Fast Start-up Polarity Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Fspr(pub u32);
impl Fspr {
#[doc = "Fast Start-up Input Polarityx"]
#[must_use]
#[inline(always)]
pub const fn fstp(&self, n: usize) -> bool {
assert!(n < 16usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Fast Start-up Input Polarityx"]
#[inline(always)]
pub const fn set_fstp(&mut self, n: usize, val: bool) {
assert!(n < 16usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Fspr {
#[inline(always)]
fn default() -> Fspr {
Fspr(0)
}
}
impl core::fmt::Debug for Fspr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Fspr")
.field("fstp[0]", &self.fstp(0usize))
.field("fstp[1]", &self.fstp(1usize))
.field("fstp[2]", &self.fstp(2usize))
.field("fstp[3]", &self.fstp(3usize))
.field("fstp[4]", &self.fstp(4usize))
.field("fstp[5]", &self.fstp(5usize))
.field("fstp[6]", &self.fstp(6usize))
.field("fstp[7]", &self.fstp(7usize))
.field("fstp[8]", &self.fstp(8usize))
.field("fstp[9]", &self.fstp(9usize))
.field("fstp[10]", &self.fstp(10usize))
.field("fstp[11]", &self.fstp(11usize))
.field("fstp[12]", &self.fstp(12usize))
.field("fstp[13]", &self.fstp(13usize))
.field("fstp[14]", &self.fstp(14usize))
.field("fstp[15]", &self.fstp(15usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Fspr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Fspr {{ fstp[0]: {=bool:?}, fstp[1]: {=bool:?}, fstp[2]: {=bool:?}, fstp[3]: {=bool:?}, fstp[4]: {=bool:?}, fstp[5]: {=bool:?}, fstp[6]: {=bool:?}, fstp[7]: {=bool:?}, fstp[8]: {=bool:?}, fstp[9]: {=bool:?}, fstp[10]: {=bool:?}, fstp[11]: {=bool:?}, fstp[12]: {=bool:?}, fstp[13]: {=bool:?}, fstp[14]: {=bool:?}, fstp[15]: {=bool:?} }}",
self.fstp(0usize),
self.fstp(1usize),
self.fstp(2usize),
self.fstp(3usize),
self.fstp(4usize),
self.fstp(5usize),
self.fstp(6usize),
self.fstp(7usize),
self.fstp(8usize),
self.fstp(9usize),
self.fstp(10usize),
self.fstp(11usize),
self.fstp(12usize),
self.fstp(13usize),
self.fstp(14usize),
self.fstp(15usize)
)
}
}
#[doc = "Interrupt Disable Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Idr(pub u32);
impl Idr {
#[doc = "Main Crystal Oscillator Status Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn moscxts(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Main Crystal Oscillator Status Interrupt Disable"]
#[inline(always)]
pub const fn set_moscxts(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "PLLA Lock Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn locka(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "PLLA Lock Interrupt Disable"]
#[inline(always)]
pub const fn set_locka(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Master Clock Ready Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn mckrdy(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Master Clock Ready Interrupt Disable"]
#[inline(always)]
pub const fn set_mckrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "UTMI PLL Lock Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn locku(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "UTMI PLL Lock Interrupt Disable"]
#[inline(always)]
pub const fn set_locku(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Programmable Clock Ready 0 Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn pckrdy(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Programmable Clock Ready 0 Interrupt Disable"]
#[inline(always)]
pub const fn set_pckrdy(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Main Oscillator Selection Status Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn moscsels(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Main Oscillator Selection Status Interrupt Disable"]
#[inline(always)]
pub const fn set_moscsels(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Main On-Chip RC Status Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn moscrcs(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Main On-Chip RC Status Interrupt Disable"]
#[inline(always)]
pub const fn set_moscrcs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Clock Failure Detector Event Interrupt Disable"]
#[must_use]
#[inline(always)]
pub const fn cfdev(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Clock Failure Detector Event Interrupt Disable"]
#[inline(always)]
pub const fn set_cfdev(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Idr {
#[inline(always)]
fn default() -> Idr {
Idr(0)
}
}
impl core::fmt::Debug for Idr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Idr")
.field("moscxts", &self.moscxts())
.field("locka", &self.locka())
.field("mckrdy", &self.mckrdy())
.field("locku", &self.locku())
.field("pckrdy[0]", &self.pckrdy(0usize))
.field("pckrdy[1]", &self.pckrdy(1usize))
.field("pckrdy[2]", &self.pckrdy(2usize))
.field("moscsels", &self.moscsels())
.field("moscrcs", &self.moscrcs())
.field("cfdev", &self.cfdev())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Idr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Idr {{ moscxts: {=bool:?}, locka: {=bool:?}, mckrdy: {=bool:?}, locku: {=bool:?}, pckrdy[0]: {=bool:?}, pckrdy[1]: {=bool:?}, pckrdy[2]: {=bool:?}, moscsels: {=bool:?}, moscrcs: {=bool:?}, cfdev: {=bool:?} }}",
self.moscxts(),
self.locka(),
self.mckrdy(),
self.locku(),
self.pckrdy(0usize),
self.pckrdy(1usize),
self.pckrdy(2usize),
self.moscsels(),
self.moscrcs(),
self.cfdev()
)
}
}
#[doc = "Interrupt Enable Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ier(pub u32);
impl Ier {
#[doc = "Main Crystal Oscillator Status Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn moscxts(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Main Crystal Oscillator Status Interrupt Enable"]
#[inline(always)]
pub const fn set_moscxts(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "PLLA Lock Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn locka(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "PLLA Lock Interrupt Enable"]
#[inline(always)]
pub const fn set_locka(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Master Clock Ready Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn mckrdy(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Master Clock Ready Interrupt Enable"]
#[inline(always)]
pub const fn set_mckrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "UTMI PLL Lock Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn locku(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "UTMI PLL Lock Interrupt Enable"]
#[inline(always)]
pub const fn set_locku(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Programmable Clock Ready 0 Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn pckrdy(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Programmable Clock Ready 0 Interrupt Enable"]
#[inline(always)]
pub const fn set_pckrdy(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Main Oscillator Selection Status Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn moscsels(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Main Oscillator Selection Status Interrupt Enable"]
#[inline(always)]
pub const fn set_moscsels(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Main On-Chip RC Status Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn moscrcs(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Main On-Chip RC Status Interrupt Enable"]
#[inline(always)]
pub const fn set_moscrcs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Clock Failure Detector Event Interrupt Enable"]
#[must_use]
#[inline(always)]
pub const fn cfdev(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Clock Failure Detector Event Interrupt Enable"]
#[inline(always)]
pub const fn set_cfdev(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Ier {
#[inline(always)]
fn default() -> Ier {
Ier(0)
}
}
impl core::fmt::Debug for Ier {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Ier")
.field("moscxts", &self.moscxts())
.field("locka", &self.locka())
.field("mckrdy", &self.mckrdy())
.field("locku", &self.locku())
.field("pckrdy[0]", &self.pckrdy(0usize))
.field("pckrdy[1]", &self.pckrdy(1usize))
.field("pckrdy[2]", &self.pckrdy(2usize))
.field("moscsels", &self.moscsels())
.field("moscrcs", &self.moscrcs())
.field("cfdev", &self.cfdev())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Ier {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Ier {{ moscxts: {=bool:?}, locka: {=bool:?}, mckrdy: {=bool:?}, locku: {=bool:?}, pckrdy[0]: {=bool:?}, pckrdy[1]: {=bool:?}, pckrdy[2]: {=bool:?}, moscsels: {=bool:?}, moscrcs: {=bool:?}, cfdev: {=bool:?} }}",
self.moscxts(),
self.locka(),
self.mckrdy(),
self.locku(),
self.pckrdy(0usize),
self.pckrdy(1usize),
self.pckrdy(2usize),
self.moscsels(),
self.moscrcs(),
self.cfdev()
)
}
}
#[doc = "Interrupt Mask Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Imr(pub u32);
impl Imr {
#[doc = "Main Crystal Oscillator Status Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn moscxts(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Main Crystal Oscillator Status Interrupt Mask"]
#[inline(always)]
pub const fn set_moscxts(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "PLLA Lock Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn locka(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "PLLA Lock Interrupt Mask"]
#[inline(always)]
pub const fn set_locka(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Master Clock Ready Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn mckrdy(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Master Clock Ready Interrupt Mask"]
#[inline(always)]
pub const fn set_mckrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "UTMI PLL Lock Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn locku(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "UTMI PLL Lock Interrupt Mask"]
#[inline(always)]
pub const fn set_locku(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Programmable Clock Ready 0 Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn pckrdy(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Programmable Clock Ready 0 Interrupt Mask"]
#[inline(always)]
pub const fn set_pckrdy(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Main Oscillator Selection Status Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn moscsels(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Main Oscillator Selection Status Interrupt Mask"]
#[inline(always)]
pub const fn set_moscsels(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Main On-Chip RC Status Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn moscrcs(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Main On-Chip RC Status Interrupt Mask"]
#[inline(always)]
pub const fn set_moscrcs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Clock Failure Detector Event Interrupt Mask"]
#[must_use]
#[inline(always)]
pub const fn cfdev(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Clock Failure Detector Event Interrupt Mask"]
#[inline(always)]
pub const fn set_cfdev(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
}
impl Default for Imr {
#[inline(always)]
fn default() -> Imr {
Imr(0)
}
}
impl core::fmt::Debug for Imr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Imr")
.field("moscxts", &self.moscxts())
.field("locka", &self.locka())
.field("mckrdy", &self.mckrdy())
.field("locku", &self.locku())
.field("pckrdy[0]", &self.pckrdy(0usize))
.field("pckrdy[1]", &self.pckrdy(1usize))
.field("pckrdy[2]", &self.pckrdy(2usize))
.field("moscsels", &self.moscsels())
.field("moscrcs", &self.moscrcs())
.field("cfdev", &self.cfdev())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Imr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Imr {{ moscxts: {=bool:?}, locka: {=bool:?}, mckrdy: {=bool:?}, locku: {=bool:?}, pckrdy[0]: {=bool:?}, pckrdy[1]: {=bool:?}, pckrdy[2]: {=bool:?}, moscsels: {=bool:?}, moscrcs: {=bool:?}, cfdev: {=bool:?} }}",
self.moscxts(),
self.locka(),
self.mckrdy(),
self.locku(),
self.pckrdy(0usize),
self.pckrdy(1usize),
self.pckrdy(2usize),
self.moscsels(),
self.moscrcs(),
self.cfdev()
)
}
}
#[doc = "Master Clock Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Mckr(pub u32);
impl Mckr {
#[doc = "Master Clock Source Selection"]
#[must_use]
#[inline(always)]
pub const fn css(&self) -> super::vals::PmcMckrCss {
let val = (self.0 >> 0usize) & 0x03;
super::vals::PmcMckrCss::from_bits(val as u8)
}
#[doc = "Master Clock Source Selection"]
#[inline(always)]
pub const fn set_css(&mut self, val: super::vals::PmcMckrCss) {
self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
}
#[doc = "Processor Clock Prescaler"]
#[must_use]
#[inline(always)]
pub const fn pres(&self) -> super::vals::PmcMckrPres {
let val = (self.0 >> 4usize) & 0x07;
super::vals::PmcMckrPres::from_bits(val as u8)
}
#[doc = "Processor Clock Prescaler"]
#[inline(always)]
pub const fn set_pres(&mut self, val: super::vals::PmcMckrPres) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
#[doc = "PLLA Divisor by 2"]
#[must_use]
#[inline(always)]
pub const fn plladiv2(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "PLLA Divisor by 2"]
#[inline(always)]
pub const fn set_plladiv2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[must_use]
#[inline(always)]
pub const fn uplldiv2(&self) -> bool {
let val = (self.0 >> 13usize) & 0x01;
val != 0
}
#[inline(always)]
pub const fn set_uplldiv2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
}
}
impl Default for Mckr {
#[inline(always)]
fn default() -> Mckr {
Mckr(0)
}
}
impl core::fmt::Debug for Mckr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mckr")
.field("css", &self.css())
.field("pres", &self.pres())
.field("plladiv2", &self.plladiv2())
.field("uplldiv2", &self.uplldiv2())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Mckr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Mckr {{ css: {:?}, pres: {:?}, plladiv2: {=bool:?}, uplldiv2: {=bool:?} }}",
self.css(),
self.pres(),
self.plladiv2(),
self.uplldiv2()
)
}
}
#[doc = "Peripheral Clock Disable Register 0"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcdr0(pub u32);
impl Pcdr0 {
#[doc = "Peripheral Clock 8 Disable"]
#[must_use]
#[inline(always)]
pub const fn pid(&self, n: usize) -> bool {
assert!(n < 24usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Peripheral Clock 8 Disable"]
#[inline(always)]
pub const fn set_pid(&mut self, n: usize, val: bool) {
assert!(n < 24usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Pcdr0 {
#[inline(always)]
fn default() -> Pcdr0 {
Pcdr0(0)
}
}
impl core::fmt::Debug for Pcdr0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pcdr0")
.field("pid[0]", &self.pid(0usize))
.field("pid[1]", &self.pid(1usize))
.field("pid[2]", &self.pid(2usize))
.field("pid[3]", &self.pid(3usize))
.field("pid[4]", &self.pid(4usize))
.field("pid[5]", &self.pid(5usize))
.field("pid[6]", &self.pid(6usize))
.field("pid[7]", &self.pid(7usize))
.field("pid[8]", &self.pid(8usize))
.field("pid[9]", &self.pid(9usize))
.field("pid[10]", &self.pid(10usize))
.field("pid[11]", &self.pid(11usize))
.field("pid[12]", &self.pid(12usize))
.field("pid[13]", &self.pid(13usize))
.field("pid[14]", &self.pid(14usize))
.field("pid[15]", &self.pid(15usize))
.field("pid[16]", &self.pid(16usize))
.field("pid[17]", &self.pid(17usize))
.field("pid[18]", &self.pid(18usize))
.field("pid[19]", &self.pid(19usize))
.field("pid[20]", &self.pid(20usize))
.field("pid[21]", &self.pid(21usize))
.field("pid[22]", &self.pid(22usize))
.field("pid[23]", &self.pid(23usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pcdr0 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pcdr0 {{ pid[0]: {=bool:?}, pid[1]: {=bool:?}, pid[2]: {=bool:?}, pid[3]: {=bool:?}, pid[4]: {=bool:?}, pid[5]: {=bool:?}, pid[6]: {=bool:?}, pid[7]: {=bool:?}, pid[8]: {=bool:?}, pid[9]: {=bool:?}, pid[10]: {=bool:?}, pid[11]: {=bool:?}, pid[12]: {=bool:?}, pid[13]: {=bool:?}, pid[14]: {=bool:?}, pid[15]: {=bool:?}, pid[16]: {=bool:?}, pid[17]: {=bool:?}, pid[18]: {=bool:?}, pid[19]: {=bool:?}, pid[20]: {=bool:?}, pid[21]: {=bool:?}, pid[22]: {=bool:?}, pid[23]: {=bool:?} }}",
self.pid(0usize),
self.pid(1usize),
self.pid(2usize),
self.pid(3usize),
self.pid(4usize),
self.pid(5usize),
self.pid(6usize),
self.pid(7usize),
self.pid(8usize),
self.pid(9usize),
self.pid(10usize),
self.pid(11usize),
self.pid(12usize),
self.pid(13usize),
self.pid(14usize),
self.pid(15usize),
self.pid(16usize),
self.pid(17usize),
self.pid(18usize),
self.pid(19usize),
self.pid(20usize),
self.pid(21usize),
self.pid(22usize),
self.pid(23usize)
)
}
}
#[doc = "Peripheral Clock Disable Register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcdr1(pub u32);
impl Pcdr1 {
#[doc = "Peripheral Clock 32 Disable"]
#[must_use]
#[inline(always)]
pub const fn pid(&self, n: usize) -> bool {
assert!(n < 13usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Peripheral Clock 32 Disable"]
#[inline(always)]
pub const fn set_pid(&mut self, n: usize, val: bool) {
assert!(n < 13usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Pcdr1 {
#[inline(always)]
fn default() -> Pcdr1 {
Pcdr1(0)
}
}
impl core::fmt::Debug for Pcdr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pcdr1")
.field("pid[0]", &self.pid(0usize))
.field("pid[1]", &self.pid(1usize))
.field("pid[2]", &self.pid(2usize))
.field("pid[3]", &self.pid(3usize))
.field("pid[4]", &self.pid(4usize))
.field("pid[5]", &self.pid(5usize))
.field("pid[6]", &self.pid(6usize))
.field("pid[7]", &self.pid(7usize))
.field("pid[8]", &self.pid(8usize))
.field("pid[9]", &self.pid(9usize))
.field("pid[10]", &self.pid(10usize))
.field("pid[11]", &self.pid(11usize))
.field("pid[12]", &self.pid(12usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pcdr1 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pcdr1 {{ pid[0]: {=bool:?}, pid[1]: {=bool:?}, pid[2]: {=bool:?}, pid[3]: {=bool:?}, pid[4]: {=bool:?}, pid[5]: {=bool:?}, pid[6]: {=bool:?}, pid[7]: {=bool:?}, pid[8]: {=bool:?}, pid[9]: {=bool:?}, pid[10]: {=bool:?}, pid[11]: {=bool:?}, pid[12]: {=bool:?} }}",
self.pid(0usize),
self.pid(1usize),
self.pid(2usize),
self.pid(3usize),
self.pid(4usize),
self.pid(5usize),
self.pid(6usize),
self.pid(7usize),
self.pid(8usize),
self.pid(9usize),
self.pid(10usize),
self.pid(11usize),
self.pid(12usize)
)
}
}
#[doc = "Peripheral Clock Enable Register 0"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcer0(pub u32);
impl Pcer0 {
#[doc = "Peripheral Clock 8 Enable"]
#[must_use]
#[inline(always)]
pub const fn pid(&self, n: usize) -> bool {
assert!(n < 24usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Peripheral Clock 8 Enable"]
#[inline(always)]
pub const fn set_pid(&mut self, n: usize, val: bool) {
assert!(n < 24usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Pcer0 {
#[inline(always)]
fn default() -> Pcer0 {
Pcer0(0)
}
}
impl core::fmt::Debug for Pcer0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pcer0")
.field("pid[0]", &self.pid(0usize))
.field("pid[1]", &self.pid(1usize))
.field("pid[2]", &self.pid(2usize))
.field("pid[3]", &self.pid(3usize))
.field("pid[4]", &self.pid(4usize))
.field("pid[5]", &self.pid(5usize))
.field("pid[6]", &self.pid(6usize))
.field("pid[7]", &self.pid(7usize))
.field("pid[8]", &self.pid(8usize))
.field("pid[9]", &self.pid(9usize))
.field("pid[10]", &self.pid(10usize))
.field("pid[11]", &self.pid(11usize))
.field("pid[12]", &self.pid(12usize))
.field("pid[13]", &self.pid(13usize))
.field("pid[14]", &self.pid(14usize))
.field("pid[15]", &self.pid(15usize))
.field("pid[16]", &self.pid(16usize))
.field("pid[17]", &self.pid(17usize))
.field("pid[18]", &self.pid(18usize))
.field("pid[19]", &self.pid(19usize))
.field("pid[20]", &self.pid(20usize))
.field("pid[21]", &self.pid(21usize))
.field("pid[22]", &self.pid(22usize))
.field("pid[23]", &self.pid(23usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pcer0 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pcer0 {{ pid[0]: {=bool:?}, pid[1]: {=bool:?}, pid[2]: {=bool:?}, pid[3]: {=bool:?}, pid[4]: {=bool:?}, pid[5]: {=bool:?}, pid[6]: {=bool:?}, pid[7]: {=bool:?}, pid[8]: {=bool:?}, pid[9]: {=bool:?}, pid[10]: {=bool:?}, pid[11]: {=bool:?}, pid[12]: {=bool:?}, pid[13]: {=bool:?}, pid[14]: {=bool:?}, pid[15]: {=bool:?}, pid[16]: {=bool:?}, pid[17]: {=bool:?}, pid[18]: {=bool:?}, pid[19]: {=bool:?}, pid[20]: {=bool:?}, pid[21]: {=bool:?}, pid[22]: {=bool:?}, pid[23]: {=bool:?} }}",
self.pid(0usize),
self.pid(1usize),
self.pid(2usize),
self.pid(3usize),
self.pid(4usize),
self.pid(5usize),
self.pid(6usize),
self.pid(7usize),
self.pid(8usize),
self.pid(9usize),
self.pid(10usize),
self.pid(11usize),
self.pid(12usize),
self.pid(13usize),
self.pid(14usize),
self.pid(15usize),
self.pid(16usize),
self.pid(17usize),
self.pid(18usize),
self.pid(19usize),
self.pid(20usize),
self.pid(21usize),
self.pid(22usize),
self.pid(23usize)
)
}
}
#[doc = "Peripheral Clock Enable Register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcer1(pub u32);
impl Pcer1 {
#[doc = "Peripheral Clock 32 Enable"]
#[must_use]
#[inline(always)]
pub const fn pid(&self, n: usize) -> bool {
assert!(n < 13usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Peripheral Clock 32 Enable"]
#[inline(always)]
pub const fn set_pid(&mut self, n: usize, val: bool) {
assert!(n < 13usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Pcer1 {
#[inline(always)]
fn default() -> Pcer1 {
Pcer1(0)
}
}
impl core::fmt::Debug for Pcer1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pcer1")
.field("pid[0]", &self.pid(0usize))
.field("pid[1]", &self.pid(1usize))
.field("pid[2]", &self.pid(2usize))
.field("pid[3]", &self.pid(3usize))
.field("pid[4]", &self.pid(4usize))
.field("pid[5]", &self.pid(5usize))
.field("pid[6]", &self.pid(6usize))
.field("pid[7]", &self.pid(7usize))
.field("pid[8]", &self.pid(8usize))
.field("pid[9]", &self.pid(9usize))
.field("pid[10]", &self.pid(10usize))
.field("pid[11]", &self.pid(11usize))
.field("pid[12]", &self.pid(12usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pcer1 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pcer1 {{ pid[0]: {=bool:?}, pid[1]: {=bool:?}, pid[2]: {=bool:?}, pid[3]: {=bool:?}, pid[4]: {=bool:?}, pid[5]: {=bool:?}, pid[6]: {=bool:?}, pid[7]: {=bool:?}, pid[8]: {=bool:?}, pid[9]: {=bool:?}, pid[10]: {=bool:?}, pid[11]: {=bool:?}, pid[12]: {=bool:?} }}",
self.pid(0usize),
self.pid(1usize),
self.pid(2usize),
self.pid(3usize),
self.pid(4usize),
self.pid(5usize),
self.pid(6usize),
self.pid(7usize),
self.pid(8usize),
self.pid(9usize),
self.pid(10usize),
self.pid(11usize),
self.pid(12usize)
)
}
}
#[doc = "Programmable Clock 0 Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pck(pub u32);
impl Pck {
#[doc = "Master Clock Source Selection"]
#[must_use]
#[inline(always)]
pub const fn css(&self) -> super::vals::PmcPckCss {
let val = (self.0 >> 0usize) & 0x07;
super::vals::PmcPckCss::from_bits(val as u8)
}
#[doc = "Master Clock Source Selection"]
#[inline(always)]
pub const fn set_css(&mut self, val: super::vals::PmcPckCss) {
self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize);
}
#[doc = "Programmable Clock Prescaler"]
#[must_use]
#[inline(always)]
pub const fn pres(&self) -> super::vals::PmcPckPres {
let val = (self.0 >> 4usize) & 0x07;
super::vals::PmcPckPres::from_bits(val as u8)
}
#[doc = "Programmable Clock Prescaler"]
#[inline(always)]
pub const fn set_pres(&mut self, val: super::vals::PmcPckPres) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u32) & 0x07) << 4usize);
}
}
impl Default for Pck {
#[inline(always)]
fn default() -> Pck {
Pck(0)
}
}
impl core::fmt::Debug for Pck {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pck")
.field("css", &self.css())
.field("pres", &self.pres())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pck {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pck {{ css: {:?}, pres: {:?} }}",
self.css(),
self.pres()
)
}
}
#[doc = "Peripheral Control Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcr(pub u32);
impl Pcr {
#[doc = "Peripheral ID"]
#[must_use]
#[inline(always)]
pub const fn pid(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x3f;
val as u8
}
#[doc = "Peripheral ID"]
#[inline(always)]
pub const fn set_pid(&mut self, val: u8) {
self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
}
#[doc = "Command"]
#[must_use]
#[inline(always)]
pub const fn cmd(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "Command"]
#[inline(always)]
pub const fn set_cmd(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "Divisor Value"]
#[must_use]
#[inline(always)]
pub const fn div(&self) -> super::vals::Div {
let val = (self.0 >> 16usize) & 0x03;
super::vals::Div::from_bits(val as u8)
}
#[doc = "Divisor Value"]
#[inline(always)]
pub const fn set_div(&mut self, val: super::vals::Div) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
}
#[doc = "Enable"]
#[must_use]
#[inline(always)]
pub const fn en(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "Enable"]
#[inline(always)]
pub const fn set_en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
}
impl Default for Pcr {
#[inline(always)]
fn default() -> Pcr {
Pcr(0)
}
}
impl core::fmt::Debug for Pcr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pcr")
.field("pid", &self.pid())
.field("cmd", &self.cmd())
.field("div", &self.div())
.field("en", &self.en())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pcr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pcr {{ pid: {=u8:?}, cmd: {=bool:?}, div: {:?}, en: {=bool:?} }}",
self.pid(),
self.cmd(),
self.div(),
self.en()
)
}
}
#[doc = "Peripheral Clock Status Register 0"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcsr0(pub u32);
impl Pcsr0 {
#[doc = "Peripheral Clock 8 Status"]
#[must_use]
#[inline(always)]
pub const fn pid(&self, n: usize) -> bool {
assert!(n < 24usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Peripheral Clock 8 Status"]
#[inline(always)]
pub const fn set_pid(&mut self, n: usize, val: bool) {
assert!(n < 24usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Pcsr0 {
#[inline(always)]
fn default() -> Pcsr0 {
Pcsr0(0)
}
}
impl core::fmt::Debug for Pcsr0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pcsr0")
.field("pid[0]", &self.pid(0usize))
.field("pid[1]", &self.pid(1usize))
.field("pid[2]", &self.pid(2usize))
.field("pid[3]", &self.pid(3usize))
.field("pid[4]", &self.pid(4usize))
.field("pid[5]", &self.pid(5usize))
.field("pid[6]", &self.pid(6usize))
.field("pid[7]", &self.pid(7usize))
.field("pid[8]", &self.pid(8usize))
.field("pid[9]", &self.pid(9usize))
.field("pid[10]", &self.pid(10usize))
.field("pid[11]", &self.pid(11usize))
.field("pid[12]", &self.pid(12usize))
.field("pid[13]", &self.pid(13usize))
.field("pid[14]", &self.pid(14usize))
.field("pid[15]", &self.pid(15usize))
.field("pid[16]", &self.pid(16usize))
.field("pid[17]", &self.pid(17usize))
.field("pid[18]", &self.pid(18usize))
.field("pid[19]", &self.pid(19usize))
.field("pid[20]", &self.pid(20usize))
.field("pid[21]", &self.pid(21usize))
.field("pid[22]", &self.pid(22usize))
.field("pid[23]", &self.pid(23usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pcsr0 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pcsr0 {{ pid[0]: {=bool:?}, pid[1]: {=bool:?}, pid[2]: {=bool:?}, pid[3]: {=bool:?}, pid[4]: {=bool:?}, pid[5]: {=bool:?}, pid[6]: {=bool:?}, pid[7]: {=bool:?}, pid[8]: {=bool:?}, pid[9]: {=bool:?}, pid[10]: {=bool:?}, pid[11]: {=bool:?}, pid[12]: {=bool:?}, pid[13]: {=bool:?}, pid[14]: {=bool:?}, pid[15]: {=bool:?}, pid[16]: {=bool:?}, pid[17]: {=bool:?}, pid[18]: {=bool:?}, pid[19]: {=bool:?}, pid[20]: {=bool:?}, pid[21]: {=bool:?}, pid[22]: {=bool:?}, pid[23]: {=bool:?} }}",
self.pid(0usize),
self.pid(1usize),
self.pid(2usize),
self.pid(3usize),
self.pid(4usize),
self.pid(5usize),
self.pid(6usize),
self.pid(7usize),
self.pid(8usize),
self.pid(9usize),
self.pid(10usize),
self.pid(11usize),
self.pid(12usize),
self.pid(13usize),
self.pid(14usize),
self.pid(15usize),
self.pid(16usize),
self.pid(17usize),
self.pid(18usize),
self.pid(19usize),
self.pid(20usize),
self.pid(21usize),
self.pid(22usize),
self.pid(23usize)
)
}
}
#[doc = "Peripheral Clock Status Register 1"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcsr1(pub u32);
impl Pcsr1 {
#[doc = "Peripheral Clock 32 Status"]
#[must_use]
#[inline(always)]
pub const fn pid(&self, n: usize) -> bool {
assert!(n < 13usize);
let offs = 0usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Peripheral Clock 32 Status"]
#[inline(always)]
pub const fn set_pid(&mut self, n: usize, val: bool) {
assert!(n < 13usize);
let offs = 0usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Pcsr1 {
#[inline(always)]
fn default() -> Pcsr1 {
Pcsr1(0)
}
}
impl core::fmt::Debug for Pcsr1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pcsr1")
.field("pid[0]", &self.pid(0usize))
.field("pid[1]", &self.pid(1usize))
.field("pid[2]", &self.pid(2usize))
.field("pid[3]", &self.pid(3usize))
.field("pid[4]", &self.pid(4usize))
.field("pid[5]", &self.pid(5usize))
.field("pid[6]", &self.pid(6usize))
.field("pid[7]", &self.pid(7usize))
.field("pid[8]", &self.pid(8usize))
.field("pid[9]", &self.pid(9usize))
.field("pid[10]", &self.pid(10usize))
.field("pid[11]", &self.pid(11usize))
.field("pid[12]", &self.pid(12usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Pcsr1 {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Pcsr1 {{ pid[0]: {=bool:?}, pid[1]: {=bool:?}, pid[2]: {=bool:?}, pid[3]: {=bool:?}, pid[4]: {=bool:?}, pid[5]: {=bool:?}, pid[6]: {=bool:?}, pid[7]: {=bool:?}, pid[8]: {=bool:?}, pid[9]: {=bool:?}, pid[10]: {=bool:?}, pid[11]: {=bool:?}, pid[12]: {=bool:?} }}",
self.pid(0usize),
self.pid(1usize),
self.pid(2usize),
self.pid(3usize),
self.pid(4usize),
self.pid(5usize),
self.pid(6usize),
self.pid(7usize),
self.pid(8usize),
self.pid(9usize),
self.pid(10usize),
self.pid(11usize),
self.pid(12usize)
)
}
}
#[doc = "System Clock Disable Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Scdr(pub u32);
impl Scdr {
#[doc = "Disable USB OTG Clock (48 MHz, USB_48M) for UTMI"]
#[must_use]
#[inline(always)]
pub const fn uotgclk(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Disable USB OTG Clock (48 MHz, USB_48M) for UTMI"]
#[inline(always)]
pub const fn set_uotgclk(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Programmable Clock 0 Output Disable"]
#[must_use]
#[inline(always)]
pub const fn pck(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Programmable Clock 0 Output Disable"]
#[inline(always)]
pub const fn set_pck(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Scdr {
#[inline(always)]
fn default() -> Scdr {
Scdr(0)
}
}
impl core::fmt::Debug for Scdr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Scdr")
.field("uotgclk", &self.uotgclk())
.field("pck[0]", &self.pck(0usize))
.field("pck[1]", &self.pck(1usize))
.field("pck[2]", &self.pck(2usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Scdr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Scdr {{ uotgclk: {=bool:?}, pck[0]: {=bool:?}, pck[1]: {=bool:?}, pck[2]: {=bool:?} }}",
self.uotgclk(),
self.pck(0usize),
self.pck(1usize),
self.pck(2usize)
)
}
}
#[doc = "System Clock Enable Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Scer(pub u32);
impl Scer {
#[doc = "Enable USB OTG Clock (48 MHz, USB_48M) for UTMI"]
#[must_use]
#[inline(always)]
pub const fn uotgclk(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Enable USB OTG Clock (48 MHz, USB_48M) for UTMI"]
#[inline(always)]
pub const fn set_uotgclk(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Programmable Clock 0 Output Enable"]
#[must_use]
#[inline(always)]
pub const fn pck(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Programmable Clock 0 Output Enable"]
#[inline(always)]
pub const fn set_pck(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Scer {
#[inline(always)]
fn default() -> Scer {
Scer(0)
}
}
impl core::fmt::Debug for Scer {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Scer")
.field("uotgclk", &self.uotgclk())
.field("pck[0]", &self.pck(0usize))
.field("pck[1]", &self.pck(1usize))
.field("pck[2]", &self.pck(2usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Scer {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Scer {{ uotgclk: {=bool:?}, pck[0]: {=bool:?}, pck[1]: {=bool:?}, pck[2]: {=bool:?} }}",
self.uotgclk(),
self.pck(0usize),
self.pck(1usize),
self.pck(2usize)
)
}
}
#[doc = "System Clock Status Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Scsr(pub u32);
impl Scsr {
#[doc = "USB OTG Clock (48 MHz, USB_48M) Clock Status"]
#[must_use]
#[inline(always)]
pub const fn uotgclk(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "USB OTG Clock (48 MHz, USB_48M) Clock Status"]
#[inline(always)]
pub const fn set_uotgclk(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Programmable Clock 0 Output Status"]
#[must_use]
#[inline(always)]
pub const fn pck(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Programmable Clock 0 Output Status"]
#[inline(always)]
pub const fn set_pck(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Scsr {
#[inline(always)]
fn default() -> Scsr {
Scsr(0)
}
}
impl core::fmt::Debug for Scsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Scsr")
.field("uotgclk", &self.uotgclk())
.field("pck[0]", &self.pck(0usize))
.field("pck[1]", &self.pck(1usize))
.field("pck[2]", &self.pck(2usize))
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Scsr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Scsr {{ uotgclk: {=bool:?}, pck[0]: {=bool:?}, pck[1]: {=bool:?}, pck[2]: {=bool:?} }}",
self.uotgclk(),
self.pck(0usize),
self.pck(1usize),
self.pck(2usize)
)
}
}
#[doc = "Status Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Sr(pub u32);
impl Sr {
#[doc = "Main XTAL Oscillator Status"]
#[must_use]
#[inline(always)]
pub const fn moscxts(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Main XTAL Oscillator Status"]
#[inline(always)]
pub const fn set_moscxts(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "PLLA Lock Status"]
#[must_use]
#[inline(always)]
pub const fn locka(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "PLLA Lock Status"]
#[inline(always)]
pub const fn set_locka(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Master Clock Status"]
#[must_use]
#[inline(always)]
pub const fn mckrdy(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Master Clock Status"]
#[inline(always)]
pub const fn set_mckrdy(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "UTMI PLL Lock Status"]
#[must_use]
#[inline(always)]
pub const fn locku(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "UTMI PLL Lock Status"]
#[inline(always)]
pub const fn set_locku(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Slow Clock Oscillator Selection"]
#[must_use]
#[inline(always)]
pub const fn oscsels(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Slow Clock Oscillator Selection"]
#[inline(always)]
pub const fn set_oscsels(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "Programmable Clock Ready Status"]
#[must_use]
#[inline(always)]
pub const fn pckrdy(&self, n: usize) -> bool {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Programmable Clock Ready Status"]
#[inline(always)]
pub const fn set_pckrdy(&mut self, n: usize, val: bool) {
assert!(n < 3usize);
let offs = 8usize + n * 1usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Main Oscillator Selection Status"]
#[must_use]
#[inline(always)]
pub const fn moscsels(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "Main Oscillator Selection Status"]
#[inline(always)]
pub const fn set_moscsels(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "Main On-Chip RC Oscillator Status"]
#[must_use]
#[inline(always)]
pub const fn moscrcs(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "Main On-Chip RC Oscillator Status"]
#[inline(always)]
pub const fn set_moscrcs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "Clock Failure Detector Event"]
#[must_use]
#[inline(always)]
pub const fn cfdev(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "Clock Failure Detector Event"]
#[inline(always)]
pub const fn set_cfdev(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "Clock Failure Detector Status"]
#[must_use]
#[inline(always)]
pub const fn cfds(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "Clock Failure Detector Status"]
#[inline(always)]
pub const fn set_cfds(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "Clock Failure Detector Fault Output Status"]
#[must_use]
#[inline(always)]
pub const fn fos(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "Clock Failure Detector Fault Output Status"]
#[inline(always)]
pub const fn set_fos(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
}
impl Default for Sr {
#[inline(always)]
fn default() -> Sr {
Sr(0)
}
}
impl core::fmt::Debug for Sr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sr")
.field("moscxts", &self.moscxts())
.field("locka", &self.locka())
.field("mckrdy", &self.mckrdy())
.field("locku", &self.locku())
.field("oscsels", &self.oscsels())
.field("pckrdy[0]", &self.pckrdy(0usize))
.field("pckrdy[1]", &self.pckrdy(1usize))
.field("pckrdy[2]", &self.pckrdy(2usize))
.field("moscsels", &self.moscsels())
.field("moscrcs", &self.moscrcs())
.field("cfdev", &self.cfdev())
.field("cfds", &self.cfds())
.field("fos", &self.fos())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Sr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Sr {{ moscxts: {=bool:?}, locka: {=bool:?}, mckrdy: {=bool:?}, locku: {=bool:?}, oscsels: {=bool:?}, pckrdy[0]: {=bool:?}, pckrdy[1]: {=bool:?}, pckrdy[2]: {=bool:?}, moscsels: {=bool:?}, moscrcs: {=bool:?}, cfdev: {=bool:?}, cfds: {=bool:?}, fos: {=bool:?} }}",
self.moscxts(),
self.locka(),
self.mckrdy(),
self.locku(),
self.oscsels(),
self.pckrdy(0usize),
self.pckrdy(1usize),
self.pckrdy(2usize),
self.moscsels(),
self.moscrcs(),
self.cfdev(),
self.cfds(),
self.fos()
)
}
}
#[doc = "USB Clock Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Usb(pub u32);
impl Usb {
#[doc = "USB Input Clock Selection"]
#[must_use]
#[inline(always)]
pub const fn usbs(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "USB Input Clock Selection"]
#[inline(always)]
pub const fn set_usbs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Divider for USB Clock."]
#[must_use]
#[inline(always)]
pub const fn usbdiv(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x0f;
val as u8
}
#[doc = "Divider for USB Clock."]
#[inline(always)]
pub const fn set_usbdiv(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
}
}
impl Default for Usb {
#[inline(always)]
fn default() -> Usb {
Usb(0)
}
}
impl core::fmt::Debug for Usb {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usb")
.field("usbs", &self.usbs())
.field("usbdiv", &self.usbdiv())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Usb {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Usb {{ usbs: {=bool:?}, usbdiv: {=u8:?} }}",
self.usbs(),
self.usbdiv()
)
}
}
#[doc = "Write Protect Mode Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wpmr(pub u32);
impl Wpmr {
#[doc = "Write Protect Enable"]
#[must_use]
#[inline(always)]
pub const fn wpen(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Write Protect Enable"]
#[inline(always)]
pub const fn set_wpen(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Write Protect KEY"]
#[must_use]
#[inline(always)]
pub const fn wpkey(&self) -> super::vals::WpKey {
let val = (self.0 >> 8usize) & 0x00ff_ffff;
super::vals::WpKey::from_bits(val as u32)
}
#[doc = "Write Protect KEY"]
#[inline(always)]
pub const fn set_wpkey(&mut self, val: super::vals::WpKey) {
self.0 = (self.0 & !(0x00ff_ffff << 8usize))
| (((val.to_bits() as u32) & 0x00ff_ffff) << 8usize);
}
}
impl Default for Wpmr {
#[inline(always)]
fn default() -> Wpmr {
Wpmr(0)
}
}
impl core::fmt::Debug for Wpmr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wpmr")
.field("wpen", &self.wpen())
.field("wpkey", &self.wpkey())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wpmr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wpmr {{ wpen: {=bool:?}, wpkey: {:?} }}",
self.wpen(),
self.wpkey()
)
}
}
#[doc = "Write Protect Status Register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Wpsr(pub u32);
impl Wpsr {
#[doc = "Write Protect Violation Status"]
#[must_use]
#[inline(always)]
pub const fn wpvs(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Write Protect Violation Status"]
#[inline(always)]
pub const fn set_wpvs(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Write Protect Violation Source"]
#[must_use]
#[inline(always)]
pub const fn wpvsrc(&self) -> u16 {
let val = (self.0 >> 8usize) & 0xffff;
val as u16
}
#[doc = "Write Protect Violation Source"]
#[inline(always)]
pub const fn set_wpvsrc(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 8usize)) | (((val as u32) & 0xffff) << 8usize);
}
}
impl Default for Wpsr {
#[inline(always)]
fn default() -> Wpsr {
Wpsr(0)
}
}
impl core::fmt::Debug for Wpsr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wpsr")
.field("wpvs", &self.wpvs())
.field("wpvsrc", &self.wpvsrc())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for Wpsr {
fn format(&self, f: defmt::Formatter) {
defmt::write!(
f,
"Wpsr {{ wpvs: {=bool:?}, wpvsrc: {=u16:?} }}",
self.wpvs(),
self.wpvsrc()
)
}
}