#[doc = "Register `CHCFG6` reader"]
pub struct R(crate::R<CHCFG6_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CHCFG6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CHCFG6_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CHCFG6_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CHCFG6` writer"]
pub struct W(crate::W<CHCFG6_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CHCFG6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CHCFG6_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CHCFG6_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SOURCE` reader - DMA Channel Source (Slot)"]
pub struct SOURCE_R(crate::FieldReader<u8, u8>);
impl SOURCE_R {
#[inline(always)]
pub(crate) fn new(bits: u8) -> Self {
SOURCE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SOURCE_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SOURCE` writer - DMA Channel Source (Slot)"]
pub struct SOURCE_W<'a> {
w: &'a mut W,
}
impl<'a> SOURCE_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x3f) | (value as u8 & 0x3f);
self.w
}
}
#[doc = "DMA Channel Trigger Enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRIG_A {
#[doc = "0: Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)"]
_0 = 0,
#[doc = "1: Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode."]
_1 = 1,
}
impl From<TRIG_A> for bool {
#[inline(always)]
fn from(variant: TRIG_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TRIG` reader - DMA Channel Trigger Enable"]
pub struct TRIG_R(crate::FieldReader<bool, TRIG_A>);
impl TRIG_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
TRIG_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> TRIG_A {
match self.bits {
false => TRIG_A::_0,
true => TRIG_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
**self == TRIG_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
**self == TRIG_A::_1
}
}
impl core::ops::Deref for TRIG_R {
type Target = crate::FieldReader<bool, TRIG_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `TRIG` writer - DMA Channel Trigger Enable"]
pub struct TRIG_W<'a> {
w: &'a mut W,
}
impl<'a> TRIG_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TRIG_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(TRIG_A::_0)
}
#[doc = "Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode."]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(TRIG_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6);
self.w
}
}
#[doc = "DMA Channel Enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ENBL_A {
#[doc = "0: DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."]
_0 = 0,
#[doc = "1: DMA channel is enabled"]
_1 = 1,
}
impl From<ENBL_A> for bool {
#[inline(always)]
fn from(variant: ENBL_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ENBL` reader - DMA Channel Enable"]
pub struct ENBL_R(crate::FieldReader<bool, ENBL_A>);
impl ENBL_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
ENBL_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> ENBL_A {
match self.bits {
false => ENBL_A::_0,
true => ENBL_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
**self == ENBL_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
**self == ENBL_A::_1
}
}
impl core::ops::Deref for ENBL_R {
type Target = crate::FieldReader<bool, ENBL_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `ENBL` writer - DMA Channel Enable"]
pub struct ENBL_W<'a> {
w: &'a mut W,
}
impl<'a> ENBL_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ENBL_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel."]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(ENBL_A::_0)
}
#[doc = "DMA channel is enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(ENBL_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7);
self.w
}
}
impl R {
#[doc = "Bits 0:5 - DMA Channel Source (Slot)"]
#[inline(always)]
pub fn source(&self) -> SOURCE_R {
SOURCE_R::new((self.bits & 0x3f) as u8)
}
#[doc = "Bit 6 - DMA Channel Trigger Enable"]
#[inline(always)]
pub fn trig(&self) -> TRIG_R {
TRIG_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 7 - DMA Channel Enable"]
#[inline(always)]
pub fn enbl(&self) -> ENBL_R {
ENBL_R::new(((self.bits >> 7) & 0x01) != 0)
}
}
impl W {
#[doc = "Bits 0:5 - DMA Channel Source (Slot)"]
#[inline(always)]
pub fn source(&mut self) -> SOURCE_W {
SOURCE_W { w: self }
}
#[doc = "Bit 6 - DMA Channel Trigger Enable"]
#[inline(always)]
pub fn trig(&mut self) -> TRIG_W {
TRIG_W { w: self }
}
#[doc = "Bit 7 - DMA Channel Enable"]
#[inline(always)]
pub fn enbl(&mut self) -> ENBL_W {
ENBL_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Channel Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chcfg6](index.html) module"]
pub struct CHCFG6_SPEC;
impl crate::RegisterSpec for CHCFG6_SPEC {
type Ux = u8;
}
#[doc = "`read()` method returns [chcfg6::R](R) reader structure"]
impl crate::Readable for CHCFG6_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [chcfg6::W](W) writer structure"]
impl crate::Writable for CHCFG6_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CHCFG6 to value 0"]
impl crate::Resettable for CHCFG6_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}