1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::FIRCDIV {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R { bits: self.register.get() }
26 }
27 #[doc = r" Writes to the register"]
28 #[inline]
29 pub fn write<F>(&self, f: F)
30 where
31 F: FnOnce(&mut W) -> &mut W,
32 {
33 let mut w = W::reset_value();
34 f(&mut w);
35 self.register.set(w.bits);
36 }
37 #[doc = r" Writes the reset value to the register"]
38 #[inline]
39 pub fn reset(&self) {
40 self.write(|w| w)
41 }
42}
43#[doc = "Possible values of the field `FIRCDIV1`"]
44#[derive(Clone, Copy, Debug, PartialEq)]
45pub enum FIRCDIV1R {
46 #[doc = "Output disabled"]
47 _000,
48 #[doc = "Divide by 1"]
49 _001,
50 #[doc = "Divide by 2"]
51 _010,
52 #[doc = "Divide by 4"]
53 _011,
54 #[doc = "Divide by 8"]
55 _100,
56 #[doc = "Divide by 16"]
57 _101,
58 #[doc = "Divide by 32"]
59 _110,
60 #[doc = "Divide by 64"]
61 _111,
62}
63impl FIRCDIV1R {
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bits(&self) -> u8 {
67 match *self {
68 FIRCDIV1R::_000 => 0,
69 FIRCDIV1R::_001 => 1,
70 FIRCDIV1R::_010 => 2,
71 FIRCDIV1R::_011 => 3,
72 FIRCDIV1R::_100 => 4,
73 FIRCDIV1R::_101 => 5,
74 FIRCDIV1R::_110 => 6,
75 FIRCDIV1R::_111 => 7,
76 }
77 }
78 #[allow(missing_docs)]
79 #[doc(hidden)]
80 #[inline]
81 pub fn _from(value: u8) -> FIRCDIV1R {
82 match value {
83 0 => FIRCDIV1R::_000,
84 1 => FIRCDIV1R::_001,
85 2 => FIRCDIV1R::_010,
86 3 => FIRCDIV1R::_011,
87 4 => FIRCDIV1R::_100,
88 5 => FIRCDIV1R::_101,
89 6 => FIRCDIV1R::_110,
90 7 => FIRCDIV1R::_111,
91 _ => unreachable!(),
92 }
93 }
94 #[doc = "Checks if the value of the field is `_000`"]
95 #[inline]
96 pub fn is_000(&self) -> bool {
97 *self == FIRCDIV1R::_000
98 }
99 #[doc = "Checks if the value of the field is `_001`"]
100 #[inline]
101 pub fn is_001(&self) -> bool {
102 *self == FIRCDIV1R::_001
103 }
104 #[doc = "Checks if the value of the field is `_010`"]
105 #[inline]
106 pub fn is_010(&self) -> bool {
107 *self == FIRCDIV1R::_010
108 }
109 #[doc = "Checks if the value of the field is `_011`"]
110 #[inline]
111 pub fn is_011(&self) -> bool {
112 *self == FIRCDIV1R::_011
113 }
114 #[doc = "Checks if the value of the field is `_100`"]
115 #[inline]
116 pub fn is_100(&self) -> bool {
117 *self == FIRCDIV1R::_100
118 }
119 #[doc = "Checks if the value of the field is `_101`"]
120 #[inline]
121 pub fn is_101(&self) -> bool {
122 *self == FIRCDIV1R::_101
123 }
124 #[doc = "Checks if the value of the field is `_110`"]
125 #[inline]
126 pub fn is_110(&self) -> bool {
127 *self == FIRCDIV1R::_110
128 }
129 #[doc = "Checks if the value of the field is `_111`"]
130 #[inline]
131 pub fn is_111(&self) -> bool {
132 *self == FIRCDIV1R::_111
133 }
134}
135#[doc = "Possible values of the field `FIRCDIV2`"]
136#[derive(Clone, Copy, Debug, PartialEq)]
137pub enum FIRCDIV2R {
138 #[doc = "Output disabled"]
139 _000,
140 #[doc = "Divide by 1"]
141 _001,
142 #[doc = "Divide by 2"]
143 _010,
144 #[doc = "Divide by 4"]
145 _011,
146 #[doc = "Divide by 8"]
147 _100,
148 #[doc = "Divide by 16"]
149 _101,
150 #[doc = "Divide by 32"]
151 _110,
152 #[doc = "Divide by 64"]
153 _111,
154}
155impl FIRCDIV2R {
156 #[doc = r" Value of the field as raw bits"]
157 #[inline]
158 pub fn bits(&self) -> u8 {
159 match *self {
160 FIRCDIV2R::_000 => 0,
161 FIRCDIV2R::_001 => 1,
162 FIRCDIV2R::_010 => 2,
163 FIRCDIV2R::_011 => 3,
164 FIRCDIV2R::_100 => 4,
165 FIRCDIV2R::_101 => 5,
166 FIRCDIV2R::_110 => 6,
167 FIRCDIV2R::_111 => 7,
168 }
169 }
170 #[allow(missing_docs)]
171 #[doc(hidden)]
172 #[inline]
173 pub fn _from(value: u8) -> FIRCDIV2R {
174 match value {
175 0 => FIRCDIV2R::_000,
176 1 => FIRCDIV2R::_001,
177 2 => FIRCDIV2R::_010,
178 3 => FIRCDIV2R::_011,
179 4 => FIRCDIV2R::_100,
180 5 => FIRCDIV2R::_101,
181 6 => FIRCDIV2R::_110,
182 7 => FIRCDIV2R::_111,
183 _ => unreachable!(),
184 }
185 }
186 #[doc = "Checks if the value of the field is `_000`"]
187 #[inline]
188 pub fn is_000(&self) -> bool {
189 *self == FIRCDIV2R::_000
190 }
191 #[doc = "Checks if the value of the field is `_001`"]
192 #[inline]
193 pub fn is_001(&self) -> bool {
194 *self == FIRCDIV2R::_001
195 }
196 #[doc = "Checks if the value of the field is `_010`"]
197 #[inline]
198 pub fn is_010(&self) -> bool {
199 *self == FIRCDIV2R::_010
200 }
201 #[doc = "Checks if the value of the field is `_011`"]
202 #[inline]
203 pub fn is_011(&self) -> bool {
204 *self == FIRCDIV2R::_011
205 }
206 #[doc = "Checks if the value of the field is `_100`"]
207 #[inline]
208 pub fn is_100(&self) -> bool {
209 *self == FIRCDIV2R::_100
210 }
211 #[doc = "Checks if the value of the field is `_101`"]
212 #[inline]
213 pub fn is_101(&self) -> bool {
214 *self == FIRCDIV2R::_101
215 }
216 #[doc = "Checks if the value of the field is `_110`"]
217 #[inline]
218 pub fn is_110(&self) -> bool {
219 *self == FIRCDIV2R::_110
220 }
221 #[doc = "Checks if the value of the field is `_111`"]
222 #[inline]
223 pub fn is_111(&self) -> bool {
224 *self == FIRCDIV2R::_111
225 }
226}
227#[doc = "Values that can be written to the field `FIRCDIV1`"]
228pub enum FIRCDIV1W {
229 #[doc = "Output disabled"]
230 _000,
231 #[doc = "Divide by 1"]
232 _001,
233 #[doc = "Divide by 2"]
234 _010,
235 #[doc = "Divide by 4"]
236 _011,
237 #[doc = "Divide by 8"]
238 _100,
239 #[doc = "Divide by 16"]
240 _101,
241 #[doc = "Divide by 32"]
242 _110,
243 #[doc = "Divide by 64"]
244 _111,
245}
246impl FIRCDIV1W {
247 #[allow(missing_docs)]
248 #[doc(hidden)]
249 #[inline]
250 pub fn _bits(&self) -> u8 {
251 match *self {
252 FIRCDIV1W::_000 => 0,
253 FIRCDIV1W::_001 => 1,
254 FIRCDIV1W::_010 => 2,
255 FIRCDIV1W::_011 => 3,
256 FIRCDIV1W::_100 => 4,
257 FIRCDIV1W::_101 => 5,
258 FIRCDIV1W::_110 => 6,
259 FIRCDIV1W::_111 => 7,
260 }
261 }
262}
263#[doc = r" Proxy"]
264pub struct _FIRCDIV1W<'a> {
265 w: &'a mut W,
266}
267impl<'a> _FIRCDIV1W<'a> {
268 #[doc = r" Writes `variant` to the field"]
269 #[inline]
270 pub fn variant(self, variant: FIRCDIV1W) -> &'a mut W {
271 {
272 self.bits(variant._bits())
273 }
274 }
275 #[doc = "Output disabled"]
276 #[inline]
277 pub fn _000(self) -> &'a mut W {
278 self.variant(FIRCDIV1W::_000)
279 }
280 #[doc = "Divide by 1"]
281 #[inline]
282 pub fn _001(self) -> &'a mut W {
283 self.variant(FIRCDIV1W::_001)
284 }
285 #[doc = "Divide by 2"]
286 #[inline]
287 pub fn _010(self) -> &'a mut W {
288 self.variant(FIRCDIV1W::_010)
289 }
290 #[doc = "Divide by 4"]
291 #[inline]
292 pub fn _011(self) -> &'a mut W {
293 self.variant(FIRCDIV1W::_011)
294 }
295 #[doc = "Divide by 8"]
296 #[inline]
297 pub fn _100(self) -> &'a mut W {
298 self.variant(FIRCDIV1W::_100)
299 }
300 #[doc = "Divide by 16"]
301 #[inline]
302 pub fn _101(self) -> &'a mut W {
303 self.variant(FIRCDIV1W::_101)
304 }
305 #[doc = "Divide by 32"]
306 #[inline]
307 pub fn _110(self) -> &'a mut W {
308 self.variant(FIRCDIV1W::_110)
309 }
310 #[doc = "Divide by 64"]
311 #[inline]
312 pub fn _111(self) -> &'a mut W {
313 self.variant(FIRCDIV1W::_111)
314 }
315 #[doc = r" Writes raw bits to the field"]
316 #[inline]
317 pub fn bits(self, value: u8) -> &'a mut W {
318 const MASK: u8 = 7;
319 const OFFSET: u8 = 0;
320 self.w.bits &= !((MASK as u32) << OFFSET);
321 self.w.bits |= ((value & MASK) as u32) << OFFSET;
322 self.w
323 }
324}
325#[doc = "Values that can be written to the field `FIRCDIV2`"]
326pub enum FIRCDIV2W {
327 #[doc = "Output disabled"]
328 _000,
329 #[doc = "Divide by 1"]
330 _001,
331 #[doc = "Divide by 2"]
332 _010,
333 #[doc = "Divide by 4"]
334 _011,
335 #[doc = "Divide by 8"]
336 _100,
337 #[doc = "Divide by 16"]
338 _101,
339 #[doc = "Divide by 32"]
340 _110,
341 #[doc = "Divide by 64"]
342 _111,
343}
344impl FIRCDIV2W {
345 #[allow(missing_docs)]
346 #[doc(hidden)]
347 #[inline]
348 pub fn _bits(&self) -> u8 {
349 match *self {
350 FIRCDIV2W::_000 => 0,
351 FIRCDIV2W::_001 => 1,
352 FIRCDIV2W::_010 => 2,
353 FIRCDIV2W::_011 => 3,
354 FIRCDIV2W::_100 => 4,
355 FIRCDIV2W::_101 => 5,
356 FIRCDIV2W::_110 => 6,
357 FIRCDIV2W::_111 => 7,
358 }
359 }
360}
361#[doc = r" Proxy"]
362pub struct _FIRCDIV2W<'a> {
363 w: &'a mut W,
364}
365impl<'a> _FIRCDIV2W<'a> {
366 #[doc = r" Writes `variant` to the field"]
367 #[inline]
368 pub fn variant(self, variant: FIRCDIV2W) -> &'a mut W {
369 {
370 self.bits(variant._bits())
371 }
372 }
373 #[doc = "Output disabled"]
374 #[inline]
375 pub fn _000(self) -> &'a mut W {
376 self.variant(FIRCDIV2W::_000)
377 }
378 #[doc = "Divide by 1"]
379 #[inline]
380 pub fn _001(self) -> &'a mut W {
381 self.variant(FIRCDIV2W::_001)
382 }
383 #[doc = "Divide by 2"]
384 #[inline]
385 pub fn _010(self) -> &'a mut W {
386 self.variant(FIRCDIV2W::_010)
387 }
388 #[doc = "Divide by 4"]
389 #[inline]
390 pub fn _011(self) -> &'a mut W {
391 self.variant(FIRCDIV2W::_011)
392 }
393 #[doc = "Divide by 8"]
394 #[inline]
395 pub fn _100(self) -> &'a mut W {
396 self.variant(FIRCDIV2W::_100)
397 }
398 #[doc = "Divide by 16"]
399 #[inline]
400 pub fn _101(self) -> &'a mut W {
401 self.variant(FIRCDIV2W::_101)
402 }
403 #[doc = "Divide by 32"]
404 #[inline]
405 pub fn _110(self) -> &'a mut W {
406 self.variant(FIRCDIV2W::_110)
407 }
408 #[doc = "Divide by 64"]
409 #[inline]
410 pub fn _111(self) -> &'a mut W {
411 self.variant(FIRCDIV2W::_111)
412 }
413 #[doc = r" Writes raw bits to the field"]
414 #[inline]
415 pub fn bits(self, value: u8) -> &'a mut W {
416 const MASK: u8 = 7;
417 const OFFSET: u8 = 8;
418 self.w.bits &= !((MASK as u32) << OFFSET);
419 self.w.bits |= ((value & MASK) as u32) << OFFSET;
420 self.w
421 }
422}
423impl R {
424 #[doc = r" Value of the register as raw bits"]
425 #[inline]
426 pub fn bits(&self) -> u32 {
427 self.bits
428 }
429 #[doc = "Bits 0:2 - Fast IRC Clock Divide 1"]
430 #[inline]
431 pub fn fircdiv1(&self) -> FIRCDIV1R {
432 FIRCDIV1R::_from({
433 const MASK: u8 = 7;
434 const OFFSET: u8 = 0;
435 ((self.bits >> OFFSET) & MASK as u32) as u8
436 })
437 }
438 #[doc = "Bits 8:10 - Fast IRC Clock Divide 2"]
439 #[inline]
440 pub fn fircdiv2(&self) -> FIRCDIV2R {
441 FIRCDIV2R::_from({
442 const MASK: u8 = 7;
443 const OFFSET: u8 = 8;
444 ((self.bits >> OFFSET) & MASK as u32) as u8
445 })
446 }
447}
448impl W {
449 #[doc = r" Reset value of the register"]
450 #[inline]
451 pub fn reset_value() -> W {
452 W { bits: 0 }
453 }
454 #[doc = r" Writes raw bits to the register"]
455 #[inline]
456 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
457 self.bits = bits;
458 self
459 }
460 #[doc = "Bits 0:2 - Fast IRC Clock Divide 1"]
461 #[inline]
462 pub fn fircdiv1(&mut self) -> _FIRCDIV1W {
463 _FIRCDIV1W { w: self }
464 }
465 #[doc = "Bits 8:10 - Fast IRC Clock Divide 2"]
466 #[inline]
467 pub fn fircdiv2(&mut self) -> _FIRCDIV2W {
468 _FIRCDIV2W { w: self }
469 }
470}