s32k144/cse_pram/
embedded_ram5ll.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u8,
8}
9impl super::EMBEDDEDRAM5LL {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R { bits: self.register.get() }
26    }
27    #[doc = r" Writes to the register"]
28    #[inline]
29    pub fn write<F>(&self, f: F)
30    where
31        F: FnOnce(&mut W) -> &mut W,
32    {
33        let mut w = W::reset_value();
34        f(&mut w);
35        self.register.set(w.bits);
36    }
37    #[doc = r" Writes the reset value to the register"]
38    #[inline]
39    pub fn reset(&self) {
40        self.write(|w| w)
41    }
42}
43#[doc = r" Value of the field"]
44pub struct RAM_LLR {
45    bits: u8,
46}
47impl RAM_LLR {
48    #[doc = r" Value of the field as raw bits"]
49    #[inline]
50    pub fn bits(&self) -> u8 {
51        self.bits
52    }
53}
54#[doc = r" Proxy"]
55pub struct _RAM_LLW<'a> {
56    w: &'a mut W,
57}
58impl<'a> _RAM_LLW<'a> {
59    #[doc = r" Writes raw bits to the field"]
60    #[inline]
61    pub unsafe fn bits(self, value: u8) -> &'a mut W {
62        const MASK: u8 = 255;
63        const OFFSET: u8 = 0;
64        self.w.bits &= !((MASK as u8) << OFFSET);
65        self.w.bits |= ((value & MASK) as u8) << OFFSET;
66        self.w
67    }
68}
69impl R {
70    #[doc = r" Value of the register as raw bits"]
71    #[inline]
72    pub fn bits(&self) -> u8 {
73        self.bits
74    }
75    #[doc = "Bits 0:7 - CRCLL stores the first 8 bits of the 32 bit RAM_"]
76    #[inline]
77    pub fn ram_ll(&self) -> RAM_LLR {
78        let bits = {
79            const MASK: u8 = 255;
80            const OFFSET: u8 = 0;
81            ((self.bits >> OFFSET) & MASK as u8) as u8
82        };
83        RAM_LLR { bits }
84    }
85}
86impl W {
87    #[doc = r" Reset value of the register"]
88    #[inline]
89    pub fn reset_value() -> W {
90        W { bits: 0 }
91    }
92    #[doc = r" Writes raw bits to the register"]
93    #[inline]
94    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
95        self.bits = bits;
96        self
97    }
98    #[doc = "Bits 0:7 - CRCLL stores the first 8 bits of the 32 bit RAM_"]
99    #[inline]
100    pub fn ram_ll(&mut self) -> _RAM_LLW {
101        _RAM_LLW { w: self }
102    }
103}
s32k144/cse_pram/embedded_ram5ll.rs

s32k144/cse_pram/
embedded_ram5ll.rs
