s32k142w_pac/sim/
misctrl0.rs

1#[doc = "Register `MISCTRL0` reader"]
2pub struct R(crate::R<MISCTRL0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MISCTRL0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MISCTRL0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MISCTRL0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MISCTRL0` writer"]
17pub struct W(crate::W<MISCTRL0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MISCTRL0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MISCTRL0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MISCTRL0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "STOP1 monitor bit\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum STOP1_MONITOR_A {
40    #[doc = "0: Bus clock enabled or STOP1 entry aborted"]
41    STOP1_MONITOR_0 = 0,
42    #[doc = "1: STOP1 entry successful"]
43    STOP1_MONITOR_1 = 1,
44}
45impl From<STOP1_MONITOR_A> for bool {
46    #[inline(always)]
47    fn from(variant: STOP1_MONITOR_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `STOP1_MONITOR` reader - STOP1 monitor bit"]
52pub struct STOP1_MONITOR_R(crate::FieldReader<bool, STOP1_MONITOR_A>);
53impl STOP1_MONITOR_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        STOP1_MONITOR_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> STOP1_MONITOR_A {
61        match self.bits {
62            false => STOP1_MONITOR_A::STOP1_MONITOR_0,
63            true => STOP1_MONITOR_A::STOP1_MONITOR_1,
64        }
65    }
66    #[doc = "Checks if the value of the field is `STOP1_MONITOR_0`"]
67    #[inline(always)]
68    pub fn is_stop1_monitor_0(&self) -> bool {
69        **self == STOP1_MONITOR_A::STOP1_MONITOR_0
70    }
71    #[doc = "Checks if the value of the field is `STOP1_MONITOR_1`"]
72    #[inline(always)]
73    pub fn is_stop1_monitor_1(&self) -> bool {
74        **self == STOP1_MONITOR_A::STOP1_MONITOR_1
75    }
76}
77impl core::ops::Deref for STOP1_MONITOR_R {
78    type Target = crate::FieldReader<bool, STOP1_MONITOR_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `STOP1_MONITOR` writer - STOP1 monitor bit"]
85pub struct STOP1_MONITOR_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> STOP1_MONITOR_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: STOP1_MONITOR_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Bus clock enabled or STOP1 entry aborted"]
95    #[inline(always)]
96    pub fn stop1_monitor_0(self) -> &'a mut W {
97        self.variant(STOP1_MONITOR_A::STOP1_MONITOR_0)
98    }
99    #[doc = "STOP1 entry successful"]
100    #[inline(always)]
101    pub fn stop1_monitor_1(self) -> &'a mut W {
102        self.variant(STOP1_MONITOR_A::STOP1_MONITOR_1)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
118        self.w
119    }
120}
121#[doc = "STOP2 monitor bit\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123pub enum STOP2_MONITOR_A {
124    #[doc = "0: System clock enabled or STOP2 entry aborted"]
125    STOP2_MONITOR_0 = 0,
126    #[doc = "1: STOP2 entry successful"]
127    STOP2_MONITOR_1 = 1,
128}
129impl From<STOP2_MONITOR_A> for bool {
130    #[inline(always)]
131    fn from(variant: STOP2_MONITOR_A) -> Self {
132        variant as u8 != 0
133    }
134}
135#[doc = "Field `STOP2_MONITOR` reader - STOP2 monitor bit"]
136pub struct STOP2_MONITOR_R(crate::FieldReader<bool, STOP2_MONITOR_A>);
137impl STOP2_MONITOR_R {
138    #[inline(always)]
139    pub(crate) fn new(bits: bool) -> Self {
140        STOP2_MONITOR_R(crate::FieldReader::new(bits))
141    }
142    #[doc = r"Get enumerated values variant"]
143    #[inline(always)]
144    pub fn variant(&self) -> STOP2_MONITOR_A {
145        match self.bits {
146            false => STOP2_MONITOR_A::STOP2_MONITOR_0,
147            true => STOP2_MONITOR_A::STOP2_MONITOR_1,
148        }
149    }
150    #[doc = "Checks if the value of the field is `STOP2_MONITOR_0`"]
151    #[inline(always)]
152    pub fn is_stop2_monitor_0(&self) -> bool {
153        **self == STOP2_MONITOR_A::STOP2_MONITOR_0
154    }
155    #[doc = "Checks if the value of the field is `STOP2_MONITOR_1`"]
156    #[inline(always)]
157    pub fn is_stop2_monitor_1(&self) -> bool {
158        **self == STOP2_MONITOR_A::STOP2_MONITOR_1
159    }
160}
161impl core::ops::Deref for STOP2_MONITOR_R {
162    type Target = crate::FieldReader<bool, STOP2_MONITOR_A>;
163    #[inline(always)]
164    fn deref(&self) -> &Self::Target {
165        &self.0
166    }
167}
168#[doc = "Field `STOP2_MONITOR` writer - STOP2 monitor bit"]
169pub struct STOP2_MONITOR_W<'a> {
170    w: &'a mut W,
171}
172impl<'a> STOP2_MONITOR_W<'a> {
173    #[doc = r"Writes `variant` to the field"]
174    #[inline(always)]
175    pub fn variant(self, variant: STOP2_MONITOR_A) -> &'a mut W {
176        self.bit(variant.into())
177    }
178    #[doc = "System clock enabled or STOP2 entry aborted"]
179    #[inline(always)]
180    pub fn stop2_monitor_0(self) -> &'a mut W {
181        self.variant(STOP2_MONITOR_A::STOP2_MONITOR_0)
182    }
183    #[doc = "STOP2 entry successful"]
184    #[inline(always)]
185    pub fn stop2_monitor_1(self) -> &'a mut W {
186        self.variant(STOP2_MONITOR_A::STOP2_MONITOR_1)
187    }
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
202        self.w
203    }
204}
205#[doc = "Field `ECC_EEERAM_STAT` reader - ECC double-bit fault detected during MGATE access to FlexRAM or PRAM"]
206pub struct ECC_EEERAM_STAT_R(crate::FieldReader<bool, bool>);
207impl ECC_EEERAM_STAT_R {
208    #[inline(always)]
209    pub(crate) fn new(bits: bool) -> Self {
210        ECC_EEERAM_STAT_R(crate::FieldReader::new(bits))
211    }
212}
213impl core::ops::Deref for ECC_EEERAM_STAT_R {
214    type Target = crate::FieldReader<bool, bool>;
215    #[inline(always)]
216    fn deref(&self) -> &Self::Target {
217        &self.0
218    }
219}
220#[doc = "Field `ECC_EEERAM_STAT` writer - ECC double-bit fault detected during MGATE access to FlexRAM or PRAM"]
221pub struct ECC_EEERAM_STAT_W<'a> {
222    w: &'a mut W,
223}
224impl<'a> ECC_EEERAM_STAT_W<'a> {
225    #[doc = r"Sets the field bit"]
226    #[inline(always)]
227    pub fn set_bit(self) -> &'a mut W {
228        self.bit(true)
229    }
230    #[doc = r"Clears the field bit"]
231    #[inline(always)]
232    pub fn clear_bit(self) -> &'a mut W {
233        self.bit(false)
234    }
235    #[doc = r"Writes raw bits to the field"]
236    #[inline(always)]
237    pub fn bit(self, value: bool) -> &'a mut W {
238        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
239        self.w
240    }
241}
242#[doc = "Field `ECC_MGRAM_STAT` reader - ECC double-bit fault detected during MGATE access to Flash firmware or MGRAM"]
243pub struct ECC_MGRAM_STAT_R(crate::FieldReader<bool, bool>);
244impl ECC_MGRAM_STAT_R {
245    #[inline(always)]
246    pub(crate) fn new(bits: bool) -> Self {
247        ECC_MGRAM_STAT_R(crate::FieldReader::new(bits))
248    }
249}
250impl core::ops::Deref for ECC_MGRAM_STAT_R {
251    type Target = crate::FieldReader<bool, bool>;
252    #[inline(always)]
253    fn deref(&self) -> &Self::Target {
254        &self.0
255    }
256}
257#[doc = "Field `ECC_MGRAM_STAT` writer - ECC double-bit fault detected during MGATE access to Flash firmware or MGRAM"]
258pub struct ECC_MGRAM_STAT_W<'a> {
259    w: &'a mut W,
260}
261impl<'a> ECC_MGRAM_STAT_W<'a> {
262    #[doc = r"Sets the field bit"]
263    #[inline(always)]
264    pub fn set_bit(self) -> &'a mut W {
265        self.bit(true)
266    }
267    #[doc = r"Clears the field bit"]
268    #[inline(always)]
269    pub fn clear_bit(self) -> &'a mut W {
270        self.bit(false)
271    }
272    #[doc = r"Writes raw bits to the field"]
273    #[inline(always)]
274    pub fn bit(self, value: bool) -> &'a mut W {
275        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
276        self.w
277    }
278}
279#[doc = "FTM0 OBE CTRL bit\n\nValue on reset: 0"]
280#[derive(Clone, Copy, Debug, PartialEq)]
281pub enum FTM0_OBE_CTRL_A {
282    #[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
283= 1'b1). Otherwise the channel output is tristated."]
284    FTM0_OBE_CTRL_0 = 0,
285    #[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
286or dual edge capture mode \\[DECAPEN=1'b1\\]."]
287    FTM0_OBE_CTRL_1 = 1,
288}
289impl From<FTM0_OBE_CTRL_A> for bool {
290    #[inline(always)]
291    fn from(variant: FTM0_OBE_CTRL_A) -> Self {
292        variant as u8 != 0
293    }
294}
295#[doc = "Field `FTM0_OBE_CTRL` reader - FTM0 OBE CTRL bit"]
296pub struct FTM0_OBE_CTRL_R(crate::FieldReader<bool, FTM0_OBE_CTRL_A>);
297impl FTM0_OBE_CTRL_R {
298    #[inline(always)]
299    pub(crate) fn new(bits: bool) -> Self {
300        FTM0_OBE_CTRL_R(crate::FieldReader::new(bits))
301    }
302    #[doc = r"Get enumerated values variant"]
303    #[inline(always)]
304    pub fn variant(&self) -> FTM0_OBE_CTRL_A {
305        match self.bits {
306            false => FTM0_OBE_CTRL_A::FTM0_OBE_CTRL_0,
307            true => FTM0_OBE_CTRL_A::FTM0_OBE_CTRL_1,
308        }
309    }
310    #[doc = "Checks if the value of the field is `FTM0_OBE_CTRL_0`"]
311    #[inline(always)]
312    pub fn is_ftm0_obe_ctrl_0(&self) -> bool {
313        **self == FTM0_OBE_CTRL_A::FTM0_OBE_CTRL_0
314    }
315    #[doc = "Checks if the value of the field is `FTM0_OBE_CTRL_1`"]
316    #[inline(always)]
317    pub fn is_ftm0_obe_ctrl_1(&self) -> bool {
318        **self == FTM0_OBE_CTRL_A::FTM0_OBE_CTRL_1
319    }
320}
321impl core::ops::Deref for FTM0_OBE_CTRL_R {
322    type Target = crate::FieldReader<bool, FTM0_OBE_CTRL_A>;
323    #[inline(always)]
324    fn deref(&self) -> &Self::Target {
325        &self.0
326    }
327}
328#[doc = "Field `FTM0_OBE_CTRL` writer - FTM0 OBE CTRL bit"]
329pub struct FTM0_OBE_CTRL_W<'a> {
330    w: &'a mut W,
331}
332impl<'a> FTM0_OBE_CTRL_W<'a> {
333    #[doc = r"Writes `variant` to the field"]
334    #[inline(always)]
335    pub fn variant(self, variant: FTM0_OBE_CTRL_A) -> &'a mut W {
336        self.bit(variant.into())
337    }
338    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
339= 1'b1). Otherwise the channel output is tristated."]
340    #[inline(always)]
341    pub fn ftm0_obe_ctrl_0(self) -> &'a mut W {
342        self.variant(FTM0_OBE_CTRL_A::FTM0_OBE_CTRL_0)
343    }
344    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
345or dual edge capture mode \\[DECAPEN=1'b1\\]."]
346    #[inline(always)]
347    pub fn ftm0_obe_ctrl_1(self) -> &'a mut W {
348        self.variant(FTM0_OBE_CTRL_A::FTM0_OBE_CTRL_1)
349    }
350    #[doc = r"Sets the field bit"]
351    #[inline(always)]
352    pub fn set_bit(self) -> &'a mut W {
353        self.bit(true)
354    }
355    #[doc = r"Clears the field bit"]
356    #[inline(always)]
357    pub fn clear_bit(self) -> &'a mut W {
358        self.bit(false)
359    }
360    #[doc = r"Writes raw bits to the field"]
361    #[inline(always)]
362    pub fn bit(self, value: bool) -> &'a mut W {
363        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
364        self.w
365    }
366}
367#[doc = "FTM1 OBE CTRL bit\n\nValue on reset: 0"]
368#[derive(Clone, Copy, Debug, PartialEq)]
369pub enum FTM1_OBE_CTRL_A {
370    #[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
371= 1'b1). Otherwise the channel output is tristated."]
372    FTM1_OBE_CTRL_0 = 0,
373    #[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
374or dual edge capture mode \\[DECAPEN=1'b1\\]."]
375    FTM1_OBE_CTRL_1 = 1,
376}
377impl From<FTM1_OBE_CTRL_A> for bool {
378    #[inline(always)]
379    fn from(variant: FTM1_OBE_CTRL_A) -> Self {
380        variant as u8 != 0
381    }
382}
383#[doc = "Field `FTM1_OBE_CTRL` reader - FTM1 OBE CTRL bit"]
384pub struct FTM1_OBE_CTRL_R(crate::FieldReader<bool, FTM1_OBE_CTRL_A>);
385impl FTM1_OBE_CTRL_R {
386    #[inline(always)]
387    pub(crate) fn new(bits: bool) -> Self {
388        FTM1_OBE_CTRL_R(crate::FieldReader::new(bits))
389    }
390    #[doc = r"Get enumerated values variant"]
391    #[inline(always)]
392    pub fn variant(&self) -> FTM1_OBE_CTRL_A {
393        match self.bits {
394            false => FTM1_OBE_CTRL_A::FTM1_OBE_CTRL_0,
395            true => FTM1_OBE_CTRL_A::FTM1_OBE_CTRL_1,
396        }
397    }
398    #[doc = "Checks if the value of the field is `FTM1_OBE_CTRL_0`"]
399    #[inline(always)]
400    pub fn is_ftm1_obe_ctrl_0(&self) -> bool {
401        **self == FTM1_OBE_CTRL_A::FTM1_OBE_CTRL_0
402    }
403    #[doc = "Checks if the value of the field is `FTM1_OBE_CTRL_1`"]
404    #[inline(always)]
405    pub fn is_ftm1_obe_ctrl_1(&self) -> bool {
406        **self == FTM1_OBE_CTRL_A::FTM1_OBE_CTRL_1
407    }
408}
409impl core::ops::Deref for FTM1_OBE_CTRL_R {
410    type Target = crate::FieldReader<bool, FTM1_OBE_CTRL_A>;
411    #[inline(always)]
412    fn deref(&self) -> &Self::Target {
413        &self.0
414    }
415}
416#[doc = "Field `FTM1_OBE_CTRL` writer - FTM1 OBE CTRL bit"]
417pub struct FTM1_OBE_CTRL_W<'a> {
418    w: &'a mut W,
419}
420impl<'a> FTM1_OBE_CTRL_W<'a> {
421    #[doc = r"Writes `variant` to the field"]
422    #[inline(always)]
423    pub fn variant(self, variant: FTM1_OBE_CTRL_A) -> &'a mut W {
424        self.bit(variant.into())
425    }
426    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
427= 1'b1). Otherwise the channel output is tristated."]
428    #[inline(always)]
429    pub fn ftm1_obe_ctrl_0(self) -> &'a mut W {
430        self.variant(FTM1_OBE_CTRL_A::FTM1_OBE_CTRL_0)
431    }
432    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
433or dual edge capture mode \\[DECAPEN=1'b1\\]."]
434    #[inline(always)]
435    pub fn ftm1_obe_ctrl_1(self) -> &'a mut W {
436        self.variant(FTM1_OBE_CTRL_A::FTM1_OBE_CTRL_1)
437    }
438    #[doc = r"Sets the field bit"]
439    #[inline(always)]
440    pub fn set_bit(self) -> &'a mut W {
441        self.bit(true)
442    }
443    #[doc = r"Clears the field bit"]
444    #[inline(always)]
445    pub fn clear_bit(self) -> &'a mut W {
446        self.bit(false)
447    }
448    #[doc = r"Writes raw bits to the field"]
449    #[inline(always)]
450    pub fn bit(self, value: bool) -> &'a mut W {
451        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
452        self.w
453    }
454}
455#[doc = "FTM2 OBE CTRL bit\n\nValue on reset: 0"]
456#[derive(Clone, Copy, Debug, PartialEq)]
457pub enum FTM2_OBE_CTRL_A {
458    #[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
459= 1'b1). Otherwise the channel output is tristated."]
460    FTM2_OBE_CTRL_0 = 0,
461    #[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
462or dual edge capture mode \\[DECAPEN=1'b1\\]."]
463    FTM2_OBE_CTRL_1 = 1,
464}
465impl From<FTM2_OBE_CTRL_A> for bool {
466    #[inline(always)]
467    fn from(variant: FTM2_OBE_CTRL_A) -> Self {
468        variant as u8 != 0
469    }
470}
471#[doc = "Field `FTM2_OBE_CTRL` reader - FTM2 OBE CTRL bit"]
472pub struct FTM2_OBE_CTRL_R(crate::FieldReader<bool, FTM2_OBE_CTRL_A>);
473impl FTM2_OBE_CTRL_R {
474    #[inline(always)]
475    pub(crate) fn new(bits: bool) -> Self {
476        FTM2_OBE_CTRL_R(crate::FieldReader::new(bits))
477    }
478    #[doc = r"Get enumerated values variant"]
479    #[inline(always)]
480    pub fn variant(&self) -> FTM2_OBE_CTRL_A {
481        match self.bits {
482            false => FTM2_OBE_CTRL_A::FTM2_OBE_CTRL_0,
483            true => FTM2_OBE_CTRL_A::FTM2_OBE_CTRL_1,
484        }
485    }
486    #[doc = "Checks if the value of the field is `FTM2_OBE_CTRL_0`"]
487    #[inline(always)]
488    pub fn is_ftm2_obe_ctrl_0(&self) -> bool {
489        **self == FTM2_OBE_CTRL_A::FTM2_OBE_CTRL_0
490    }
491    #[doc = "Checks if the value of the field is `FTM2_OBE_CTRL_1`"]
492    #[inline(always)]
493    pub fn is_ftm2_obe_ctrl_1(&self) -> bool {
494        **self == FTM2_OBE_CTRL_A::FTM2_OBE_CTRL_1
495    }
496}
497impl core::ops::Deref for FTM2_OBE_CTRL_R {
498    type Target = crate::FieldReader<bool, FTM2_OBE_CTRL_A>;
499    #[inline(always)]
500    fn deref(&self) -> &Self::Target {
501        &self.0
502    }
503}
504#[doc = "Field `FTM2_OBE_CTRL` writer - FTM2 OBE CTRL bit"]
505pub struct FTM2_OBE_CTRL_W<'a> {
506    w: &'a mut W,
507}
508impl<'a> FTM2_OBE_CTRL_W<'a> {
509    #[doc = r"Writes `variant` to the field"]
510    #[inline(always)]
511    pub fn variant(self, variant: FTM2_OBE_CTRL_A) -> &'a mut W {
512        self.bit(variant.into())
513    }
514    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
515= 1'b1). Otherwise the channel output is tristated."]
516    #[inline(always)]
517    pub fn ftm2_obe_ctrl_0(self) -> &'a mut W {
518        self.variant(FTM2_OBE_CTRL_A::FTM2_OBE_CTRL_0)
519    }
520    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
521or dual edge capture mode \\[DECAPEN=1'b1\\]."]
522    #[inline(always)]
523    pub fn ftm2_obe_ctrl_1(self) -> &'a mut W {
524        self.variant(FTM2_OBE_CTRL_A::FTM2_OBE_CTRL_1)
525    }
526    #[doc = r"Sets the field bit"]
527    #[inline(always)]
528    pub fn set_bit(self) -> &'a mut W {
529        self.bit(true)
530    }
531    #[doc = r"Clears the field bit"]
532    #[inline(always)]
533    pub fn clear_bit(self) -> &'a mut W {
534        self.bit(false)
535    }
536    #[doc = r"Writes raw bits to the field"]
537    #[inline(always)]
538    pub fn bit(self, value: bool) -> &'a mut W {
539        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
540        self.w
541    }
542}
543#[doc = "FTM3 OBE CTRL bit\n\nValue on reset: 0"]
544#[derive(Clone, Copy, Debug, PartialEq)]
545pub enum FTM3_OBE_CTRL_A {
546    #[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
547= 1'b1). Otherwise the channel output is tristated."]
548    FTM3_OBE_CTRL_0 = 0,
549    #[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
550or dual edge capture mode \\[DECAPEN=1'b1\\]."]
551    FTM3_OBE_CTRL_1 = 1,
552}
553impl From<FTM3_OBE_CTRL_A> for bool {
554    #[inline(always)]
555    fn from(variant: FTM3_OBE_CTRL_A) -> Self {
556        variant as u8 != 0
557    }
558}
559#[doc = "Field `FTM3_OBE_CTRL` reader - FTM3 OBE CTRL bit"]
560pub struct FTM3_OBE_CTRL_R(crate::FieldReader<bool, FTM3_OBE_CTRL_A>);
561impl FTM3_OBE_CTRL_R {
562    #[inline(always)]
563    pub(crate) fn new(bits: bool) -> Self {
564        FTM3_OBE_CTRL_R(crate::FieldReader::new(bits))
565    }
566    #[doc = r"Get enumerated values variant"]
567    #[inline(always)]
568    pub fn variant(&self) -> FTM3_OBE_CTRL_A {
569        match self.bits {
570            false => FTM3_OBE_CTRL_A::FTM3_OBE_CTRL_0,
571            true => FTM3_OBE_CTRL_A::FTM3_OBE_CTRL_1,
572        }
573    }
574    #[doc = "Checks if the value of the field is `FTM3_OBE_CTRL_0`"]
575    #[inline(always)]
576    pub fn is_ftm3_obe_ctrl_0(&self) -> bool {
577        **self == FTM3_OBE_CTRL_A::FTM3_OBE_CTRL_0
578    }
579    #[doc = "Checks if the value of the field is `FTM3_OBE_CTRL_1`"]
580    #[inline(always)]
581    pub fn is_ftm3_obe_ctrl_1(&self) -> bool {
582        **self == FTM3_OBE_CTRL_A::FTM3_OBE_CTRL_1
583    }
584}
585impl core::ops::Deref for FTM3_OBE_CTRL_R {
586    type Target = crate::FieldReader<bool, FTM3_OBE_CTRL_A>;
587    #[inline(always)]
588    fn deref(&self) -> &Self::Target {
589        &self.0
590    }
591}
592#[doc = "Field `FTM3_OBE_CTRL` writer - FTM3 OBE CTRL bit"]
593pub struct FTM3_OBE_CTRL_W<'a> {
594    w: &'a mut W,
595}
596impl<'a> FTM3_OBE_CTRL_W<'a> {
597    #[doc = r"Writes `variant` to the field"]
598    #[inline(always)]
599    pub fn variant(self, variant: FTM3_OBE_CTRL_A) -> &'a mut W {
600        self.bit(variant.into())
601    }
602    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
603= 1'b1). Otherwise the channel output is tristated."]
604    #[inline(always)]
605    pub fn ftm3_obe_ctrl_0(self) -> &'a mut W {
606        self.variant(FTM3_OBE_CTRL_A::FTM3_OBE_CTRL_0)
607    }
608    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
609or dual edge capture mode \\[DECAPEN=1'b1\\]."]
610    #[inline(always)]
611    pub fn ftm3_obe_ctrl_1(self) -> &'a mut W {
612        self.variant(FTM3_OBE_CTRL_A::FTM3_OBE_CTRL_1)
613    }
614    #[doc = r"Sets the field bit"]
615    #[inline(always)]
616    pub fn set_bit(self) -> &'a mut W {
617        self.bit(true)
618    }
619    #[doc = r"Clears the field bit"]
620    #[inline(always)]
621    pub fn clear_bit(self) -> &'a mut W {
622        self.bit(false)
623    }
624    #[doc = r"Writes raw bits to the field"]
625    #[inline(always)]
626    pub fn bit(self, value: bool) -> &'a mut W {
627        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
628        self.w
629    }
630}
631impl R {
632    #[doc = "Bit 9 - STOP1 monitor bit"]
633    #[inline(always)]
634    pub fn stop1_monitor(&self) -> STOP1_MONITOR_R {
635        STOP1_MONITOR_R::new(((self.bits >> 9) & 0x01) != 0)
636    }
637    #[doc = "Bit 10 - STOP2 monitor bit"]
638    #[inline(always)]
639    pub fn stop2_monitor(&self) -> STOP2_MONITOR_R {
640        STOP2_MONITOR_R::new(((self.bits >> 10) & 0x01) != 0)
641    }
642    #[doc = "Bit 11 - ECC double-bit fault detected during MGATE access to FlexRAM or PRAM"]
643    #[inline(always)]
644    pub fn ecc_eeeram_stat(&self) -> ECC_EEERAM_STAT_R {
645        ECC_EEERAM_STAT_R::new(((self.bits >> 11) & 0x01) != 0)
646    }
647    #[doc = "Bit 12 - ECC double-bit fault detected during MGATE access to Flash firmware or MGRAM"]
648    #[inline(always)]
649    pub fn ecc_mgram_stat(&self) -> ECC_MGRAM_STAT_R {
650        ECC_MGRAM_STAT_R::new(((self.bits >> 12) & 0x01) != 0)
651    }
652    #[doc = "Bit 16 - FTM0 OBE CTRL bit"]
653    #[inline(always)]
654    pub fn ftm0_obe_ctrl(&self) -> FTM0_OBE_CTRL_R {
655        FTM0_OBE_CTRL_R::new(((self.bits >> 16) & 0x01) != 0)
656    }
657    #[doc = "Bit 17 - FTM1 OBE CTRL bit"]
658    #[inline(always)]
659    pub fn ftm1_obe_ctrl(&self) -> FTM1_OBE_CTRL_R {
660        FTM1_OBE_CTRL_R::new(((self.bits >> 17) & 0x01) != 0)
661    }
662    #[doc = "Bit 18 - FTM2 OBE CTRL bit"]
663    #[inline(always)]
664    pub fn ftm2_obe_ctrl(&self) -> FTM2_OBE_CTRL_R {
665        FTM2_OBE_CTRL_R::new(((self.bits >> 18) & 0x01) != 0)
666    }
667    #[doc = "Bit 19 - FTM3 OBE CTRL bit"]
668    #[inline(always)]
669    pub fn ftm3_obe_ctrl(&self) -> FTM3_OBE_CTRL_R {
670        FTM3_OBE_CTRL_R::new(((self.bits >> 19) & 0x01) != 0)
671    }
672}
673impl W {
674    #[doc = "Bit 9 - STOP1 monitor bit"]
675    #[inline(always)]
676    pub fn stop1_monitor(&mut self) -> STOP1_MONITOR_W {
677        STOP1_MONITOR_W { w: self }
678    }
679    #[doc = "Bit 10 - STOP2 monitor bit"]
680    #[inline(always)]
681    pub fn stop2_monitor(&mut self) -> STOP2_MONITOR_W {
682        STOP2_MONITOR_W { w: self }
683    }
684    #[doc = "Bit 11 - ECC double-bit fault detected during MGATE access to FlexRAM or PRAM"]
685    #[inline(always)]
686    pub fn ecc_eeeram_stat(&mut self) -> ECC_EEERAM_STAT_W {
687        ECC_EEERAM_STAT_W { w: self }
688    }
689    #[doc = "Bit 12 - ECC double-bit fault detected during MGATE access to Flash firmware or MGRAM"]
690    #[inline(always)]
691    pub fn ecc_mgram_stat(&mut self) -> ECC_MGRAM_STAT_W {
692        ECC_MGRAM_STAT_W { w: self }
693    }
694    #[doc = "Bit 16 - FTM0 OBE CTRL bit"]
695    #[inline(always)]
696    pub fn ftm0_obe_ctrl(&mut self) -> FTM0_OBE_CTRL_W {
697        FTM0_OBE_CTRL_W { w: self }
698    }
699    #[doc = "Bit 17 - FTM1 OBE CTRL bit"]
700    #[inline(always)]
701    pub fn ftm1_obe_ctrl(&mut self) -> FTM1_OBE_CTRL_W {
702        FTM1_OBE_CTRL_W { w: self }
703    }
704    #[doc = "Bit 18 - FTM2 OBE CTRL bit"]
705    #[inline(always)]
706    pub fn ftm2_obe_ctrl(&mut self) -> FTM2_OBE_CTRL_W {
707        FTM2_OBE_CTRL_W { w: self }
708    }
709    #[doc = "Bit 19 - FTM3 OBE CTRL bit"]
710    #[inline(always)]
711    pub fn ftm3_obe_ctrl(&mut self) -> FTM3_OBE_CTRL_W {
712        FTM3_OBE_CTRL_W { w: self }
713    }
714    #[doc = "Writes raw bits to the register."]
715    #[inline(always)]
716    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
717        self.0.bits(bits);
718        self
719    }
720}
721#[doc = "Miscellaneous control register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [misctrl0](index.html) module"]
722pub struct MISCTRL0_SPEC;
723impl crate::RegisterSpec for MISCTRL0_SPEC {
724    type Ux = u32;
725}
726#[doc = "`read()` method returns [misctrl0::R](R) reader structure"]
727impl crate::Readable for MISCTRL0_SPEC {
728    type Reader = R;
729}
730#[doc = "`write(|w| ..)` method takes [misctrl0::W](W) writer structure"]
731impl crate::Writable for MISCTRL0_SPEC {
732    type Writer = W;
733}
734#[doc = "`reset()` method sets MISCTRL0 to value 0"]
735impl crate::Resettable for MISCTRL0_SPEC {
736    #[inline(always)]
737    fn reset_value() -> Self::Ux {
738        0
739    }
740}
s32k142w_pac/sim/misctrl0.rs

s32k142w_pac/sim/
misctrl0.rs
