1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Status and Control register"]
5 pub sc: crate::Reg<sc::SC_SPEC>,
6 #[doc = "0x04 - Modulus register"]
7 pub mod_: crate::Reg<mod_::MOD_SPEC>,
8 #[doc = "0x08 - Counter register"]
9 pub cnt: crate::Reg<cnt::CNT_SPEC>,
10 #[doc = "0x0c - Interrupt Delay register"]
11 pub idly: crate::Reg<idly::IDLY_SPEC>,
12 #[doc = "0x10 - Channel n Control register 1"]
13 pub ch0c1: crate::Reg<chc1::CHC1_SPEC>,
14 #[doc = "0x14 - Channel n Status register"]
15 pub ch0s: crate::Reg<chs::CHS_SPEC>,
16 #[doc = "0x18 - Channel n Delay 0 register"]
17 pub ch0dly0: crate::Reg<chdly0::CHDLY0_SPEC>,
18 #[doc = "0x1c - Channel n Delay 1 register"]
19 pub ch0dly1: crate::Reg<chdly1::CHDLY1_SPEC>,
20 #[doc = "0x20 - Channel n Delay 2 register"]
21 pub ch0dly2: crate::Reg<chdly2::CHDLY2_SPEC>,
22 #[doc = "0x24 - Channel n Delay 3 register"]
23 pub ch0dly3: crate::Reg<chdly3::CHDLY3_SPEC>,
24 #[doc = "0x28 - Channel n Delay 4 register"]
25 pub ch0dly4: crate::Reg<chdly4::CHDLY4_SPEC>,
26 #[doc = "0x2c - Channel n Delay 5 register"]
27 pub ch0dly5: crate::Reg<chdly5::CHDLY5_SPEC>,
28 #[doc = "0x30 - Channel n Delay 6 register"]
29 pub ch0dly6: crate::Reg<chdly6::CHDLY6_SPEC>,
30 #[doc = "0x34 - Channel n Delay 7 register"]
31 pub ch0dly7: crate::Reg<chdly7::CHDLY7_SPEC>,
32 #[doc = "0x38 - Channel n Control register 1"]
33 pub ch1c1: crate::Reg<chc1::CHC1_SPEC>,
34 #[doc = "0x3c - Channel n Status register"]
35 pub ch1s: crate::Reg<chs::CHS_SPEC>,
36 #[doc = "0x40 - Channel n Delay 0 register"]
37 pub ch1dly0: crate::Reg<chdly0::CHDLY0_SPEC>,
38 #[doc = "0x44 - Channel n Delay 1 register"]
39 pub ch1dly1: crate::Reg<chdly1::CHDLY1_SPEC>,
40 #[doc = "0x48 - Channel n Delay 2 register"]
41 pub ch1dly2: crate::Reg<chdly2::CHDLY2_SPEC>,
42 #[doc = "0x4c - Channel n Delay 3 register"]
43 pub ch1dly3: crate::Reg<chdly3::CHDLY3_SPEC>,
44 #[doc = "0x50 - Channel n Delay 4 register"]
45 pub ch1dly4: crate::Reg<chdly4::CHDLY4_SPEC>,
46 #[doc = "0x54 - Channel n Delay 5 register"]
47 pub ch1dly5: crate::Reg<chdly5::CHDLY5_SPEC>,
48 #[doc = "0x58 - Channel n Delay 6 register"]
49 pub ch1dly6: crate::Reg<chdly6::CHDLY6_SPEC>,
50 #[doc = "0x5c - Channel n Delay 7 register"]
51 pub ch1dly7: crate::Reg<chdly7::CHDLY7_SPEC>,
52 _reserved24: [u8; 0x0130],
53 #[doc = "0x190 - Pulse-Out n Enable register"]
54 pub poen: crate::Reg<poen::POEN_SPEC>,
55 _reserved_25_dly1: [u8; 0x04],
56}
57impl RegisterBlock {
58 #[doc = "0x194 - PDB1_DLY2 register."]
59 #[inline(always)]
60 pub fn pdb1_dly2(&self) -> &crate::Reg<pdb1_dly2::PDB1_DLY2_SPEC> {
61 unsafe {
62 &*(((self as *const Self) as *const u8).add(404usize)
63 as *const crate::Reg<pdb1_dly2::PDB1_DLY2_SPEC>)
64 }
65 }
66 #[doc = "0x194 - Pulse-Out n Delay register"]
67 #[inline(always)]
68 pub fn pdb1_podly(&self) -> &crate::Reg<pdb1_podly::PDB1_PODLY_SPEC> {
69 unsafe {
70 &*(((self as *const Self) as *const u8).add(404usize)
71 as *const crate::Reg<pdb1_podly::PDB1_PODLY_SPEC>)
72 }
73 }
74 #[doc = "0x196 - PDB1_DLY1 register."]
75 #[inline(always)]
76 pub fn dly1(&self) -> &crate::Reg<dly1::DLY1_SPEC> {
77 unsafe {
78 &*(((self as *const Self) as *const u8).add(406usize)
79 as *const crate::Reg<dly1::DLY1_SPEC>)
80 }
81 }
82}
83#[doc = "SC register accessor: an alias for `Reg<SC_SPEC>`"]
84pub type SC = crate::Reg<sc::SC_SPEC>;
85#[doc = "Status and Control register"]
86pub mod sc;
87#[doc = "MOD register accessor: an alias for `Reg<MOD_SPEC>`"]
88pub type MOD = crate::Reg<mod_::MOD_SPEC>;
89#[doc = "Modulus register"]
90pub mod mod_;
91#[doc = "CNT register accessor: an alias for `Reg<CNT_SPEC>`"]
92pub type CNT = crate::Reg<cnt::CNT_SPEC>;
93#[doc = "Counter register"]
94pub mod cnt;
95#[doc = "IDLY register accessor: an alias for `Reg<IDLY_SPEC>`"]
96pub type IDLY = crate::Reg<idly::IDLY_SPEC>;
97#[doc = "Interrupt Delay register"]
98pub mod idly;
99#[doc = "CHC1 register accessor: an alias for `Reg<CHC1_SPEC>`"]
100pub type CHC1 = crate::Reg<chc1::CHC1_SPEC>;
101#[doc = "Channel n Control register 1"]
102pub mod chc1;
103#[doc = "CHS register accessor: an alias for `Reg<CHS_SPEC>`"]
104pub type CHS = crate::Reg<chs::CHS_SPEC>;
105#[doc = "Channel n Status register"]
106pub mod chs;
107#[doc = "CHDLY0 register accessor: an alias for `Reg<CHDLY0_SPEC>`"]
108pub type CHDLY0 = crate::Reg<chdly0::CHDLY0_SPEC>;
109#[doc = "Channel n Delay 0 register"]
110pub mod chdly0;
111#[doc = "CHDLY1 register accessor: an alias for `Reg<CHDLY1_SPEC>`"]
112pub type CHDLY1 = crate::Reg<chdly1::CHDLY1_SPEC>;
113#[doc = "Channel n Delay 1 register"]
114pub mod chdly1;
115#[doc = "CHDLY2 register accessor: an alias for `Reg<CHDLY2_SPEC>`"]
116pub type CHDLY2 = crate::Reg<chdly2::CHDLY2_SPEC>;
117#[doc = "Channel n Delay 2 register"]
118pub mod chdly2;
119#[doc = "CHDLY3 register accessor: an alias for `Reg<CHDLY3_SPEC>`"]
120pub type CHDLY3 = crate::Reg<chdly3::CHDLY3_SPEC>;
121#[doc = "Channel n Delay 3 register"]
122pub mod chdly3;
123#[doc = "CHDLY4 register accessor: an alias for `Reg<CHDLY4_SPEC>`"]
124pub type CHDLY4 = crate::Reg<chdly4::CHDLY4_SPEC>;
125#[doc = "Channel n Delay 4 register"]
126pub mod chdly4;
127#[doc = "CHDLY5 register accessor: an alias for `Reg<CHDLY5_SPEC>`"]
128pub type CHDLY5 = crate::Reg<chdly5::CHDLY5_SPEC>;
129#[doc = "Channel n Delay 5 register"]
130pub mod chdly5;
131#[doc = "CHDLY6 register accessor: an alias for `Reg<CHDLY6_SPEC>`"]
132pub type CHDLY6 = crate::Reg<chdly6::CHDLY6_SPEC>;
133#[doc = "Channel n Delay 6 register"]
134pub mod chdly6;
135#[doc = "CHDLY7 register accessor: an alias for `Reg<CHDLY7_SPEC>`"]
136pub type CHDLY7 = crate::Reg<chdly7::CHDLY7_SPEC>;
137#[doc = "Channel n Delay 7 register"]
138pub mod chdly7;
139#[doc = "POEN register accessor: an alias for `Reg<POEN_SPEC>`"]
140pub type POEN = crate::Reg<poen::POEN_SPEC>;
141#[doc = "Pulse-Out n Enable register"]
142pub mod poen;
143#[doc = "PDB1_PODLY register accessor: an alias for `Reg<PDB1_PODLY_SPEC>`"]
144pub type PDB1_PODLY = crate::Reg<pdb1_podly::PDB1_PODLY_SPEC>;
145#[doc = "Pulse-Out n Delay register"]
146pub mod pdb1_podly;
147#[doc = "PDB1_DLY2 register accessor: an alias for `Reg<PDB1_DLY2_SPEC>`"]
148pub type PDB1_DLY2 = crate::Reg<pdb1_dly2::PDB1_DLY2_SPEC>;
149#[doc = "PDB1_DLY2 register."]
150pub mod pdb1_dly2;
151#[doc = "DLY1 register accessor: an alias for `Reg<DLY1_SPEC>`"]
152pub type DLY1 = crate::Reg<dly1::DLY1_SPEC>;
153#[doc = "PDB1_DLY1 register."]
154pub mod dly1;