s32k142_pac/ftm0/
synconf.rs

1#[doc = "Register `SYNCONF` reader"]
2pub struct R(crate::R<SYNCONF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYNCONF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYNCONF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYNCONF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYNCONF` writer"]
17pub struct W(crate::W<SYNCONF_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYNCONF_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYNCONF_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYNCONF_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Hardware Trigger Mode\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum HWTRIGMODE_A {
40    #[doc = "0: FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2."]
41    _0 = 0,
42    #[doc = "1: FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2."]
43    _1 = 1,
44}
45impl From<HWTRIGMODE_A> for bool {
46    #[inline(always)]
47    fn from(variant: HWTRIGMODE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `HWTRIGMODE` reader - Hardware Trigger Mode"]
52pub struct HWTRIGMODE_R(crate::FieldReader<bool, HWTRIGMODE_A>);
53impl HWTRIGMODE_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        HWTRIGMODE_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> HWTRIGMODE_A {
61        match self.bits {
62            false => HWTRIGMODE_A::_0,
63            true => HWTRIGMODE_A::_1,
64        }
65    }
66    #[doc = "Checks if the value of the field is `_0`"]
67    #[inline(always)]
68    pub fn is_0(&self) -> bool {
69        **self == HWTRIGMODE_A::_0
70    }
71    #[doc = "Checks if the value of the field is `_1`"]
72    #[inline(always)]
73    pub fn is_1(&self) -> bool {
74        **self == HWTRIGMODE_A::_1
75    }
76}
77impl core::ops::Deref for HWTRIGMODE_R {
78    type Target = crate::FieldReader<bool, HWTRIGMODE_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `HWTRIGMODE` writer - Hardware Trigger Mode"]
85pub struct HWTRIGMODE_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> HWTRIGMODE_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: HWTRIGMODE_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2."]
95    #[inline(always)]
96    pub fn _0(self) -> &'a mut W {
97        self.variant(HWTRIGMODE_A::_0)
98    }
99    #[doc = "FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2."]
100    #[inline(always)]
101    pub fn _1(self) -> &'a mut W {
102        self.variant(HWTRIGMODE_A::_1)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "CNTIN Register Synchronization\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123pub enum CNTINC_A {
124    #[doc = "0: CNTIN register is updated with its buffer value at all rising edges of FTM input clock."]
125    _0 = 0,
126    #[doc = "1: CNTIN register is updated with its buffer value by the PWM synchronization."]
127    _1 = 1,
128}
129impl From<CNTINC_A> for bool {
130    #[inline(always)]
131    fn from(variant: CNTINC_A) -> Self {
132        variant as u8 != 0
133    }
134}
135#[doc = "Field `CNTINC` reader - CNTIN Register Synchronization"]
136pub struct CNTINC_R(crate::FieldReader<bool, CNTINC_A>);
137impl CNTINC_R {
138    #[inline(always)]
139    pub(crate) fn new(bits: bool) -> Self {
140        CNTINC_R(crate::FieldReader::new(bits))
141    }
142    #[doc = r"Get enumerated values variant"]
143    #[inline(always)]
144    pub fn variant(&self) -> CNTINC_A {
145        match self.bits {
146            false => CNTINC_A::_0,
147            true => CNTINC_A::_1,
148        }
149    }
150    #[doc = "Checks if the value of the field is `_0`"]
151    #[inline(always)]
152    pub fn is_0(&self) -> bool {
153        **self == CNTINC_A::_0
154    }
155    #[doc = "Checks if the value of the field is `_1`"]
156    #[inline(always)]
157    pub fn is_1(&self) -> bool {
158        **self == CNTINC_A::_1
159    }
160}
161impl core::ops::Deref for CNTINC_R {
162    type Target = crate::FieldReader<bool, CNTINC_A>;
163    #[inline(always)]
164    fn deref(&self) -> &Self::Target {
165        &self.0
166    }
167}
168#[doc = "Field `CNTINC` writer - CNTIN Register Synchronization"]
169pub struct CNTINC_W<'a> {
170    w: &'a mut W,
171}
172impl<'a> CNTINC_W<'a> {
173    #[doc = r"Writes `variant` to the field"]
174    #[inline(always)]
175    pub fn variant(self, variant: CNTINC_A) -> &'a mut W {
176        self.bit(variant.into())
177    }
178    #[doc = "CNTIN register is updated with its buffer value at all rising edges of FTM input clock."]
179    #[inline(always)]
180    pub fn _0(self) -> &'a mut W {
181        self.variant(CNTINC_A::_0)
182    }
183    #[doc = "CNTIN register is updated with its buffer value by the PWM synchronization."]
184    #[inline(always)]
185    pub fn _1(self) -> &'a mut W {
186        self.variant(CNTINC_A::_1)
187    }
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
202        self.w
203    }
204}
205#[doc = "INVCTRL Register Synchronization\n\nValue on reset: 0"]
206#[derive(Clone, Copy, Debug, PartialEq)]
207pub enum INVC_A {
208    #[doc = "0: INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
209    _0 = 0,
210    #[doc = "1: INVCTRL register is updated with its buffer value by the PWM synchronization."]
211    _1 = 1,
212}
213impl From<INVC_A> for bool {
214    #[inline(always)]
215    fn from(variant: INVC_A) -> Self {
216        variant as u8 != 0
217    }
218}
219#[doc = "Field `INVC` reader - INVCTRL Register Synchronization"]
220pub struct INVC_R(crate::FieldReader<bool, INVC_A>);
221impl INVC_R {
222    #[inline(always)]
223    pub(crate) fn new(bits: bool) -> Self {
224        INVC_R(crate::FieldReader::new(bits))
225    }
226    #[doc = r"Get enumerated values variant"]
227    #[inline(always)]
228    pub fn variant(&self) -> INVC_A {
229        match self.bits {
230            false => INVC_A::_0,
231            true => INVC_A::_1,
232        }
233    }
234    #[doc = "Checks if the value of the field is `_0`"]
235    #[inline(always)]
236    pub fn is_0(&self) -> bool {
237        **self == INVC_A::_0
238    }
239    #[doc = "Checks if the value of the field is `_1`"]
240    #[inline(always)]
241    pub fn is_1(&self) -> bool {
242        **self == INVC_A::_1
243    }
244}
245impl core::ops::Deref for INVC_R {
246    type Target = crate::FieldReader<bool, INVC_A>;
247    #[inline(always)]
248    fn deref(&self) -> &Self::Target {
249        &self.0
250    }
251}
252#[doc = "Field `INVC` writer - INVCTRL Register Synchronization"]
253pub struct INVC_W<'a> {
254    w: &'a mut W,
255}
256impl<'a> INVC_W<'a> {
257    #[doc = r"Writes `variant` to the field"]
258    #[inline(always)]
259    pub fn variant(self, variant: INVC_A) -> &'a mut W {
260        self.bit(variant.into())
261    }
262    #[doc = "INVCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
263    #[inline(always)]
264    pub fn _0(self) -> &'a mut W {
265        self.variant(INVC_A::_0)
266    }
267    #[doc = "INVCTRL register is updated with its buffer value by the PWM synchronization."]
268    #[inline(always)]
269    pub fn _1(self) -> &'a mut W {
270        self.variant(INVC_A::_1)
271    }
272    #[doc = r"Sets the field bit"]
273    #[inline(always)]
274    pub fn set_bit(self) -> &'a mut W {
275        self.bit(true)
276    }
277    #[doc = r"Clears the field bit"]
278    #[inline(always)]
279    pub fn clear_bit(self) -> &'a mut W {
280        self.bit(false)
281    }
282    #[doc = r"Writes raw bits to the field"]
283    #[inline(always)]
284    pub fn bit(self, value: bool) -> &'a mut W {
285        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
286        self.w
287    }
288}
289#[doc = "SWOCTRL Register Synchronization\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq)]
291pub enum SWOC_A {
292    #[doc = "0: SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
293    _0 = 0,
294    #[doc = "1: SWOCTRL register is updated with its buffer value by the PWM synchronization."]
295    _1 = 1,
296}
297impl From<SWOC_A> for bool {
298    #[inline(always)]
299    fn from(variant: SWOC_A) -> Self {
300        variant as u8 != 0
301    }
302}
303#[doc = "Field `SWOC` reader - SWOCTRL Register Synchronization"]
304pub struct SWOC_R(crate::FieldReader<bool, SWOC_A>);
305impl SWOC_R {
306    #[inline(always)]
307    pub(crate) fn new(bits: bool) -> Self {
308        SWOC_R(crate::FieldReader::new(bits))
309    }
310    #[doc = r"Get enumerated values variant"]
311    #[inline(always)]
312    pub fn variant(&self) -> SWOC_A {
313        match self.bits {
314            false => SWOC_A::_0,
315            true => SWOC_A::_1,
316        }
317    }
318    #[doc = "Checks if the value of the field is `_0`"]
319    #[inline(always)]
320    pub fn is_0(&self) -> bool {
321        **self == SWOC_A::_0
322    }
323    #[doc = "Checks if the value of the field is `_1`"]
324    #[inline(always)]
325    pub fn is_1(&self) -> bool {
326        **self == SWOC_A::_1
327    }
328}
329impl core::ops::Deref for SWOC_R {
330    type Target = crate::FieldReader<bool, SWOC_A>;
331    #[inline(always)]
332    fn deref(&self) -> &Self::Target {
333        &self.0
334    }
335}
336#[doc = "Field `SWOC` writer - SWOCTRL Register Synchronization"]
337pub struct SWOC_W<'a> {
338    w: &'a mut W,
339}
340impl<'a> SWOC_W<'a> {
341    #[doc = r"Writes `variant` to the field"]
342    #[inline(always)]
343    pub fn variant(self, variant: SWOC_A) -> &'a mut W {
344        self.bit(variant.into())
345    }
346    #[doc = "SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock."]
347    #[inline(always)]
348    pub fn _0(self) -> &'a mut W {
349        self.variant(SWOC_A::_0)
350    }
351    #[doc = "SWOCTRL register is updated with its buffer value by the PWM synchronization."]
352    #[inline(always)]
353    pub fn _1(self) -> &'a mut W {
354        self.variant(SWOC_A::_1)
355    }
356    #[doc = r"Sets the field bit"]
357    #[inline(always)]
358    pub fn set_bit(self) -> &'a mut W {
359        self.bit(true)
360    }
361    #[doc = r"Clears the field bit"]
362    #[inline(always)]
363    pub fn clear_bit(self) -> &'a mut W {
364        self.bit(false)
365    }
366    #[doc = r"Writes raw bits to the field"]
367    #[inline(always)]
368    pub fn bit(self, value: bool) -> &'a mut W {
369        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
370        self.w
371    }
372}
373#[doc = "Synchronization Mode\n\nValue on reset: 0"]
374#[derive(Clone, Copy, Debug, PartialEq)]
375pub enum SYNCMODE_A {
376    #[doc = "0: Legacy PWM synchronization is selected."]
377    _0 = 0,
378    #[doc = "1: Enhanced PWM synchronization is selected."]
379    _1 = 1,
380}
381impl From<SYNCMODE_A> for bool {
382    #[inline(always)]
383    fn from(variant: SYNCMODE_A) -> Self {
384        variant as u8 != 0
385    }
386}
387#[doc = "Field `SYNCMODE` reader - Synchronization Mode"]
388pub struct SYNCMODE_R(crate::FieldReader<bool, SYNCMODE_A>);
389impl SYNCMODE_R {
390    #[inline(always)]
391    pub(crate) fn new(bits: bool) -> Self {
392        SYNCMODE_R(crate::FieldReader::new(bits))
393    }
394    #[doc = r"Get enumerated values variant"]
395    #[inline(always)]
396    pub fn variant(&self) -> SYNCMODE_A {
397        match self.bits {
398            false => SYNCMODE_A::_0,
399            true => SYNCMODE_A::_1,
400        }
401    }
402    #[doc = "Checks if the value of the field is `_0`"]
403    #[inline(always)]
404    pub fn is_0(&self) -> bool {
405        **self == SYNCMODE_A::_0
406    }
407    #[doc = "Checks if the value of the field is `_1`"]
408    #[inline(always)]
409    pub fn is_1(&self) -> bool {
410        **self == SYNCMODE_A::_1
411    }
412}
413impl core::ops::Deref for SYNCMODE_R {
414    type Target = crate::FieldReader<bool, SYNCMODE_A>;
415    #[inline(always)]
416    fn deref(&self) -> &Self::Target {
417        &self.0
418    }
419}
420#[doc = "Field `SYNCMODE` writer - Synchronization Mode"]
421pub struct SYNCMODE_W<'a> {
422    w: &'a mut W,
423}
424impl<'a> SYNCMODE_W<'a> {
425    #[doc = r"Writes `variant` to the field"]
426    #[inline(always)]
427    pub fn variant(self, variant: SYNCMODE_A) -> &'a mut W {
428        self.bit(variant.into())
429    }
430    #[doc = "Legacy PWM synchronization is selected."]
431    #[inline(always)]
432    pub fn _0(self) -> &'a mut W {
433        self.variant(SYNCMODE_A::_0)
434    }
435    #[doc = "Enhanced PWM synchronization is selected."]
436    #[inline(always)]
437    pub fn _1(self) -> &'a mut W {
438        self.variant(SYNCMODE_A::_1)
439    }
440    #[doc = r"Sets the field bit"]
441    #[inline(always)]
442    pub fn set_bit(self) -> &'a mut W {
443        self.bit(true)
444    }
445    #[doc = r"Clears the field bit"]
446    #[inline(always)]
447    pub fn clear_bit(self) -> &'a mut W {
448        self.bit(false)
449    }
450    #[doc = r"Writes raw bits to the field"]
451    #[inline(always)]
452    pub fn bit(self, value: bool) -> &'a mut W {
453        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
454        self.w
455    }
456}
457#[doc = "FTM counter synchronization is activated by the software trigger\n\nValue on reset: 0"]
458#[derive(Clone, Copy, Debug, PartialEq)]
459pub enum SWRSTCNT_A {
460    #[doc = "0: The software trigger does not activate the FTM counter synchronization."]
461    _0 = 0,
462    #[doc = "1: The software trigger activates the FTM counter synchronization."]
463    _1 = 1,
464}
465impl From<SWRSTCNT_A> for bool {
466    #[inline(always)]
467    fn from(variant: SWRSTCNT_A) -> Self {
468        variant as u8 != 0
469    }
470}
471#[doc = "Field `SWRSTCNT` reader - FTM counter synchronization is activated by the software trigger"]
472pub struct SWRSTCNT_R(crate::FieldReader<bool, SWRSTCNT_A>);
473impl SWRSTCNT_R {
474    #[inline(always)]
475    pub(crate) fn new(bits: bool) -> Self {
476        SWRSTCNT_R(crate::FieldReader::new(bits))
477    }
478    #[doc = r"Get enumerated values variant"]
479    #[inline(always)]
480    pub fn variant(&self) -> SWRSTCNT_A {
481        match self.bits {
482            false => SWRSTCNT_A::_0,
483            true => SWRSTCNT_A::_1,
484        }
485    }
486    #[doc = "Checks if the value of the field is `_0`"]
487    #[inline(always)]
488    pub fn is_0(&self) -> bool {
489        **self == SWRSTCNT_A::_0
490    }
491    #[doc = "Checks if the value of the field is `_1`"]
492    #[inline(always)]
493    pub fn is_1(&self) -> bool {
494        **self == SWRSTCNT_A::_1
495    }
496}
497impl core::ops::Deref for SWRSTCNT_R {
498    type Target = crate::FieldReader<bool, SWRSTCNT_A>;
499    #[inline(always)]
500    fn deref(&self) -> &Self::Target {
501        &self.0
502    }
503}
504#[doc = "Field `SWRSTCNT` writer - FTM counter synchronization is activated by the software trigger"]
505pub struct SWRSTCNT_W<'a> {
506    w: &'a mut W,
507}
508impl<'a> SWRSTCNT_W<'a> {
509    #[doc = r"Writes `variant` to the field"]
510    #[inline(always)]
511    pub fn variant(self, variant: SWRSTCNT_A) -> &'a mut W {
512        self.bit(variant.into())
513    }
514    #[doc = "The software trigger does not activate the FTM counter synchronization."]
515    #[inline(always)]
516    pub fn _0(self) -> &'a mut W {
517        self.variant(SWRSTCNT_A::_0)
518    }
519    #[doc = "The software trigger activates the FTM counter synchronization."]
520    #[inline(always)]
521    pub fn _1(self) -> &'a mut W {
522        self.variant(SWRSTCNT_A::_1)
523    }
524    #[doc = r"Sets the field bit"]
525    #[inline(always)]
526    pub fn set_bit(self) -> &'a mut W {
527        self.bit(true)
528    }
529    #[doc = r"Clears the field bit"]
530    #[inline(always)]
531    pub fn clear_bit(self) -> &'a mut W {
532        self.bit(false)
533    }
534    #[doc = r"Writes raw bits to the field"]
535    #[inline(always)]
536    pub fn bit(self, value: bool) -> &'a mut W {
537        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
538        self.w
539    }
540}
541#[doc = "MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger\n\nValue on reset: 0"]
542#[derive(Clone, Copy, Debug, PartialEq)]
543pub enum SWWRBUF_A {
544    #[doc = "0: The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
545    _0 = 0,
546    #[doc = "1: The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
547    _1 = 1,
548}
549impl From<SWWRBUF_A> for bool {
550    #[inline(always)]
551    fn from(variant: SWWRBUF_A) -> Self {
552        variant as u8 != 0
553    }
554}
555#[doc = "Field `SWWRBUF` reader - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger"]
556pub struct SWWRBUF_R(crate::FieldReader<bool, SWWRBUF_A>);
557impl SWWRBUF_R {
558    #[inline(always)]
559    pub(crate) fn new(bits: bool) -> Self {
560        SWWRBUF_R(crate::FieldReader::new(bits))
561    }
562    #[doc = r"Get enumerated values variant"]
563    #[inline(always)]
564    pub fn variant(&self) -> SWWRBUF_A {
565        match self.bits {
566            false => SWWRBUF_A::_0,
567            true => SWWRBUF_A::_1,
568        }
569    }
570    #[doc = "Checks if the value of the field is `_0`"]
571    #[inline(always)]
572    pub fn is_0(&self) -> bool {
573        **self == SWWRBUF_A::_0
574    }
575    #[doc = "Checks if the value of the field is `_1`"]
576    #[inline(always)]
577    pub fn is_1(&self) -> bool {
578        **self == SWWRBUF_A::_1
579    }
580}
581impl core::ops::Deref for SWWRBUF_R {
582    type Target = crate::FieldReader<bool, SWWRBUF_A>;
583    #[inline(always)]
584    fn deref(&self) -> &Self::Target {
585        &self.0
586    }
587}
588#[doc = "Field `SWWRBUF` writer - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger"]
589pub struct SWWRBUF_W<'a> {
590    w: &'a mut W,
591}
592impl<'a> SWWRBUF_W<'a> {
593    #[doc = r"Writes `variant` to the field"]
594    #[inline(always)]
595    pub fn variant(self, variant: SWWRBUF_A) -> &'a mut W {
596        self.bit(variant.into())
597    }
598    #[doc = "The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
599    #[inline(always)]
600    pub fn _0(self) -> &'a mut W {
601        self.variant(SWWRBUF_A::_0)
602    }
603    #[doc = "The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
604    #[inline(always)]
605    pub fn _1(self) -> &'a mut W {
606        self.variant(SWWRBUF_A::_1)
607    }
608    #[doc = r"Sets the field bit"]
609    #[inline(always)]
610    pub fn set_bit(self) -> &'a mut W {
611        self.bit(true)
612    }
613    #[doc = r"Clears the field bit"]
614    #[inline(always)]
615    pub fn clear_bit(self) -> &'a mut W {
616        self.bit(false)
617    }
618    #[doc = r"Writes raw bits to the field"]
619    #[inline(always)]
620    pub fn bit(self, value: bool) -> &'a mut W {
621        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
622        self.w
623    }
624}
625#[doc = "Output mask synchronization is activated by the software trigger\n\nValue on reset: 0"]
626#[derive(Clone, Copy, Debug, PartialEq)]
627pub enum SWOM_A {
628    #[doc = "0: The software trigger does not activate the OUTMASK register synchronization."]
629    _0 = 0,
630    #[doc = "1: The software trigger activates the OUTMASK register synchronization."]
631    _1 = 1,
632}
633impl From<SWOM_A> for bool {
634    #[inline(always)]
635    fn from(variant: SWOM_A) -> Self {
636        variant as u8 != 0
637    }
638}
639#[doc = "Field `SWOM` reader - Output mask synchronization is activated by the software trigger"]
640pub struct SWOM_R(crate::FieldReader<bool, SWOM_A>);
641impl SWOM_R {
642    #[inline(always)]
643    pub(crate) fn new(bits: bool) -> Self {
644        SWOM_R(crate::FieldReader::new(bits))
645    }
646    #[doc = r"Get enumerated values variant"]
647    #[inline(always)]
648    pub fn variant(&self) -> SWOM_A {
649        match self.bits {
650            false => SWOM_A::_0,
651            true => SWOM_A::_1,
652        }
653    }
654    #[doc = "Checks if the value of the field is `_0`"]
655    #[inline(always)]
656    pub fn is_0(&self) -> bool {
657        **self == SWOM_A::_0
658    }
659    #[doc = "Checks if the value of the field is `_1`"]
660    #[inline(always)]
661    pub fn is_1(&self) -> bool {
662        **self == SWOM_A::_1
663    }
664}
665impl core::ops::Deref for SWOM_R {
666    type Target = crate::FieldReader<bool, SWOM_A>;
667    #[inline(always)]
668    fn deref(&self) -> &Self::Target {
669        &self.0
670    }
671}
672#[doc = "Field `SWOM` writer - Output mask synchronization is activated by the software trigger"]
673pub struct SWOM_W<'a> {
674    w: &'a mut W,
675}
676impl<'a> SWOM_W<'a> {
677    #[doc = r"Writes `variant` to the field"]
678    #[inline(always)]
679    pub fn variant(self, variant: SWOM_A) -> &'a mut W {
680        self.bit(variant.into())
681    }
682    #[doc = "The software trigger does not activate the OUTMASK register synchronization."]
683    #[inline(always)]
684    pub fn _0(self) -> &'a mut W {
685        self.variant(SWOM_A::_0)
686    }
687    #[doc = "The software trigger activates the OUTMASK register synchronization."]
688    #[inline(always)]
689    pub fn _1(self) -> &'a mut W {
690        self.variant(SWOM_A::_1)
691    }
692    #[doc = r"Sets the field bit"]
693    #[inline(always)]
694    pub fn set_bit(self) -> &'a mut W {
695        self.bit(true)
696    }
697    #[doc = r"Clears the field bit"]
698    #[inline(always)]
699    pub fn clear_bit(self) -> &'a mut W {
700        self.bit(false)
701    }
702    #[doc = r"Writes raw bits to the field"]
703    #[inline(always)]
704    pub fn bit(self, value: bool) -> &'a mut W {
705        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
706        self.w
707    }
708}
709#[doc = "Inverting control synchronization is activated by the software trigger\n\nValue on reset: 0"]
710#[derive(Clone, Copy, Debug, PartialEq)]
711pub enum SWINVC_A {
712    #[doc = "0: The software trigger does not activate the INVCTRL register synchronization."]
713    _0 = 0,
714    #[doc = "1: The software trigger activates the INVCTRL register synchronization."]
715    _1 = 1,
716}
717impl From<SWINVC_A> for bool {
718    #[inline(always)]
719    fn from(variant: SWINVC_A) -> Self {
720        variant as u8 != 0
721    }
722}
723#[doc = "Field `SWINVC` reader - Inverting control synchronization is activated by the software trigger"]
724pub struct SWINVC_R(crate::FieldReader<bool, SWINVC_A>);
725impl SWINVC_R {
726    #[inline(always)]
727    pub(crate) fn new(bits: bool) -> Self {
728        SWINVC_R(crate::FieldReader::new(bits))
729    }
730    #[doc = r"Get enumerated values variant"]
731    #[inline(always)]
732    pub fn variant(&self) -> SWINVC_A {
733        match self.bits {
734            false => SWINVC_A::_0,
735            true => SWINVC_A::_1,
736        }
737    }
738    #[doc = "Checks if the value of the field is `_0`"]
739    #[inline(always)]
740    pub fn is_0(&self) -> bool {
741        **self == SWINVC_A::_0
742    }
743    #[doc = "Checks if the value of the field is `_1`"]
744    #[inline(always)]
745    pub fn is_1(&self) -> bool {
746        **self == SWINVC_A::_1
747    }
748}
749impl core::ops::Deref for SWINVC_R {
750    type Target = crate::FieldReader<bool, SWINVC_A>;
751    #[inline(always)]
752    fn deref(&self) -> &Self::Target {
753        &self.0
754    }
755}
756#[doc = "Field `SWINVC` writer - Inverting control synchronization is activated by the software trigger"]
757pub struct SWINVC_W<'a> {
758    w: &'a mut W,
759}
760impl<'a> SWINVC_W<'a> {
761    #[doc = r"Writes `variant` to the field"]
762    #[inline(always)]
763    pub fn variant(self, variant: SWINVC_A) -> &'a mut W {
764        self.bit(variant.into())
765    }
766    #[doc = "The software trigger does not activate the INVCTRL register synchronization."]
767    #[inline(always)]
768    pub fn _0(self) -> &'a mut W {
769        self.variant(SWINVC_A::_0)
770    }
771    #[doc = "The software trigger activates the INVCTRL register synchronization."]
772    #[inline(always)]
773    pub fn _1(self) -> &'a mut W {
774        self.variant(SWINVC_A::_1)
775    }
776    #[doc = r"Sets the field bit"]
777    #[inline(always)]
778    pub fn set_bit(self) -> &'a mut W {
779        self.bit(true)
780    }
781    #[doc = r"Clears the field bit"]
782    #[inline(always)]
783    pub fn clear_bit(self) -> &'a mut W {
784        self.bit(false)
785    }
786    #[doc = r"Writes raw bits to the field"]
787    #[inline(always)]
788    pub fn bit(self, value: bool) -> &'a mut W {
789        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
790        self.w
791    }
792}
793#[doc = "Software output control synchronization is activated by the software trigger\n\nValue on reset: 0"]
794#[derive(Clone, Copy, Debug, PartialEq)]
795pub enum SWSOC_A {
796    #[doc = "0: The software trigger does not activate the SWOCTRL register synchronization."]
797    _0 = 0,
798    #[doc = "1: The software trigger activates the SWOCTRL register synchronization."]
799    _1 = 1,
800}
801impl From<SWSOC_A> for bool {
802    #[inline(always)]
803    fn from(variant: SWSOC_A) -> Self {
804        variant as u8 != 0
805    }
806}
807#[doc = "Field `SWSOC` reader - Software output control synchronization is activated by the software trigger"]
808pub struct SWSOC_R(crate::FieldReader<bool, SWSOC_A>);
809impl SWSOC_R {
810    #[inline(always)]
811    pub(crate) fn new(bits: bool) -> Self {
812        SWSOC_R(crate::FieldReader::new(bits))
813    }
814    #[doc = r"Get enumerated values variant"]
815    #[inline(always)]
816    pub fn variant(&self) -> SWSOC_A {
817        match self.bits {
818            false => SWSOC_A::_0,
819            true => SWSOC_A::_1,
820        }
821    }
822    #[doc = "Checks if the value of the field is `_0`"]
823    #[inline(always)]
824    pub fn is_0(&self) -> bool {
825        **self == SWSOC_A::_0
826    }
827    #[doc = "Checks if the value of the field is `_1`"]
828    #[inline(always)]
829    pub fn is_1(&self) -> bool {
830        **self == SWSOC_A::_1
831    }
832}
833impl core::ops::Deref for SWSOC_R {
834    type Target = crate::FieldReader<bool, SWSOC_A>;
835    #[inline(always)]
836    fn deref(&self) -> &Self::Target {
837        &self.0
838    }
839}
840#[doc = "Field `SWSOC` writer - Software output control synchronization is activated by the software trigger"]
841pub struct SWSOC_W<'a> {
842    w: &'a mut W,
843}
844impl<'a> SWSOC_W<'a> {
845    #[doc = r"Writes `variant` to the field"]
846    #[inline(always)]
847    pub fn variant(self, variant: SWSOC_A) -> &'a mut W {
848        self.bit(variant.into())
849    }
850    #[doc = "The software trigger does not activate the SWOCTRL register synchronization."]
851    #[inline(always)]
852    pub fn _0(self) -> &'a mut W {
853        self.variant(SWSOC_A::_0)
854    }
855    #[doc = "The software trigger activates the SWOCTRL register synchronization."]
856    #[inline(always)]
857    pub fn _1(self) -> &'a mut W {
858        self.variant(SWSOC_A::_1)
859    }
860    #[doc = r"Sets the field bit"]
861    #[inline(always)]
862    pub fn set_bit(self) -> &'a mut W {
863        self.bit(true)
864    }
865    #[doc = r"Clears the field bit"]
866    #[inline(always)]
867    pub fn clear_bit(self) -> &'a mut W {
868        self.bit(false)
869    }
870    #[doc = r"Writes raw bits to the field"]
871    #[inline(always)]
872    pub fn bit(self, value: bool) -> &'a mut W {
873        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
874        self.w
875    }
876}
877#[doc = "FTM counter synchronization is activated by a hardware trigger\n\nValue on reset: 0"]
878#[derive(Clone, Copy, Debug, PartialEq)]
879pub enum HWRSTCNT_A {
880    #[doc = "0: A hardware trigger does not activate the FTM counter synchronization."]
881    _0 = 0,
882    #[doc = "1: A hardware trigger activates the FTM counter synchronization."]
883    _1 = 1,
884}
885impl From<HWRSTCNT_A> for bool {
886    #[inline(always)]
887    fn from(variant: HWRSTCNT_A) -> Self {
888        variant as u8 != 0
889    }
890}
891#[doc = "Field `HWRSTCNT` reader - FTM counter synchronization is activated by a hardware trigger"]
892pub struct HWRSTCNT_R(crate::FieldReader<bool, HWRSTCNT_A>);
893impl HWRSTCNT_R {
894    #[inline(always)]
895    pub(crate) fn new(bits: bool) -> Self {
896        HWRSTCNT_R(crate::FieldReader::new(bits))
897    }
898    #[doc = r"Get enumerated values variant"]
899    #[inline(always)]
900    pub fn variant(&self) -> HWRSTCNT_A {
901        match self.bits {
902            false => HWRSTCNT_A::_0,
903            true => HWRSTCNT_A::_1,
904        }
905    }
906    #[doc = "Checks if the value of the field is `_0`"]
907    #[inline(always)]
908    pub fn is_0(&self) -> bool {
909        **self == HWRSTCNT_A::_0
910    }
911    #[doc = "Checks if the value of the field is `_1`"]
912    #[inline(always)]
913    pub fn is_1(&self) -> bool {
914        **self == HWRSTCNT_A::_1
915    }
916}
917impl core::ops::Deref for HWRSTCNT_R {
918    type Target = crate::FieldReader<bool, HWRSTCNT_A>;
919    #[inline(always)]
920    fn deref(&self) -> &Self::Target {
921        &self.0
922    }
923}
924#[doc = "Field `HWRSTCNT` writer - FTM counter synchronization is activated by a hardware trigger"]
925pub struct HWRSTCNT_W<'a> {
926    w: &'a mut W,
927}
928impl<'a> HWRSTCNT_W<'a> {
929    #[doc = r"Writes `variant` to the field"]
930    #[inline(always)]
931    pub fn variant(self, variant: HWRSTCNT_A) -> &'a mut W {
932        self.bit(variant.into())
933    }
934    #[doc = "A hardware trigger does not activate the FTM counter synchronization."]
935    #[inline(always)]
936    pub fn _0(self) -> &'a mut W {
937        self.variant(HWRSTCNT_A::_0)
938    }
939    #[doc = "A hardware trigger activates the FTM counter synchronization."]
940    #[inline(always)]
941    pub fn _1(self) -> &'a mut W {
942        self.variant(HWRSTCNT_A::_1)
943    }
944    #[doc = r"Sets the field bit"]
945    #[inline(always)]
946    pub fn set_bit(self) -> &'a mut W {
947        self.bit(true)
948    }
949    #[doc = r"Clears the field bit"]
950    #[inline(always)]
951    pub fn clear_bit(self) -> &'a mut W {
952        self.bit(false)
953    }
954    #[doc = r"Writes raw bits to the field"]
955    #[inline(always)]
956    pub fn bit(self, value: bool) -> &'a mut W {
957        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
958        self.w
959    }
960}
961#[doc = "MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger\n\nValue on reset: 0"]
962#[derive(Clone, Copy, Debug, PartialEq)]
963pub enum HWWRBUF_A {
964    #[doc = "0: A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
965    _0 = 0,
966    #[doc = "1: A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
967    _1 = 1,
968}
969impl From<HWWRBUF_A> for bool {
970    #[inline(always)]
971    fn from(variant: HWWRBUF_A) -> Self {
972        variant as u8 != 0
973    }
974}
975#[doc = "Field `HWWRBUF` reader - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger"]
976pub struct HWWRBUF_R(crate::FieldReader<bool, HWWRBUF_A>);
977impl HWWRBUF_R {
978    #[inline(always)]
979    pub(crate) fn new(bits: bool) -> Self {
980        HWWRBUF_R(crate::FieldReader::new(bits))
981    }
982    #[doc = r"Get enumerated values variant"]
983    #[inline(always)]
984    pub fn variant(&self) -> HWWRBUF_A {
985        match self.bits {
986            false => HWWRBUF_A::_0,
987            true => HWWRBUF_A::_1,
988        }
989    }
990    #[doc = "Checks if the value of the field is `_0`"]
991    #[inline(always)]
992    pub fn is_0(&self) -> bool {
993        **self == HWWRBUF_A::_0
994    }
995    #[doc = "Checks if the value of the field is `_1`"]
996    #[inline(always)]
997    pub fn is_1(&self) -> bool {
998        **self == HWWRBUF_A::_1
999    }
1000}
1001impl core::ops::Deref for HWWRBUF_R {
1002    type Target = crate::FieldReader<bool, HWWRBUF_A>;
1003    #[inline(always)]
1004    fn deref(&self) -> &Self::Target {
1005        &self.0
1006    }
1007}
1008#[doc = "Field `HWWRBUF` writer - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger"]
1009pub struct HWWRBUF_W<'a> {
1010    w: &'a mut W,
1011}
1012impl<'a> HWWRBUF_W<'a> {
1013    #[doc = r"Writes `variant` to the field"]
1014    #[inline(always)]
1015    pub fn variant(self, variant: HWWRBUF_A) -> &'a mut W {
1016        self.bit(variant.into())
1017    }
1018    #[doc = "A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization."]
1019    #[inline(always)]
1020    pub fn _0(self) -> &'a mut W {
1021        self.variant(HWWRBUF_A::_0)
1022    }
1023    #[doc = "A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization."]
1024    #[inline(always)]
1025    pub fn _1(self) -> &'a mut W {
1026        self.variant(HWWRBUF_A::_1)
1027    }
1028    #[doc = r"Sets the field bit"]
1029    #[inline(always)]
1030    pub fn set_bit(self) -> &'a mut W {
1031        self.bit(true)
1032    }
1033    #[doc = r"Clears the field bit"]
1034    #[inline(always)]
1035    pub fn clear_bit(self) -> &'a mut W {
1036        self.bit(false)
1037    }
1038    #[doc = r"Writes raw bits to the field"]
1039    #[inline(always)]
1040    pub fn bit(self, value: bool) -> &'a mut W {
1041        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
1042        self.w
1043    }
1044}
1045#[doc = "Output mask synchronization is activated by a hardware trigger\n\nValue on reset: 0"]
1046#[derive(Clone, Copy, Debug, PartialEq)]
1047pub enum HWOM_A {
1048    #[doc = "0: A hardware trigger does not activate the OUTMASK register synchronization."]
1049    _0 = 0,
1050    #[doc = "1: A hardware trigger activates the OUTMASK register synchronization."]
1051    _1 = 1,
1052}
1053impl From<HWOM_A> for bool {
1054    #[inline(always)]
1055    fn from(variant: HWOM_A) -> Self {
1056        variant as u8 != 0
1057    }
1058}
1059#[doc = "Field `HWOM` reader - Output mask synchronization is activated by a hardware trigger"]
1060pub struct HWOM_R(crate::FieldReader<bool, HWOM_A>);
1061impl HWOM_R {
1062    #[inline(always)]
1063    pub(crate) fn new(bits: bool) -> Self {
1064        HWOM_R(crate::FieldReader::new(bits))
1065    }
1066    #[doc = r"Get enumerated values variant"]
1067    #[inline(always)]
1068    pub fn variant(&self) -> HWOM_A {
1069        match self.bits {
1070            false => HWOM_A::_0,
1071            true => HWOM_A::_1,
1072        }
1073    }
1074    #[doc = "Checks if the value of the field is `_0`"]
1075    #[inline(always)]
1076    pub fn is_0(&self) -> bool {
1077        **self == HWOM_A::_0
1078    }
1079    #[doc = "Checks if the value of the field is `_1`"]
1080    #[inline(always)]
1081    pub fn is_1(&self) -> bool {
1082        **self == HWOM_A::_1
1083    }
1084}
1085impl core::ops::Deref for HWOM_R {
1086    type Target = crate::FieldReader<bool, HWOM_A>;
1087    #[inline(always)]
1088    fn deref(&self) -> &Self::Target {
1089        &self.0
1090    }
1091}
1092#[doc = "Field `HWOM` writer - Output mask synchronization is activated by a hardware trigger"]
1093pub struct HWOM_W<'a> {
1094    w: &'a mut W,
1095}
1096impl<'a> HWOM_W<'a> {
1097    #[doc = r"Writes `variant` to the field"]
1098    #[inline(always)]
1099    pub fn variant(self, variant: HWOM_A) -> &'a mut W {
1100        self.bit(variant.into())
1101    }
1102    #[doc = "A hardware trigger does not activate the OUTMASK register synchronization."]
1103    #[inline(always)]
1104    pub fn _0(self) -> &'a mut W {
1105        self.variant(HWOM_A::_0)
1106    }
1107    #[doc = "A hardware trigger activates the OUTMASK register synchronization."]
1108    #[inline(always)]
1109    pub fn _1(self) -> &'a mut W {
1110        self.variant(HWOM_A::_1)
1111    }
1112    #[doc = r"Sets the field bit"]
1113    #[inline(always)]
1114    pub fn set_bit(self) -> &'a mut W {
1115        self.bit(true)
1116    }
1117    #[doc = r"Clears the field bit"]
1118    #[inline(always)]
1119    pub fn clear_bit(self) -> &'a mut W {
1120        self.bit(false)
1121    }
1122    #[doc = r"Writes raw bits to the field"]
1123    #[inline(always)]
1124    pub fn bit(self, value: bool) -> &'a mut W {
1125        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
1126        self.w
1127    }
1128}
1129#[doc = "Inverting control synchronization is activated by a hardware trigger\n\nValue on reset: 0"]
1130#[derive(Clone, Copy, Debug, PartialEq)]
1131pub enum HWINVC_A {
1132    #[doc = "0: A hardware trigger does not activate the INVCTRL register synchronization."]
1133    _0 = 0,
1134    #[doc = "1: A hardware trigger activates the INVCTRL register synchronization."]
1135    _1 = 1,
1136}
1137impl From<HWINVC_A> for bool {
1138    #[inline(always)]
1139    fn from(variant: HWINVC_A) -> Self {
1140        variant as u8 != 0
1141    }
1142}
1143#[doc = "Field `HWINVC` reader - Inverting control synchronization is activated by a hardware trigger"]
1144pub struct HWINVC_R(crate::FieldReader<bool, HWINVC_A>);
1145impl HWINVC_R {
1146    #[inline(always)]
1147    pub(crate) fn new(bits: bool) -> Self {
1148        HWINVC_R(crate::FieldReader::new(bits))
1149    }
1150    #[doc = r"Get enumerated values variant"]
1151    #[inline(always)]
1152    pub fn variant(&self) -> HWINVC_A {
1153        match self.bits {
1154            false => HWINVC_A::_0,
1155            true => HWINVC_A::_1,
1156        }
1157    }
1158    #[doc = "Checks if the value of the field is `_0`"]
1159    #[inline(always)]
1160    pub fn is_0(&self) -> bool {
1161        **self == HWINVC_A::_0
1162    }
1163    #[doc = "Checks if the value of the field is `_1`"]
1164    #[inline(always)]
1165    pub fn is_1(&self) -> bool {
1166        **self == HWINVC_A::_1
1167    }
1168}
1169impl core::ops::Deref for HWINVC_R {
1170    type Target = crate::FieldReader<bool, HWINVC_A>;
1171    #[inline(always)]
1172    fn deref(&self) -> &Self::Target {
1173        &self.0
1174    }
1175}
1176#[doc = "Field `HWINVC` writer - Inverting control synchronization is activated by a hardware trigger"]
1177pub struct HWINVC_W<'a> {
1178    w: &'a mut W,
1179}
1180impl<'a> HWINVC_W<'a> {
1181    #[doc = r"Writes `variant` to the field"]
1182    #[inline(always)]
1183    pub fn variant(self, variant: HWINVC_A) -> &'a mut W {
1184        self.bit(variant.into())
1185    }
1186    #[doc = "A hardware trigger does not activate the INVCTRL register synchronization."]
1187    #[inline(always)]
1188    pub fn _0(self) -> &'a mut W {
1189        self.variant(HWINVC_A::_0)
1190    }
1191    #[doc = "A hardware trigger activates the INVCTRL register synchronization."]
1192    #[inline(always)]
1193    pub fn _1(self) -> &'a mut W {
1194        self.variant(HWINVC_A::_1)
1195    }
1196    #[doc = r"Sets the field bit"]
1197    #[inline(always)]
1198    pub fn set_bit(self) -> &'a mut W {
1199        self.bit(true)
1200    }
1201    #[doc = r"Clears the field bit"]
1202    #[inline(always)]
1203    pub fn clear_bit(self) -> &'a mut W {
1204        self.bit(false)
1205    }
1206    #[doc = r"Writes raw bits to the field"]
1207    #[inline(always)]
1208    pub fn bit(self, value: bool) -> &'a mut W {
1209        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
1210        self.w
1211    }
1212}
1213#[doc = "Software output control synchronization is activated by a hardware trigger\n\nValue on reset: 0"]
1214#[derive(Clone, Copy, Debug, PartialEq)]
1215pub enum HWSOC_A {
1216    #[doc = "0: A hardware trigger does not activate the SWOCTRL register synchronization."]
1217    _0 = 0,
1218    #[doc = "1: A hardware trigger activates the SWOCTRL register synchronization."]
1219    _1 = 1,
1220}
1221impl From<HWSOC_A> for bool {
1222    #[inline(always)]
1223    fn from(variant: HWSOC_A) -> Self {
1224        variant as u8 != 0
1225    }
1226}
1227#[doc = "Field `HWSOC` reader - Software output control synchronization is activated by a hardware trigger"]
1228pub struct HWSOC_R(crate::FieldReader<bool, HWSOC_A>);
1229impl HWSOC_R {
1230    #[inline(always)]
1231    pub(crate) fn new(bits: bool) -> Self {
1232        HWSOC_R(crate::FieldReader::new(bits))
1233    }
1234    #[doc = r"Get enumerated values variant"]
1235    #[inline(always)]
1236    pub fn variant(&self) -> HWSOC_A {
1237        match self.bits {
1238            false => HWSOC_A::_0,
1239            true => HWSOC_A::_1,
1240        }
1241    }
1242    #[doc = "Checks if the value of the field is `_0`"]
1243    #[inline(always)]
1244    pub fn is_0(&self) -> bool {
1245        **self == HWSOC_A::_0
1246    }
1247    #[doc = "Checks if the value of the field is `_1`"]
1248    #[inline(always)]
1249    pub fn is_1(&self) -> bool {
1250        **self == HWSOC_A::_1
1251    }
1252}
1253impl core::ops::Deref for HWSOC_R {
1254    type Target = crate::FieldReader<bool, HWSOC_A>;
1255    #[inline(always)]
1256    fn deref(&self) -> &Self::Target {
1257        &self.0
1258    }
1259}
1260#[doc = "Field `HWSOC` writer - Software output control synchronization is activated by a hardware trigger"]
1261pub struct HWSOC_W<'a> {
1262    w: &'a mut W,
1263}
1264impl<'a> HWSOC_W<'a> {
1265    #[doc = r"Writes `variant` to the field"]
1266    #[inline(always)]
1267    pub fn variant(self, variant: HWSOC_A) -> &'a mut W {
1268        self.bit(variant.into())
1269    }
1270    #[doc = "A hardware trigger does not activate the SWOCTRL register synchronization."]
1271    #[inline(always)]
1272    pub fn _0(self) -> &'a mut W {
1273        self.variant(HWSOC_A::_0)
1274    }
1275    #[doc = "A hardware trigger activates the SWOCTRL register synchronization."]
1276    #[inline(always)]
1277    pub fn _1(self) -> &'a mut W {
1278        self.variant(HWSOC_A::_1)
1279    }
1280    #[doc = r"Sets the field bit"]
1281    #[inline(always)]
1282    pub fn set_bit(self) -> &'a mut W {
1283        self.bit(true)
1284    }
1285    #[doc = r"Clears the field bit"]
1286    #[inline(always)]
1287    pub fn clear_bit(self) -> &'a mut W {
1288        self.bit(false)
1289    }
1290    #[doc = r"Writes raw bits to the field"]
1291    #[inline(always)]
1292    pub fn bit(self, value: bool) -> &'a mut W {
1293        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
1294        self.w
1295    }
1296}
1297impl R {
1298    #[doc = "Bit 0 - Hardware Trigger Mode"]
1299    #[inline(always)]
1300    pub fn hwtrigmode(&self) -> HWTRIGMODE_R {
1301        HWTRIGMODE_R::new((self.bits & 0x01) != 0)
1302    }
1303    #[doc = "Bit 2 - CNTIN Register Synchronization"]
1304    #[inline(always)]
1305    pub fn cntinc(&self) -> CNTINC_R {
1306        CNTINC_R::new(((self.bits >> 2) & 0x01) != 0)
1307    }
1308    #[doc = "Bit 4 - INVCTRL Register Synchronization"]
1309    #[inline(always)]
1310    pub fn invc(&self) -> INVC_R {
1311        INVC_R::new(((self.bits >> 4) & 0x01) != 0)
1312    }
1313    #[doc = "Bit 5 - SWOCTRL Register Synchronization"]
1314    #[inline(always)]
1315    pub fn swoc(&self) -> SWOC_R {
1316        SWOC_R::new(((self.bits >> 5) & 0x01) != 0)
1317    }
1318    #[doc = "Bit 7 - Synchronization Mode"]
1319    #[inline(always)]
1320    pub fn syncmode(&self) -> SYNCMODE_R {
1321        SYNCMODE_R::new(((self.bits >> 7) & 0x01) != 0)
1322    }
1323    #[doc = "Bit 8 - FTM counter synchronization is activated by the software trigger"]
1324    #[inline(always)]
1325    pub fn swrstcnt(&self) -> SWRSTCNT_R {
1326        SWRSTCNT_R::new(((self.bits >> 8) & 0x01) != 0)
1327    }
1328    #[doc = "Bit 9 - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger"]
1329    #[inline(always)]
1330    pub fn swwrbuf(&self) -> SWWRBUF_R {
1331        SWWRBUF_R::new(((self.bits >> 9) & 0x01) != 0)
1332    }
1333    #[doc = "Bit 10 - Output mask synchronization is activated by the software trigger"]
1334    #[inline(always)]
1335    pub fn swom(&self) -> SWOM_R {
1336        SWOM_R::new(((self.bits >> 10) & 0x01) != 0)
1337    }
1338    #[doc = "Bit 11 - Inverting control synchronization is activated by the software trigger"]
1339    #[inline(always)]
1340    pub fn swinvc(&self) -> SWINVC_R {
1341        SWINVC_R::new(((self.bits >> 11) & 0x01) != 0)
1342    }
1343    #[doc = "Bit 12 - Software output control synchronization is activated by the software trigger"]
1344    #[inline(always)]
1345    pub fn swsoc(&self) -> SWSOC_R {
1346        SWSOC_R::new(((self.bits >> 12) & 0x01) != 0)
1347    }
1348    #[doc = "Bit 16 - FTM counter synchronization is activated by a hardware trigger"]
1349    #[inline(always)]
1350    pub fn hwrstcnt(&self) -> HWRSTCNT_R {
1351        HWRSTCNT_R::new(((self.bits >> 16) & 0x01) != 0)
1352    }
1353    #[doc = "Bit 17 - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger"]
1354    #[inline(always)]
1355    pub fn hwwrbuf(&self) -> HWWRBUF_R {
1356        HWWRBUF_R::new(((self.bits >> 17) & 0x01) != 0)
1357    }
1358    #[doc = "Bit 18 - Output mask synchronization is activated by a hardware trigger"]
1359    #[inline(always)]
1360    pub fn hwom(&self) -> HWOM_R {
1361        HWOM_R::new(((self.bits >> 18) & 0x01) != 0)
1362    }
1363    #[doc = "Bit 19 - Inverting control synchronization is activated by a hardware trigger"]
1364    #[inline(always)]
1365    pub fn hwinvc(&self) -> HWINVC_R {
1366        HWINVC_R::new(((self.bits >> 19) & 0x01) != 0)
1367    }
1368    #[doc = "Bit 20 - Software output control synchronization is activated by a hardware trigger"]
1369    #[inline(always)]
1370    pub fn hwsoc(&self) -> HWSOC_R {
1371        HWSOC_R::new(((self.bits >> 20) & 0x01) != 0)
1372    }
1373}
1374impl W {
1375    #[doc = "Bit 0 - Hardware Trigger Mode"]
1376    #[inline(always)]
1377    pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W {
1378        HWTRIGMODE_W { w: self }
1379    }
1380    #[doc = "Bit 2 - CNTIN Register Synchronization"]
1381    #[inline(always)]
1382    pub fn cntinc(&mut self) -> CNTINC_W {
1383        CNTINC_W { w: self }
1384    }
1385    #[doc = "Bit 4 - INVCTRL Register Synchronization"]
1386    #[inline(always)]
1387    pub fn invc(&mut self) -> INVC_W {
1388        INVC_W { w: self }
1389    }
1390    #[doc = "Bit 5 - SWOCTRL Register Synchronization"]
1391    #[inline(always)]
1392    pub fn swoc(&mut self) -> SWOC_W {
1393        SWOC_W { w: self }
1394    }
1395    #[doc = "Bit 7 - Synchronization Mode"]
1396    #[inline(always)]
1397    pub fn syncmode(&mut self) -> SYNCMODE_W {
1398        SYNCMODE_W { w: self }
1399    }
1400    #[doc = "Bit 8 - FTM counter synchronization is activated by the software trigger"]
1401    #[inline(always)]
1402    pub fn swrstcnt(&mut self) -> SWRSTCNT_W {
1403        SWRSTCNT_W { w: self }
1404    }
1405    #[doc = "Bit 9 - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger"]
1406    #[inline(always)]
1407    pub fn swwrbuf(&mut self) -> SWWRBUF_W {
1408        SWWRBUF_W { w: self }
1409    }
1410    #[doc = "Bit 10 - Output mask synchronization is activated by the software trigger"]
1411    #[inline(always)]
1412    pub fn swom(&mut self) -> SWOM_W {
1413        SWOM_W { w: self }
1414    }
1415    #[doc = "Bit 11 - Inverting control synchronization is activated by the software trigger"]
1416    #[inline(always)]
1417    pub fn swinvc(&mut self) -> SWINVC_W {
1418        SWINVC_W { w: self }
1419    }
1420    #[doc = "Bit 12 - Software output control synchronization is activated by the software trigger"]
1421    #[inline(always)]
1422    pub fn swsoc(&mut self) -> SWSOC_W {
1423        SWSOC_W { w: self }
1424    }
1425    #[doc = "Bit 16 - FTM counter synchronization is activated by a hardware trigger"]
1426    #[inline(always)]
1427    pub fn hwrstcnt(&mut self) -> HWRSTCNT_W {
1428        HWRSTCNT_W { w: self }
1429    }
1430    #[doc = "Bit 17 - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger"]
1431    #[inline(always)]
1432    pub fn hwwrbuf(&mut self) -> HWWRBUF_W {
1433        HWWRBUF_W { w: self }
1434    }
1435    #[doc = "Bit 18 - Output mask synchronization is activated by a hardware trigger"]
1436    #[inline(always)]
1437    pub fn hwom(&mut self) -> HWOM_W {
1438        HWOM_W { w: self }
1439    }
1440    #[doc = "Bit 19 - Inverting control synchronization is activated by a hardware trigger"]
1441    #[inline(always)]
1442    pub fn hwinvc(&mut self) -> HWINVC_W {
1443        HWINVC_W { w: self }
1444    }
1445    #[doc = "Bit 20 - Software output control synchronization is activated by a hardware trigger"]
1446    #[inline(always)]
1447    pub fn hwsoc(&mut self) -> HWSOC_W {
1448        HWSOC_W { w: self }
1449    }
1450    #[doc = "Writes raw bits to the register."]
1451    #[inline(always)]
1452    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1453        self.0.bits(bits);
1454        self
1455    }
1456}
1457#[doc = "Synchronization Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synconf](index.html) module"]
1458pub struct SYNCONF_SPEC;
1459impl crate::RegisterSpec for SYNCONF_SPEC {
1460    type Ux = u32;
1461}
1462#[doc = "`read()` method returns [synconf::R](R) reader structure"]
1463impl crate::Readable for SYNCONF_SPEC {
1464    type Reader = R;
1465}
1466#[doc = "`write(|w| ..)` method takes [synconf::W](W) writer structure"]
1467impl crate::Writable for SYNCONF_SPEC {
1468    type Writer = W;
1469}
1470#[doc = "`reset()` method sets SYNCONF to value 0"]
1471impl crate::Resettable for SYNCONF_SPEC {
1472    #[inline(always)]
1473    fn reset_value() -> Self::Ux {
1474        0
1475    }
1476}
s32k142_pac/ftm0/synconf.rs

s32k142_pac/ftm0/
synconf.rs
